TWI278035B - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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TWI278035B
TWI278035B TW094110285A TW94110285A TWI278035B TW I278035 B TWI278035 B TW I278035B TW 094110285 A TW094110285 A TW 094110285A TW 94110285 A TW94110285 A TW 94110285A TW I278035 B TWI278035 B TW I278035B
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Taiwan
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gas
conductive layer
etching
layer
amount
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TW094110285A
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TW200532792A (en
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Myung-Kyu Ahn
Yun-Seok Cho
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Hynix Semiconductor Inc
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Priority claimed from KR1020050018765A external-priority patent/KR100680437B1/en
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Publication of TWI278035B publication Critical patent/TWI278035B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
    • H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The present invention relates to a method for fabricating a semiconductor device with a capacitor by performing a plasma blanket etch-back process without employing a supplemental layer for isolating lower electrodes. The method includes the steps of: forming an insulation layer with a plurality of openings on a substrate to form lower electrodes; forming a conductive layer on the insulation layer; and etching first portions of the conductive layer formed outside the openings in a faster rate than second portions of the conductive layer formed inside the openings, thereby isolating the lower electrodes from each other.

Description

1278035 九、發明說明： 【發明所屬之技術領域】 本發明爲關於一種用於製造半導體元件之方法；且，更 特定地，爲關於一種用於以一電容器製造半導體元件之方 法。 【先前技術】 對整合規模之增加與半導體元件之最小線寬減少已導 致電容器面積之減少，因爲此減低電容器面積之結果，它強 ® 迫電容器對每一晶胞（cell)需要最小具有電容大於約25fF， 因此’不同的方法以製造具備高電容之電容器於一限制面積 已被嘗試，其中一方法爲使用一具有高介電常數之介電材料 如氧化钽（Ta205)、氧化鋁（Al2〇3)或氧化鈴（Hf02)而不使用 • 具有介電常數3.8之矽氧化物與具有介電常數7之氮化物， ， 另一方法爲形成電容器之一下電極於三度空間形狀，如一柱 形或一凹形使得增加下電極之面積，另一方法爲藉生長介穩 (metastable)多晶矽（MPS)顆粒於下電極之表面上，增加下電 ^ 極之有效表面面積大於約1 .7至2倍原先表面面積。 當一電容器之柱形或凹形型式被製造，它主要執行一下 電極隔離製程其係利用一化學機械硏磨製程或一電漿全面 回蝕製程。 第1 A至1 D圖爲截面積圖例示一傳統方法使用一電漿 全面回蝕製程用於隔離下電極。 參考第1 A圖，複數個接面區域1 2如電晶體之源極與汲 極被形成於基板1 1之預定區域中，在此，雖然未例示，先 1278035 於形成該接面區域1 2 ’ 一場氧化層用於元件隔離被形成， 且接著閘結構被形成於基板1 1上。 其次，一層間絕緣層1 3被形成於基板1 1上，雖未例示， 先於形成層間（inter-layer)絕緣層1 3，一層間絕緣層形成製 程使用另一層間絕緣層用以覆蓋該閘結構，且一位元線形成 製程被執行，因此’層間絕緣層1 3具有一多層結構。 然後，該層間絕緣層1 3被蝕刻以形成複數個儲存節點 接觸孔1 4，其每一個曝露該接面區域1 2，接著，複數個儲 ® 存節點接觸插座（Plug)15被塡入該儲存節點接觸孔14，在 此，該儲存節點接觸插座1 5作爲電容器與電晶體間致能訊 號處理之角色。 一鈾刻障壁層1 6與一絕緣層1 7用以形成一電容器結 - 構，連續地被形成於層間絕緣層1 3與儲存節點接觸插座1 5 ， 上，接著，該飩刻障壁層1 6與該絕緣層1 7連續地被蝕刻以 形成複數個開口 1 8而曝露儲存節點接觸插座1 5。 於開口 1 8形成後，一導電層用於一下電極中，例如， • 一多晶矽層1 9被形成於絕緣層1 7上與進入該開口 1 8之每 一者，其後，一下電極隔離製程被實施，與一光阻層2 0作 爲一補充層用於該下電極隔離被形成於多晶矽層1 9上。 參考第1B圖，光阻層 20之一部分藉一電漿全面 (blanket)回蝕製程被移除，使得光阻層20仍僅在開口 18之 內部。 參考第1 C圖，設置於絕緣層1 7上之多晶砂層1 9部分 藉執行電漿全面回飩製程被移除，使得柱形下電極1 9 A被形[Technical Field] The present invention relates to a method for manufacturing a semiconductor element; and, more particularly, to a method for manufacturing a semiconductor element with a capacitor. [Prior Art] The increase in the integration scale and the reduction in the minimum line width of the semiconductor element have led to a reduction in the area of the capacitor. As a result of this reduction in the area of the capacitor, it is required to have a minimum capacitance greater than that of each cell. About 25fF, so 'different methods to manufacture capacitors with high capacitance have been tried in a limited area, one of which is to use a dielectric material with a high dielectric constant such as tantalum oxide (Ta205), aluminum oxide (Al2〇). 3) or oxidized bell (Hf02) without using • a cerium oxide having a dielectric constant of 3.8 and a nitride having a dielectric constant of 7, and another method of forming a lower electrode of the capacitor in a three-dimensional shape, such as a columnar shape Or a concave shape increases the area of the lower electrode, and another method is to grow metastable polycrystalline germanium (MPS) particles on the surface of the lower electrode to increase the effective surface area of the lower electrode by more than about 1.7 to 2. The original surface area. When a cylindrical or concave version of a capacitor is fabricated, it primarily performs an electrode isolation process using a chemical mechanical honing process or a plasma etchback process. Figures 1A through 1D illustrate cross-sectional areas illustrating a conventional method using a plasma full etchback process for isolating the lower electrode. Referring to FIG. 1A, a plurality of junction regions 12 such as a source and a drain of a transistor are formed in a predetermined region of the substrate 11. Here, although not illustrated, 1278035 is formed first to form the junction region 1 2 A field oxide layer is formed for element isolation, and then a gate structure is formed on the substrate 11. Next, an interlayer insulating layer 13 is formed on the substrate 11. Although not illustrated, an inter-layer insulating layer forming process is used to form an inter-layer insulating layer 13 to cover the interlayer insulating layer. The gate structure, and one bit line forming process is performed, so the 'interlayer insulating layer 13 has a multilayer structure. Then, the interlayer insulating layer 13 is etched to form a plurality of storage node contact holes 14 each exposed to the junction region 12, and then a plurality of storage node contact plugs 15 are inserted into the junction The storage node contact hole 14 is here in contact with the socket 15 as a function of enabling signal processing between the capacitor and the transistor. An uranium barrier layer 16 and an insulating layer 17 are formed to form a capacitor junction, which is continuously formed on the interlayer insulating layer 13 and the storage node contact socket 15 , and then the etch barrier layer 1 6 is continuously etched with the insulating layer 17 to form a plurality of openings 18 to expose the storage node contact socket 15. After the opening 18 is formed, a conductive layer is used in the lower electrode, for example, a polysilicon layer 19 is formed on the insulating layer 17 and enters each of the openings 18, and thereafter, the lower electrode isolation process It is implemented, and a photoresist layer 20 is used as a supplementary layer for the lower electrode isolation to be formed on the polysilicon layer 19. Referring to Figure 1B, a portion of the photoresist layer 20 is removed by a plasma blanket etchback process such that the photoresist layer 20 is still only inside the opening 18. Referring to FIG. 1C, the portion of the polycrystalline sand layer 19 disposed on the insulating layer 17 is removed by performing a plasma full-return process, so that the cylindrical lower electrode 1 9 A is shaped.

I27803S 成於開口 1 8之內部。 以移除光 形下電極 離下電極 壞，且避 19A之表 可被輕易 :情形中， 隔離下電 丨淨製程， 層是困難 回蝕製程 圓之一些 ，當金屬 成下電極 造一半導 會損壞下 之一補充 參考第1D圖，一剝離製程藉使用氧氣電漿用 阻層2 0被實施，且接著，絕緣層1 7藉此曝露該柱 19A被移除。 如上所述，光阻層20被用作爲補充層用以隔 1 9 A以避免電容器之內側於下電極隔離製程中被損 免一污染問題發生，當一接續製程用以增加下電極 面面積被施加，而且，使用氧氣電漿，光阻層20 ®地移除而不會損害低電極19A。 然而，於對下電極隔離使用電漿全面回蝕製程 它必須執行至少四額外的步驟；形成補充層用以 極、移除部分補充層、完全移除補充層與執行一湧 - 更且，於次l〇〇nm奈米科技中對完全移除該補充 _ 的，例如，當光阻層被用作爲補充層，於電漿全面 後實施移除補充層之步驟中，光阻層仍可保持於晶 區域上，且此殘餘光阻層可導致單一位元失效發生 ® 如氮化鈦（TiN)與釕（Ri〇被使用爲一導電層用以形 時，此問題可被觀察到。 【發明內容】 因此，本發明之一目的爲提供一種方法用以製 體兀件，其能夠以一簡單下電極隔離製程進行而不 電極且避免單一位元失效發生，當用於下電極隔離 層被使用時。 依據本發明之一觀點，提供一種用以製造一半導體元件 1278035 方法，包含步驟：（a)在基板上形成具有複數個開口的一絕緣 層，以形成下電極；（b)在絕緣層上形成一導電層；與（c)以 較形成於開口內之導電層之第二部分爲快的蝕刻形成於開 口外之導電層第一部分，藉以相互隔離下電極。 【實施方式】 依據本發明之一較佳實施例，一種用於製造一半導體元 件之方法將於以下參考附圖提出而詳細描述。 爲簡化將變得複雜之下電極隔離製程，當使用一補充層 ® 如一光阻層用以避免於下電極隔離製程中下電極之內側與 底部表面被損壞，本發明之較佳實施例例示於使用一電漿全 面回蝕製程用以隔離下電極而不會損害下電極，甚至係於缺 少補充層之情形下時。 • 弟2A至2D圖爲截面積圖，例不依據本發明之一較佳 ^ 實施例用以製造具有一電容器之半導體元件之方法。 參考第2A圖，一些接面區域22如電晶體之源極/汲極 被形成於一基板2 1中，雖未例示，先於形成接面區域22， I 一場氧化層用於兀件隔離被形成，且一些閘結構被形成於基 板21上。 於接面區域22形成後，一層間絕緣層23被形成於基板 2 1上，雖未例示，先於形成層間絕緣層23，另一層間絕緣 層用以覆蓋閘結構被形成且接著，蝕刻以形成位元線，因 此，層間絕緣層2 3具有一多層結構· 其次，層間絕緣層23被蝕刻以形成儲存節點接觸孔24 曝露該個別接面區域22，與一插座材料被塡入儲存節點接觸 1278035 孔2 4，藉以形成一些儲存節點接觸插座2 5 點接觸插座25被塡入儲存節點接觸孔24作 體間致能訊號處理之一角色，其將接著被形 其後，一蝕刻障壁層26與一絕緣層27 器結構連續地被形成於層間絕緣層2 3與儲 2 5上，接著，絕緣層2 7與蝕刻障壁層2 6連 成一些開口 2 8曝露個別儲存節點接觸插座 一導電層2 9以形成下電極被形成於絕糸 k 開口 2 8，在此，導電層2 9被基於選自於一 矽、一堆未掺雜多晶矽/掺雜多晶矽、鎢（W) 釕（Ru)與鉑（Pt)之材料。 參考第2B圖，一下電極隔離製程被實 • 成柱形下電極，一電漿全面回蝕製程被執行 . 阻層’其爲一補充層用於傳統方法中使用於 且’視所用材料用以形成導電層2 9而定， 的不同。 > 此後，假定導電層29用以形成下電極 選取材料，電漿全面回蝕製程將詳細被描述 通常地，一電漿蝕刻裝置包括具有一頂 電極之室，一具備耙（t a r g e t)餓刻結構之晶 極之頂部上，在此，頂部電極爲一電極用以 產生一電漿，同時底部電極爲一電極用以供 吸引電漿之離子與原子團（radicals)朝向晶B 與底部電極相互被分離，它可能分別控制離 ，在此，儲存節 爲電容器與電晶 成。 用以形成一電容 存節點接觸插座 續地被蝕刻以形 25 ° 彖層27上且進入 群包括掺雜多晶 、氮化鈦（TiN)、 施，此時，爲形 而不需使用一光 下電極隔離，而 蝕刻製程配方變 爲基於TiN之一 ；〇 部電極與一底部 圓被設置底部電 供應一源功率以 應一偏壓電源以 B，因爲頂部電極 子與原子團之能The I27803S is built into the interior of the opening 18. To remove the light-shaped lower electrode from the lower electrode, and avoid the 19A table can be easily: in the case, the electricity is cleaned under the net process, the layer is a part of the difficult etch-back process circle, when the metal is made into the lower electrode to make a half guide One of the damages is supplemented with reference to Fig. 1D, a stripping process is carried out by using the oxygen plasma resist layer 20, and then the insulating layer 17 is thereby exposed to remove the column 19A. As described above, the photoresist layer 20 is used as a supplementary layer for isolating 19 A to prevent the inside of the capacitor from being damaged in the lower electrode isolation process, and a subsequent process is used to increase the area of the lower electrode surface. Applied, and, with oxygen plasma, the photoresist layer 20 is removed without damaging the low electrode 19A. However, it is necessary to perform at least four additional steps in the plasma etchback process for the lower electrode isolation; forming a supplemental layer for the pole, removing a portion of the supplemental layer, completely removing the supplemental layer, and performing a surge - and more In the case of the complete removal of the supplement _, for example, when the photoresist layer is used as a supplemental layer, the photoresist layer can remain in the step of removing the supplemental layer after the plasma is fully integrated. This problem can be observed when the residual photoresist layer can cause a single bit failure to occur, such as titanium nitride (TiN) and tantalum (Ri〇 is used as a conductive layer for shape). SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for forming a body member that can be performed in a simple lower electrode isolation process without electrodes and avoiding single bit failures when used in the lower electrode isolation layer. In accordance with one aspect of the present invention, a method for fabricating a semiconductor device 1278035 is provided, comprising the steps of: (a) forming an insulating layer having a plurality of openings on a substrate to form a lower electrode; (b) Forming a conductive layer on the layer; and (c) forming a first portion of the conductive layer outside the opening by etching faster than the second portion of the conductive layer formed in the opening, thereby isolating the lower electrode from each other. DETAILED DESCRIPTION OF THE INVENTION A preferred method for fabricating a semiconductor device will be described in detail below with reference to the accompanying drawings. To simplify the electrode isolation process which will become complicated, when a complementary layer such as a photoresist layer is used In order to avoid damage to the inner and bottom surfaces of the lower electrode in the lower electrode isolation process, a preferred embodiment of the present invention is exemplified by using a plasma full etchback process for isolating the lower electrode without damaging the lower electrode, or even In the absence of a supplemental layer. • The 2A to 2D diagram is a cross-sectional area diagram, and is not a method for fabricating a semiconductor device having a capacitor according to a preferred embodiment of the present invention. Referring to FIG. 2A, some The junction region 22, such as the source/drain of the transistor, is formed in a substrate 21, although not illustrated, prior to forming the junction region 22, a field oxide layer is formed for the isolation of the element. And some gate structures are formed on the substrate 21. After the junction regions 22 are formed, an interlayer insulating layer 23 is formed on the substrate 21, although not illustrated, prior to forming the interlayer insulating layer 23, another interlayer insulating layer A cover gate structure is formed and then etched to form a bit line, and therefore, the interlayer insulating layer 23 has a multilayer structure. Second, the interlayer insulating layer 23 is etched to form a storage node contact hole 24 to expose the individual junction. The area 22 is in contact with a socket material into the storage node 1278035 hole 2 4, thereby forming some storage node contact socket 25 point contact socket 25 is inserted into the storage node contact hole 24 to perform one of the functions of inter-body enabling signal processing. It will be subsequently formed, an etch barrier layer 26 and an insulating layer 27 are continuously formed on the interlayer insulating layer 23 and the reservoir 25. Then, the insulating layer 27 is connected to the etch barrier layer 26. A plurality of openings 28 exposing the individual storage node contacts the socket-conductive layer 209 to form a lower electrode formed on the 糸k opening 2, where the conductive layer 296 is based on a stack of undoped polysilicon /Doped more Silicon, tungsten (W), ruthenium (Ru) and platinum (Pt) of the material. Referring to Figure 2B, the lower electrode isolation process is implemented as a cylindrical lower electrode, and a plasma full etchback process is performed. The resist layer is a complementary layer used in conventional methods and is used as the material used. The difference in the formation of the conductive layer 2 9 is determined. > Thereafter, assuming that the conductive layer 29 is used to form the lower electrode selection material, the plasma full etch back process will be described in detail. Generally, a plasma etching apparatus includes a chamber having a top electrode, and a target is hungry. At the top of the crystal pole of the structure, the top electrode is an electrode for generating a plasma, and the bottom electrode is an electrode for attracting plasma ions and radicals toward the crystal B and the bottom electrode. Separation, it may control the separation separately, where the storage section is a capacitor and an electric crystal. The contact socket for forming a capacitor node is continuously etched to form a 25° layer 27 and the group includes doped polycrystalline, titanium nitride (TiN), and at this time, it is shaped without using a light. The lower electrode is isolated, and the etching process recipe becomes one based on TiN; the bottom electrode and a bottom circle are provided with a bottom supply electric source to supply a bias power supply to B because of the energy of the top electrode and the atomic group

I27803S 藉使用上述電漿蝕刻裝置實施之電漿回蝕製程可被分 類成一物理蝕刻製程、一化學蝕刻製程與一物理化學蝕刻製 程。 首先，於物理融刻製程中，一電漿藉使用一惰氣如氬 (Ar) ’氨（He)與氙（Xe)被產生。電漿之正離子垂直打擊到晶 圓，藉此物理性蝕刻一蝕刻靶層。另一方面，化學蝕刻製程 藉使用一氣體產生一電漿，製造蝕刻靶層之一蝕刻，其中該 ^ 氣體對該鈾刻靶層於一電漿相中爲化學反應的，且接著經由 電漿之致動中性原子團之使用，化學性鈾刻該蝕刻靶層。物 理化學蝕刻製程藉使用正離子之強大撞擊能量產生一蝕 刻，其中該撞擊能量係當電漿之正離子撞擊晶圓且同時電漿 . 之原子團所生成，其係對蝕刻靶層爲化學性反應。物理化學 . 蝕刻製程之這些特性結果，它能以一較快步驟獲得增加蝕刻 速率之一配合作用效果。 基於上述之電漿蝕刻製程原則，當導電層29，即TiN ® 層被蝕刻時，一 Ar與Cl2氣體之混合氣體被使用導入TiN 層29之一物理化學蝕刻。即是，Ar氣體爲用於TiN層29 之一物理蝕刻，同時基於Cl2氣體對TiN爲化學性反應之事 實，Cl2氣體爲用於TiN層29之一化學蝕刻。 在假設物理蝕刻製程僅藉使用Ar氣體被實施下，當TiN 層29經歷電漿全面回蝕製程而不用使用一補充層用以形成 下電極，形成於開口 28外與形成於開口 28內之TiN層29 被蝕刻。而且，於物理蝕刻製程中碰撞之TiN分子變成連續 -10- 1278035 沉積於蝕刻室之壁上，結果，會有減低功率傳送效率與產生 不想要粒子的問題。 假如化學蝕刻製程僅藉使用C ! 2氣體被實施以形成下電 極而不用使用補充層，一等方性（i s 〇 t r 〇 p i c)蝕刻特色，即， 無具有方向性，會在化學蝕刻製程中被觀察到。因此，設置 於開口 2 8外側與在每一開口 2 8內側之深區域上之TiN層 29部分被蝕刻，且因此，下電極之高度減少。而且，當Cl2 氣體沿TiN層29之顆粒擴散時，TiN層29被蝕刻藉此導致 胃下電極之粗糙性與非均勻形狀。而且，TiN層29之顆粒容 易被剝離甚至在一小震動下，而導致元件瑕疵。另外，假如 絕緣層之一蝕刻構形之縱橫比（aspect rati 〇)27爲小的，設置 於每一開口 28內側之底部部分上的TiN層29被蝕刻，導致 - 下電極之完全蝕刻。 . 因此，爲達到下電極之一意欲隔離而不用使用補充層， 形成於開口 2 8外側之TiN層2 9藉同時施加物理蝕刻製程與 化學蝕刻製程，被設定以一較快速率飩刻。同時，形成於個 ^ 別開口 2 8內部，更特定地，形成於每一開口 2 8內側之底部 部分與側面部分上之TiN層29，藉控制蝕刻氣體與蝕刻配 方被設定以一較慢速率化學性蝕刻。 通常地，於蝕刻多晶矽與金屬情形中，因爲離子之方向 性，物理蝕刻製程很少發生於每一開口 2 8之內側面部分。 然而，在每一開口 2 8之內底部部分，物理蝕刻製程發生。 爲抑制物理蝕刻製程發生於每一開口 2 8之內底部部分，每 一開口 2 8之內部壓力藉引入離子與存在於個別開口 2 8內部 -11- 1278035 之其他粒子的撞擊被增加，造成在垂直方向進入個別開口 2 8 之離子的能量損失。個別開口 2 8之內部壓力可藉使用一蝕 刻氣體施加一電漿蝕刻製程被增加，其中該蝕刻氣體能相對 於形成在個別開口 2 8內部之下電極材料，導入一化學蝕刻。 此時，當設置於個別開口 2 8內部之大量下電極材料與 於化學蝕刻中被產生的蝕刻殘餘物，每一開口 2 8之內部壓 力可被增加且結果，進入每一開口 2 8內側之離子撞擊蝕刻 殘餘物，造成離子能量損失。因此，即使離子抵達每一開□ ^ 2 8之內底部部分，能量減少係夠大以阻止物理蝕刻製程發 生。 除開口 2 8之內部壓力增加外，它必須減少進入每一開 口 28內側之離子的能量水準以最小化或除去每一開口 28之 ^ 內底部部分上之物理蝕刻製程效果。即是，即使個別開口 2 8 ^ 之內部壓力爲高的，假如離子之能量水準仍爲高的，物理蝕 刻可發生於個別開口 28之內底部部分。因此，於每一開口 2 8之內底部部分附近之離子能量水準藉結合由蝕刻殘餘物 • 造成之個別開口 2 8之內部壓力與決定離子能量水準之一偏 壓功率被決定。 爲調整由蝕刻殘餘物所造成之個別開口 2 8之內部壓 力，即是，於化學蝕刻製程中所產生之蝕刻殘餘物量的調 整，它對選取引發化學蝕刻之一合適蝕刻氣體與調整用於物 理蝕刻製程之一蝕刻氣體與用於化學蝕刻製程之一蝕刻氣 體間之一組成比率爲重要的。而且，它宜儘可能減少離子能 量以最小化個別開口 2 8之內底部部分附近離子能量水準。 -12-The plasma etchback process implemented by the I27803S using the above plasma etching apparatus can be classified into a physical etching process, a chemical etching process, and a physicochemical etching process. First, in the physical etching process, a plasma is produced by using an inert gas such as argon (Ar) 'ammonia (He) and xenon (Xe). The positive ions of the plasma strike perpendicularly to the crystal, thereby physically etching an etch target layer. In another aspect, the chemical etching process etches an etch target layer by using a gas to generate a plasma, wherein the gas is chemically reacted into the uranium engraved layer in a plasma phase, and then via plasma The use of a neutral atomic group, the chemical uranium engraves the etch target layer. The physicochemical etching process generates an etch by using the strong impact energy of the positive ions, wherein the impact energy is generated when the positive ions of the plasma strike the wafer and are simultaneously formed by the atomic groups of the plasma. . Physical Chemistry. As a result of these characteristics of the etching process, it is possible to obtain a synergistic effect of increasing the etching rate in a faster step. Based on the above-described plasma etching process principle, when the conductive layer 29, i.e., the TiN ® layer, is etched, a mixed gas of Ar and Cl 2 gases is etched into the TiN layer 29 using a physical chemical etching. That is, the Ar gas is used for physical etching of one of the TiN layers 29, and based on the fact that the Cl2 gas is chemically reacted to TiN, the Cl2 gas is used for chemical etching of one of the TiN layers 29. Assuming that the physical etching process is performed only by using Ar gas, when the TiN layer 29 is subjected to a plasma full etch back process without using a supplemental layer for forming the lower electrode, the TiN formed outside the opening 28 and formed in the opening 28 Layer 29 is etched. Moreover, the TiN molecules colliding in the physical etching process become continuous -10- 1278035 deposited on the walls of the etching chamber, and as a result, there is a problem of reducing power transmission efficiency and generating unwanted particles. If the chemical etching process is performed only by using C 2 gas to form the lower electrode without using a supplemental layer, an isotropic (is 〇tr 〇pic) etching feature, ie, no directionality, will be in the chemical etching process. be observed. Therefore, the portion of the TiN layer 29 disposed outside the opening 28 and deep on the inner side of each of the openings 28 is etched, and therefore, the height of the lower electrode is reduced. Moreover, when the Cl2 gas diffuses along the particles of the TiN layer 29, the TiN layer 29 is etched thereby resulting in a rough and non-uniform shape of the lower stomach electrode. Moreover, the particles of the TiN layer 29 are easily peeled off even under a small shock, resulting in component defects. Further, if the aspect ratio 27 of the etching structure of one of the insulating layers is small, the TiN layer 29 provided on the bottom portion of the inner side of each opening 28 is etched, resulting in complete etching of the lower electrode. Therefore, in order to achieve isolation of one of the lower electrodes without using a supplemental layer, the TiN layer 29 formed outside the opening 28 is set to be etched at a relatively rapid rate by applying both a physical etching process and a chemical etching process. At the same time, it is formed inside the opening 28, and more specifically, the TiN layer 29 formed on the bottom portion and the side portion of the inner side of each opening 28 is set at a slower speed by controlling the etching gas and the etching recipe. Rate chemical etching. Generally, in the case of etching polysilicon and metal, the physical etching process rarely occurs in the side portion of each opening 28 because of the directionality of the ions. However, a physical etching process occurs at the bottom portion within each opening 28. In order to suppress the physical etching process from occurring in the bottom portion of each of the openings 28, the internal pressure of each opening 28 is increased by the impact of the introduced ions and other particles present in the interior of the individual openings 28-11-1278035, resulting in The energy loss of ions entering the individual openings 28 in the vertical direction. The internal pressure of the individual openings 28 can be increased by applying a plasma etching process using an etch gas which is capable of introducing a chemical etch relative to the electrode material formed beneath the individual openings 28. At this time, when a large amount of the lower electrode material disposed inside the individual opening 28 and the etching residue generated in the chemical etching, the internal pressure of each opening 28 can be increased and as a result, enter the inside of each opening 28. The ions strike the etching residue, causing loss of ion energy. Therefore, even if the ions reach the bottom portion within each opening ^ 2 8 , the energy reduction is large enough to prevent the physical etching process from occurring. In addition to the increased internal pressure of the opening 28, it must reduce the level of energy entering the ions inside each opening 28 to minimize or remove the physical etching process effect on the bottom portion of each opening 28. That is, even if the internal pressure of the individual openings 2 8 ^ is high, if the energy level of the ions is still high, physical etching may occur in the bottom portion of the individual openings 28 . Therefore, the level of ion energy in the vicinity of the bottom portion of each opening 28 is determined by combining the internal pressure of the individual openings 28 caused by the etching residue and the biasing power of one of the ion energy levels. In order to adjust the internal pressure of the individual openings 28 caused by the etching residue, that is, the adjustment of the amount of etching residue generated in the chemical etching process, it is suitable for selecting one of the chemical etchings to etch the gas and adjusting it for physical use. It is important that the composition ratio of one of the etching process and one of the etching gases used in the chemical etching process is important. Moreover, it is desirable to minimize the amount of ion energy to minimize ion energy levels near the bottom portion of the individual openings 28. -12-

I27803S 然而，假如，爲抑制物理蝕刻製程發生，該偏壓功率減少至 一極低水準，形成於開口 2 8外部之TiN層2 9可不被物理性 蝕刻。爲此，該偏壓功率應被適當地設定。 總之，不使用補充層實施之電漿全面回蝕製程需要一適 合的蝕刻與蝕刻氣體組合，其使形成個別開口 2 8外部之下 電極材料一部分被化學性與物理性蝕刻，同時形成於個別開 口 2 8之內側面與底部部分上之下電極材料之另一部分被化 學性蝕刻。 ^ 例如，於TiN情況下，一 Ar與Cl2混合氣體被用以在 個別開口 2 8之外側產生一物理化學蝕刻製程，且爲抑制物 理蝕刻製程在個別開口 2 8之內底部部分發生，一偏壓功率 被調整至一低水準範圍從約30W至約3 0 0W。而且，在Ar - 與Cl2氣體之混合氣體中之Cl2氣體成份百分比被調整至於 _ 一範圍從約1 %至約5 0%，以控制一化學蝕刻製程程度。 而且，蝕刻室之壓力被控制於一範圍從約lmtorr至約 5 Omtorr，以使物理蝕刻與化學蝕刻被執行於意欲之程度。 ® 另外，頂部電極之功率、腔室壓力、頂部電極之溫度與腔室 溫度在電漿全面回蝕製程上並無大的影響，但被調整以適當 地施加至每一所需的製程配方。 在上述製程配方下於電漿全面回蝕製程被實施情形，設 置於個別開口 28外部之TiN層29以一較快速率被蝕刻，其 中設置於個別開口 2 8之內側面部分TiN層2 9被最小地蝕 刻，因爲設置於個別開口 28之內側面部分上之TiN層29的 化學蝕刻，藉調整Cl2氣體之成份百分比在1%至50%範圍’ 1278035 以一慢速率被設定實施。 而且，因爲原子團與形成於個別開口 2 8之內側面部分 之TiN層29間的反應副產品塡滿開口 28，每一開口 28之 內部壓力增加且偏壓功率被調整至從約3 0W至約3 00 W之低 範圍。因此，朝個別開口 28之內底部部分擴散之電漿之原 子團與進入個別開口 2 8之內底部部分之電漿之正離子被抑 制流向內部且結果，形成於每一開口 2 8之內底部部分之TiN 層2 9是較少蝕刻的。 整體上，以上所提及之製程係設定使形成於個別開口 2 8 外部之TiN層29藉物理化學蝕刻製程快速蝕刻，且使TiN 層29設置於個別開口 28之內側面部分與內底部部分上之 TiN層29,以較形成於個別開口 28外部之TiN層29被速率 ^ 爲慢蝕刻，且因此，電漿全面回蝕製程被執行於一垂直方向 . 而不用使用補充層，它仍能獲得一意欲下電極蝕刻構形。 當電漿全面回蝕製程相對於TiN層29被實施，在個別 開口 28之內側面與底部部分蝕刻速率相較於個別開口 28之 ® 外部，被調整至一範圍從約1 %至約70%，而且，在個別開 口 2 8之內側面部分蝕刻速率被調整至與個別開口 2 8之內底 部部分相同。 對此等意欲蝕刻速率，一特定配方被設定。首先’一室 壓力與一室溫度被分別維持在約1〇mt〇rr與4〇〇c，而且，一 源功率約3 0 0 W與一偏壓功率約1 0 0 W被供應。此時’大約 10 seem之Cl2氣體與大約190 seem之Ar氣體被提供。而且， 終端點（EOP)與過度蝕刻（0E)分別爲大約16”=tl”與10”。 -14- 1278035 在以上預定配方下，當TiN層29之厚度被假設爲大約 3 00 A，在個別開口 28外側之一蝕刻速率爲大約每分鐘 1 1 20A，且在個別開口 28之內側面部分與內底部部分一蝕刻 速率減少一較大程度約每分鐘1 0A，在此，個別開口 28外 側之TiN層29之蝕刻速率視一蝕刻配方而改變，蝕刻速率 之一平均値爲一範圍從大約每分鐘 5 00A至大約每分鐘 2000A，因此，在個別開口 28之內側面與底部部分上TiN 層29之一平均蝕刻速率範圍從大約每分鐘5 A至大約每分鐘 ^ 140A，後者蝕刻速率爲大約7%正式蝕刻速率其大約爲每分 鐘 2000A 。 而且，鈾刻速率其因Cl2氣體與Ar氣體之組成比率調 整而變化，爲大於約每分鐘5 00A當Cl2氣體對Ar氣體之組 • 成比率非常低時，另一方面，當Cl2氣體對Ar氣體之組成 . 比率爲非常高時，蝕刻速率變成至約每分鐘3 000A，即是， 蝕刻速率可改變於一範圍從約每分鐘 5 00A至約每分鐘 3 000A經由調整Cl2氣體與Ar氣體之組成比率，然而，因爲 ® 下電極並不厚，此並非一問題，雖然，蝕刻配方被調整至減 緩鈾刻速率用以控制蝕刻構形、過度蝕刻與相類物目的。 較佳地，電漿全面回蝕製程於一壓力約5mtorr至約 20mtorr進行，一源功率約3 00W至約800W且一偏壓功率約 3 0W至約3 00W，此時，Cl2氣體百分比對於Ar與Cl2混合 氣體宜爲於一範圍從約1%至約50%，且一電極溫度較佳地 於一範圍從約1 〇 ° C至約4 0 ^ C . 以上本發明之較佳實施例中，一蝕刻氣體其於電漿全面 -15- l278〇35 ®蝕製程中導入化學蝕刻製程於TiN層29上可爲一單一溴 基氣體選自於一群包含Cl2，HC1與CC14或藉混合以上列溴 基氣體所得之氣體之結合，另外使用此處所提及之混合氣 體，一氣體如Ar，Xe與He可被單獨添加或聯合以穩定電漿， 控制靶氣體數量與稀釋蝕刻氣體。而且，它可能添加一者或 〇2氣體與N2氣體二者用以鈍化目的或作爲一反應抑制物用 以避免被主要執行於化學蝕刻製程時下電極被損壞之目的。 雖然本發明之較佳實施例例示蝕刻配方當TiN被用以 下電極，蝕刻配方視使用於導電層29之材料而變化。 首先，於一矽基材料被用作爲導電層2 9用以形成下電 極’ 一蝕刻氣體用於電漿全面回鈾製程之化學蝕刻製程被單 獨選取或結合從一群包含氟化基之氣體如SF6，NF3或CF4， 一氯化基氣體如Cl2與一硼化基氣體如HBr.I27803S However, if the bias power is reduced to a very low level in order to suppress the physical etching process, the TiN layer 29 formed outside the opening 28 may not be physically etched. For this reason, the bias power should be set as appropriate. In summary, a plasma etchback process that is performed without the use of a supplemental layer requires a suitable combination of etching and etching gas that causes a portion of the electrode material that is formed outside the individual openings 28 to be chemically and physically etched while being formed in individual openings. Another portion of the electrode material on the side and bottom portions of the inner portion of the inner portion is chemically etched. ^ For example, in the case of TiN, a mixed gas of Ar and Cl2 is used to generate a physicochemical etching process on the outer side of the individual openings 28, and to suppress the physical etching process from occurring in the bottom portion of the individual openings 28, a bias The pressure power is adjusted to a low level ranging from about 30 W to about 300 W. Further, the percentage of the Cl2 gas component in the mixed gas of the Ar- and Cl2 gases is adjusted to a range of from about 1% to about 50% to control the degree of a chemical etching process. Moreover, the pressure of the etch chamber is controlled to a range from about lmtorr to about 5 Omtorr, so that physical etching and chemical etching are performed to the extent desired. In addition, the power of the top electrode, the chamber pressure, the temperature of the top electrode, and the chamber temperature have no major effect on the overall plasma etchback process, but are adjusted to be properly applied to each desired process recipe. In the above process recipe, in the case where the plasma etchback process is carried out, the TiN layer 29 disposed outside the individual openings 28 is etched at a relatively fast rate, wherein the TiN layer 291 is disposed on the inner side portion of the individual openings 28. The minimum etching is performed because the chemical etching of the TiN layer 29 disposed on the inner side portion of the individual opening 28 is set at a slow rate by adjusting the composition percentage of the Cl2 gas in the range of 1% to 50% ' 1278035. Moreover, since the reaction byproducts between the atomic group and the TiN layer 29 formed on the inner side portion of the individual opening 28 fill the opening 28, the internal pressure of each opening 28 is increased and the bias power is adjusted from about 30 W to about 3 00 W low range. Therefore, the positive ions of the plasma that diffuse toward the bottom portion of the individual opening 28 and the plasma that enters the bottom portion of the individual opening 28 are suppressed from flowing to the inside and, as a result, are formed in the bottom portion of each opening 28. The TiN layer 209 is less etched. In general, the above-mentioned process is set such that the TiN layer 29 formed outside the individual openings 28 is quickly etched by a physicochemical etching process, and the TiN layer 29 is disposed on the inner side portion and the inner bottom portion of the individual openings 28. The TiN layer 29 is slowly etched at a rate of the TiN layer 29 formed outside the individual openings 28, and thus, the plasma full etch back process is performed in a vertical direction. Without using a supplemental layer, it can still be obtained. One desires to etch the electrode configuration. When the plasma etchback process is performed relative to the TiN layer 29, the etch rate of the side and bottom portions of the individual openings 28 is adjusted to a range from about 1% to about 70% compared to the outside of the individual openings 28. Moreover, the side portion etch rate within the individual openings 28 is adjusted to be the same as the bottom portion within the individual openings 28. For this etch rate, a specific recipe is set. First, the 'one chamber pressure and one chamber temperature are maintained at about 1 〇 〇 rr and 4 〇〇 c, respectively, and a source power of about 300 W and a bias power of about 100 W are supplied. At this time, about 10 seemingly Cl2 gas and about 190 seem of Ar gas are supplied. Moreover, the termination point (EOP) and over-etching (0E) are about 16"=tl" and 10", respectively. -14- 1278035 Under the above predetermined formulation, when the thickness of the TiN layer 29 is assumed to be about 300 A, The etching rate of one of the outer sides of the individual openings 28 is about 1 1 20 A per minute, and the etching rate of the inner side portion and the inner bottom portion of the individual openings 28 is reduced by a relatively large degree of about 10 A per minute, where the individual openings 28 are outside. The etch rate of the TiN layer 29 varies depending on an etch recipe, and one of the etch rates averages from about 50,000 A per minute to about 2000 A per minute, thus, the TiN layer on the side and bottom portions of the individual openings 28 An average etch rate of 29 ranges from about 5 A per minute to about 140 A per minute, the latter having an etch rate of about 7% of the formal etch rate of about 2000 A per minute. Moreover, the uranium engraving rate is due to the Cl2 gas and the Ar gas. The composition ratio is varied to be greater than about 50,000 A per minute when the ratio of Cl2 gas to Ar gas is very low, and on the other hand, when the ratio of Cl2 gas to Ar gas is very high, The engraving rate becomes about 3 000 A per minute, that is, the etching rate can be varied from a range of about 50,000 A per minute to about 3 000 A per minute by adjusting the composition ratio of Cl 2 gas to Ar gas, however, because the lower electrode is Not thick, this is not a problem, although the etch recipe is adjusted to slow the uranium engraving rate to control the etch configuration, over etch and phase objects. Preferably, the plasma etchback process is at a pressure of about 5 mtorr to Approximately 20 mtorr is performed, a source power of about 300 W to about 800 W and a bias power of about 30 W to about 300 W. At this time, the Cl2 gas percentage is preferably in the range of from about 1% to about 50 for the mixed gas of Ar and Cl2. %, and an electrode temperature is preferably in the range of from about 1 〇 ° C to about 40 ° C. In the preferred embodiment of the invention, an etching gas is present in the plasma -15 - l278 〇 35 ® Introducing a chemical etching process into the TiN layer 29 in the etching process may be a single bromine-based gas selected from the group consisting of a mixture of Cl2, HC1 and CC14 or a gas obtained by mixing the above bromine-based gas, additionally used herein. Mixed gas, a gas such as Ar, Xe and H e may be added alone or in combination to stabilize the plasma, control the amount of target gas and dilute the etching gas. Moreover, it may add one or both 〇2 gas and N2 gas for passivation purposes or as a reaction inhibitor to avoid The lower electrode is mainly damaged during the chemical etching process. Although the preferred embodiment of the present invention exemplifies the etching recipe, when the TiN is used with the following electrodes, the etching recipe varies depending on the material used for the conductive layer 29. First, The ruthenium-based material is used as the conductive layer 209 to form the lower electrode'. The etching process for the plasma full uranium process is separately selected or combined from a group of fluorinated-containing gases such as SF6, NF3 or CF4. , a monochlorinated gas such as Cl2 and a boronic group gas such as HBr.

於使用鎢（W)作爲導電層2 9用以形成下電極情形下，鈾 刻氣體用於電漿全面回蝕製程之化學蝕刻製程被單獨選取 或結合從一群氟化基之氣體包括SF6，NF3與CF4。 假如一貴金屬如釕（Ru)或鉑（Pt)被用作爲導電層29用 以形成下電極，02氣體與Cl2氣體被單獨選取或結合被用作 爲蝕刻氣體用於電漿全面回蝕製程之化學蝕刻製程。 當執行電漿全面回蝕製程使用矽基材料，鎢與一貴金屬 中之一者，除上述之蝕刻氣體用於化學蝕刻製程外，一惰氣 被用作爲一蝕刻氣體用於物理蝕刻製程，而且，一惰氣單獨 選取或從一群包括Ar，Xe與He之結合被用以穩定電漿，控 制所選氣體之數量與稀釋主要餓刻氣體，假如化學餓刻特性 -16- 1278035 因爲上述蝕刻氣體用於化學蝕刻製程之使用出現主導性，其 一者或 〇2氣體與 N2氣體二者被添加作爲一鈍化 (passivation)介質或一反應抑制劑用以抑制化學蝕刻特性。 電漿蝕刻裝置用於電漿全面回蝕製程之例子爲一感應 耦合電漿（ICP)蝕刻裝置，一電子迴旋加速共振器（ECR)蝕刻 裝置，一微波蝕刻裝置，與一電容耦合電漿蝕刻製程。蝕刻 氣體之成份百分比，源電源、偏壓功率、頂部電極之壓力與 溫度且底部電極被調整以控制基板結構之一蝕刻構形，其於 ® 下電極之隔離中被形成於開口 2 8之外側。 第2C圖顯示前述之下電極29A藉如第2B圖中所例示 之下電極隔離製程被形成，在此，下電極29A爲一柱形型式。 參考第2D圖，一溼浸出（wet dip-out)製程被執行以移 . 除絕緣層27，由此溼浸出製程，柱形下電極29A被曝露。 ^ 依據本發明之較佳實施例，電漿全面回蝕製程使它可能 隔離下電極而不會在下電極之底部部分產生凹孔（punch)，甚 至在缺少補充層下，此補充層之省除提供避免單一位元失效 # 發生效果，藉此導致半導體元件產出更增加。 而且，因爲當一般使用電漿鈾刻裝置被使用時蝕刻製程 配方被調整，沒有成本相關的負擔用以設置新裝置以形成電 容器，而且，物理蝕刻製程之同時性能具有垂直方向性之特 色且化學蝕刻製程具有一等方性蝕刻特色提供蝕刻均勻度 上一額外改進效果。 本發明包含主體關於韓國專利申請號KR 2004-002206 1 與2 00 5 -00 1 8 7 5 6，其係2004年3月3 1日與200 5年3月7 1278035 日個別申請於韓國專利局，其全部內容被倂入於此作爲參 考。 當本發明 關於一些較佳實施例已被描述，它對技藝中人 士將是明顯的各種變更與修改可不用偏離如界定於以下專 利申請範圍之本發明精神與範疇。 【圖式簡單說明】 本發明之以上與其他目的與特色將對於連同附圖之較 佳實施例之以下描述而變得更佳了解，其中： 第1 A至1 D圖爲截面積圖例示一傳統方法使用一電漿 全面回蝕製程用於隔離下電極；與 第2A至2D圖爲截面積圖例示依據本發明之一較佳實 施例用以製造一半導體元件之方法。 【主要元件符號說明】 19 多晶砂層 - 19A ， 29A 下電極 1 1，2 1 基板 _ 12 ， 22 接面區域 13，23 層間絕緣層 14，2 4 儲存節點接觸孔 15，25 儲存節點接觸插座 16，2 6 蝕刻障壁層 17，27 絕緣層 1 8，28 開口 29 導電層 -18-In the case where tungsten (W) is used as the conductive layer 2 to form the lower electrode, the chemical etching process for the etched gas for the plasma etchback process is separately selected or combined from a group of fluorinated gases including SF6, NF3. With CF4. If a noble metal such as ruthenium (Ru) or platinum (Pt) is used as the conductive layer 29 to form the lower electrode, 02 gas and Cl2 gas are separately selected or combined and used as an etching gas for the chemistry of the plasma comprehensive etchback process. Etching process. When performing a plasma full etchback process using a ruthenium-based material, one of tungsten and a noble metal, in addition to the etching gas described above for the chemical etching process, an inert gas is used as an etching gas for the physical etching process, and , an inert gas alone or from a group including Ar, Xe and He is used to stabilize the plasma, control the amount of selected gases and dilute the main hungry gas, if the chemical hungry characteristics -16 - 1278035 because of the above etching gas The use of a chemical etching process is dominant, one of which is either a passivation medium or a reaction inhibitor to suppress chemical etching characteristics. An example of a plasma etching apparatus for a plasma full etchback process is an inductively coupled plasma (ICP) etching apparatus, an electron cyclotron resonance (ECR) etching apparatus, a microwave etching apparatus, and a capacitive coupling plasma etching. Process. The percentage of the composition of the etching gas, the source power, the bias power, the pressure and temperature of the top electrode, and the bottom electrode is adjusted to control an etched configuration of the substrate structure, which is formed on the outside of the opening 28 in the isolation of the lower electrode . Fig. 2C shows that the aforementioned lower electrode 29A is formed by the electrode isolation process as illustrated in Fig. 2B, where the lower electrode 29A is of a cylindrical type. Referring to Fig. 2D, a wet dip-out process is performed to remove the insulating layer 27, whereby the wet leaching process, the cylindrical lower electrode 29A is exposed. According to a preferred embodiment of the present invention, the plasma full etch back process allows it to isolate the lower electrode without creating a punch in the bottom portion of the lower electrode, even in the absence of a supplemental layer. Providing the effect of avoiding a single bit failure #, resulting in an increase in the output of semiconductor components. Moreover, since the etching process recipe is adjusted when the plasma uranium engraving apparatus is generally used, there is no cost-related burden for setting up a new device to form a capacitor, and the physical etching process has the characteristics of vertical directionality and chemistry. The etch process has an isotropic etch feature that provides an additional improvement in etch uniformity. The present invention includes a subject relating to Korean Patent Application No. KR 2004-002206 1 and 2 00 5 -00 1 8 7 5 6, which are separately applied to the Korean Patent Office on March 31, 2004 and March 7, 12,780,835. , the entire contents of which are incorporated herein by reference. While the present invention has been described with respect to the preferred embodiments, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the spirit and scope of the invention as defined in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present invention will become better understood from the following description of the preferred embodiments of the accompanying drawings, wherein: FIG. 1A to FIG. The conventional method uses a plasma full etch back process for isolating the lower electrode; and FIGS. 2A through 2D are cross-sectional areas illustrating a method for fabricating a semiconductor device in accordance with a preferred embodiment of the present invention. [Main component symbol description] 19 polycrystalline sand layer - 19A, 29A lower electrode 1, 1, 2 1 substrate _ 12, 22 junction area 13, 23 interlayer insulation layer 14, 2 4 storage node contact hole 15, 25 storage node contact socket 16,2 6 etch barrier layer 17,27 insulation layer 1,28 opening 29 conductive layer -18-

Claims (1)

1278035 第94 1 1 02 8 5號「一種製造半導體元件之方法」專利案 (2006年5月修正） 十、申請專利範圍： 1. 一種製造半導體元件之方法，其包含： 在基板上形成具有複數個開口的一絕緣層，以形成多個 下電極； 在該絕緣層上形成一導電層；與 以較形成於開口內之導電層之第二部分更快的蝕刻速 率進行触刻形成於開口外之導電層第一部分，如此獲得相 互隔離之多個下電極。 2. 如申請專利範圍第1項之方法，其中該鈾刻步驟使用一混 合氣體，包括一第一氣體，其大體上垂直於基板之方向而 被引入以誘發物理性蝕刻與一第二氣體，其在電漿相對該 導電層反應而誘發化學性蝕刻。3 .如申請專利範圍第2項 之方法，其中該第一氣體之量等於該第二氣體之量。 4.如申請專利範圍第2項之方法，其中該第一氣體之量小於 該第二氣體之量。 5 .如申請專利範圍第3項之方法，其中該第二氣體之數量百 分比係在約1 %至約5 0 %的範圍內。 6.如申請專利範圍第4項之方法，其中該第二氣體之数量百 分比係在約1 %至約5 0 %的範圍內。 7 ·如申請專利範圍第2項之方法，其中該混合氣體包含氧 氣、氮氣以及氧氣跟氮氣混合氣體之其中之一。 8 .如申請專利範圍第1項之方法，其中該蝕刻步驟包含調整 1278035 一偏壓功率，使得發生於各開口之內底部的物理性蝕刻少 於發生於各開口之外部者。 9 .如申請專利範圍第8項之方法，其中該偏壓功率係被調整 至約3 0 W至約3 0 0 W的範圍內。 10.如申請專利範圍第2項之方法，其中當該導電層包含TiN 時，該第一氣體與該第二氣體分別爲一惰性氣體與一氯基 氣體。 1 1 .如申請專利範圍第1 0項之方法，其中該氯基氣體係選自 由Cl2、HC1、CC14及該等氣體組合物所組成之群體中之一 者。 12·如申請專利範圍第2項之方法，其中當該導電層包括一矽 基材料時，該第一氣體爲一惰性氣體；且該第二氣體係選 自由氟基氣體、氯基氣體、溴基氣體與該等氣體組合物所 組成之群體中之一者。 1 3 ·如申請專利範圍第1 2項之方法，其中該氟基氣體包括 SF6、NF3及CF4，且該氯基氣體及該溴基氣體分別爲Cl2 氣體及HBr氣體。 1 4 ·如申請專利範圍第2項之方法，其中當該導電層包含鎢 時’該第一氣體和第二氣體分別爲一惰性氣體及一氟基氣 两曲 體。 1 5 ·如申請專利範圍第1 4項之方法，其中該氟基氣體係選自 由SF6、NF3、CF4與該等氣體組合物所組成之群體之中之 一者。 1 6 .如申請專利範圍第2項之方法，其中當該導電層包含一以 1278035 貴金屬基之材料時，該第一氣體爲一惰性氣體；且該第二 氣體係選自由〇2氣體、C12氣體與該等氣體組合物所組成 之一群體中之一者。 1 7 ·如申請專利範圍第1項之方法，其中該蝕刻步驟採用一電 漿全面回蝕製程。 1 8.如申請專利範圍第1項之方法，其中該蝕刻步驟，係使用 一混合氣體，包括一第一氣體，其大體上垂直於基板之方 向而被引入以誘發物理性蝕刻，與一第二氣體，其在電漿 ® 相對該導電層反應而誘發化學性蝕刻，且調整一偏壓功 率，使得發生於各開口之內底部的物理性蝕刻少於發生於 各開口之外部者。 1 9 ·如申請專利範圍第1 8項之方法，其中該第一氣體之量等 - 於該第二氣體之量。 .2 0 .如申請專利範圍第1 8項之方法，其中該第一氣體之量少 於該第二氣體之量。 21.如申請專利範圍第19項之方法，其中該第二氣體之數量 B 百分比的範圍爲約1%至約50%。 2 2.如申請專利範圍第20項之方法，其中該第二氣體之數量 百分比的範圍爲約1%至約50%。 2 3.如申請專利範圍第18項之方法，其中該混合氣體係被添 力口 〇2氣體、N2氣體及02氣體和N2氣體之混合氣體之一 者。 24.如申請專利範圍第18項之方法，其中該偏壓功率被調整 至約3 0 W至約3 0 0 W的範圍中。1278035 No. 94 1 1 02 8 5 "A method for manufacturing semiconductor components" Patent (amended in May 2006) X. Patent application scope: 1. A method for manufacturing a semiconductor device, comprising: forming a plurality on a substrate An insulating layer of the opening to form a plurality of lower electrodes; forming a conductive layer on the insulating layer; and forming a contact at a faster etching rate than a second portion of the conductive layer formed in the opening The first portion of the conductive layer is such that a plurality of lower electrodes are isolated from each other. 2. The method of claim 1, wherein the uranium engraving step uses a mixed gas comprising a first gas that is introduced substantially perpendicular to the direction of the substrate to induce physical etching and a second gas, It induces a chemical etch in the plasma reacting with the conductive layer. 3. The method of claim 2, wherein the amount of the first gas is equal to the amount of the second gas. 4. The method of claim 2, wherein the amount of the first gas is less than the amount of the second gas. 5. The method of claim 3, wherein the amount of the second gas is in the range of from about 1% to about 50%. 6. The method of claim 4, wherein the amount of the second gas is in the range of from about 1% to about 50%. 7. The method of claim 2, wherein the mixed gas comprises one of oxygen, nitrogen, and a mixed gas of oxygen and nitrogen. 8. The method of claim 1, wherein the etching step comprises adjusting 1278035 a bias power such that physical etching occurring at the bottom of each opening is less than occurring outside of each opening. 9. The method of claim 8, wherein the bias power is adjusted to a range of from about 30 W to about 300 W. 10. The method of claim 2, wherein when the conductive layer comprises TiN, the first gas and the second gas are an inert gas and a chlorine-based gas, respectively. The method of claim 10, wherein the chlorine-based gas system is selected from the group consisting of Cl2, HC1, CC14, and the gas compositions. 12. The method of claim 2, wherein when the conductive layer comprises a ruthenium-based material, the first gas is an inert gas; and the second gas system is selected from the group consisting of a fluorine-based gas, a chlorine-based gas, and a bromine One of a group of base gases and such gas compositions. The method of claim 12, wherein the fluorine-based gas comprises SF6, NF3, and CF4, and the chlorine-based gas and the bromine-based gas are Cl2 gas and HBr gas, respectively. The method of claim 2, wherein when the conductive layer comprises tungsten, the first gas and the second gas are respectively an inert gas and a fluorine-based gas two-curve. The method of claim 14, wherein the fluorine-based gas system is selected from the group consisting of SF6, NF3, CF4 and the gas compositions. The method of claim 2, wherein when the conductive layer comprises a material of 1278035 precious metal base, the first gas is an inert gas; and the second gas system is selected from the group consisting of 〇2 gas, C12 One of a group of gases and such gas compositions. 1 7 The method of claim 1, wherein the etching step employs a plasma full etch back process. The method of claim 1, wherein the etching step uses a mixed gas comprising a first gas which is introduced substantially perpendicular to the direction of the substrate to induce physical etching, A second gas that induces a chemical etch in the plasma® to react with the conductive layer and adjusts a bias power such that a physical etch that occurs within the bottom of each opening is less than occurs outside of each opening. The method of claim 18, wherein the amount of the first gas is equal to the amount of the second gas. The method of claim 18, wherein the amount of the first gas is less than the amount of the second gas. 21. The method of claim 19, wherein the percentage B of the second gas ranges from about 1% to about 50%. 2. The method of claim 20, wherein the percentage of the second gas ranges from about 1% to about 50%. 2. The method of claim 18, wherein the mixed gas system is added to one of a gas of 〇2, an N2 gas, and a mixed gas of 02 gas and N2 gas. 24. The method of claim 18, wherein the bias power is adjusted to a range of from about 30 W to about 300 W.
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