TWI277852B - A switching control circuit for controlling output current at the primary side of a power converter - Google Patents

Abstract

A switching control circuit controlling output current at the primary side of a power converter is provided. A waveform detector generates a current-waveform signal. A discharge-time detector detects a discharge-time of a secondary side switching current. An oscillator generates an oscillation signal for determining the switching frequency of the switching signal. An integrator generates an integrated signal by integrating an average current signal with the discharge-time. The average current signal is generated in response to the current-waveform signal. The time constant of the integrator is correlated with the switching period of the switching signal, therefore the integrated signal is proportional to the output current. An error amplifier amplifies the integrated signal and provides a loop gain for output current control. A comparator controls the pulse width of the switching signal in reference to the output of the error amplifier. Therefore, the output current of the power converter can be regulated.

Description

1277852 IX. Description of the Invention: [Technical Field] The present invention relates to a switching control device, and more particularly to a switching control device applied to a power supply. [Prior Art] A power supply wire which can provide a stable voltage and current has been widely used in each (four) sub-device. Based on safety regulations (safe_requirement, the off-line power supply (0ff-line p〇wer c〇nverter) must provide galvanic isolation between its primary and secondary sides. In many chargers In the relevant application fields, the requirements for constant current curve and low cost are very high. In the current disclosed technology, the control of the power supply can not be accurately controlled on the secondary side of the power supply. The current is due to the (10) normalized constant current curve. In addition, in order to achieve the above-mentioned constant current curve, the paste must be increased to achieve a constant current, and the cost must be increased. Therefore, if the power supply is properly controlled# 10 π Problem. (10) U and cost reduction are quite important. [Summary of the invention] The library uses the above purpose. The present invention proposes a switching control device applied to a power supply. M ^ _ human side, used to control the output of the power supply H _ changeable control (four) set-to-cut controller system can generate a switching heart -, (4) switching type ^, the switching signal can be switched The voltage regulator and 6 1277852 stably adjust the output of the electric county. The switching controller includes - the amplifier and the - reference voltage set - the error amplifier, the system, the - comparator combination - the pulse width modulator, The pulse width of the switching signal is controlled according to the wheel of the error amplifier.

The switching control device further comprises a eliminator, wherein the oscillating device generates a slit signal for determining the switching frequency of the switching signal; the waveform Detector uses the sampling once (four) to change the current signal to use the domain-current waveform Signal; - Discharge time thief is connected to the transformer to detect a discharge time of the secondary side switching current '- integral purely by the integral - average current signal and the discharge time for generating an integral signal. The fresh average current _ is the average value of the electric money signal and the inter-integrator (four) constant is proportional to the switching period of the switching signal. Therefore, the impurity signal is proportional to the output electric current of the power supply wire. The 2-minute signal is connected to the input terminal of the error amplifier, and the switching controller can adjust the output current according to the integral signal. More than one overview and the following detailed descriptions are exemplary in nature, and are intended to be a step-by-step description of this issue. (4) The other purposes and the point of inflammation will be explained in the following explanations and illustrations. [Embodiment] 翏^―图, which is set to the power supply for the Japanese-style change-controlled woven fabric. The power supply includes a transformer 1 〇, a transformer] auxiliary winding NA, a secondary winding Np, and a secondary side winding power supply _. Switching control with the output current V: 2: 7 1277852 The switching signal VPWM is generated through the switching transistor 20 for switching the converter 10. The switch controller 70 includes a supply terminal VCC and a power detection terminal.

• VDET, ground terminal gnd, current detection terminal vs. output VPWM. The output VPWM outputs the switching signal VPWM. The voltage detecting terminal VDET is connected to the auxiliary winding NA through the resistor 50 for detecting the reflected voltage VAUX, and the reflected voltage VAUX is further charged to the capacitor through the rectifier to supply energy to the switching controller 70. The current detecting end VS is connected to the current detecting resistor 30, and the current detecting resistor 30 is connected from the source of the transistor 20 to the ground to convert the primary side switching current 1? into the primary side switching current signal VIP. . For the first figure, please refer to the second figure, which is the signal waveform of each point in the discontinuous conduction mode for the power supply of the first figure. The above discontinuous conduction mode means that the energy storage of the transformer is completely released before the start of the next switching cycle. When the switching signal Vpwm transitions to the high level, a side switching current Ip is generated. The peak value IpA of the primary side switching current Ip can be expressed as:

Ipa =,xTon ...................................

Lp (1) where VIN is the input voltage of transformer 10; Lp is the inductance of the primary side of transformer 1〇 • group NP; T0N is the conduction time of switching signal VpwM. - When the switching signal VpwMT drops to the low level, the energy stored in the transformer 1〇 will be released to the secondary side of (4) $1G, and the amount of transmission through the rectifier 4() can be 8 1277852 to the power supply: The output. Peak value of secondary side switching current Is

Isa can T (V〇+ VF) ISA = U^XT_ ....................................... (2) where V〇 is the output of the power supply, VF is in the forward compression across the rectifier 40, and Ls is the inductance of the secondary winding Ns of the transformer. The value ·' Tdsd is the discharge time of the one-side switching current Is in the discontinuous conduction mode. When the signal VPWA is switched, 卩夂..., + to the low level, the auxiliary winding of the transformer 1〇, and na will generate the reflected voltage v

Tna Aux. The reflected voltage VAUX can be expressed as:

Vaux = ~~—X(V〇+ Vf)------ I NS """ one-face-face job _____ (3) where TNA and TNS stand for 懕 and & The number of turns of the auxiliary winding NA of 10 and the secondary side winding Ns. When the secondary side switching current Is drops to zero, the reflected voltage V峨 will begin to decrease. At this time, the energy storage of the transformer 1G will be completely released. The discharge time of equation (2) can be measured from the falling edge of the switching signal % to the falling point of the reflected power VAUX. Referring to the second figure, the power supply of the first diagram is operated as a waveform diagram of each point in the continuous conduction mode. The above continuous conduction mode = the dragon energy storage energy is not completely released before the start of the next-her___. When the power supply is operating in continuous conduction mode, —

The peak value of I (ΡΕΑΚ) is ··

Ip(peak) = Ipa + Ipb (4) 9 1277852 T VlN Ιρα =-x Ion Lp _...(3) where IPB is expressed as the energy stored in the transformer. When the switching signal vPWM drops to a low level, the transformer ι is transmitted to the secondary side of the transformer K). Therefore, the secondary side field current Is can be determined by the sub-cutting L transformer 1G shouting group. The peak value IypEAjg of the = side switching current Is can be expressed as:

Is(PEAK)=^xIP(PEAK)=I^x(IpA + IpB)

Tns

Tns (6) where TNP is the resistance of the transformer, 1 〇 _ secondary winding & Referring to the fourth figure, a preferred embodiment of the switching control device of the present invention is shown. A waveform system II 3GG # is sampled - the secondary side switching current signal % is used to generate current waveform signals Va and Vb. The discharge time detector surveys the auxiliary winding Na through the transformer 10 to measure the discharge time Tdsd/Tdsc of the secondary side switching current is. The oscillating unit 200 generates an oscillating signal pLS for determining the slice rate of the switching signal VPWM. The integrator generates the integral signal Vx by integrating the average current signal and discharging the TDSD/TDSe wire. When considering the non-continuous (4) and even (4) it mode, the current waveform signals νΑ and VB are used to generate the oblique average current signal. The time constant of the integrator 5 (8) is proportional to the switching period of the switching signal VPWM, and the integral signal Vx is proportional to the output current of the power supply. The switching control H includes an operational amplifier A' § 71 and a reference voltage V to form an output amplification control to achieve output current control. The comparator 75 is combined with the pulse 1277852 wide modulation circuit _, according to the wheel (4) of the error amplifier to control the pulse width of the switching signal vPWM. Lai New cuts the integral signal % and provides loop gain for output current control. For example, 贞__ secondary side switching current ^ to modulation this switching signal vPWM·wave width - the way (four) into a current control loop. The current control loop is used to control the amplitude value of the primary side switching current 1? according to the reference voltage v. The relationship between the secondary side switching current ^ and the primary side switching current Ip is as shown in equation (6). Please refer to the waveform diagram shown in Figure 2 and the second diagram. The output current 1〇 of the power supply and read supply is the average value of the one-side switching current Is. Therefore, the output current of the emperor τ π main-A · % / original 仏 〇 can be expressed as: 10 plus soap) + (1. order - .............. ...... where TDS is expressed as w under discontinuous conduction mode. Therefore, the wheel, DSD or continuous conduction mode of the electric secret device switches the input current signal vIP at one time. Waveform detector 300 __ + Two sides

And produces electric seams _ vA and vB. # , %流流VlP Equation (7) to design: I minus ^ can be n as shown below vx = (vB+Zi^Xi)xI^ 2 Τι where (8)

Tns ^ ,τ

Va =-x Rs x (Isa + Isb) _

Tnp (9) - (10) !277852 Τνρ xRsxIsb· where Α is the time constant of the integrator 500. τ Tns :— X---- Τι Τνρ With reference to equation (7)(10), the integral signal Vx can be integrated into:

Vx=—x^xRsxfo T Tns .........................................( Π) It can be known that the integral signal Vx is proportional to the power supply current V when the output current! . When increasing, the integral signal Vx increases. However, = over current control _ road stability, the most recorded score signal Vx is subject to inflammation test. Under the feedback control of the current control loop, the maximum wheel current I 〇 (MAX) is expressed as: I 〇 (MAX) = — X — GaxGswX VR1 Tns Rs κ} 1 + (Ga x Gsw x ...... ............................(12) where K is a constant (four) to Ti/T; Vri is the voltage of the reference voltage v_ A is the sum of the differential amplification 3; Gsw is the gain of the switching circuit. If the loop gain of the current control loop is higher than the X GW» ^, the maximum output current icHMAX} can be expressed as: I〇(MAX) = KXX - -------

Tns Rs _____________(13) The large-capacity current I〇_) of the private source should be adjusted to a fixed current according to the magnitude of the reference voltage. The voltage V is turned on. The correspondence with the output current 1〇 can be seen through the schematic diagram shown in the fifth figure. . . In the preferred embodiment of the present invention, the pulse width modulation -400 packet 3 D type positive and negative benefit 95, the inverter %, the gate and the ship ρ 12 1277852 gate 92 are generated for the switching signal I. The input (D) of the D-type flip-flop 95 is supplied by the supply voltage Vcc. The oscillation signal PLS is configured to set the D-type flip-flop 95 through the inverter 93. The output terminal (Q) of the D-type flip-flop 95 is connected to the first wheel-in terminal of the AND gate 92. The second input of the AND gate 92 is coupled to the output of the inverter 93. The output of the gate % is also the output of the switching signal VpwM wide modulator _. The D-type flip-flop 95 is reset according to the round-out end of the AND gate 91. The first input end of the AND gate 91 receives the voltage loop signal %, and the voltage loop signal Sv is generated by the voltage control loop. Control ^ circuit system is used to stably adjust the power supply (4) output 赖V. . The current loop signal S! is generated by the output of the comparator 75 and simultaneously output to the And gate 91 ^ second input terminal for output current control. The positive terminal of the comparator 75 is connected to the output of the operational amplifier S71, and the terminal of the comparator 75 is connected to the oscillator 200' by the ramp signal RMp. The voltage loop signal, with the current loop 峨Sl can reset the D-type flip-flop 95, (4) limit and ^ integral " switching signal VPWM slit width ' (four) also reach the prison Xi as voltage = with the output current 1 〇. Private 〇 Referring to Figure 6 is a schematic diagram of a waveform detector of a preferred embodiment of the present invention. The positive terminal of the first comparator 310 is connected to the current detecting terminal % for receiving the under-side switching current (four)-the secondary side switching current signal %, and the negative terminal thereof is connected to the first capacitor 321 , the first capacitor 321 can maintain the peak value of the secondary side switching current signal vIP. The first constant current source 3〇5 charges the first capacitor milk 13 1277852. The first switch 311 is connected between the first constant current source 3〇5 and the first capacitor 321 . The output of the first comparator, 310, is used to turn the first switch on or off. When the first switch is turned on, the first constant current source 3 〇 5 is used to charge the first capacitor 321 , and the peak voltage signal VSP is waited across the first capacitor 321 . In conjunction with the third graph, the peak voltage signal v is proportional to the sum current of IpA plus IPB. The first transistor 3〇8 is connected in parallel with the first-electrode 321 to discharge the first capacitor 321. Switch 312 is used to periodically sample peak voltage signal VSP from first capacitor 321 to third capacitor 322. Then, a slope current waveform signal VA is obtained across the third capacitor 322. A switch 314 is connected between the current detecting terminal vs and the second capacitor 324. The second capacitor 324 is used to maintain the initial value of the primary side switching current signal Vip. A voltage signal Vsi is obtained across the second capacitor 324. In conjunction with the third figure, the initial value of the turtle pressure nickname VSI is proportional to the current value of the current ιΡΒ. The second transistor is coupled in parallel with the second capacitor 324 for discharging the second capacitor 324. The switch 315 is for periodically sampling the initial voltage signal VSI from the second capacitor 324 to the fourth capacitor 325. Then, an offset current waveform signal VB is obtained across the fourth capacitor 325. Referring to the sixth diagram, the inverter 351, the current source 352, the transistor 353, the capacitor 354, and the AND gate 355 constitute a first time delay circuit. The inverter 361, the current source 362, the transistor 363, the capacitor 364, the AND gate 365, and the inverter 366 14 1277852 constitute a first-shot trigger signal generator for outputting the storage signal STR, and the storage signal STR is a single Sub-trigger signal. The input of the first time delay circuit is provided by the switching signal VPWM. The current J352 of current source 352 and the capacitance of capacitor 354 determine the delay time of the first time delay circuit. The output of the first time delay circuit is coupled to the input of the first one shot signal generator. The current of the current source 362 - the capacitance of the capacitor 364 determines the pulse width of the stored signal str. The storage signal STR controls the second switch 314 to sample the initial value of the primary side switching current signal VIP. Therefore, the rising edge of the delayed switching signal is used to generate the stored signal STR. After the delay time, a delayed switching signal is generated according to the rising edge of the switching signal VPWM. The delay time is added to avoid interference from switching surges. Referring to the seventh figure, a schematic diagram of an integrator of a preferred embodiment of the present invention is shown. The first timing amplifier 51 〇, the first timing resistor 511 and the first timing transistor 512 form a first voltage to current converter, and the first programmable current 1512 is generated according to the offset current waveform signal vB. The transistors 514, 515 and 519 form a first current mirror, by mapping the first planable current - for generating current and current. The transistors M6 and 5Π form a second current mirror, which is used to generate a current In? by mapping the current Iw. The second timing operational amplifier 53A, the second timing resistor 531 and the second timing transistor 532 form a second voltage to current converter for generating a second programmable current bn according to the slope current waveform signal Va. The electric crystals 534 and 535 form a third current mirror for generating a current Is5 by mapping a second programmable current & 15 1277852. The transistors 536 and 537 form a fourth current mirror for generating a current I537 based on the current I535 and the current 1^7. The current [Μ7 can be expressed as 1537 = 1535 - 1517 0 • The geometry of the transistor 536 is twice that of the transistor 537. Therefore, the current of current I536 is twice that of current I537. The transistor and 539 form a fifth current mirror, which is used to generate a current "Μ" by mapping the current 1 „7. The drain of transistor 519 is interconnected with transistor 539 by summing the current he and current • 1539 to produce an average current signal I·. Average current signal | Tiger Iavg can represent 1 as:

Iavg=-^- + -^~... R511 2 幽·一·•诵(14) The first-time resistor 5n, the second timing resistor 531 and the chronograph capacitor 57 determine the integrator 5〇〇 The time constant 'the second timing resistor 531 is proportional to the first timing power in accordance with the 511 system. When the resistance of the second timing resistor 531 is set = equal to the resistance value of the first-time resistor 511, the equation (14) can be heavy, τ 1 Va - Vb 八·

Iavg = x (Vb -\------------------- Han 511 2 — — — — — — — — (1_5) The fifth switch 550 is connected to the Thunder Office ς Wen Wang Bao 日 Japanese body 519 between the bungee and the timing of the electricity. Switch 550 conduction only in the secondary side switching current 1 § discharge tds period. The third transistor 56G is connected with the chronograph capacitor 57Q, the test The timing capacitor 570 is discharged. The sixth switch +, the switch 551 is used to provide a periodic sampling across the timing capacitor 570 to the wheel discharge | 'six% valley 571 voltage. Integral signal Vx. 16 1277852

Vx R511C570 A/ , Va-Vb, ^ (Vb + ---) x Tds-------- 2 (16) ^ The eighth figure is a schematic diagram of an oscillator according to a preferred embodiment of the present invention. The oscillating operational amplifier 2 (Π, oscillating electric and vibrating crystal) constitutes a third voltage-to-current converter. The third voltage-to-current converter is used to generate a reference current w according to the reference voltage v 个 a slit transistor 25^ n

The 254 and 255 form a current mirror, which is used to generate a recharge charging current ι 253 and a repelling money l255 according to the reference current l25 。. The drain of the transistor 253 generates a woven charge current I253, and the drain of the transistor 255 generates an oscillating discharge current by. The first oscillating switch 230 is connected between the drain of the transistor 253 and the oscillating capacitor 215. The second oscillation switch 231 is connected between the drain of the transistor 255 and the oscillating capacitor 215 across the oscillating capacitor 215 to obtain a ramp signal RMp. The normalization of the oscillating comparator 5 is connected to the squeezing capacitor 215, and the output of the oscillating comparator 205 generates a oscillating number PLS 'Violation signal pls determines the switching frequency, and can turn on or off the switches 312, 315 and sixth Switch 551. The first end of the third oscillation switch 232 is provided by a high threshold voltage VH, and the first creep of the fourth oscillation switch 233 is provided by the low threshold voltage vL. The second end of the third oscillation switch 232 ", the second end of the fourth oscillation switch 233 is commonly connected to the negative end of the oscillation comparator 2〇5. The input of the oscillating inverter 260 is coupled to the wheel terminal of the oscillating comparator 2 〇 5 for generating an inverted oscillating signal / PLS. The oscillation signal PLS is used to turn on or off the second oscillation switch 231 and the fourth oscillation switch 233. The inverted oscillation signal /PLs is used to turn on or off the first oscillation switch 230 and the third oscillation switch 232. 17 1277852 The inverters 261, 262, 263 and 264 are connected to each other in series. The input of the first inverter 26i is provided by the vibration number PLS. The output of the AND gate 270 produces a clear signal CLR whose first input is connected to the output of the inverter 264 and whose second input is connected to the output of the - inverter 261. The clear signal (10) is used to turn on or wear the first transistor 308, the second transistor 3〇9 and the third transistor 560. The resistance of the oscillating resistor 210 and the oscillating capacitor 215 determine the switching period T of the switching signal VPWM. (17) VREF2/R210 VREF2 where Vosc = VH_VL, C2 is 5 is the capacitance value of the oscillation capacitor 215. Referring to the ninth diagram, it is a schematic diagram of the discharge time extractor of the preferred embodiment of the present invention. The first zero point detection inverter 15 电, transistor 丨 ★ one brother one zero point detection

The current source 120, the first zero point detection capacitor 121 盥 first 0曰, the music point detection AND gate 155 constitutes a second time delay circuit, and the input end of the second time delay circuit is provided by the switching signal vPWM. The second time delay u. ^ provides a transmission delay for the falling edge of the switching signal VpWM. The current zero of the first zero point Uo and the power of the first zero point detecting capacitor 121 determine the delay of the transmission delay. The inverter 151, the inverter 152, the transistor ^ ά, Ο, the second zero detection constant current source 123, the second zero detection capacitance 124 and the _th, the heart AND gate 156 form a second single time A trigger signal generator for generating a sample signal SMP. The second single-trigger signal generator is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The 20th point price measures the pulse width of the current source 123 and the pulse width of the electric valley value voltage sampling signal of the second zero point. The zero-point detection operational amplifier 101 operates like a buffer amplifier, and its negative terminal and the output terminal are connected to each other. The positive terminal is also the input terminal of the buffer amplifier, and is connected to the voltage detecting terminal VDET. The voltage measuring terminal vdet is connected to the auxiliary winding Na of the transformer 透过 through the resistor 5 , to detect the reflected voltage %. The sampling switch (10) is connected between the end of the stagnation (4) and the county ΐ ΐ2. The voltage sampling signal is used to control the on or off of the sampling switch. Therefore, the sampling action of the reflected voltage vAUX is like the voltage V. The voltage V is maintained across the sampling capacitor (1) 2. — Zero side comparator 1G5剌 detects the decrease in pressure Vaux. The zero point is connected to the positive end of the request to the valley 112. The reference cable threshold 1〇6 is connected to the zero point to determine the negative end of the comparator and the knowledge of the buffer amplifier to provide a threshold for detecting the decrease in V·. Therefore, when the amount of decrease in the reflected electric power V· is greater than = test = critical value, the zero-side comparator (10) will produce a high level. The input end of the second second 1 inverter 115 is provided by the switching signal ν· provided by the input terminal of the object 116 _ sampling signal gang, the shame zero point AND 119 of the first input end Connect to the zero point to become the output of the I-#105. ^ 31 positive and negative is 117 and the second erroneous flip-flop 118 has a ''rising edge touch (four) end and a high level trigger reset input, respectively. Second 19 1277852

The set terminal (8) of the SR type positive and negative 11 118 is connected to the fifth zero point _ inverter 116 of the turn-out terminal 'the reset end (8) is provided by the switching signal VPWM, and its output terminal (, connected to the third zero point) Detecting the second input of the gate 119. The input (4) (9) of the first feedback 117 is connected to the first input of the fourth _ side gate 114. The second input of the fourth zero side 141 The terminal is connected to the output end of the fourth zero-point detecting inverter i 15. The output end of the fourth zero-detecting layer gate i 产生 generates a discharging time signal Sds. The setting end (8) of the first-SR type flip-flop m is also Connected to the output of the fourth zero-point detecting inverter 115, the reset terminal W is connected to the output terminal of the third zero-point side AND gate 119. The discharging time is on the SDJ pass-through or off-off 55G. The pulse width of the SDS is proportional to the discharge time of the secondary side switching current Is. 'The fourth figure, the sixth figure and the first figure' integral signal % and the secondary side switching current Is and the output of the power supply The current 1〇 is proportional to the relationship. Therefore, equation (11) can be rewritten as: V Tns (18)

Vx = mx xRsxI〇_

Inp where m is a constant, which can be expressed as 1X1 = R210 X C215 Vosc R511 X C570 VREF2 ""~ **-(19) The resistance value of the first-time resistor 511 is equal to the resistance value of the oscillating resistor 21〇. A proportional relationship. The capacitance value of the timing capacitor 57 ― is proportional to the capacitance value C215 of the oscillation capacitor 215. Therefore, the integral signal % is proportional to the output current of the power supply 1〇. 20 1277852 The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; that is, the equivalent variations and modifications made by the scope of the present invention are the scope of the present invention. Covered.

21 [Simple description of the diagram] The figure shows that the switch-type control device of the present invention is installed on the power supply shore, and the second picture is the first m-m privilege, which should be unbearable, and the signal waveform of each point; The first ~_ power supply ϋ operation in the connected tiger waveform; •, the power supply operation in the discontinuous conduction mode in the continuous conduction mode

Figure 4 is a schematic diagram of a switchable control device of the preferred embodiment of the present invention; the figure is a curve showing the correspondence between the output 4V〇 and the output current I. The sixth figure is a schematic diagram of the waveform soot according to the preferred embodiment of the present invention. 7 is a schematic diagram of an integrator according to a preferred embodiment of the present invention; FIG. 8 is a schematic diagram of an oscillator according to a preferred embodiment of the present invention; and a ninth diagram is a schematic diagram of a discharge time detector according to a preferred embodiment of the present invention. [Main component symbol description]

Transformer: 10 transistors · 20, 122, 125, 250, 251, 252, 253, 254, 255, 308, 309, 353, 363, 512, 519, 532, 534, 535, 536, 537, 538, 539 , 560 current detection resistance: 30 rectifier: 40 resistance · · 50, 210, 511, 531 rectifier: 60 22 1277852 capacitance: 65, 112, 121, 124, 215, 354, 570, 571 switching control device: 70 operation Amplifier: 71. Comparator: 75, 105, 205, 310 AND Gate: 9 Bu 92, 114, 119, 155, 156, 270, 355, 365 Inverter: 93, 115, 116, 150, 15 Bu 152, 260, 26 262, 263, 264, 351, 361, 366 • D-type flip-flops · 95 Discharge time detector: 100 Reference voltage: 106 SR type flip-flop: 1 Π, 118 oscillator · · 200 operation Amplifier: 101, 201 Waveform Detector: 300 ® Constant Current Source: 120, 123, 124, 305, 352, 362 Switch: 109, 230, 23 Bu 232, 233, 3U, 312, 314, 315, 550, 551 Capacitance: 321, 322, 324, 325, 364 Pulse Width Modulation Circuit: 400 ' Integrator: 500 First Timing Amplifier: 510 23

Claims (1)

1277852 X. Patent Application Scope 1. A switching control device is applied to the primary side of a transformer of a power supply to control an output current, including: - Waveform fine n 'Transmission-T flow detection component Sampling the primary side switching current of the transformer for generating a current waveform $峨; a discharge time detector connected to the transformer for detecting a discharge time of the secondary side switching current of the transformer; ^ - integrator Connected to the waveform _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The switching signal is generated by the switching signal (4), and the output current of the power supply is stably adjusted according to the reference voltage. Heart 2. If you apply for the switch-controlled control of the FFI 丨 丨 item, the needle width controller includes: - Operational amplification H 'Connect the integral II 'Receive the integral woven and _ reference voltage' to enlarge the Integral signal; and - comparator, connected to the operational amplifier and the "pulse width relay circuit, according to the amplified integral signal, through the pulse width of the pulse width of the woman's pulse and '镰 考 考 敎 敎 敎 赖 赖 赖 赖 供应 供应^ Output current. Λ 3· If you apply for the switched control device described in item 1 above, the step includes an oscillator connected to the waveform _, the integrator and the switching controller for generating an oscillating signal at 24 1277852. To determine the switching frequency of the switching signal. 4. The switching control device of claim 1, wherein a time constant of the integrator is proportional to a switching period of the switching signal. 5. The switching control device of claim 1, wherein the waveform detector comprises: a first comparator that obtains a primary side switching current signal of the transformer from its positive terminal and a negative terminal connection thereof a first capacitor for maintaining the peak value of the primary side switching current signal of the transformer, and outputting a control at the output end thereof to control whether the first switch is turned on or off. The value of the primary side switching current signal of the transformer is proportional to the primary side switching. a value of the current; a first constant current source, the first capacitor is charged through the first switch; a first transistor connected in parallel to the first capacitor for discharging the first capacitor; Capacitor, obtaining a primary side switching current signal of the transformer through a second switch, and maintaining an initial value of the primary side switching current signal of the transformer; the second switch is turned on or worn according to a stored signal; a second transistor, The second capacitor is connected in parallel to discharge the second capacitor; a third capacitor is periodically sampled across the third switch The voltage of the first capacitor is used to generate a slope current waveform signal; and a fourth capacitor is periodically sampled through a fourth switch across the m of the first to the second 25 1277852 to generate a bias Shift current waveform signal. The integrator package 6. The switching control device described in claim 1, wherein the first-electric current is difficult to turn, according to the current waveform, (4) generating - the first can supplement the electric power; The offset (10) waveform 峨 is used to generate a second programmable charging current; the slanting chronograph capacitor is transmitted through the fifth _ the _ the second _ domain is added to the affiliation - the average trait ^ % current and charging; children 'grass ring to make a line; electricity: transistor 'parallel connection of the timing capacitor ~ ^ ^ - wheel capacitance, through a sixth switch week series, used to generate the integration signal. Firstly, the capacitor is surrounded by the switch, and the oscillator is surrounded by the switching control device described in the third item, including: a three-electrical-to-current converter having a resistance and an oscillation having a vibration-magnification-magnification-current; The body/, medium-three voltage-to-current conversion ϋ generates a parametric current mirror, which has a first oscillating transistor, a first _ ̄ ̄, and a β 晶体 crystal plaque as a second, ^ ^ 一 振荡 电 电, And a transistor, wherein the third oscillating transistor generates __26 1277852 charging current; - a first oscillating current mirror having a fourth oscillating transistor and a _ fifth oscillating transistor, wherein the fifth slotted transistor generates - a squirting capacitor; x - oscillating capacitor, through - oscillating _ connected to the third transistor of the third tempering transistor 'connected to the second oscillating switch to the fifth oscillating transistor Bungee; - oscillation comparison H, its JL terminal is connected to the oscillating capacitor, the health _ Zhenbao signal is used to turn on or off the second oscillating switch; a second oscillating switch, a first end of which is connected to a high a threshold voltage, a second end connected to the negative terminal of the oscillation comparator; a fourth oscillating switch having a first end connected to a low threshold voltage and a second end connected to the negative end of the oscillating comparator controlled by the oscillating signal; an oscillating inverter having an input end Connected to the output of the oscillating comparator to generate an inverted oscillating signal for turning on or off the first oscillating switch and the third oscillating switch; a first inverter and a second inverter a third inverter is connected in series with a fourth inverter, wherein an input end of the first inverter is provided by the oscillation signal; and an AND gate is used to generate a clear signal, wherein the AND a first input end of the gate is connected to the wheel-out end of the fourth inverter, wherein a second wheel-in end of the AND gate is connected to a wheel-out end of the first inverter, wherein the clear signal is used to 27 1277852 The first transistor, the second transistor and the third transistor are turned on or off. According to the switching control relay described in the above-mentioned item, the discharge time detector includes There is: a delay circuit, Lin should switch the falling edge of the 峨Supply-transmission delay, wherein the time of the impurity delay is determined by the current of one of the first zero-point current sources and the capacitance of a first zero-point detection capacitor; the single-shot signal generator is connected to The delay circuit is configured to generate a voltage sampling signal according to the transmission delay, wherein the pulse width of the voltage sampling signal is detected by a second zero point of the internal current source and a second zero point detection The capacitance of the capacitor is determined; a zero-point detection operational amplifier whose positive terminal is connected to the auxiliary winding of the transformer for detecting a reflected voltage; a sampling capacitor 'connected to the zero detection operation through a sampling switch The output end of the amplifier is used to sample the reflected voltage according to the on or off of the sampling switch; the zero-point detection comparator has a positive terminal connected to the sampling capacitor, and a negative terminal connected to a zero point through a reference voltage threshold "[Measure the negative and output of the operational amplifier; a fourth zero detection inverted state] has an input is supplied by the switching signal; a fifth zero The measurement inversion is 'having an input terminal supplied by the voltage sampling signal 28 1277852; - a third zero detection detection room having a -first input terminal connected to the output of the zero detection comparator; a fourth zero Mi_AND gate for generating a discharge time signal, wherein the first input terminal between the fourth zero point detection AND is connected to the wheel output end of the fourth zero point detection inverter; The SR type flip-flop has an output connected to the first __2f private connection to the surface three zero detection __ output; the first SR type anti-theft thief's one set end rain (four) round The output terminal receives the switching signal: 1 = '_ Detects the second input between the 20 points detection AND. & ^Connect to 29