1277329 九、發明說明： I：發明戶斤屬之技術領域3 發明領域 本說明書所說明之各種實施例，一般係論及資訊處 5 理，諸如一些被用來處理資料，包括個別之資料元素和資 料封包，等之裝置、系統、和方法。 I：先前技術I 發明背景 Φ 處理元件之陣列，可達成大量與一般所認知之任務相 ίο 關的處理能力。然而，彼等個別元件之同步運作，可能會 引起不當之結果，包括浪費電力和可用資源之無效率使用。 V 【發明内容】 " 發明概要 本發明係為一種方法，其係包含下列步驟：響應於至 - 15 少一狀態指示符，而獨立地調整多個耦合至對應多個網路 ' 處理器之處理器時鐘。 ® 圖式簡單說明 第1圖係一依據各種實施例之裝置和系統的方塊圖； 第2圖係一可例示幾種依據各種實施例之方法的流程 20 圖；而 第3圖則係一依據各種實施例之產品的方塊圖。 L實施方式：i 較佳實施例之詳細說明 在某些實施例中，可基於需要（以使個別元件可非同步 1277329 地加以日寸控），藉由調整施加至對應之個別元件的時鐘頻率 ，而使多個處理元件運作，來處理資訊。在某些情況中， 此可能意謂一些在低於全载下運作之元件，係經選擇使在 一較其他元件為低之頻率下運作。在某些情況中，—此 —- 5法處理彼等分配之工作負荷的元件，可能會使彼等施加之 時鐘頻率增加。在某些實施例中，一些用來連接個別之處 理元件的路由器，可能會在一同步之方式中運作。此種處 理貧訊之解決方案，可能會造成電力利用率之降低，和可 用處理資源更公平之配置。 10 就此一文件而言，術語”能量導管”，可能包括任何類 型有能力來回於空間傳輸及/或接收能量之置或設備。此種 能量導管之範例，姑不論其他，係包括天線(例如，全向性 、定向性、指向性、接線式、單極式、偶極式、等等）、紅 外線發射器、紅外線接收器、紅外線收發器、光發射器（例 15如，光發射二極體）、光接收器（例如，光電池）、和電荷耦 合裝置。 ，網路處理器"，可能論及任一群組之兩個或以上的處 理7L件，彼等係互相連接而使能夠分享一共同來源所提供 之資Λ，及/或能夠傳送資訊給_共同之目的地，此處之共 20同來源或目的地，可能為一記憶體、網路、路由器、交換 杰、等等。在某些實施例中，彼等網路處理器，可使共同 位於曰曰粒和/或主機板上面。在某些實施例中，彼等網路 處理器，可能構成全球資訊網路之_部分。 一”狀態指示器”，可能意謂任何機構(例如，電路、物 1277329 件、軟體或硬體旗標、暫存 5 供一有關處理資源用量之位準的指示符或資訊’彼等传= 括但不限於：缓㈣/财巧填充轉、_賴存哭殖^ 速率之預測、先前之緩衝器/儲存器填充加速率、網路内 網痒處之擁擠位準、運作頻率、資料傳輸速率、資料奸 速率、資料取得速率中之預測變化、隨時間之寫人運作^ 數目、隨時間之先前讀取運作的數目、等等。舉例而丄 -第-緩衝器填充量(例如，50%)，可使與一第二_真 充量(例如，75%)比較’藉以決定該第二緩衝器，在一特定 1〇之時刻，係較該第一緩衝器利用更完全。另一範例係包括 -可指示若-當前之資源分配被維持時便預測—處理元件 要使用其分配之能量預算的110%之警報。 術語”收發器”(例如，一包括發射器和接收器之裝置) ，在遍及此一文件，係可被用來替代，，發射器，，或，，接收器，， 15 。同理，術語’’接收器’’或/或"發射器”，在遍及此一文件， 係可被用來替代’’收發器”。 第1圖係一依據各種實施例之裝置100和系統11〇的方 塊圖。舉例而言，一裝置100可能包含一調整模組114，其 可獨立調整多個搞合至對應多個網路處理器PEi、PE2、 20 、PEX之處理裔時鐘CL1、CL2、…、CLX。此調整模組114 ，可運作使響應該裝置100内所包含之一或多的狀態指示符 A、B、C、D，來調整一或多之時鐘信號CL1、CL2、…、 或CLX(和CLKR)。該裝置100可能包含一在上述調整模組 114内之主機處理器118。該裝置100可能亦包含一或多之類 1277329 比組件，諸如類比前置輸入-輸出節點AFE 10 NOTE，和類 比前置器AFE1、AFE2、AFE3，彼等復可能包含任何數目 之組成元件，諸如一所舉為例之收發器。 在許多實施例中，一或多之緩衝器BFR1、BFR5、… 5 、BFRX，可使耦合至該等狀態指示符A、B、C、和D。此 等缓衝器BFR1、BFR5、…、BFRX，係直接或間接耦合至 多個網路處理器PEI、PE2、…、PEX。任何一個或以上之 多個網路處理器PEI、PE2、…、PEX，可以此一方式使與 一或多之緩衝器BFR1、BFR5、…、BFRX相聯結。在某些 10 實施例中，任何數目之緩衝器，諸如緩衝器BFR14和BFRX ，可使分別獨立地耦合至該等狀態指示符，諸如狀態指示 符C和D。誠如先前所指，狀態指示符A、B、C、和D，可 不受限地被用來指示一緩衝器填充狀態、緩衝器填充速率 、和緩衝器填充加速，姑不論裝置100之其他元件的運作和 15 /或資源用量。 在某些實施例中，該裝置100可能包含多個或成一對一 之關係或成多對一之關係（例如，多重耦合至單一處理器之 路由器，和/或多重耦合至單一路由器之處理器），而使直接 (或間接）耦合至對應多個網路處理器PEI、PE2、…、PEX 20 的路由器Rl、R2、...、RX。在某些實施例中，該等路由器 Rl、R2、…、RX，可能包含多個或許由一單一時鐘信號源 CLKR加以時控之同步時控式路由器Rl、R2、R3和R4。 在某些實施例中，該等多個網路處理器PEI、PE2、… 、PEX之處理元件，可能係屬不同種類，以及可能執行不 1277329 同之功能。因此，該等多個網路處理器PEI、PE2、...、PEX 所包含之一個、兩個、或所有的處理元件，可能最好是在 一些不同的時鐘頻率下運作，或許就此等多個網路處理器 PEI、PE2、…、PEX所包含之每一處理元件，使修整至其 5 所需之工作負荷。誠如先前所指明，在某些實施例中，該 等網路處理器PEI、PE2、…、PEX，可能係使共同位於一 晶粒156和/或主機板158上面。在某些實施例中，該等網路 處理器PE卜PE2、…、PEX，可能構成全球資訊網路160之 一部分。 10 在某些實施例中，一些非同步時鐘頻率，可能係由該 等時鐘信號CL1、CL2、···、CLX來提供。該等平衡分配在 多個網路處理器PEI、PE2、…、PEX内所包含之處理元件 當中的工作負荷，可藉由此等在多個網路處理器PEI、PE2 、…、PEX内所包含之處理元件當中傳輸的資料封包化而使 15致能。該等緩衝器BFR1、BFR5、…、BFRX，可運作為該 專夕個網路處理器PEI、PE2、…、PEX内所包含之處理元 件與路由器R1、R2、…、rx當中的界面，而可適應上述在 一時鐘頻率下執行之傳輸網路(例如，路由器Rl、R2、... 、RX和一些至該等多個網路處理器叩卜pE2、…、？既之 2〇連接體）與各種處理器元件時鐘頻率（彼等可能與某些實施 例中由時鐘信號CLKR所提供之傳輸網路時鐘頻率相同或 不同）當中的非同步性。在某些實施例中，該等多個路由器 R1、R2、…、RX，可能屬一同步時鐘速率之時鐘速率，亦 可忐獨立地被調整。該等多個網路處理器pE1、pE2、...、 1277329 PEX中所包含之非同步時控處理元件當中，可經由一或多 4似所舉為例之缓衝器狀態指示符C和D的狀態指示符，來 完成通。1277329 IX. INSTRUCTIONS: I: TECHNICAL FIELD OF INSTITUTIONS AREAS 3 FIELD OF THE INVENTION The various embodiments described in this specification generally relate to information processing, such as some used to process data, including individual data elements and Data packets, devices, systems, and methods. I: Prior Art I Background of the Invention Φ An array of processing elements can achieve a large amount of processing power in accordance with generally recognized tasks. However, the simultaneous operation of their individual components can lead to undue consequences, including wasted power and inefficient use of available resources. V SUMMARY OF THE INVENTION The present invention is a method comprising the steps of independently adjusting a plurality of couplings to a corresponding plurality of network 'processors in response to a state indicator being less than -15 Processor clock. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a device and system in accordance with various embodiments; Fig. 2 is a flow chart 20 illustrating several methods in accordance with various embodiments; and Fig. 3 is a basis A block diagram of the products of various embodiments. L Embodiments: i DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT In some embodiments, the clock frequency applied to the corresponding individual component can be adjusted based on the need (so that the individual components can be non-synchronized 1277329) And let multiple processing elements operate to process the information. In some cases, this may mean that some components operating below full load are selected to operate at a lower frequency than the other components. In some cases, the -5 method of processing the components of their assigned workload may increase the frequency of their application. In some embodiments, some routers used to connect individual physical components may operate in a synchronized manner. Such a solution to poor communication may result in a reduction in power utilization and a more equitable configuration of available processing resources. 10 For the purposes of this document, the term “energy conduit” may include any type of device or device capable of transmitting and/or receiving energy to and from space. Examples of such energy conduits, including others, include antennas (eg, omnidirectional, directional, directional, wired, monopolar, dipole, etc.), infrared emitters, infrared receivers, Infrared transceivers, light emitters (eg, 15 such as light emitting diodes), light receivers (eg, photovoltaic cells), and charge coupled devices. , Network Processor ", may address two or more of the processing of 7L pieces of any group, which are interconnected to enable sharing of the resources provided by a common source, and/or the ability to transmit information to The destination, here a total of 20 with the source or destination, may be a memory, network, router, exchange Jie, and so on. In some embodiments, their network processors can be co-located on the granules and/or the motherboard. In some embodiments, their network processors may form part of the global information network. A "status indicator" may mean any mechanism (eg, circuit, object 1277329, software or hardware flag, temporary storage 5 for an indicator of the level of processing resource usage or information 'their pass = Including but not limited to: slow (four) / rich fill, _ 存 哭 ^ ^ rate forecast, previous buffer / storage fill rate, network intranet itch congestion level, operating frequency, data transmission Rate, data rate, predicted change in data acquisition rate, number of write operations over time, number of previous read operations over time, etc. For example, 丄-第 buffer fill (eg, 50) %), can be compared with a second _ true charge (for example, 75%) to determine the second buffer, at a specific time, more complete than the first buffer. Another The example includes - an alert indicating that if the current resource allocation is maintained - the processing component is to use 110% of its allocated energy budget. The term "transceiver" (eg, a device including a transmitter and a receiver) ), in this file, can be To replace, transmitter, or,,, receiver, 15. Similarly, the term ''receiver'' or / or "transmitter", in this file, can be used instead of '' The first embodiment is a block diagram of a device 100 and a system 11 according to various embodiments. For example, a device 100 may include an adjustment module 114, which can independently adjust multiple fits to corresponding multiples. The processing clocks CL1, CL2, ..., CLX of the network processors PEi, PE2, 20, PEX. The adjustment module 114 is operable to respond to one or more status indicators A included in the device 100, B, C, D, to adjust one or more clock signals CL1, CL2, ..., or CLX (and CLKR). The device 100 may include a host processor 118 within the adjustment module 114. The device 100 may Also includes one or more 1277329 ratio components, such as an analog front input-output node AFE 10 NOTE, and analog preamps AFE1, AFE2, AFE3, which may contain any number of constituent elements, such as one Example transceiver. In many embodiments, one or more buffers BFR1, BFR5, ... 5, BFRX, can be coupled to the status indicators A, B, C, and D. These buffers BFR1, BFR5, ..., BFRX are directly or indirectly coupled to multiple networks Processors PEI, PE2, ..., PEX. Any one or more of the network processors PEI, PE2, ..., PEX may be associated with one or more buffers BFR1, BFR5, ..., BFRX in this manner. In some 10 embodiments, any number of buffers, such as buffers BFR14 and BFRX, may be independently coupled to the status indicators, such as status indicators C and D, respectively. As previously indicated, status indicators A, B, C, and D can be used without limitation to indicate a buffer fill status, buffer fill rate, and buffer fill acceleration, regardless of other components of device 100. The operation and 15 / or resource usage. In some embodiments, the apparatus 100 may include multiple or one-to-one relationships or many-to-one relationships (eg, multiple coupled to a single processor router, and/or multiple coupled to a single router) And directly (or indirectly) couple to routers R1, R2, ..., RX corresponding to a plurality of network processors PEI, PE2, ..., PEX 20. In some embodiments, the routers R1, R2, ..., RX may include a plurality of synchronous time-controlled routers R1, R2, R3, and R4 that may be time-controlled by a single clock source CLKR. In some embodiments, the processing elements of the plurality of network processors PEI, PE2, ..., PEX may be of different kinds and may perform the same functions as 1277329. Therefore, one, two, or all of the processing elements included in the plurality of network processors PEI, PE2, ..., PEX may preferably operate at different clock frequencies, and perhaps more Each processing component included in the network processors PEI, PE2, ..., PEX is trimmed to the workload required by its 5th. As previously indicated, in some embodiments, the network processors PEI, PE2, ..., PEX may be co-located on a die 156 and/or motherboard 158. In some embodiments, the network processors PE, PE2, ..., PEX may form part of the global information network 160. In some embodiments, some of the asynchronous clock frequencies may be provided by the clock signals CL1, CL2, ..., CLX. The balances are distributed among the processing elements included in the plurality of network processors PEI, PE2, ..., PEX, and thus can be used in a plurality of network processors PEI, PE2, ..., PEX The data transmitted among the processing elements included is packetized to enable 15 enabling. The buffers BFR1, BFR5, ..., BFRX can operate as an interface between the processing elements included in the network processors PEI, PE2, ..., PEX and the routers R1, R2, ..., rx. It can be adapted to the above-mentioned transmission network executed at a clock frequency (for example, routers R1, R2, ..., RX, and some to the plurality of network processors, pE2, ..., ? The non-synchronization among the various processor component clock frequencies (which may or may not be the same or different than the transmission network clock frequencies provided by the clock signal CLKR in some embodiments). In some embodiments, the plurality of routers R1, R2, ..., RX may be clocked at a synchronous clock rate and may be independently adjusted. Among the asynchronous timing processing elements included in the plurality of network processors pE1, pE2, ..., 1277329 PEX, one or more of the buffer status indicators C and D's status indicator to complete the pass.
在某些實施例中，該等時鐘信號(：^1、CL2、…、CLX 和CLKR有關之時鐘頻率，可在實質編譯之時刻下靜態地 被决疋。然而，動態時鐘管理亦可被執行，或許是取決於 些緩衝器填充狀態指示符。舉例而言，一在其分配之任 矛力後面的處理元件PE1(由於處理器網路之動態性或某些在 、’扁厚打未被預期之因素），可使其時鐘頻率（例如，由cU提 1〇供)依需要增加，直至緩衝器BFR1處之潛在緩衝器溢位的情 況緩和為止。 其他之實施例係可被實現。舉例而言，一系統110可能 包含一頬似或等同先前所說明之裝置100的裝置100，加上 一耗合至一或多之多個類比前置器AFE1、AFE2、AFE3、 I5和/或網路處理器PE1、酸、…、ΡΕΧ的能量導管15〇。誠 如先刖所指，至少某些多個處理器時鐘信號CL1、CL2、… CLX和CLKR有關之速率，係可在一通常要由對應多個 網路處理器PE1、ΡΕ2、···、ΡΕΧ來執行之程式有關的實質 編譯之時刻下靜態地被決定。因此，舉例而言，該等多個 20網路處理器pE卜PE2、…、PEX内所包含之第一處理器PE1 和第二處理器PE2，正如時鐘信號CL1和CL2所決定，可能 具有不同之運作速率。 在某些實施例中，一或多之狀態指示符A、B、C、和D ’可此係獨立地指示一或多耗合至對應多個網路處理器PE1 1277329 、PE2、…、PEX之路由器]^、R2、…、Rx的狀態。舉例 而言，狀態指示符A和B，可能分別獨立地指示該等路由器 R4和R9之狀態。當然，該等狀態指示符A、B、C、和〇， 可能係指示許多與上述裝置1〇〇和系統U〇之運作和資源用 量相關聯的不同元素，諸如網路訊務負荷。因此，舉例而 言，該等狀態指示符A和B，可能係指示上述耦合至多個網 路處理IsPEl、PE2、…、pex之網路154相關聯的兩個不同 點處所加載之網路訊務量。 10 該等裝置100、系統11〇、調整模組114、主機處理器118 、旎ϊ導官150、網路I54、晶粒156、主機板158、資訊網 路160、類比前置輸入_輸出節點八？]£ I〇 N〇TE、類比前置 态 AFE卜 AFE2、AFE3、緩衝器 BFR卜 BFR5、 、bfrm 15 、bfrx、時鐘信號cu、CL2、、CLX、clkr 網路處 理器PE卜ΡΕ2、.··、ΡΕχ、路由器RbR2、、Rx、和狀 態指^符，在本說明書中可能全係特性化為 松組。此種板組可能包括硬體電路、和/或一或多之卢理 器、和/或記憶電路、軟體程式模組、包括 ：、 和/或韋刃體、和彼等之組合，如同該 " —& X W 罝川0和糸統110之 …十師所布望，以及如同本發明之各種實 20體所適用。 W寸疋具現 亦應瞭解的是，各種實施例之裝 ^ 予、統’可被使用 在-w處理器晶粒和主機板外及除無線系統外之應用 例中，以及因而各種實施例不應受限於 ^ 邊寺裝置100和 糸統削之圖例，係意使對各種實_之結構提供—般性之 11 1277329 瞭解，以及彼等並非意欲充做一些或會利用本說明書所說 明之結構的裝置和系統之所有元件和特徵的完全說明。 一些可能包括各種實施例之新奇裝置和系統的應用例 ，係包含一被使用在高速電腦、通訊和信號處理電路、數 5 據機、處理器模組、内嵌式處理器、資料交換器、和一些 包含多階層、多晶片模組等專用模組之電子電路中。此種 裝置和系統，可能進一步係作為子組件而使包含在種類繁 多之電子系統内，諸如電視機，蜂巢式電話、個人電腦、 個人數位助理(PDA)、工作站、收音機、錄影機、交通工具 10 、等等。 第2圖係一可例示幾種依據各種實施例之方法的流程 圖。因此，在本發明之某些實施例中，一方法211可能開始 是在區塊221處響應一或多之狀態指示符(選擇性地)來調整 (或許是獨立地）多個耦合至對應多個網路處理器之處理器 15 時鐘。舉例而言，彼等狀態指示符，可能係獨立地與該等 對應多個網路處理器内所包含之一或多的處理器之進度位 準相關聯。 在某些實施例中，該方法211可能包括在區塊225處響 應一或多之對應多個網路處理器的進度位準來調整一或多 20 之封包長度。在某些實施例中，該方法211可能包括在區塊 231處響應一或多之對應多個網路處理器的進度位準來調 整一或多之取樣區塊尺寸。 誠如先前所指明，該等狀態指示符，可能指示一或多 之處理器依據一或多獨立地與一或多之對應多個網路處理 12 1277329 器相關聯的缓衝器之狀態的進度位準。舉例而言，此所指 之狀態，可能係選自一或多之緩衝器填充量、缓衝器填充 比率、和緩衝器填充加速，姑不論其他。 在某些實施例中，該方法211可能包括在區塊235處同 5 步時控多個耦合至對應多個網路處理器之路由器。在某些 實施例中，該方法211可能包括在區塊241處，或許是大體 上在一通常要由對應多個網路處理器來執行之程式有關的 編譯之時刻下，就至少某些多個處理器時鐘，靜態地決定 兩個或以上之不同速率。 10 在某些實施例中，該方法211可能包括在區塊245處獨 立地調整一或多之多個處理器時鐘的速率，藉以平衡一處 理器工作負荷測量不平衡性。此不平衡性可能係由一或多 之狀態指示符來指明，諸如第一指示符和第二指示符（例如 ，見第1圖，正如狀態指示符C和D可能被用來指示依據類 15 似缓衝器填充狀態等BFR14狀態和BFRX狀態之工作負荷 進度和/或平衡）。因此，任何數目之狀態指示符，可能被用 來獨立地指示一或多之緩衝器的狀態，此等緩衝器係獨立 地與一或多之對應多個網路處理器的進度和/或資源用量 相關聯。舉例而言，此所指示之狀態，可能係選自至少一 20 取樣率和一取樣率中之改變，姑不論其他。 在某些實施例中，該方法211可能包括在區塊251處獨 立地調整一或多之多個處理器時鐘之速率，藉以改變各種 性能元素，或一些與本說明書所揭示之裝置和系統相關聯 的進度之指示符，包括緩衝器行為，諸如一或多之缓衝器 13 1277329 填充數ί、缓衝器填充比率、和緩衝器填充加速，姑不論 其他。在某些實施例中，該方法211可能包括在區塊255處 獨立地調整-或多之多個處理器時鐘的速率，藉以補償一 或多之預測性能元素，痞太％日日蚩仏粗一 次本祝明書所揭不之裝置和系統相 關聯的進度之指示符，白杯 匕括預測之工作負荷和/或預測之網 路訊務負荷，姑不論其他。 10 里應/主心的疋，本說明書所說明之方法，在執行上非 必然要依此說明之順序，或依任何特定之順序。此外，各 種在說明上參照本說明書所指明之方法的活動’係可在序 列二:：或t代之方式中被執行。為此-文件之目的， 術语> ’’和’’賁料，’，可六μ 寸 了又換地加以使用。一些包括參數、 指令、運异元等資料，采甘 他L括各種格式(例如，分時、 多重存取)之資料、和各種 喱頦型（例如，二進制、文數、音訊 、視訊）之資料等資料，可 或夕之載波的形式來傳送及 15 接收。 在讀取及理解此一揭示 奋4，本技蟄之一般從業人 貝將可瞭解到一軟體程式 帝 篆乂在一基於電腦之系統中使 一黾月自易項式媒體起動來勃 + 一 執仃此軟體程式中所界定的功能 之万式。本技藝之一般從童人^In some embodiments, the clock frequencies associated with the clock signals (:^1, CL2, ..., CLX, and CLKR can be statically asserted at the time of substantial compilation. However, dynamic clock management can also be performed , perhaps depending on the buffer fill status indicator. For example, a processing element PE1 behind its assigned power (due to the dynamic nature of the processor network or some of the 'flat thickness' is not expected Factor) may increase its clock frequency (eg, by cU) as needed until the potential buffer overflow at buffer BFR1 is mitigated. Other embodiments may be implemented. A system 110 may include a device 100 similar to or identical to the device 100 previously described, plus one or more analogous preamps AFE1, AFE2, AFE3, I5, and/or network processing. The energy conduits of the PE1, acid, ..., ΡΕΧ 15 〇. As indicated above, at least some of the plurality of processor clock signals CL1, CL2, ... CLX and CLKR are associated with a rate that can be correspondingly Multiple network processors PE1, ΡΕ 2, · ································································ PE1 and second processor PE2, as determined by clock signals CL1 and CL2, may have different operating rates. In some embodiments, one or more of state indicators A, B, C, and D' may be Independently indicating one or more states of the routers ^^, R2, ..., Rx corresponding to the plurality of network processors PE1 1277329, PE2, ..., PEX. For example, the status indicators A and B may be respectively The states of the routers R4 and R9 are independently indicated. Of course, the status indicators A, B, C, and 〇 may indicate a number of operations associated with the operation and resource usage of the device 1 and the system U〇 described above. Different elements, such as network traffic load. Thus, for example, the status indicators A and B may indicate the two associated with the network 154 coupled to the plurality of network processes IsPE1, PE2, ..., pex. The amount of network traffic loaded at different points. 10 The device 100, the system 11, the adjustment module 114, the host processor 118, the controller 150, the network I54, the die 156, the motherboard 158, the information network 160, the analog front input_output node eight? £I〇N〇TE, analog preamp AFE, AFE2, AFE3, buffer BFR, BFR5, bfrm 15, bfrx, clock signal cu, CL2, CLX, clkr network processor PE, ΡΕ2, . ·, ΡΕχ, router RbR2, Rx, and status indicator, in this specification may be characterized as a loose group. Such a board set may include a hardware circuit, and/or one or more of a processor, and/or a memory circuit, a software program module, including:, and/or a blade body, and combinations thereof, as such "&&; XW 罝川0 and 糸 110 110... The tenth division is expected, and the various real 20 bodies of the present invention are applicable. It should also be understood that the various embodiments of the present invention can be used in applications outside the -w processor die and motherboard and in addition to wireless systems, and thus various embodiments are not It should be limited to the legends of the 边 寺 temple installation 100 and the 削 削 , , , , , , , , , , , , , , , , 11 11 11 11 11 11 11 11 11 11 12 12 12 12 11 11 11 11 11 11 11 11 11 11 11 11 A complete description of all the components and features of the structure of the device and system. Some examples of applications that may include novel devices and systems of various embodiments include the use of high speed computers, communication and signal processing circuits, microprocessors, processor modules, embedded processors, data switches, And some electronic circuits that contain dedicated modules such as multi-level, multi-chip modules. Such devices and systems may further be included as sub-components for inclusion in a wide variety of electronic systems, such as televisions, cellular phones, personal computers, personal digital assistants (PDAs), workstations, radios, video recorders, vehicles 10, and so on. Figure 2 is a flow diagram illustrating several methods in accordance with various embodiments. Thus, in some embodiments of the present invention, a method 211 may begin by adjusting one or more status indicators (optionally) at block 221 to adjust (perhaps independently) multiple couplings to corresponding multiples. The processor 15 clock of the network processor. For example, their status indicators may be independently associated with the progress levels of one or more processors included in the corresponding plurality of network processors. In some embodiments, the method 211 may include adjusting one or more packet lengths at block 225 in response to one or more progress levels of the plurality of network processors. In some embodiments, the method 211 may include adjusting one or more sample block sizes at block 231 in response to one or more progress levels of the plurality of network processors. As indicated previously, the status indicators may indicate the progress of one or more processors in accordance with one or more independent buffer states associated with one or more corresponding plurality of network processing 12 1277329 devices. Level. For example, the state referred to herein may be selected from one or more buffer fill levels, buffer fill ratios, and buffer fill acceleration, regardless of others. In some embodiments, the method 211 may include controlling a plurality of routers coupled to a plurality of network processors at the same time as the 5th step. In some embodiments, the method 211 may be included at block 241, perhaps at least some of the time at which compilation is typically performed by a program that is typically executed by a plurality of network processors. The processor clocks statically determine two or more different rates. In some embodiments, the method 211 may include independently adjusting the rate of one or more processor clocks at block 245 to balance a processor workload measurement imbalance. This imbalance may be indicated by one or more status indicators, such as the first indicator and the second indicator (eg, see Figure 1 as the status indicators C and D may be used to indicate according to class 15 Workload progress and/or balance of BFR14 state and BFRX state, such as buffer fill state. Thus, any number of status indicators may be used to independently indicate the status of one or more buffers that are independently associated with one or more of the progress and/or resources of the plurality of network processors. The amount is associated. For example, the state indicated herein may be selected from at least a 20 sample rate and a sample rate change, regardless of others. In some embodiments, the method 211 may include independently adjusting the rate of one or more processor clocks at block 251 to change various performance elements, or some related to the apparatus and system disclosed herein. An indicator of the progress of the association, including buffer behavior, such as one or more buffers 13 1277329 padding ί, buffer fill ratio, and buffer fill acceleration, regardless of others. In some embodiments, the method 211 may include independently adjusting - or more than a plurality of processor clock rates at block 255 to compensate for one or more predicted performance elements, 痞 too % day to day An indicator of the progress associated with the device and system not disclosed in the book, the white cup includes the predicted workload and/or the predicted network traffic load, regardless of the other. 10 应/主心疋, the methods described in this manual are not necessarily executed in the order described, or in any particular order. In addition, various activities in the description with reference to the methods specified in the specification can be performed in the manner of the sequence 2:: or t generation. For the purposes of this document, the terms > ' and '', ', can be used up to six inches. Some include data such as parameters, instructions, and different elements, such as data in various formats (for example, time-sharing, multiple access), and various types of gels (for example, binary, text, audio, video). Data such as data can be transmitted in the form of a carrier or a carrier on the evening. After reading and understanding this revelation, the general practitioner of this technology will learn that a software program emperor will start a month of self-propelled media in a computer-based system. Execute the functions defined in this software program. The general skill of this art from the children ^
耒人貝，將可進一步瞭解各種可 20被採用來建立一或多被設計夾月B 、 ΐ；^具現並執行本說明書所揭示 之方法的幸人體程式之程式士 T ^ S。此等程式可能係使用一類 似Java或C++等物件導向式技一 ㊂，使結構化成一物件導向格 式。或者’該等程式可能係使用1似組合語言或C等程序 语吕’使結構化成-程序導向格式。該等軟體組件係可使 1277329 用任一為本技藝之專業人貝所習見的眾多機構相通訊’諸 如應用程式界面或程序間（inter-process)通訊技術，包括遠 距程序呼叫。各種實施例之授義内容，並非受限於任一特 定之程式語言或環境。因此，其他之實施例係可加以實現 5 ，正如第3圖中所示。 第3圖係一依據各種實施例之產品385的方塊圖，諸如 電腦、記憶體系統、磁碟或光碟、某些其他之儲存器裝置 、和/或任何類型之電子裝置或系統。此產品385可能係包 含一處理器387，其係耦合至一機器可存取式媒體，諸如一 10 記憶體389(例如’一包含電氣、光學、或電磁導體之記憶 體）’其係具有相聯結之資料391 (例如，電腦程式指令，和/ 或其他資料），其在存取時可使一機器（例如，處理器387) ，執行一些類似獨立地調整多個_合至對應多個可響應至 少一狀態指示符之網路處理器的處理器時鐘之動作。誠如 15先前所指明，彼等狀態指示符，可能獨立地指示一或多之 緩衝杰的狀恶，彼等復可能獨立地與該等對應多個網路處 理Is之進度相關聯。上述被指示之狀態，可能係選自任何 數目之元素，諸如一取樣率和一取樣率中之改變，姑不論 其他。 20 其他之活動可能包括獨立地調整一或多之多個處理器 時鐘的速率，藉以改變緩衝器填充量、緩衝器填充比率、 和緩衝器填充加速中之至少_個，姑不論處理器進度之其 他可能指示符。-些進一步之活動，可能包括獨立地調整 -或多之多做理！！時鐘的速率，藉以猶—預測之工作 15 1277329 負荷和/或一預測之網路訊務負荷，姑不論處理器進度之其 他可能指示符。 a 考慮本說明書所說明之裝置、系統、方法、和產品， 理應注意的是，該等多個網路處理器pE1、pE2、...、ρΕχ 5内之個別處王里器的時鐘速率，加上上述傳輸網路之時鐘速 率，係可加以調整，使達成一總體之性能目標，或許係由 一或夕之潛時/響應需求和/或產能需求來建立。在某些實施 例中，5亥性能目標可加以修飾，使在低於一指定之電力消 耗極限下運作。在某些實施例中，該性能目標可在完成上 10使達成最低可能之電力消耗。誠如本技藝之專業人員在 讀取此一揭示内容後可認識到的，一或多之策略可被建立 來導引上述調整模組114之行為，使響應一或多之狀態指示 付A B、C、和D，來調整該等經由上述傳輸網路154(例如 ’或许使用一或多之時鐘信號CL卜CL2、…、CLX、和CLKR) 15耦合之個別處理器和路由器有關的時鐘速率，藉以達成上 述之性能。 具現本說明書所說明之裝置、系統、和方法，可能會 在一網路群組之處理元件中，造成非同步之資訊處理。某 些、個、或無處理器時鐘係可使分佈，以及在某些實施 20例中，每—處理單元若有需要，可用一可獨立調整之時鐘 信號來運作。一個、某些、或所有處理元件有關之時鐘信 號設定，可依據各種狀態指示符以響應之方式來加以調整 ，而在某些實施例中，可容許動態緩衝器管理，或許是基 於即日守之工作負荷和緩衝器狀態。此種運作可能產生一些 16 1277329 "、有可軚定之性能和需求之資訊處理系統。 a該等所附形成本說明書之一部分的繪圖，係藉由圖例 而無限制意地顯示-些可在其中實現此主題之特定實施例 。此等例示之實施例，係做充份詳細之說明，可使本技藝 之專業人員此貫現本說明書所揭示之授義内容。由其係可 利用及導出其他之實施例，以致在不違離此揭示内容之界 定範圍，將可完成-些結構上和邏輯上之替代品和變更形 式。所以’此-『實施方式』不應被視為有限制意，以及 各種實施例之界定範圍，僅係由所附申請專利範圍連同此 10等主張被授權之整個範圍的等價體來加以界定。 此等為發明主題之實施例，在本說明書中可能係個別 及/或集體地以術語”本發明，，來指稱，其僅為例示計，而非 意欲自動使此申請案限制至任一單一發明或原創性觀念， 倘若事實上有多於一個被揭示。因此，雖然本說明書已例 15示及說明一些特定之實施例，但理應瞭解的是，任何被气 劃來達成相同目的之安排，可被用來替代該等顯示出之特 定實施例。此一揭示内容係意使涵蓋各種實施例之任何和 所有的適應體或變更形式。上述諸實施例之組合，和本^ 明書未明確說明之其他實施例，將會為本技藝之專業人員 20在檢視上文之說明時得以明瞭。 、 『發明摘要』一節，在提出上係遵照37 C.F.R § 1.72(b) ’要求一可谷許讀者能迅速掌握其技術揭示内容之 性質。其在提交上係瞭解到，其將不被用來理釋或限制申 請專利範圍之界定範圍或意義。此外，在前文之『實施方 17 1277329 式』一節中’各種特徵可見為簡化此揭示内容，係使聚集 在一單一實施例中。此一揭示方法不應被理釋為反映意圖 使此等主張之實施例需要多於每一主張中所明白列舉的特 认更確切的是，正如下列之主張所反映，此原創性主題 5係著重少於一單一揭示之實施例的所有特徵。因此，以下 之申請專利範圍，係藉此合併進『實施方式』一節内，而 使母一主張自立為一單獨之實施例。 【圖式簡單說明3 第1圖係一依據各種實施例之裝置和系統的方塊圖； 弟2圖係一可例不幾種依據各種貫施例之方法的流程 圖；而 第3圖則係一依據各種實施例之產品的方塊圖。 【主要元件符號說明】 100…裝置 110…系統 114…調整模組 118…主機處理器 150···能量導管 154.··網路 156…晶粒 158…主機板 16CX··全球資訊網路 385…產品 387…處理器 389…記憶體耒人贝, will be able to further understand the various programs that can be used to create one or more designed moons B, ΐ; ^ is now and implements the method disclosed in this specification. These programs may use a class-oriented approach such as Java or C++ to structure into an object-oriented format. Or 'these programs may be structured into a program-oriented format using a 1-like combination language or a program such as C. These software components enable the 1277329 to communicate with a variety of mechanisms known to those skilled in the art, such as application interface or inter-process communication techniques, including remote program calls. The content of the various embodiments is not limited to any particular programming language or environment. Thus, other embodiments can be implemented 5 as shown in Figure 3. Figure 3 is a block diagram of a product 385 in accordance with various embodiments, such as a computer, a memory system, a magnetic or optical disk, some other storage device, and/or any type of electronic device or system. The product 385 may include a processor 387 coupled to a machine-accessible medium, such as a 10 memory 389 (eg, a memory containing electrical, optical, or electromagnetic conductors) Linked data 391 (eg, computer program instructions, and/or other materials) that, when accessed, can cause a machine (eg, processor 387) to perform a number of similarly independent adjustments to multiple corresponding ones. The action of the processor clock of the network processor in response to at least one status indicator. As previously indicated by 15 , their status indicators may independently indicate one or more buffers, and their complexes may be independently associated with the progress of the corresponding plurality of network processing Is. The above indicated state may be selected from any number of elements, such as a change in sampling rate and a sampling rate, regardless of others. 20 Other activities may include independently adjusting the rate of one or more processor clocks to change at least one of buffer fill, buffer fill ratio, and buffer fill acceleration, regardless of processor progress. Other possible indicators. - Some further activities may include independent adjustments - or more! ! The rate of the clock, by which the predictions work 15 1277329 load and / or a predicted network traffic load, regardless of other possible indicators of the processor's progress. a considering the devices, systems, methods, and products described in this specification, it should be noted that the clock rates of the individual geeks in the plurality of network processors pE1, pE2, ..., ρΕχ 5, In addition to the above-mentioned transmission network clock rate, it can be adjusted to achieve an overall performance goal, perhaps established by a latent/response requirement and/or capacity requirement. In some embodiments, the 5H performance goal can be modified to operate below a specified power consumption limit. In some embodiments, the performance goal can be achieved by completing 10 to achieve the lowest possible power consumption. As can be appreciated by those skilled in the art after reading this disclosure, one or more strategies can be established to guide the behavior of the adjustment module 114 to cause one or more status indications to be paid, C, and D, to adjust the clock rates associated with the individual processors and routers coupled via the transport network 154 described above (e.g., perhaps using one or more clock signals CLb, ..., CLX, and CLKR) 15, In order to achieve the above performance. The devices, systems, and methods described in this specification may cause unsynchronized information processing in the processing elements of a network group. Some, one, or no processor clocks can be distributed, and in some implementations, each processing unit can operate with an independently adjustable clock signal if needed. The clock signal settings associated with one, some, or all of the processing elements can be adjusted in response to various status indicators, and in some embodiments, dynamic buffer management can be tolerated, perhaps based on day-to-day work. Load and buffer status. Such operations may result in some information processing systems with determinable performance and requirements. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in the claims These exemplified embodiments are described in sufficient detail to enable those skilled in the art to present the teachings disclosed herein. Other embodiments may be utilized and derived so that structural and logical alternatives and modifications can be made without departing from the scope of the disclosure. Therefore, the scope of the various embodiments is not to be construed as limited by the scope of the appended claims. . These are examples of the subject matter of the invention, which may be referred to individually and/or collectively in the present specification by the term "the invention", which is merely an illustration, and is not intended to automatically limit the application to any single Invention or originality, if more than one is actually revealed, therefore, although this specification has shown and described some specific embodiments, it should be understood that any arrangement that is tempered to achieve the same purpose, The present invention is intended to be limited to the specific embodiments disclosed. It is intended to cover any and all adaptations or variations of the various embodiments. combinations of the above embodiments, and Other embodiments of the description will be apparent to those skilled in the art in view of the above description. The "Summary of the Invention" section is submitted in accordance with 37 CFR § 1.72(b) ' The reader is able to quickly grasp the nature of the disclosure of the technology. It is known in the submission that it will not be used to interpret or limit the scope or meaning of the scope of the patent application. The description of the various features in the section of the "Practices 17 1277329" can be seen as a simplification of the disclosure, and is disclosed in a single embodiment. This disclosure should not be construed as reflecting the embodiments intended to make such claims. More specific than what is explicitly stated in each claim is more precisely that, as reflected in the following claims, this original subject matter 5 focuses on less than all features of a single disclosed embodiment. Therefore, the following patent application The scope is incorporated into the "Embodiment" section, and the parent is claimed to be self-contained as a separate embodiment. [Schematic Description 3 Figure 1 is a block diagram of a device and system in accordance with various embodiments; The second diagram is a block diagram of a method according to various embodiments; and the third diagram is a block diagram of a product according to various embodiments. [Main component symbol description] 100...device 110...system 114...adjustment module 118...host processor 150··energy conduit 154.·network 156...die 158...host board 16CX··global information network 385...product 387...processor 389...memory
391…資料 A、B、C、D…狀態指示符 AFE 10 NOTE…類比前置輸入-輸 出節點 AFE1、AFE2、AFE3·.·類比前置器 BFTU、BFR5〜BFRX···緩衝器 CU、CL2〜CLX…時鐘信號 CUL、CL2〜CLX…處理器時鐘 CLKR.··時鐘信號源 PEI、PE2〜PEX···網路處理器 Rl、R2〜RX.··路由器 18391...Data A, B, C, D... Status indicator AFE 10 NOTE... Analog pre-input-output node AFE1, AFE2, AFE3·. Analogous preamplifier BFTU, BFR5~BFRX···Buffer CU, CL2 ~CLX...clock signal CUL, CL2~CLX...processor clock CLKR.··clock signal source PEI, PE2~PEX···network processor Rl, R2~RX.··router 18