1273435 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種動態隨機存取記憶體模組之存 取控制方法，更詳而言之，係有關於一種以相同的BIOS 程式即可供記憶體控制器存取DDR-I DRAM DIMM或 DDR-II DRAM DIMM之動態隨機存取記憶體模組之存取 控制方法。 【先前技術】 動態隨機存取記憶體（Dynamic Random Access Memory ; DRAM )因具有儲存容量大及成本低之特性，因 此，許多電子產品（例如桌上型電腦、筆記型電腦、伺服 器或工作站等）均採用其當作最佳的記憶體解決方案，更 是電子產品不可或缺的零組件之一。 再者，為提升DRAM的傳輪速度，因此DRAM業者 亦不斷地推出不同的DRAM，例如DDR-I ( Double Data Rate- I ) DRAM和DDR-II DRAM，並透過雙面針腳定義 記憶體模組（Dual In-line Memory Modules ; DIMM )插槽 (Slot)將此兩種DRAM DIMM插入於基板（Base Board) 上，一般而言，不同的DRAM (即DDR-I DRAM或DDR-II DRAM) DIMM即具有對應的DIMM插槽。 為配合 DDR-I DRAM DIMM(以下簡稱 DDR-I DIMM) 及 DDR-II DRAM DIMM (以下簡稱 DDR- II DIMM )兩種 規格的DRAM模組，Intel公司亦推出可支援DDR-I DIMM 及DDR-II DIMM的晶片組Lindenhurst，其内含一種記憶 5 18379 1273435 體控制器（在此將Lindenhurst晶片組簡稱為記憶體晶片組 Lindenhurst)。如第1 ( A )圖及第1 ( B )圖所示者係分別 用以顯示使用DDR-I DRAM DIMM插槽的基板7及 DDR-II DRAM DIMM插槽的基板7’所需的基本架構方塊 示意圖。兩基板（7、7’）分別使用相同的記憶體控制器1 (例如Intel公司所推出的記憶體晶片組Lindenhurst)且 各別使用DDR-I DIMM插槽區2及DDR-II DIMM插槽區 2’，此處之DIMM插槽區（2、2，）均具有8個DIMM插 槽（20、21、…、27 以及 20,、21，、…、27,），且兩 DIMM 插槽區（2、2’）其中的6個DIMM插槽各別安裝有DDR-1 DRAM DIMM 3 及 DDR-II DRAM DIMM 4 〇 由於 DDR-1 DRAM DIMM 3 及 DDR-II DRAM DIMM 4並不相容，且兩者的硬體設計亦不相同，故，雖然DDR-I DRAM DIMM 3 及 DDR-II DRAM DIMM 4 均可由 Intel 公 司的記憶體晶片組Lindenhurst支援，然而，在無法同時支 援的情況下，即須於兩基板（7、7’）上安裝不同的BIOS 程式（5、5 ’）以令該記憶體晶片組Lindenhurst判斷受其 執行存取控制對象的DIMM插槽區（2、2，）規格為何。 由上可知，此種作法顯然造成電子產品業者在BIOS 程式設計、BIOS程式燒錄、基板測試等過程的不便。因此， 如何讓電子產品業者僅需利用相同的BIOS程式即可隨意 設計及製造出以該記憶體晶片組Lindenhurst支援DDR-I DIMM或DDR-II DDR-II DIMM的基板，即是目前所需解 決的問題。 6 18379 1273435 【發明内容】 為解決上述習知技術之缺點，本發明之主要目的在於 提供一種動悲隨機存取5己憶體模組之存取控制方法，透過 同一 BIOS程式即可令記憶體控制器對DDR-Ι dram DIMM或DDR-II DRAM DIMM進行存取控制。 為達成上述及其他目的’本發明提供_種動態隨機存 取記憶體模組之存取控制方法。本發明之動態隨機存取記 憶體核組之存取控制方法’係應用於設有至少》一第一規格 動態隨機存取記憶體（DRAM)模組插槽或至少一第二規格 DRAM模組插槽、記憶體控制器及基本輸入輸出系統 (Basic Input/Ontput System，BIOS)程式之基板，以供該基 板對安裝於第一規格DRAM模組插槽之第一 dram模組 或安裝於第二規格DRAM模組插槽之第二DRAM模組進 行存取控制，該方法至少包括以下步驟：令該BIOS程式 預存第一規格DRAM模組及第二規格DRAM模組相關資 料；令該基板根據該BIOS程式執行記憶體初始化程序 (Memory Initialization);令該記憶體控制器於記憶體初始 化程序中對該基板上所設之記憶體模組進行存取，並對記 憶體模組透過SM ( System Management)匯流排以12C協 定（Protocol)進行其 SPD(Serial Present Detect)資料讀取， 根據DRAM模組SPD貢料之記憶體型式搁位（Memory Type Field)值判斷安裝於該DRAM模組插槽為第一 DRAM 模組或第二DRAM模組；以及令該記憶體控制器以該 DRAM模組自該BIOS程式讀取與該DRAM模組對應之 7 18379 1273435 DRAM模組相關資料，以供記憶體控制器根據所讀取到的 DRAM模組相關資料對安裝於該DRAM模組插槽中的 DRAM模組進行存取控制。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 如第2圖所示者係為應用本發明之動態隨機存取記憶 體模組之存取控制方法使記憶體控制器以同一 BIOS程式 即可對DDR-I DRAM DIMM(以下簡稱為DDR-I DIMM)或 DDR-II DRAM DIMM(以下簡稱為 DDR-II DIMM)進行存 取控制之基本架構方塊示意圖。於本實施例中，本發明之 動態隨機存取記憶體模組之存取控制方法所需之構件係包 括：記憶體控制器1、BIOS程式6以及DDR-I DIMM插槽 區2或DDR-II DIMM插槽區2’，該些構件係設於基板（在 此未予以圖示）上，以供安裝該基板的電子裝置（例如筆記 型電腦、桌上型電腦、伺服器或工作站）以相同的BIOS程 式6即可對DDR-I DIMM或DDR-II DIMM進行存取控 制。在此須提出說明的是，該基板另具有其它各式功能單 元，為簡化圖式及說明，此處之架構僅顯示與本發明有關 之構件，其它無關之構件，例如南橋及北橋等之硬體架構， 8 18379 1273435 並未顯示於本圖式中。 電子裝置之基板上的DRAM均使用相同的DRAM規 格，亦即，該基板具有統一的DRAM規格，本實施例即以 DDR-I DRAM或DDR-II DRAM為例說明，且因應不同 DRAM規格而於基板上設有相對應的雙面針腳定義記憶體 模組（Dual In-line Memory Modules ; DIMM )插槽（DIMM Slot)，亦即，不同DRAM規格所對應的DIMM外觀即不 相同，以提供防呆設計之功能，故可使基板上DRAM規格 安裝正確。 本實施例之DDR-I DRAM模組插槽區2及DDR-II DRAM模組插槽區2，均具有8個DIMM插槽（20、21、…、 27 以及 20’、21’、…、27’），其中，該 DDR-I DRAM 模 組插槽區2之DIMM插槽（20、21、22、24、25及26)各 安裝一個DDR-I DIMM 3，而該DDR-II DIMM插槽區2’ 之 DIMM 插槽（2Γ、22’、23’、25’、26’及 27，）各安裝一個 DDR-II DIMM4。各個 DIMM ( 20、21、22、24、25、26 以及21’、22’ 、23’ 、25，、26’ 、27，）各別具有例如 EEPROM之記憶體（在此未予以圖示），用以儲存DIMM 參數，亦即為 SPD ( Serial Presence Detect ; SPD )資料， 且DIMM之SPD資料包含記憶體型態（Memory Type )之 欄位，故我們可由此欄位值得知此DIMM為DDR-Ι或 DDR-II。再者，每個DIMM插槽皆具有一 SM(System Management)匯流排，其具有2條信號線，一為資料線 (Data Line )，另一為時脈線（Clock Line )，以連接至 9 18379 1273435 此插槽，其乃為系統透過SM匯流排使用I2C協定（Protocol) 去存取DIMM SPD資料，且DIMm之規格規定DIMM插 槽之 I2C 位址規範為 A〇H、A2H、A4H、A6H、A8H、 AAH、ACH以及AEH。再者，該DIMM插槽的數量並未 限定為本實施例所示之八個，亦可為六個或四個等，端視 實施例而定。 再者’本實施例之記憶體控制器1係指Intel公司的 記憶體晶片組Lindenhurst，由於基板僅具有單一種DRAM 規格，故BIOS僅需掃描各mMM插槽（20、21、…、 27以及20’、21’、···、27，）之SPD資料中的記憶體型態 欄位（Memory Type Filed)便可知安裝於該mMM插槽上 的 DRAM DIMM 規格為 DDR-Ι DIMM 3 或 DDR-II DIMM 4。SPD資料有其標準定義（其定於PC SDRAM Serial Presence Detect)，其中Byte 2之資料代表記憶體型態，其 值 07 代表 DDR-I DIMM ;其值 08 代表 DDR-II DIMM。 由上可知，BIOS以掃描方式讀取各DIMM插槽（20、 21.....27以及20,、21，.....27，）之記憶體所儲存之 SPD資料的Byte 2 (Memory Type Field)值，即可判斷目 前安裝於DIMM插槽上的DRAM DIMM規格，並自該BIOS 程式6讀取與該DRAM DIMM規格相對應的資料（亦即程 式或資料）以供電子裝置於開機程序中即順利完成記憶體 初始化。由於上述BIOS程式及電腦裝置開機初始化程序 均為一般電腦系統於運作前之必要構件及程序，亦為習於 電腦技術者所熟知之技術’因此以下將不對其運作功能及 10 18379 1273435 内部架構作說明。 如第3圖所示者係用以顯示本發明之動態隨機存取記 憶體模組之存取控制方法之流程步驟示意圖。如圖所示， 首先進行步驟S1，由於DDR-I DIMM及DDR-II DIMM之 特性不同，故硬體布線的需求即不相同，例如DIMM CS(ChiP Select)組態、DIMM插槽之I2C位址、日寺脈控制 方式、CKE腳（Pin )模式為共用或獨立以及DIMM數量 等，故需根據DDR-I DRAM及DDR-II DRAM之特性預先 於該BIOS程式6中加入DDR-I DIMM 3以及DDR-II DIMM 4的相關資料，接著進至步驟S2。 於該步驟S2中，令該電子裝置之基板根據該BIOS程 式6執行記憶體初始化程序，以使該記憶體控制器1於初 始化程序中對該基板上所設之用以安裝DDR-I DIMM 3之 DIMM插槽（亦即DDR-I DIMM插槽區2 )或用以安裝 DDR-II DIMM 4 之 DIMM 插槽（亦即 DDR-II DIMM 插槽 區2’）進行存取，並對所有DRAM DIMM插槽進行SPD 資料讀取，亦即BIOS以掃描方式（由I2C位址AOH、A2H、 A4H、A6H、A8H、AAH、ACH 及 AEH 依序對 DIMM 插 槽進行掃描），以取得SPD記憶體型態欄位（即Byte 2) 之資料值，並根據該資料值而判斷DIMM插槽區為DDR-I DIMM 3或DDR-II DIMM 4，接著進行步驟S3。 於該步驟S3中，BIOS藉由讀取SPD記憶體型態欄位 (即Byte 2)之資料值做為判斷DIMM插槽是否為DDR-I DIMM 3 或 DDR_II DIMM 4 (亦即，該 Byte 2 資料值為 07 11 18379 1273435 則代表DIMM插槽區為DDR-I DIMM ;該Byte 2資料值為 08則代表DIMM插槽區為DDR-II DIMM )。故若該記憶 體控制器1判斷目前的DRAM模組為DDR-II DIMM 4，則 進至步驟S4 ;反之，則進行步驟S5。 於該步驟S4中，令該記憶體控制器1以判斷出DDR-II DIMM規格自該BIOS程式6讀取與該DDR-II DIMM規格 對應之DRAM DIMM相關資料，例如，用以宣告DDR-II DIMM硬體電路布局之變數及程式段，以供該記憶體控制 器1根據所讀取到的DDR-II DIMM相關資料對安裝於該 DIMM插槽中的DDR-II DIMM進行存取控制。 於該步驟S5中，令該記憶體控制器1以判斷出DDR-I DIMM規格自該BIOS程式6讀取與該DDR-I DIMM規格 對應之DRAM DIMM相關資料，例如，用以宣告DDR-I DIMM硬體電路布局之變數及程式段，以供該記憶體控制 器1根據所讀取到的DDR-I DIMM相關資料對安裝於該 DIMM插槽中的DDR-I DIMM進行存取控制。 綜上所述，本發明之動態隨機存取記憶體模組之存取 控制方法係根據DDR-I DIMM及DDR-II DIMM的特性而 於原有的BIOS程式中加入DDR-I DIMM以及DDR-II DIMM的相關資料，且於記憶體初始化程序中令BIOS以 掃描方式（由I2C位址AOh、A2h、…、AEh依序對DIMM插 槽進行掃描）對DIMM插槽之SPD資料進行讀取，即可判 斷出該DRAM規格為何，故俾使電子產品業者透過單一個 BIOS程式即可隨意設計及製造出以記憶體控制器支援 12 18379 1273435 DDR-I DIMM或DDR-II DIMM的基板，故本發明之動態 隨機存取記憶體模組之存取控制方法顯然能有效解決習知 電子產品業者在記憶體控制器存取DDR-I DIMM或 DDR-II DIMM時的BIOS程式設計、BIOS程式燒錄、基 板測試等過程的不便。 上述實施例僅為例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修飾 與變化。因此，本發明之權利保護範圍，應如後述之申請 專利範圍所列。 【圖式簡單說明】 第1(A)及1(B)圖係分別用以顯示使用DDR-I DIMM 及DDR-II DIMM作為記憶體模組之基板所需的基本架構 方塊不意圖， 第2圖係用以顯示應用本發明之動態隨機存取記憶體 模組之存取控制方法使記憶體控制器以同一 BIOS程式即 可對DDR-I DIMM或DDR-II DIMM進行存取控制之基本 架構方塊不意圖，以及 第3圖係用以顯示本發明之動態隨機存取記憶體模組 之存取控制方法之流程步驟示意圖。 【主要元件符號說明】 1 記憶體控制器 2 DDR-I DIMM插槽區 2， DDR-II DIMM 插槽區 13 18379 1273435 20 至 27 DIMM插槽 20,至 27， 3 DIMM插槽 DDR-1 DRAM DIMM ( DDR-I DIMM) 4 DDR-II DRAM DIMM ( DDR-II DIMM) 5,5，，6 BIOS程式 7 DDR-I DRAM的基板 7， DDR-II DRAM 的基板 S1，S2，S3，S4，S5 步驟 14 183791273435 IX. Description of the Invention: [Technical Field] The present invention relates to an access control method for a dynamic random access memory module, and more specifically, a BIOS module can be used in the same manner. An access control method for a dynamic random access memory module in which a memory controller accesses a DDR-I DRAM DIMM or a DDR-II DRAM DIMM. [Prior Art] Dynamic Random Access Memory (DRAM) has many storage products, such as desktop computers, notebook computers, servers, workstations, etc., because of its large storage capacity and low cost. It is used as the best memory solution and is one of the indispensable components of electronic products. Furthermore, in order to increase the speed of DRAM transfer, DRAM manufacturers are constantly introducing different DRAMs, such as DDR-I (Double Data Rate-I) DRAM and DDR-II DRAM, and defining memory modules through double-sided pins. (Dual In-line Memory Modules; DIMM) Slots plug these two DRAM DIMMs into a Base Board. In general, different DRAM (ie DDR-I DRAM or DDR-II DRAM) DIMMs That is, there is a corresponding DIMM slot. To support DDR-I DRAM DIMMs (hereinafter referred to as DDR-I DIMMs) and DDR-II DRAM DIMMs (hereinafter referred to as DDR-II DIMMs), Intel has also introduced DDR-I DIMMs and DDR- The II DIMM chipset Lindenhurst contains a memory 5 18379 1273435 body controller (the Lindenhurst chipset is referred to herein as the memory chip group Lindenhurst). The basic architecture required to display the substrate 7 of the DDR-I DRAM DIMM slot and the substrate 7' of the DDR-II DRAM DIMM slot, as shown in Figures 1 (A) and 1 (B), respectively. Block diagram. The two substrates (7, 7') use the same memory controller 1 (such as the memory chipset Lindenhurst introduced by Intel Corporation) and use DDR-I DIMM slot area 2 and DDR-II DIMM slot area respectively. 2', here the DIMM slot area (2, 2,) has 8 DIMM slots (20, 21, ..., 27 and 20, 21, ..., 27), and two DIMM slot areas (2, 2') Six of the DIMM slots are separately equipped with DDR-1 DRAM DIMM 3 and DDR-II DRAM DIMM 4 〇 Since DDR-1 DRAM DIMM 3 and DDR-II DRAM DIMM 4 are not compatible, The hardware design of the two is different. Therefore, although DDR-I DRAM DIMM 3 and DDR-II DRAM DIMM 4 can be supported by Intel's memory chipset Lindenhurst, if it cannot be supported at the same time, A different BIOS program (5, 5 ') must be installed on the two substrates (7, 7') to make the memory chipset Lindenhurst determine the DIMM slot area (2, 2,) specifications for which the access control object is to be executed. Why? As can be seen from the above, this practice obviously causes inconvenience to the electronics manufacturer in the process of BIOS programming, BIOS programming, and substrate testing. Therefore, how to enable electronic products manufacturers to design and manufacture substrates supporting DDR-I DIMMs or DDR-II DDR-II DIMMs with the memory chipset Lindenhurst can be freely designed and manufactured by using the same BIOS program. The problem. 6 18379 1273435 SUMMARY OF THE INVENTION In order to solve the above disadvantages of the prior art, the main object of the present invention is to provide an access control method for a sorrow random access 5 memory module, which can be used to save memory through the same BIOS program. The controller has access control for DDR-Ι dram DIMMs or DDR-II DRAM DIMMs. To achieve the above and other objects, the present invention provides an access control method for a dynamic random access memory module. The access control method for the dynamic random access memory core set of the present invention is applied to at least one first size dynamic random access memory (DRAM) module slot or at least one second size DRAM module. a slot, a memory controller, and a base of a Basic Input/Ontput System (BIOS) program for the first Dram module mounted on the DRAM module slot of the first specification or mounted on the substrate The second DRAM module of the second DRAM module slot performs access control, and the method includes at least the following steps: pre-storing the BIOS program with the first DRAM module and the second DRAM module related data; The BIOS program executes a memory initialization program (Memory Initialization); the memory controller accesses the memory module provided on the substrate in the memory initialization program, and transmits the memory module through the SM (System) Management) The bus is read by SPC (Serial Present Detect) data in accordance with the 12C protocol, and is installed according to the memory type field value of the DRAM module SPD tribute. The DRAM module slot is a first DRAM module or a second DRAM module; and the memory controller reads the 7 18379 1273435 DRAM module corresponding to the DRAM module from the BIOS program by using the DRAM module The related information is used by the memory controller to perform access control on the DRAM module installed in the DRAM module slot according to the read DRAM module related data. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. As shown in FIG. 2, the access control method of the dynamic random access memory module to which the present invention is applied enables the memory controller to use the same BIOS program for the DDR-I DRAM DIMM (hereinafter referred to as DDR-I). Block diagram of the basic architecture of access control for DIMMs or DDR-II DRAM DIMMs (hereafter referred to as DDR-II DIMMs). In this embodiment, the components required for the access control method of the dynamic random access memory module of the present invention include: a memory controller 1, a BIOS program 6, and a DDR-I DIMM slot area 2 or DDR- II DIMM slot area 2', these components are mounted on a substrate (not shown here) for mounting the electronic device of the substrate (such as a notebook computer, desktop computer, server or workstation) The same BIOS program 6 allows access control of DDR-I DIMMs or DDR-II DIMMs. It should be noted that the substrate has other various functional units. For the sake of simplicity and description, the structure herein only shows the components related to the present invention, and other unrelated components, such as the south bridge and the north bridge. Body architecture, 8 18379 1273435 is not shown in this diagram. The DRAMs on the substrate of the electronic device all use the same DRAM specification, that is, the substrate has a uniform DRAM specification. This embodiment is exemplified by DDR-I DRAM or DDR-II DRAM, and is adapted to different DRAM specifications. The corresponding DIMM Slots are provided on the substrate, that is, the DIMMs corresponding to different DRAM specifications are different in appearance to provide protection. The design function is left, so the DRAM specifications on the substrate can be installed correctly. The DDR-I DRAM module slot area 2 and the DDR-II DRAM module slot area 2 of this embodiment each have 8 DIMM slots (20, 21, ..., 27 and 20', 21', ..., 27'), wherein DIMM slots (20, 21, 22, 24, 25, and 26) of the DDR-I DRAM module slot area 2 are each mounted with a DDR-I DIMM 3, and the DDR-II DIMM is inserted Install a DDR-II DIMM4 in each of the DIMM slots (2Γ, 22', 23', 25', 26', and 27) of slot 2'. Each of the DIMMs (20, 21, 22, 24, 25, 26 and 21', 22', 23', 25, 26', 27,) has a memory such as an EEPROM (not shown here), It is used to store the DIMM parameters, which is SPD (Serial Presence Detect (SPD) data, and the SPD data of the DIMM contains the memory type (Memory Type) field. Therefore, we can know that the DIMM is DDR- by this field value. Ι or DDR-II. Furthermore, each DIMM slot has an SM (System Management) bus with two signal lines, one for the Data Line and the other for the Clock Line to connect to the 9 18379 1273435 This slot is used by the system to access the DIMM SPD data through the I2C protocol (Protocol) through the SM bus. The specification of the DIMm specifies that the I2C address specification of the DIMM slot is A〇H, A2H, A4H, A6H. , A8H, AAH, ACH and AEH. Furthermore, the number of the DIMM slots is not limited to eight as shown in the embodiment, and may be six or four, etc., depending on the embodiment. Furthermore, the memory controller 1 of the present embodiment refers to the memory chipset Lindenhurst of Intel Corporation. Since the substrate has only a single DRAM specification, the BIOS only needs to scan each mMM slot (20, 21, ..., 27, and The Memory Type Filed in the SPD data of 20', 21', ..., 27, etc. shows that the DRAM DIMMs installed in the mMM slot are DDR-Ι DIMM 3 or DDR. -II DIMM 4. SPD data has its standard definition (which is set in PC SDRAM Serial Presence Detect), where Byte 2 data represents the memory type, and its value 07 represents DDR-I DIMM; its value 08 represents DDR-II DIMM. As can be seen from the above, the BIOS scans the Byte 2 of the SPD data stored in the memory of each DIMM slot (20, 21.....27 and 20, 21, . . . 27,). The value of the Memory Type Field can be used to determine the DRAM DIMM size currently installed on the DIMM slot, and read the data (ie, program or data) corresponding to the DRAM DIMM specification from the BIOS program 6 for the electronic device. Memory initialization is completed successfully during the boot process. Since the above BIOS program and computer device boot initialization program are the necessary components and procedures for the general computer system before operation, and are also familiar to the computer technology technology, so the following will not be used for its operational functions and internal architecture of 10 18379 1273435 Description. As shown in Fig. 3, the flow chart of the access control method of the dynamic random access memory module of the present invention is shown. As shown in the figure, step S1 is first performed. Since the characteristics of DDR-I DIMM and DDR-II DIMM are different, the requirements for hardware wiring are different, such as DIMM CS (ChiP Select) configuration, I2C of DIMM slot. The address, the Japanese temple control method, the CKE pin (Pin) mode are shared or independent, and the number of DIMMs. Therefore, DDR-I DIMMs must be added to the BIOS program 6 according to the characteristics of DDR-I DRAM and DDR-II DRAM. 3 and related information of DDR-II DIMM 4, and then proceed to step S2. In the step S2, the substrate of the electronic device is executed according to the BIOS program 6 to perform a memory initialization process, so that the memory controller 1 is provided on the substrate for mounting the DDR-I DIMM 3 in the initialization process. DIMM slot (also known as DDR-I DIMM slot area 2) or DIMM slot for DDR-II DIMM 4 (also known as DDR-II DIMM slot area 2') for access and all DRAM The DIMM slot reads the SPD data, that is, the BIOS scans the DIMM slots sequentially by the I2C addresses AOH, A2H, A4H, A6H, A8H, AAH, ACH, and AEH to obtain the SPD memory. The data value of the type field (ie, Byte 2), and judge the DIMM slot area as DDR-I DIMM 3 or DDR-II DIMM 4 according to the data value, and then proceed to step S3. In the step S3, the BIOS reads whether the DIMM slot is DDR-I DIMM 3 or DDR_II DIMM 4 by reading the data value of the SPD memory type field (ie, Byte 2) (that is, the Byte 2) The data value is 07 11 18379 1273435, which means the DIMM slot area is DDR-I DIMM; the Byte 2 data value of 08 means the DIMM slot area is DDR-II DIMM). Therefore, if the memory controller 1 determines that the current DRAM module is the DDR-II DIMM 4, the process proceeds to step S4; otherwise, the process proceeds to step S5. In the step S4, the memory controller 1 reads the DRAM DIMM related data corresponding to the DDR-II DIMM specification from the BIOS program 6 by determining the DDR-II DIMM specification, for example, to announce the DDR-II. The DIMM hardware circuit layout variables and blocks for the memory controller 1 to access and control the DDR-II DIMMs installed in the DIMM slot based on the read DDR-II DIMM related data. In the step S5, the memory controller 1 reads the DRAM DIMM related data corresponding to the DDR-I DIMM specification from the BIOS program 6 by determining the DDR-I DIMM specification, for example, to announce the DDR-I. The DIMM hardware circuit layout variables and blocks are provided for the memory controller 1 to access and control the DDR-I DIMMs installed in the DIMM slot based on the read DDR-I DIMM related data. In summary, the access control method of the dynamic random access memory module of the present invention adds DDR-I DIMMs and DDR- to the original BIOS according to the characteristics of DDR-I DIMMs and DDR-II DIMMs. II DIMM related information, and in the memory initialization program, the BIOS reads the SPD data of the DIMM slot by scanning (scanning the DIMM slot sequentially by the I2C addresses AOh, A2h, ..., AEh). It is possible to determine the DRAM specification, so that the electronics manufacturer can design and manufacture a substrate with a memory controller supporting 12 18379 1273435 DDR-I DIMM or DDR-II DIMM through a single BIOS program. The access control method of the dynamic random access memory module of the invention can obviously solve the BIOS programming and BIOS programming of the memory controller when the memory controller accesses the DDR-I DIMM or the DDR-II DIMM. Inconvenience in the process of substrate testing. The above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as listed in the scope of the patent application to be described later. [Simplified Schematic] The first (A) and 1 (B) diagrams are used to show the basic architecture of the DDR-I DIMM and DDR-II DIMM as the base of the memory module. The figure is used to display the basic structure of the access control method of the dynamic random access memory module to which the present invention is applied, so that the memory controller can access and control the DDR-I DIMM or DDR-II DIMM by the same BIOS program. The block diagram is not intended, and FIG. 3 is a schematic diagram showing the flow of steps of the access control method of the DRAM module of the present invention. [Main component symbol description] 1 Memory controller 2 DDR-I DIMM slot area 2, DDR-II DIMM slot area 13 18379 1273435 20 to 27 DIMM slot 20, to 27, 3 DIMM slot DDR-1 DRAM DIMM (DDR-I DIMM) 4 DDR-II DRAM DIMM (DDR-II DIMM) 5,5,,6 BIOS 7 DDR-I DRAM Substrate 7, DDR-II DRAM Substrate S1, S2, S3, S4, S5 Step 14 18379