TWI267951B - A device having multiple silicide types and a method for its fabrication - Google Patents

Abstract

Provided are a semiconductor device and a method for its fabrication. In one example, the semiconductor device includes an active region formed on a substrate using a first silicide type and another active region formed on the substrate using another silicide type. The two silicide types differ and at least one of the two silicides is an alloy silicide. An etch stop layer may overlay at least one of the silicide regions.

Description

1267951 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to the field of semiconductor integrated circuits, and more particularly to a device having a plurality of metal-lithium forms and a method of manufacturing the same. [Prior Art] 'The material volume circuit (1C) industry has developed rapidly, and the integrated circuit (IC) material and design technology has made the product of the new generation integrated circuit (10) more compact and complicated. However, such progress will be increased. The complexity of the integrated circuit (IC) and process technology is required, so the same development is required in the fabrication of integrated circuits (ic) and processes. «The development of the touch circuit (10), when the financial (the smallest part of the production of parts) shrinks, the functional density (the number of interconnects per wafer area) increases, and the process shrinks to increase production efficiency and This reduces the cost, but such a miniaturization also results in a relatively high power consumption, especially when making low-profile miscellaneous equipment such as semi-electric m (cm〇s). "Complementary MOS semi-transistor (CMOS) consists of two different transistors, an N-type MOS transistor and a P-type MOS transistor (10) 〇s), known to be converted instantaneously. The mutual MOSQS GaN ribs only have a transistor operation, so high impedance may occur between the power line (Vdd) and the ground line (Vss), temporarily ignoring the state of switching cries. Therefore, complementary metal oxide semi-transistors (CM〇s) may contain logic gates for consumption; power generation (standbypower) in the gold-oxygen half-field transistor (10) SFET technology, self-aligned metallurgical compounds can be used ( sdf-aHgned si brain, salicide structure, which may contain a metal stone on a polycrystalline tree, in which polycrystalline forms a rare pole and a source and a difficult source to provide a gold-oxygen half-field effect Crystal (Cong FET). Metallic stone cerium can be used for human genus and base to connect foxes, such as multiple secrets, material poles and Wei Lang turn surface, will be gold ^

0503-A31625TWF 1267951 The human lithium compound is placed on the source and the drain to reduce the planar resistance of the channel between the metal contact and the underlying structure. However, the axis uses the same gold chevron in the form of the recording crystal, different transistors. The planar resistance of (eg, coffee beans and PMOS) may vary depending on the type of metal or compound used. 'There is a way to - use a variety of forms of metal lithology to make integrated circuits (5)), the device 'also provides a device with a variety of forms of metal lithology, each of which can be in the manufacturing process Adjustments are made. Moreover, it is desirable to reduce the loss of metal telluride during the contact etching process after the metallization of the device is fabricated. SUMMARY OF THE INVENTION The present invention provides an integrated circuit having a _first active region and a second active region, wherein the first active region has a -NM〇s transistor, and the first form of metal material a pattern and a tensile stress stop-stop layer (CESL) structure, and the second active region has a - PMOS transistor having a second form of metal-lithium pattern and a compressive stress contact stop Layer (CESL) structure. The first and second forms of the metal lithium pattern provide a stronger point resistance connected to the active region, and the thin side stop layer (CESL) structure helps to optimize the formation of the yk, and the formation of the π The process towel level controls the termination point. By applying the stress to the active region, the first and second contact residual stop layer (CESL) structures further increase the integrated electrical performance; in the implementation, the tensile stress of the fine side stop layer (CESL), The NMOS can have a young carrier rate, and the compression stress of the stop layer (cesl) can have a better carrier mobility; in another embodiment, a contact stop layer (CESL) It is formed only in one of the first and second active regions. The present invention discloses that a semiconductor device has a first active region and a second active region formed in a substrate; a plurality of first metallization patterns, which are composed of a first metal dream Formed by the compound, located in the first active region; a Dom-two gold chemical pattern formed by the second metal impurity, located in the second active region, which is composed of - the second metal stone Xihua 0503 A31625TWF. 1267951 is formed in the second active zone, and the second metal dreaming compound is different from the first metallization yx and the at least one metal-based alloy-alloy; and one The side stop layer covers at least the __ master secret of the first main secret and the second main dragon. At least one of the first and second active regions in the semi-body device comprises a rising source and a wire, or a structure transistor (βη stmeture threat effeet &

FmFET) structure. The first active region comprises a _N-type MOS transistor (Liss s), and the second host system comprises a P-type MOS transistor (pM〇s). The side stop layer has a -th-stress in the first-active_, and - a second stress in the second active zone. In an example, the _ stress system - tensile stress, and the second stress system - compressive stress. In the example - the first stress has a tensile stress system greater than (6) Pascal (A (8), and the second stress has a compressive stress system greater than 1 〇 9 Pascal (trans (1). The side stop layer system 匕 'material' Selecting from a nitrogen-containing material, an oxygen-containing material, and a composition thereof. The money-stopping layer contains a material selected from the group consisting of nitrite, nitrous oxide, oxidized stone, and a high dielectric value Ough- k) The material has a -k value of at least 1 (), and a composition thereof. The casting device of the invention of claim i, further comprising: a contact structure w flute to the inside of the opening D, wherein The at least-opening system extends through the side stop layer, and reaches at least the gold-injection pattern of the di-metal artifact pattern and the second metal-property pattern in the semiconductor device, the first-gold-emitting material and the first The at least one of the two metal alloys comprises a mono-metal pure substance, the first metal-wet material and the second gold core: a package-material, which is selected from Wei Lu, Wei (four) Huahe, Wei , bismuth bait, deuterated palladium and combinations thereof. In the semiconductor device, the first active region and the The second active region includes a gate dielectric layer g oxygen cut, a high dielectric value __k) material and its group 'er, ^ system has a dielectric constant of at least 1G, the high dielectric value (h-k) half (10) Electrical value (峋(4) material contains - material, which is exhausted

0503-A31625TWF 1267951 - selected from metal oxides, metal nitrides, metal halides, transition metal oxides, transition metal nitrides, transition metal halides, metal oxynitrides, metal aluminates, strontium ruthenate, aluminate鍅, -2,2,2,2,2,2,2,2,2,2,2,2,2,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5 ZrSixOy), nitrous oxide (HfSix〇yNz), aluminum oxide (A12〇3), titanium dioxide (Ή02), pentoxide (Ta205), bismuth dioxide • 'cerium dioxide (Ce〇2) , Shi Xi acid (Bi4Si2〇i2), oxidized crane (w〇3), oxidized (Y203), __ (LaA103), barium titanate (Bai_xSrxTi〇3), barium titanate (BaTi〇3), wrong Acid error (PbZr〇3), N. citrate (PbSczTal_z〇3, abbreviated as psT), _ _Zinc wrong (PbZn interesting-z〇3, abbreviated as p, wrong titanium acid error (pbZr〇3_pbTi〇3, referred to as PZT) And yttrium oxide (PbMgzNbl-z03, abbreviated!>_) and a composition thereof. In a semiconductor device, the first main secret and the second main secret system comprise a gate electrode, and the gate electrode system comprises a material selected from the group consisting of a stone material, a cerium-containing material, a metal-containing material and a composition thereof, the gate electrode comprising a material selected from the group consisting of polycrystalline stellite, polycrystalline stellite, metal, and metallic stone An oxime compound, a metal IUb material, a metal oxide, and a combination thereof. In a semiconductor device, the substrate comprises an elemental semiconductor such as a stone-like compound, the substrate comprises a compound semiconductor, and the bottom of the county comprises an alloy semiconductor. Including - material, pot selection # choose from the stone Xi (4), containing riding materials and carbon-containing materials, the alloy semiconductor purely contains, the substrate contains a -graduate stone fault structure, the substrate contains a stone cover insulating layer (5) let Such as the insulator 'SOI) structure, such as 矽 covering the insulation layer pattern. [Embodiment] The == jin exposure is related to the field of semiconductor integrated circuits, and more particularly to a paste, a singular metal halide form, and a method of manufacturing the same. ^ δ ′ NM0S and PM〇s devices use the same metal or metal alloy Shi Xi Chemical Institute

Γ〇δ ^ PMOS extremely fine _, suppressing the rotation of the pole and 汲 (four) fine number (the shirt _ is different,

0503-A31625TWF 1267951 Therefore, it is difficult for the gold recording material to have a contact plane resistance of the PMOS source and the drain. Side low NMOS and 2, August 29th, the United States _ plant code the first coffee, the heart revealed - a kind of complementary metal stone Xihua storage health, its mutual surface Wei structure to provide a mutual device For example, -N-type gold-oxygen semi-transistor (deleted and _ p-type complementary · Wei-wei structure _ lake Wei material material for micro-system 曰 仔 - - - - - - - - - - - - - - - - - - - - - - - The junction of the pole _ and the series resistance. (10) 'In the process of the joint side, there may be a problem outside the chicken (four), for example, in the deep submicron technology, such as (U Qing and its subsequent processes, metal lithium The thickness is usually less than 350 Α and is sensitive to thickness fluctuation and loss. In addition, it is difficult for the multiple metal weft structure to be side and control the termination point of the contact. If the contact does not stop at the appropriate time, % ' may generate extra The loss of the metal lithium compound 'the loss of the metal lithology during the contact surname process increases the resistance of the junction' to deteriorate the short channel effect and increase the leakage current at the junction. More details will be revealed in the following description. A contact button engraved stop layer on the contact side In the process, it can be used to minimize the loss of metal telluride. For convenience of explanation, all the diagrams indicate that *4 represents the structure, and Lu represents the PMOS structure, for example, when referring to the figure below, Please refer to the figure and the brothers 1-2, and so on, and will not repeat them. Please refer to Figure 1, in an embodiment, a complementary metal telluride is provided in a single structure, including a N-type MOS semi-transistor (NMOS) 1 〇〇 and a P-type MOS transistor (PMOS) 120 ' 观 08 100 and 卩! ^ 08 120 are on a semiconductor substrate (not shown) Manufactured. NMOS 100 includes a gate polysilicon region 1〇2, spacer layers 1〇4 and 1〇6, gate dielectric layer 108, gate metal germanide region 114, a source (not shown) and A source metallization region 116' is a poleless (not shown) and a immersion metal lithium region ns, and a contact etch stop layer (CESL or ESL) 112, such as a thin film. PMOS 120 system A gate polysilicon region 122, spacer layers 124 and 126, gate dielectric layer 128, gate metal germanide region 0503-A31625TWF 9 1 267951 - % ' / 134, a source (not shown) and a source metallization region 136, a drain (not shown) and a bungee metal lithiation region 138, and a contact Insert stop layer (CESL or off), • For example, it can be understood that other parts or other layers may exist, but the figure is not clearly shown. The 00S 100 and PMOS 12〇 on the substrate can be used by Use - elemental semiconductors, • such as single (four), polycrystalline hard, non-Japanese (four), wrong, and diamonds, - synthetic semiconductors, such as the infiltrated Shihua, Kunhua gallium ' or - alloy semiconductors, such as Shi Xixi, Shi Shen phosphorus Gallium (GaAsp), indium sulphide (AlInAs), gallium deification (A1GaAs), indium gallium phosphide (6) off and its composition. Further, the semiconductor substrate may be a semiconductor on the insulator, such as a stellite insulator (SOI). For example, the semiconductor substrate may comprise a doped epitaxial layer, a graded semiconductor layer, or a semiconducting region containing a semiconductor layer covering-different form, for example, a layer formed on the layer of the bribe. In other examples, the composite semiconductor system comprises a multiple layered structure or a multilayered semiconductor structure. The mouthwash NM0S 100 and the PM0S 120 can be fabricated using a p-type well (p-in-law and n-well) structure, and can be fabricated directly on or in a semiconductor substrate, in the example of the present invention, There is an isolation region between NM0S 100 and PM0S 120 (not shown). This secret φ region can be formed by isolation technology, such as local oxidation (LOCOS) and shallow trench isolation (STI). Furthermore, NM0S and The PM0S may have a rising source and drain structure, a fin structure field effect transistor (FinFET) structure, or a double gate structure. In addition, the NM0S and PMOS may comprise a high stress film. The gate dielectric layer 122 in the gate dielectric layer 〇2 and the gate 812 of the NMOS 100 may be any suitable dielectric material, preferably having high integrity and low leakage current, and may contain oxidation.矽, nitrous oxide oxide, or a high dielectric (highk) dielectric layer, such as oxidized, oxidized, alumina, yttria and alumina (HfOrAl 2 〇 3) alloys, or combinations thereof. nmqs gate The dielectric layer and the PMOS gate dielectric layer 122 may be doped polycrystals having the same or different doping Shi Xi. The spacers 1〇4 and 1〇6 on both sides of the NM0S gate 102, and on both sides of the pm〇s idle pole 122

0503-A31625TWF 1267951

The spacer layers 124 and 126 may comprise a dielectric layer material such as nitride nitride, bismuth oxynitride, and combinations thereof. The gasification and carbonization NMOS can include a source and a recording (not shown) formed directly on the semiconductor substrate in a 'P-well' structure or using a rising structure. Metal halides may be formed over the top of the source and gate to form source metal halide regions IK and ', and the metal metal cleavage region 118' may also be formed over the top of the polycrystalline second gate 1〇2. The metal is shredded to form a gate metal halide region 114, and the metal halide region 114, ι6, ι8 in the NMOS 100

The invention comprises nickel telluride, cobalt telluride, tungsten antimonide, antimony telluride, titanium telluride, uranium hydride, oxidized slant, palladium, or a combination thereof. The PMOS 120 may include a source and a drain (not shown) formed directly on the semiconductor substrate, in an N-well structure, or using a _raised structure, which may be at the source A metal telluride is formed over the top of the gate and the gate to form a source metal germanide region 136 and a drain metal germanide region 138, respectively, and a metal germanide may be formed over the top of the polysilicon gate 122 to form a gate metal germanium. In the object region 134, the metal telluride regions 134, 136, and 138 in the NMOS 120 include nickel telluride, cobalt telluride, tungsten telluride, telluride, titanium telluride, platinum telluride, antimony telluride, dreams, or combinations thereof.

The gate stop layers 112 and 132 may comprise a type of material, which has a high endurance in the process of the contact surname, and may protect the underlying metal telluride during the contact etching process, contacting the etch stop layer 112 and The material of 132 may be selected from an insulating material, for example, including tantalum nitride, hafnium oxynitride, tantalum carbide, niobium oxide, and combinations thereof. It is understood that contact etch stop layers 112 and 132 mean the number of layers associated with the separation. Contains a single contact residual stop layer. The contact silver stop layers 112 and 132 can be deposited using different methods, for example, the contact etch stop layers 112 and 132 can be deposited to cover a substantial area including nmos 1 and pM〇s 120, in some embodiments, The etch stop layers 112 and 132 are patterned to cover selective regions, such as only NMOS 100 or PMOS 120, or only contact regions such as source, drain, and gate, if desired, etched at the contacts to remove After the insulation material, it can be moved from the coverage area

0503-A31625TWF 11 1267951 ' In addition to contacting the etch stop layers 112 and 132. - In some embodiments, contact etch stop layers 112 and 132 may be selected and fabricated to conform to established pressure criteria, for example, forming a contact etch stop layer having a tensile stress greater than 1 〇 giga pascal to cover NMOS 1 〇〇 Similarly, the formation of a contact stop layer has a compressive stress greater than L0 gigapascal to cover pm〇s 120, and each contact stop layer 112 and 132 has a fine-tuned stress to increase efficiency, such as NM0S 1〇〇 PM〇s 12〇's carrier movement' rate. In the structure of Fig. 1, the metal telluride formed in the metal silicide regions 114, 116, 118 of the NMOS 100 (hereinafter referred to as the metal halide region) is different from the metal halide regions 134, 136 of the PMOS 120. The metal telluride formed in 138 (hereinafter referred to as the PM0S metal telluride region), for example, the NM〇S metal telluride region and the pM0S metal telluride region may all be metallized, but the forms are different, or may be It is an alloy telluride of different composition, or an alloy telluride of the same composition but having a different material ratio. In the same case, the NMOS metal telluride region may be a metal telluride, but the PM0S metal telluride region may be an alloy lithiate, or Conversely, such a metallic compound structure is sometimes referred to as a c〇mplementaiy silicide, and the complementary metal telluride provides a variable fine-tuning of the metal telluride region and the pM〇s metal telluride region to improve Contact resistance, adhesion, and consistency. In the case of a complementary metal halide, different combinations of nickel and cobalt can be used to fine tune the composition of the NM0S metallization and the PMOS metal halide to suit the desired work function and planar resistance, for example, NM0S metal. The work function of the telluride can be fine-tuned to less than 4.4 eV, but the work function of the PM0S metal telluride can be fine-tuned to be greater than 4.6 eV. It is understood that the complementary metal halide is not limited to the NMOS and PMOS structures, but may be used to form any two metal ruthenium regions connected to a substrate, wherein the first region has a first form of metal ruthenium and the second region has a The second form of metal telluride, each zone may contain a structure such as a dream change or a polycrystalline area, "source, ^ - no pole, and a gate" and then the structure of the mother area The device may include a device such as an NM0S, a PM0S, a CMOS, a fin structure, a 0503-A31625TWF 12 1267951 crystal (fm structure field effect transistor, FinFET), a bipolar transistor, an electrical device, a resistor, or combination. Referring to Figures 2a and 2b to 2h, in one embodiment, a method 2 can be used to form the complementary metal halide structure of Figure 1 having one and one pM〇s,

2h is a schematic cross-sectional view showing an integrated circuit in one of the corresponding manufacturing steps in Fig. 2a. The following is a more detailed description of the method 200 in Fig. 2a, and the cross-sectional views in Fig. 2b to 2h correspond to the reference The purpose of the present invention is understood to be that the method 200 is not limited to the formation of a complementary metal halide structure of one of the states 3, 1 and 3, but can be used to form any two regions in a semiconductor process. Wherein the first-region has -_ or the material has a different composition or material ratio than the second region. As shown in Fig. 2b, in the example of the present invention, the first zone is a NM0S 240 and the second zone is a PMOS 270, it being understood that parts of the Radisson 8 24 and the PMOS 270 can be manufactured before the method is performed. For example, the NM〇s 24〇 system includes a polycrystalline silicon gate 242, a spacer layer 246, and a gate dielectric layer 248. The PM〇s 27〇 system includes a polysilicon gate 272 and a spacer layer 274. And 276, and a gate dielectric layer 278. Referring specifically to Figures 2a and 2c, Method 2 first deposits first metal portions 250, 280 (using the same metal, A,) in accordance with step 21, to cover the respective 〇 3 24 〇 and pM 〇 s 27〇, the deposition method of the first-metal portions 250, 280 includes using physical vapor deposition (pVD), such as surface and evaporation, or electric clock, or chemical vapor deposition (CVD), such as electrical reinforcement. ^ (PECVD), atmospheric pressure CVD, low pressure, high density plasma CVD (HDPCvd) and atomic layer (10) (4), or other deposition processes, in the case of the present invention, the antimony deposit, the first metal part can be included Nickel, Si, Dan, Titanium, m or any other metal is reacted with Shi Xi at a temperature of the lift to form a metal halide of a low resistance state. ...

In the example of the present invention, the first metal portion 25 is made of nickel, and the metal material technology having a size smaller than ai3 gm in the metallization of the metal has a certain amount of gamma because other suitable metals require a lower heat supply. At relatively low temperatures, the formation of nickel in the heating step of about 2 degrees Celsius to _^, 0503-A31625TWF 13 1267951 reduces the amount of material consumed in the substrate, and thus enables pole bonding in the step. The field can be used to form nickel deposits, and nickel plating can be performed in a suitable process. 3 gas acid, a heterogeneous ammonia side to prepare the surface of the stone, and the following material = map and step 212, the metal portion can be selectively removed, leaving the complete metal part 250, which has been in the prior art It is known that lithography and side processes can be used to selectively remove the metal portion 280, including forming photoresist on the metal portions 25 and 28, converting the pattern from the reticle to the photoresist, etching, and stripping. In addition to the photoresist, it can also be etched after stripping the photoresist. The mounting is preferably based on the first metal portion 28〇. For example, if the material is nickel, the wet side process can be selected to use the surface shot. Mixture (Jeremiah 4 + Shame Pool), if the material is recorded, the wet side solution may contain a mineral acid (such as HCl) and a hydrogen peroxide solution. Referring to FIG. 2e and step 214, second metal portions 252, 282 are deposited to cover NM〇S 240 and PMOS 270, respectively, using the same metal (metal, B,) to form second metal portions 252, 282, 4 using different metals. Or a metal composition to form the first metal portions 250, 280, the deposition process may use physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the second metal portions 252, 282 may comprise nickel, tin, tungsten. , button, titanium, platinum, oblique, palladium, or any other metal, which reacts with helium at a raised temperature to form a metal halide of a low resistance state, in the present example, second metal portion 252 282 is cobalt. Referring to FIG. 2f and step 216, a metal halide is formed on both NMOS 240 and PMOS 270. However, the metal halide formed on NMOS 240 is different from the metal halide formed on PMOS 270 because of formation on NMOS 240. The metal halide includes a first metal portion 250 (metal A or nickel) and a second metal portion 252 (metal B or cobalt) (refer to alloy telluride), but the metal halide formed on the PMOS 270 is only A second metal portion 282 (recorded) is included. As depicted in Figure 2f, a metal telluride is formed at the gate, source, and drain of NMOS 240, resulting in gate metal telluride 254, source metal germanide 256, and bungee metal dream 258, 0503- A31625TWF 14 1267951, the formation of metal telluride on the gate, source and drain of PMOS 270, resulting in gate metal deuteration, 4, source metal telluride 286, and germanium metal telluride 288, gate metal deuteration 254, • source metal telluride 256, and bismuth metal telluride 258 alloy bismuth (nickel and cobalt), but gate metal lithium 284, source metal lithium 286, and bismuth metal Xixiang 288 series Shi Xi • Cobalt. The ratio of metal A/B (eg, nickel) in the alloy ceramsite can be adjusted by optimizing the metal deposition process and the hydration process to provide the desired work function; at a temperature that is elevated according to one of the particular metals selected, The deuteration process promotes the reaction between the second metal (or the first and second metals) and the antimony (or polysilicon); referring to the annealing step, in a gaseous environment, such as argon, helium, nitrogen or other inert gases, In a rapid thermal annealing (RTA) process, the reacted metallazine may be in a metastable phase or a reversed state, requiring a second annealing step or RTA (eg, based on a specific One of the metals and compounds is selected to be at a higher temperature), thus forming a stable metal telluride state with reduced electrical resistance. Such a second annealing may also be performed after the unreacted metal is removed in step 218 (described below). Steps; it will be appreciated that some metal halides such as nickel telluride may be formed in a step RTA at a lower temperature. Refer to the figure and step 218, which can be obtained from _〇3 24〇? ]〇〇827〇Remove unreacted_Metal as other areas (not shown), such as an isolation structure, the metal attached to the isolated area may not be reacted by the wire-cut layer, and the metal side solution is required for selection. In the private process, the etching can be completed in two steps. For different metals, different solutions and targets can be used in each step, and will be left on the polycrystalline gate and the source/drain contact area. Integral metallide, in general, does not require a lithography process to pattern the metallization layer of the joint, because by selective reaction and side (refer to self-alignment, salicide) The metal telluride is aligned with the gate and source/drain regions. Referring to FIG. 2h and step 220, contact etch stop layers 26A and 29A are formed. As described above, the contact etch stop layers 26A and 29B have a relatively high endurance for the contact side process, and are associated with the metal lithium compound. Mum (for example, it can adhere well to the metallurgical compound and does not react with it or

0503-A31625TWF 15

1267951 2 scattered to the lower metal halide), contact etching stop layer fine and thorough material selection, according to an insulating layer material (Figure 〒 ^ ^ ^ ^, the etchant used in the heart, for example, can be used nitrided Cong ts=M=::=layer fine and depositable covering all areas. Although it is known to use a selective deposition process, the specific sinking method can be selected according to the order of the stop layer and (4) the material, and Can be, CVD, or - heating process, and can be done in multiple steps, for example, the / τ stop layer 260 and 290 can choose _ nitride dream film, by Lpcv 〇, pEcw, or "he knows the square wire Nitrogen-cut film, for the purpose of illustration - um ^ process, can be mentioned

= low temperature fine-filament structure, in pECVD needle, can be deposited in the towel reaction, 'yuan ^ silane' and ammonia (or nitrogen), can be formed by the trimethyl zebra burning (like coffee espresso) pEcvD % (SiC), the prior art knows that the image can be used to stop the layer 260, 290 〇 / refer to the 3a and 3b to 3h diagrams, in another embodiment, the method can be used The schematic diagram of the integrated circuit is illustrated by the one of the corresponding manufacturing steps of the complementary metallization structure of the first figure having a blue (3) and "pM〇s", and the north to the 3h figure. The method 3 in Figure 3a is described in more detail below. The cross-sectional view of the % to % graph corresponds to the purpose of the eight '. It is understood that the method 3 is not limited to the formation of a complementary metal lithium structure. However, it can be used in the semiconductor process to form any two regions, wherein the first region has a composition or material ratio and the second region has a different composition or material ratio. As shown in Fig. 3b, in the example of the present invention, the first zone is a NM〇s 34〇 and the second zone is a PMOS 370, it being understood that it is possible to manufacture (10) 34〇 before performing the method 3〇〇 The PMOS 370 knives 'for example, the full 〇 〇 34 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 包含 PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS PMOS 372 372 372 372 372 372 372 372 , spacer layers 374 and 376, and 'seat dielectric layer 378.

0503-A31625TWF 16 1267951, in particular with reference to Figures 3a and 3c, the method 300 first deposits the first metal portions 350, 380 (using the same metal, A,) in accordance with step 310 to cover 34 〇 and pM 〇 s, respectively. 37. The deposition method of the first metal portions 350, 380 includes using a PVD or CVD process, the first metal. The P-knife 35〇, 380 may comprise nickel, nickel, tantalum, titanium, turn, turn, turn, or any other metal genus that reacts with the stone at a raised temperature to form a low resistance state. Metallic stone. In the example of the present invention, the first metal portions 350, 380 comprise nickel, which can be formed by bribing nickel to form a recorded deposit. In a suitable process step, the method includes: soaking the nitrogen side of the hydrofluoric acid to prepare the crucible. Surface, and subsequent splashing of nickel. Referring to Figure 3d and step 312, second metal portions 352, 382 are deposited to cover _0!5 340 and PMOS 370, respectively, using the same metal (metal, b,) to form second metal portions 352, 382, but using different Metal or metal composition to form first metal portions 35〇, 38〇, deposition process may use PVD or CVD, and second metal portions 352, 382 may include nickel, tungsten, group, titanium, platinum, rhodium, palladium, Or any other metal, which reacts with hydrazine at a elevated temperature to form a low resistance metal alloy, in the example of the invention, the second metal portion is %. Referring to FIG. 3e and step 314, the second metal portion 382 can be selectively removed leaving a complete second metal portion 352, which is known in the art to selectively remove the second metal using a lithography and etching process. The portion 382 includes forming photoresist on the metal portions 352 and 382, converting the etching pattern from the mask to the photoresist, etching, and stripping the photoresist, and etching may also be performed after stripping the photoresist, and the etching process is the most It depends on the composition of the second metal portion 382. Referring to FIG. 3f and step 316, a metal germanide is formed on both NMOS 340 and PMOS 370. However, the metal formed on NMOS 340 is different from the metal germanide formed on PM〇s 37〇 because of NMOS. The metal telluride formed on the 34th layer is an alloy telluride comprising both the first metal portion 350 (nickel) telluride and the second metal portion 352 (cobalt) telluride, but the metal formed on the PMOS 370 Shi Xixiang only contains the second metal part to move (record) Shi Xi compound. As shown in Fig. 3f, a metal, a telluride is formed on the gate, source, and drain of NM〇s 340, and 0503-A31625TWF 17 1267951 generates a gate metal fragment 354, a source metal lithium 356, and The immersion metal lithium 358' forms a metal ruthenium on the gate, source and drain of the PMOS 37, resulting in a gate metal telluride 38 source metal bismuth 386 and a germanium metal bismuth 388. Gate metal telluride 354, source metal germanide 356, and bismuth metal telluride 358 alloy bismuth (nickel and cobalt), but gate metal telluride 384, source metal telluride 386, and drain metal Telluride 388 is a nickel-deposited nickel. The ratio of metal A/B (for example, nickel/start) in the alloy ceramsite can be optimized by metal deposition.

The private and deuteration processes are adjusted to provide the desired work function; the deuteration process promotes the second metal (or first and second metal) and germanium (or polycrystalline) at a temperature that is elevated according to one of the particular metals selected The reaction between the metal sulphate; the metal sulphate of the reaction may be in a metastable phase or a stable state, requiring a second annealing step or a second annealing step, thereby forming a stable metal bismuth state. Having a reduced electrical resistance; such a third annealing step can also be performed after removing the unreacted metal in step 318 (described below); it will be understood that some metal cerium compounds such as shihua nickel can be lower It is formed in Dingba in one step at a temperature. Referring to FIG. 3g and step 318, unreacted metal can be removed from NMOS 340 and PMOS 370 as other regions (not shown), such as an isolation structure, metal wire and oxygen cut layer attached to the isolation region or The nitrogen-cut layer reaction requires the selective removal of the metal butterfly solution, which will be used in the noisy and miscellaneous/vine layouts. In general, the alloy layer of the joints is not discussed. A self-aligned metal salicide. Referring to the 3h figure and the step 32〇, the contact stop layer and 39〇 are formed. As described above, the contact side stop layer and the unique pair of thieves have a high endurance, while the money metal stone touches the touch, paving the side. The selection of the stop layer and the material, the slit in the example of the present invention, the contact engraving stop layer and the depositable coating with NMOS 340 and PMOS 37 〇, although 0 can be used - selective deposition process, - fossil eve, stone anaerobic fossil Evening, or oxidized stone eve, to form a contact with the last stop layer 36 〇 and .

0503-A31625TWF 18 1267951 _: The choice of the method can be based on the materials used to contact the wafer stop and 39 ,, and can be 3 PVD CVD, or - heating process, and can be completed in multiple steps, for example, • The contact side T-stop layers 36G and 390 may be selected from a nitrogen-cut film to form a nitride film by LPCVD, PECVD, or other known methods, for the purpose of illustration, process, extraction, and supply-low temperature process Capacitance of the underlying structure, in the pECV〇 process, can be deposited in the electropolymerization

• decane (five) ane) and ammonia (or nitrogen), which can be opened by the PECVD of trimethyl-Wei/SiC. [SiC] It is known in the prior art to use the lithography and side process to pattern the contact side stop layer 360, 390. Referring to Figures 4a and 4b to 41, in another embodiment, the method can be used to form a complementary metal-lithium structure of the first embodiment, having a pass j〇S and a pM〇s, FIG. 41 is a schematic cross-sectional view showing an integrated circuit in one of the corresponding manufacturing steps in FIG. 4A. The method 400 in FIG. 4a is described in more detail below, and the cross-sectional views in FIGS. 4b to 41 correspond to For the purposes indicated, it is understood that the method 4 is not limited to the formation of a complementary metal-lithium structure, but can be used to form any two regions in a semiconductor process, wherein the first region has a composition or material. The ratio and the second zone have a different composition or material ratio. As shown in FIG. 4b, in the example of the present invention, the first zone is an employee § 44 〇 and the second zone φ is a PM 〇 S 470, it being understood that the NMOS 440 and the PMOS can be fabricated prior to performing the method 400. In part 470, for example, the nmos 44〇 system comprises a polysilicon gate, a spacer layer 4 and a 446, and a gate dielectric layer 448. The pM〇s 47〇 comprises a polysilicon gate, a spacer layer 474, and 476, and a gate dielectric layer 478. Referring specifically to FIGS. 4a and 4c, method 400 first deposits hard mask portions 449, 479 to cover NMOS 440 and PMOS 470, respectively, in step 410. The deposition method of hard mask portions 449, 479 includes using a pvD process. , CVD process, or one of the high/reaction reactions between nitrogen or oxygen' hard mask portions 449, 479 may comprise oxidized stone, cerium nitride, carbonized; ceram, or a combination thereof, for example, by high temperature CVD , LPCVD, or PECVD to form a nitride, which can be reacted by dichloromethane (siCUH2) and ammonia (NH3) to form LPCVD nitrogen.

0503-A31625TWF 19 1267951 -$ ▼ The formation of oxidized stone by thermal oxidation or cvd process, the formation of niobium carbide (Sic) by PECVD of trimethyl-stone. ", with reference to Figure 4d and step 412, the hard mask portion 449 can be selectively removed, leaving a complete, more masked mask, 9 which is known in the prior art to use lithography and side processes to selectively The removable, hard mask portion 449 includes photoresist formed on the hard mask portions 449 and 479, the pattern is transferred from the mask to the photoresist, and the photoresist is stripped, and the photoresist can also be stripped. After the side, the side process is preferably based on the material of the mask, for example, after photoresist coating, exposure, and development, according to a pre-designed pattern on the mask to convert to the photoresist for drying. φ etched carbide hard mask. Referring to Fig. 4e and the steps, the first metal portions wo,·# are respectively covered with Lishui 3 440 and PMOS 470, and the same metal (metal, A,) is used to form the first metal portions 45〇, 48〇, and the deposition process can be performed. Using PVD or CVD, the first metal portion may comprise nickel, tin, tungsten, group, titanium, turn, or any other metal, reacting it with a stone at a raised temperature to open a low resistance In the example of the present invention, the first metal portions 45A, 480 are recorded. Referring to FIG. 4f and step 416, a metal lithium compound is formed on the NMOS 440, and the nmos 440 is formed. The metal telluride contains only the first metal portion 450 (e.g., metal A or nickel) germanide, however, since the PMOS 470 is covered by the hard mask 479, the metal A (nickel) containing the first metal portion 480 cannot be combined with pm〇S a 470 or a polycrystalline germanium reaction. As shown in Fig. 4f, a metal telluride is formed on the gate, source, and drain of nm〇s 440 to generate a gate metal telluride 454, a source metal germanide 456, and Bungee metal telluride 458, based on specific gold At the elevated temperature, the deuteration process promotes the reaction between metal A and germanium (or polysilicon); the deuteration process may include a second annealing step to cause the metallization of the annealed reaction to be metastable ( Metastable phase, or transforming the steady state, and forming a stable metal halide state with reduced electrical resistance; such a second annealing step may also be performed after removing unreacted metal in step 418 (described below); Some metal lithium 0503-A31625TWF 20 1267951: a compound such as nickel telluride can be formed in a step RTA at a lower temperature. • Referring to Figure 4g and step 418, the NMOS 440 and PMOS 470 can be removed. Reaction • Metal 'like other regions (not shown), such as an isolation structure, the unreacted metal attached to NMOS 440 contains the residue of metal A after step 418; is connected to the isolation region, nitriding • Shi Xi / oxidation The metal layer of Shishi, and the metal of PM〇S 470 (on which the hard mask is covered) does not react with the oxidized stone layer or the layer of nitrite, and a gold can be used. It is removed in a residual manner, leaving a complete metal cerium compound on the polysilicon gate and source/no-pole contact regions on Nm〇s 440. Refer to Figure 4h and step 420 to remove the hard from PMOS 470. The mask portion 479 can be removed by an etching process such as wet etching or dry etching to remove the hard mask portion 479, for example, in wet etching, an etching solution can be selected, in tantalum nitride and other materials (including There is a high etch selectivity between yttrium oxide and metal ruthenium. Referring to Figure 4i and step 422, second metal portions 452, 482 are deposited to cover NMOS 440 and PMOS 470, respectively, using the same metal (metal ruthenium). The second metal portions 452, 482, but using different metals or metal composites to form the first metal portions 450, 480, the deposition process can use PVD or CVD, and the metal portions 452, 482 can include records, inscriptions, irons, groups , ruthenium, platinum, rhodium, palladium, or any other metal that reacts with hydrazine at a elevated temperature to form a metal halide of a low low resistance state, in the present example, second metal portion 452, 482 It is cobalt. Referring to FIG. 4j and step 424, a metal germanide is formed on both NMOS 440 and PMOS 470. However, the metal halide formed on NMOS 440 is different from the metal germanide formed on PMOS 470 because NMOS 44 is on The formed metal halide is an alloy telluride comprising both a first metal portion 450 (metal A or nickel) telluride and a second metal portion 452 (metal B or cobalt) germanide, but formed on the PMOS 470 The metal lithium compound only contains the second metal portion 482 (cobalt) telluride. As depicted in Figure 4j, a metal telluride is formed on the gate, source, and drain of NMOS 440, resulting in a gate metal germanide 454, a source metal germanide 456, and a germanium metal germanide 458, in PMOS 470. Metal cleavage is formed on the gate, source and drain, resulting in gate metal deuteration 0503-A31625TWF 21 1267951 484, source metal telluride 486, and germanium metal telluride 488, gate metal telluride 454, source The polar metal lithium 456 and the bismuth metal lithium 458 alloy shi shi (recorded and recorded), but the gate metal hydride 484, the source metal hydride 486, and the ruthenium metal 488 system ! Ancient 0 As previously described, during step 416, a metal A telluride is first formed on NMOS 440. In the current step 424, metal A telluride on NMOS 440 reacts with metal B to form an alloy telluride. . The ratio of metal A/B (eg nickel/start) in the alloy telluride can be adjusted by optimizing the metal/child process and the Shihua process to provide the required work function'. At the temperature, the deuteration process promotes the reaction between the second metal (or the first and second metals) and the stone (or polycrystalline stone); the reaction of the metallization may be in a metastable phase. Or a second annealing step or rta is required in the conversion of the stable state, so that the formation of the -stabilized metallization state has a reduced electrical resistance, and after the removal of the unreacted metal in the step (described below), Such a second annealing step is carried out; it will be understood that some metal impurities such as Wei-nickel may be formed in the step rta at a lower temperature. Referring to Figure 4k and step 426, unreacted metal may be removed from the toilet (3) 44〇 and pM〇s 47〇, as in other areas (not shown), such as an isolation structure, the metal attached to the isolation area may not be associated with The oxygen cut or the Nina layer reaction requires selective removal using a metal solution, leaving a complete gold shot on the polycrystalline soot and source-contact areas. Referring to FIG. 41 and step 428, contact side stop layers 460 and 490 are formed. As described above, the contact side stop layer and the contact side process have a relatively high endurance, and contact with the silver stop layer 460. And the choice of 490 materials may be based on an insulating material mountain (not shown) to conform to the surname used, for example, using nitrite, oxynitride, or yttrium oxide to form contact. The money is carved to stop the layer and 3 as. In the example of the present invention, the 'contact side stop layer 46' and the depositable cover all areas 0 and PMOS 470, although it is known that a selective deposition process can be used, the specific deposition method can be selected according to the contact etch stop layer and The materials used, and can be ^

0503-A31625TWF

22 1267951 / 匕 'PVD, CVD, or a heating process, and can be completed in multiple steps, for example, contact with the stop layer and optional - nitrogen cut film, by LPCVD, PECVD, or, he is known The method forms a nitride film, which is used for the purpose of illustration, and provides a low temperature process compatible with the underlying structure. In the pECVD process, it can be deposited in the electrical assembly.

, 矽 ( (811 咖 ) and ammonia (or nitrogen), can be reduced by trimethylsilane PECVD, minus g ^ Sl C) 'previously known fine micro-shadow and side-cut case contact money stop Layers 460, 490 〇 refer to FIG. 5a and FIGS. 5b to 5i, and in another embodiment, method 5 〇〇 can be used to form the complementary metal halide structure of FIG. 1 having one and one pM〇s, 5b • The schematic diagram of the integrated circuit is illustrated in one of the corresponding manufacturing steps in the diagram of the Θ, 曰, 曰 弟, 5, and the following section explains the method 5〇〇, section 5b to 5i in Fig. 5a. The schematic diagram corresponds to the purpose thereof, and it is understood that the method 5 is not limited to the formation of an intermetallic metallurgical structure, but can be used to form any two regions in the semiconductor process, wherein the first region has A composition or ratio of materials and the second zone has a distinct composition or ratio of materials. As shown in FIG. 5b, in the example of the present invention, the first zone is a _ 〇 354 〇 and the second zone is a PMOS 570, it being understood that _ 〇 3 54 制造 can be fabricated before the method 5 进行• Part of PM〇S 570, for example, S 540 includes a polysilicon gate 542, spacer layers 544 and 546, and a gate dielectric layer 548, which includes a polysilicon gate 572, Spacer layers 574 and 576, and a gate dielectric layer 578. Referring specifically to Figures 5a and 5c, method 500 first deposits first metal portions 550, 580 (using the same metal, A,) in accordance with step 510 to cover Li Wei 8 54〇 and pM〇s 57〇, respectively. The deposition of a metal portion 550, 580 includes the use of a PVD or €1) process, a first metal. The P-knives 550, 580 may comprise nickel, tin, tungsten, ruthenium, titanium, turn, bait, free, or any other metal that reacts with helium at a raised temperature to form a metal halide of a low resistance state. In the example of the present invention, the first metal portion 55〇, 58〇 contains nickel, which can be formed by sputtering nickel to form nickel, and in a suitable process step, including: soaking hydrofluoric acid, before sputtering Argon etching

0503-A31625TWF 23

1267951 ; Prepare the surface of the crucible, and then the nickel plating.

• Referring to Figure 5d and step 512, second metal portions 552, 582 are deposited to cover NM0S • 540 and TM〇S 570, respectively, using the same metal (metal, B,) to form a second metal portion, 5 phantoms, but using Different metals or metal composites to form first metal portions 55〇, 58〇, deposition process • PVD or CVD may be used, and second metal portions 552, 582 may include nickel, cobalt, tungsten, button, titanium, platinum, rhodium, Palladium, or any other metal, reacts with hydrazine at a elevated temperature to form a low resistance sorrow metal slag. In the present example, the second metal portions M2, M2 are inscribed. Referring to FIG. 5e and step 5M, the third metal portions 553, 583 are deposited to cover the NMOS 540 and the PMOS 570, respectively, and the third metal portions 553, 583 are formed using the same metal (metal, A,) as the first metal portion 550. 580, forming a factory sandwich structure, forming a layer of metal B (nickel/recording/recording) between the two layers of metal a, the deposition process may use pvD or CVD, and the third metal portions 553, 583 may comprise nickel, lead, Tungsten, Syrian, titanium, turned, oblique, absolutely, or any other metal, reacting with the dream at a temperature of -lifting to form a gold-emitting material in a low-sister state, in the present example, the second metal portion 553 583 is nickel, which can be formed by sputtering nickel to form nickel. In a suitable process step, immersing hydrofluoric acid is called the argon side of the clock to prepare the surface of the stone, and then sputtering nickel. φ Referring to FIG. 5f and step 516, the third metal portion 583 can be selectively removed leaving a complete third metal portion 553, which is known in the art to selectively remove the third using lithography and engraving processes The metal portion 583 includes forming a photoresist on the metal portions M3 and 583, converting a money pattern from the photomask to the photoresist, engraving, and stripping the photoresist, and may also perform the engraving after stripping the photoresist. The magnetic flux is preferably based on the composition of the third metal portion 583. For example, if the material is recorded, a wet etching process may be employed using a metal etching solution such as a mixture of sulfuric acid and hydrogen peroxide. Referring to FIG. 5g and step 518, a metal cerium compound is formed on both NM〇s 54〇 and pM〇s, but the metal formed on the NMOS 540 is different from the metal formed on the contact Shi Xi Compound 'Because of the metal lithology formed on the NMOS · an alloy alloy Xi's contains a large amount of metal A (such as nickel)' However, the metal yttrium formed on PM〇s 57〇 is 0503-A31625TWF 24 1267951 - Contains a small amount of metal A, in other words, both alloy compounds containing metals A and B (such as nickel and cobalt), but with different compositions. • as depicted in Figure 5g, a metal-lithium compound is formed on the gate, source, and drain of NMOS 540 to produce gate metal germanide 554, source metal germanide 556, and drain metal germanide 558, Metallic ceramide is formed on the gate, source and immersion of PM0S 570, resulting in gate metal lithium 584, source metal telluride 586, and ruthenium metal telluride 588, gate metal crystallization 554, Source metal telluride 556, and bismuth metal telluride 558 series alloy telluride, containing a large amount of metal A (nickel), but gate metal telluride 584, source metal telluride 586, and ruthenium metal ruthenium 588 series alloy telluride containing a small amount of metal A. The ratio of metal (eg, nickel/ruthenium) in the alloy telluride can be adjusted by optimizing the metal deposition process and the deuteration process to provide the desired work function; the deuteration process is carried out at a temperature that is selected according to one of the particular metals selected Promoting a reaction between the second metal (or the first and second metals) and the ruthenium (or polycrystalline stone); the reacted metal halide may be in a metastable phase or a stable state. The second annealing step or RTA, thus forming a stable metal telluride state, has a reduced electrical resistance; it is also possible to perform such a second annealing step after removing the unreacted metal in step 52G (described below), it being understood that Some metal materials such as nickel can be formed in a step RTA at a lower temperature. Referring to Figure 5h and Step 52, unreacted metals can be removed from NMOS 54〇 and pM〇s 57〇, as in other regions (not shown), such as isolation structures, metals attached to the isolation regions may not The coam layer or the nitriding pin reaction requires the gamma side solution for selective removal' to leave a complete metal artifact on the polycrystalline seconds gate and source/drain contact areas. Referring to the first diagram and step 552, the contact formation stop layers 56〇 and 59〇 are formed. As described above, the contact engraving stop layers 560 and 590 have a relatively high endurance for the joint surname engraving process, and are associated with the metal lithium compound. Compatible, the contact side stop layer _ and (4) may be selected according to an insulating material _ not shown to conform to the side agent used, for example, gas cutting, nitrous oxide, stone reversal, or oxidation may be used. Shi Xi, to form a contact with the stop layer 56 and other.

°503-A3l625TWF 25 1267951 / In the example of the present invention, the contact residue stop layers 560 and 590 may deposit all of the regions 3 〇S 540 and PM 〇S 570, although it is known to use a selective deposition process, a specific sink The selection method can be selected according to the materials used in the contact stop layers 560 and 590, and can be performed by a CVD or a hot-melt process, and can be completed in multiple steps, for example, a 4-contact magnetic stop layer 56G and 59G selectable - nitriding second film, formed by nitriding film by LPCVD, PECVD, or other known methods, for the purpose of illustration - PECVD violet process, can provide - the process is compatible with the underlying structure, in pECVD In the process, it is possible to deposit Shi Xizhuo (four) lang and ammonia (or nitrogen) in the plasma right, which can be reversed by the formation of trimethyl decane (Mmethylsilane). The lithography and engraving process pattern contacts the surname stop layers 560, 590. Multi-test 6a and 6b to 6ι' In another embodiment, a method 6〇〇 can be used to form the 1® intermetallic metallurgical structure having - and _ pM〇s, The image is taken from the corresponding manufacturing step in Fig. 6a to illustrate a schematic cross-sectional view of the integrated circuit. The method 600 of Fig. 6a is described in more detail below, and the cross-sectional view of Fig. 6b to Fig. corresponds to its function. The purpose of the invention is understood to be that the method 6 is not limited to the formation of a complementary metallization structure, but may be used to form any two regions in the semiconductor wafer process, and the towel region has a composition or The material ratio and the second zone have a different composition or material ratio. ^ As shown in FIG. 6b, in the example of the present invention, the first region is a cis (10) 64 〇 and the second region PMOS 67 〇 ' It is understood that the surface "ο and PMOS 670 can be fabricated before the method 6 is performed. Μ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' Still, spacer layers 674 and 676, and a gate dielectric layer 678. Special surface, 6a and 6e ® , method 6GG first according to step (10), depositing the first metal portion 650, 680 (using the same metal 'a ,) to cover Li Wei 8 64〇 and pM〇s 67〇, respectively, the deposition method of the first metal portions 650, 680 includes using a pvD sCVD process, the first metal portions 650, 680 may comprise nickel, Ming, crane, surface , 鈇, turn, oblique, finch, or any other gold

0503-A31625TWF 26 1267951 is a gold-emitting compound that is formed at a temperature of the elevated temperature and formed by Wei. 2 In the example of the present invention, the first metal portion 65〇, (4) is included in the recording, and can be formed by a smear to form a recorded squirrel in a suitable process step: soaking hydrogen _, - the argon side before the 贱 以Prepare the surface of the crucible 'and the subsequent sputter nickel. Referring to Figure 6d and step 612, the first metal portion 68A can be selectively removed leaving a complete - metal portion 650, which is known in the art to use lithography and engraving to selectively A metal portion 680' includes a photoresist formed on the metal portions 650 and 68〇, and the paste pattern is switched from a mask to a fine ±, side, and age photoresist, and can also be used to supplement the light etching. It is based on the first metal portion 680. Referring to FIG. 6e and step 614, second metal portions 652, 682 are deposited to cover _〇5 640 and PMOS 670, respectively, using the same metal (metal, B,) to form second metal portion 652, anvil 2, but using different metals Or a metal composition to form the first metal portions 65〇, 68〇, the deposition process may use PVD or CVD, and the second metal portions 652, 682 may comprise nickel, tin, tungsten, ruthenium, titanium, platinum, rhodium, palladium, or Any other metal, which reacts with helium at a raised temperature to form a metal-lithium compound of a low resistance state, in the example of the present invention, the second metal portion 652 is the first. The third metal portions 653, 683 are deposited to cover the respective portions of the ^^\403 φ 640 and the PM0S 670, and the third metal portions 653, 683 are formed using the same metal (metal, A,) as described in FIG. The first metal portions 650, 680 form a "sandwich" structure on the NMOS 640, forming a layer of metal B (nickel/start/nickel) between the two layers of metal A, and the deposition process can use PVD or cvd, the second metal Portions 653, 683 may comprise nickel, melamine, cast, button, titanium, turn, solution, ki, or any other metal that reacts with yttrium at a elevated temperature to form a metal halide of a low resistance state, In the example of the present invention, the third metal portions 653, 683 are nickel, which can be formed by sputtering nickel to form nickel, including immersion of hydrofluoric acid in a suitable process step, and argon etching prior to sputtering to prepare Shi Xi surface, and the town of Qian Zhong. Referring to FIG. 6g and step 618, a metal ruthenium compound is formed on both the NMOS 640 and the PMOS 670. However, the metal ruthenium formed on the NMOS 640 is different from the metal formed on the pm 〇S 670 by 0503-A31625TWF 27 1267951 - Telluride, because the metal telluride formed on NMOS 640 is an alloy alloy, containing a large amount of metal A (such as nickel), but the metal sulphate package formed on PM0S 670 - containing a small amount of metal A, In other words, both are alloy compounds containing metals A and B (such as nickel and cobalt), but with different compositions. • As depicted in Figure 6g, 'metal cerium compound is formed on the gate, source, and drain of NMOS 64, resulting in gate metal telluride 654, source metal telluride 656, and drain metal lithium 658. A metal telluride is formed on the gate d and the drain of the PMOS 670, resulting in a gate metal germanide 684, a source metal germanide 686, and a gate metal germanide 688, a gate metal germanide 654, 0 source. Metal telluride 656, and bismuth metal telluride 658 alloy telluride, containing a large amount of metal A (recorded), but gate metal scrap 684, source metal scrap, and eutectic metal telluride 688 alloy Telluride, containing a small amount of metal A. The ratio of metal (eg, nickel/start) in the alloy telluride can be adjusted by optimizing the metal deposition process and the deuteration process to provide the desired work function; the deuteration process is carried out at a temperature that is elevated according to one of the particular metals selected Promoting a reaction between the second metal (or the first and second metals) and the dream (or polycrystalline dream); the metal halide of the reaction may be in a metastable phase or a stable state. The second annealing step, the thief RTA, thus forming a stable metal propagule state with reduced electrical resistance; Lu may also perform such a second annealing step after removing unreacted metal in step 620 (described below); understandable Some metal halides, such as nickel telluride, can be formed in a step RTA at a lower temperature. Referring to Figure 6h and step 620, the unreacted metal can be removed from 64〇 and pM〇s 67〇 as other regions (not shown), such as the isolation structure, the metal attached to the isolation region may not be associated with The oxidation of the oxidized stone layer or the nitriding layer requires the use of a metal meal solution for selective removal of f to leave intact ages on the polycrystalline slab gate and source-level contact regions. Referring to FIG. 6i and step 652, the contact side stop layers _ and _ are formed. As described above, the contact side stop layers 660 and 690 have a relatively high endurance for the joint engraving process, and are compatible with the metal debris, and the contact side stops. Layer _ and _ material selection, based on an insulation

0503-A31625TWF 28 1267951 _ layer material (not shown) to conform to the etchant used, for example, tantalum nitride, oxynitride, strontium carbide, tantalum oxide, or yttria may be used to form contact etch stop layer 660 And 690. In the example of the present invention, contact etch stop layers 660 and 690 can be deposited to cover all regions including NMOS 640 and PMOS 670. Although it is known to use a selective deposition process, the particular sink method can be selected based on the contact etch stop layer. The materials used in 660 and 690, and may include PVD, CVD, or a heating process, and may be performed in multiple steps, for example, contact etch stop layers 660 and 690 may select a tantalum nitride film by LPCVD, PECVD, or other known methods to form a tantalum nitride film, for the purpose of illustration using a PECVD process, can provide a low temperature process compatible with the underlying structure, in the PECVD process, can be deposited in the plasma (silane) and gas (or nitrogen), tantalum carbide (SiC) can be formed by trimethyl sulphide (pEcyj), which is known in the prior art to pattern contact etch stop layers 660, 690 using lithography and etching processes. Referring to FIG. 7a and FIGS. 7b to 7e, in another embodiment, a method 7A can be used to form a dual contact etch stop layer (dual CESL) and the complementary metal germanide structure of FIG. 1 has an NMOS. And a PMOS, the 7b to 7e diagram depicts a cross-sectional view of the integrated circuit illustrated in one of the corresponding manufacturing steps in FIG. 7a, and the method 7 〇〇 7b to 7e in FIG. 7a is described in more detail below. The cross-sectional schematic diagram corresponds to the purpose of the reference, and it is understood that the method 700 is not limited to the formation of a complementary metal-lithium compound and a two-contact stop stop layer (iualCESL) structure. As shown in Fig. 7b, In an embodiment of the invention, method 70 first provides a complementary metal halide structure having a first region, such as NMOS 740, and a second region, such as PMOS 770, in accordance with step 71. For example, NMOS 740 includes a polysilicon. Gate 742, spacer layers 744 and 746, and a gate dielectric layer 748, and a first metal halide metal halide pattern 754, 756, 758; PMOS 770 includes a polysilicon gate 772, spacer layer 774 And 776, and a gate dielectric layer 778, a second metal halide metal halide pattern 784, 786, 788. The complementary metallization structure of NM〇s 740 and PMOS 770 can be fabricated prior to performing method 700; Prior to CESL), a method of 0503-A31625TWF 29 1267951 is similar to one of methods 200 to _, forming a complementary structure of faces w(10) and (10); for example, by - process, including Forming a first metal layer to selectively remove the first metal layer from the second region to form a second metal to cover the first region and the second region Forming metal fragments on the _ region and the second region to remove unreacted metals from the first region and the first region to form a complementary metal bismuth structure of NMQS 740 and PMOS 770. 7a and 7c, method 7〇〇, step 712, forming a contact stop layer (cesl) in νμμ 74〇 and PMOS 770, which forms a contact side stop layer (CESL) similar to the method 2〇〇 to _. > test 7_ and step Sichuan, by _ A patterning process, such as a lithography process, can be used to implant an ion implant mask 765 on a ray, for example, a photoresist layer can be placed on the surface of the 〇74〇 and pM〇s 77〇, and then a lithography is used. The process patterning the photoresist, removing the photoresist layer covering the (five) 70 after development, leaving the photoresist layer covering the NMOS 740. [Material No. and Step 716, when the S 74 is covered by the ion implantation mask 765 When protected, the lamp ion implantation process can release the contact side stop layer ([) 760 in the pM〇s region. The stress is divided so that the contact etch stop layer in the pM〇s region can be converted into a contact paste stop layer (c disorder), which has different stresses, and the implanted ions can contain germanium or other suitable ions, which can be micro Nazi planted the ship and energy to get the required stress. /, E, and 8b to 8k, in another embodiment, a method of 8 〇〇, a complementary metal metal structure of the graph and a double contact side stop layer (·ι ', 冓 can be used. An example of the corresponding manufacturing steps in the figure b to 8k is illustrated as a schematic diagram of the integrated circuit. The following is a detailed description of the method in FIG. 8a, and the cross-sectional view of the 8th to the digraph corresponds to For the purposes of the present invention, it is to be understood that the method 800 is not limited to a complementary metal-lithium structure and a complementary contact stop layer (c〇_emen_乱(五) as shown in FIG. 8b' in the present invention example , method _ first follow the steps in the preparation, provide

0503-A31625TWF 30 1267951, a complementary metal structure has a -first region, such as NMOS84G, and - a second region, ># such as PMOS 870 ' It is understood that the toilet bowl 8 can be manufactured before the method is fine. 84〇• and PM0S 870 parts; for example, the Gus S 840 series includes a polycrystalline slab gate 842, spacer layers 844 and 846, and a gate dielectric layer 848, and the PM〇s 87 system contains a polycrystal. 787, 872, 876, and a gate dielectric layer 878. • Referring to Figure 8a and the & Figure, method _ proceeds to step 812 to form a first layer; the electrical layer (ILD) 862 'and then selectively removes at least - part thereof, which may have been The first interlayer dielectric layer (10) is formed and then selectively removed such that the first interlayer dielectric layer (ILD) 862 covers the MOS __, but exposes the PMOS 870. Referring to the figure and step 814, the first metal lithium material is used in the PMOS 870 by a suitable method to open the metal lithium pattern, _, and 888 of the metal-lithium compound. Referring to FIG. 8e and step 816, a -contact-etch etch stop layer (CESL) 863 is formed to cover the drain and the gate (10) by a method similar to that of the method 2 to 7 - The contact stop layer (CESL) 863 has a tensile stress, a composition of the first engraving stop layer (CESL) 863 and a contact etching stop layer (CESL) similar to that described in methods 2A through 6(8) In an example, the first contact side stop layer (CESL) 863 may comprise tantalum nitride formed by a low pressure chemical vapor deposition (LPCVD); / The degree of process parameters such as the degree of the dish, the micro-na _ pick-up stop layer (cesl) 863 stress, but also through the ion implants, such as the lion implant, 峨 stress. Referring to Figure 8f and step 818, a second interlayer dielectric (ILD) 864 can be formed over the etched and etched regions to cover the first contact stop layer (CESL) 863. Referring to the Sg diagram and the step 82, the second interlayer dielectric layer (10) 864 and the first contact side stop layer ((10) 863 are selectively removed from the toilet 〇 _ _ area by the lithography and side process methods. And a first interlayer dielectric layer (ILD) 862. Referring to the 8th figure and the step δη, the second gold is used by a method similar to the step method

0503-A31625TWF 31 1267951: is a material material 'formed in NMOS 840 - a second metal consumable metal material pattern - 854, 856, and 858. • Referring to FIG. 8i and step 824, a second contact etch stop layer (CESL) 865 is formed to cover both the NM0S 840 and PMOS 870 regions, and the second contact etch stop layer (CESL) contains a compressive stress, second. The composition of the contact stop layer (CESL) 865 and the formation of a contact etch stop layer (CESL) similar to that described in methods 200 through 600, in an example, the first contact side stop layer (CESL) 865 can include Nitride, formed by plasma enhanced chemical vapor deposition (PECVD); fine-tuning the first contact stop layer (CESL) 863 by process parameters such as 矽/nitrogen ratio and deposition temperature Stress can be fine-tuned by ion implantation processes such as cesium ion implantation. Referring to FIG. 8j and step 826, a third interlayer dielectric layer (Liaogong j) may be formed to cover the NM0S 840 and the second contact stop layer (cesl) 865 of the PMOS 870. Referring to FIG. 8k and step 828, the planarization process can be used to remove the metal crystallization compound of pM〇s 87〇 by a suitable process such as chemical mechanical polishing (CMp), planarization of NM0S 840 and PM0S 870'. a third interlayer dielectric layer (ild) 866 and a second contact etch stop layer (CESL) 865 over the pattern 884, and partially removing a second interlayer dielectric layer (ILD) 864 in the same region, thus pM〇s φ The second interlayer dielectric layer (ILD) 864 of 870 and the third interlayer dielectric layer 彳 ILD 866 of NMOS 840 may be coplanar. The first interlayer dielectric layer (ILD) 862, the second interlayer dielectric layer (ild) 864, and the third interlayer dielectric layer (ILD) 866 comprise: dioxide dioxide, spin-coated glass (spil) K) Nglass, s〇G), Doxite Glass (FSG), Polyimide, Carbon Doped Cerium Oxide, Black Diamond (Black

Diamond, Applied Materials of Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, poly-p-xylylene (卩& Bicyclobenzene (1^-]^112 (^ 1 1 13 blood 1 milk, 8 (^), 1 ^ (Dow Chmical, Midland, Michigan), or other materials. Interlayer dielectric layer (ILD) ) can be formed by chemical vapor deposition (CVD), spin coating, physical vapor deposition (pvd), atom 0503-A31625TWF 32 1267951: layer deposition (ALD) or other processes. The stop layer (CESL) 863 and the second contact stop layer (CESL) 865 • A high endurance for the contact etch process, and compatible with metal telluride, the first contact stop layer (CESL) 863 And the composition and shape of the second contact etch stop layer (CESL) 865 can be respectively based on the second interlayer dielectric layer (ILD) 864 and the third interlayer dielectric layer (ild) 866, for example, the first contact etch stop Layer (CESL) 863 and second contact etch stop layer (CESL) 865 may comprise cerium nitride, nitrogen oxide; Carbonization; eve, or other suitable materials. Interconnects can be formed in the NMOS and PMOS regions. For example, an interlayer dielectric layer (ild) 864 can be patterned in pM〇s 870 and A third interlayer dielectric layer (ILD) 866 in the NMOS 840 to form a contact opening, the contact opening extending to the metal germanide patterns 884, 886, and 888 in the PM 〇 s 87 ,, and the metal in the NMOS 840 The lithology patterns 854, 856, 858. For example, the interlayer dielectric layer (ILD) may be etched first, and then the contact side stop layer (CESL) is etched in a subsequent process, and the pattern method includes lithography and side processes. The side process further includes a plurality of steps to remove the interlayer dielectric layer (ILD) structure and the contact etch stop layer (CESL) to expose the metal lithium pattern for connection, and the conductive material filled in the contact opening is substantially Similar to the composition of the gate electrodes 842 and 872, the filled conductive material can be planarized by a suitable process such as chemical mechanical polishing (CMP) to form a contact pattern, using other suitable processes, such as a dual damascene process, To form other interconnections The drawings, such as the vias and the metal wires, are well-received as described above, and are intended to be illustrative of the invention, and those skilled in the art, without departing from the spirit and scope of the invention, A number of changes and modifications may be made. Therefore, the scope of protection of the present invention is subject to the definition of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1-1, 1-2 are diagrams showing an exemplary structure of the present invention. Figure 2a shows a flow chart of the _first-exemplary method for manufacturing the first-order structure. 33

0503-A31625TWF

1267951 '21st>1, 2b-2 to 2h-l, 2h-2 diagram is a schematic cross-sectional view of the structure of the μ1, 丨_2 diagram according to the method of Fig. 2a. Figure 3a is a flow chart depicting a second exemplary method of fabricating a third, 1-2, structure. The 3b-l, 3B-2 to 3h-l, 3h-2 diagrams are schematic views of the structure of the 1-1, 丨 2 diagram structure according to the method of Fig. 3a. Figure 4a is a flow chart depicting a third exemplary method for fabricating the structure of the μ, 1-2. The 牝_1, 4b_2 to 41-1, 41-2 diagrams are based on the method of Fig. 4a, and the cross-sectional view of the structure process of Fig. 1, 丨-2 is fabricated. ► Figure 5a is a flow chart depicting a fourth exemplary method for fabricating the structure of the first, 1-2. 5b-1, 5b-2 to 5i-1, and 5i-2 are schematic cross-sectional views showing the structure of the first 1-U-2 structure according to the method of Fig. 5a. Fig. 6a is a flow chart showing a fifth exemplary method for fabricating the mth, uth figure structure. Figures 6b-1, 6b-2 to 6i-1, and 6i-2 are schematic cross-sectional views showing the structural process of Figures 1-1, 1-2 in accordance with the method of Figure 6a. Fig. 7a is a flow chart showing a sixth exemplary method for fabricating the structure of the μ, 丨-2. Figures 7b-1, 7b-2 to 7e-1, and 7e-2 are schematic cross-sectional views of the structural process of Figures 1-1, 1-2 according to the method of Figure 7a. Figure 8a is a flow chart depicting a seventh exemplary method for fabricating a third, μ2 map structure. 8b-l, 81> 2 to 8k_1, 8k_2 are schematic cross-sectional views showing the process of the structure of Figs. 1-1, 1-2 according to the method of Fig. 8a. [Major component symbol description] N-type gold oxide semi-transistor (丽〇8) ~1〇〇, mo, 340, 440, 540, 640, 740, 840; P-type gold oxide semi-transistor (PMOS) ~ 120, 270, 370, 470, 570, 670, 770, 870; 0503-A31625TWF 34 1267951 _ polysilicon gates - 102, 122, 242, 272, 342, 372, 442, 472, 542, 572, 642, 672, 742, 772, 842, 872; spacers ~ 104, 106, 124, 126, 244, 246, 274, 276, 344, 346, 374, 376, 444, 446, 474, 476, 544, 546, 574, 576, 644 646, 674, 676, 744, 746, 774, 776, 844, 846, 874, 876; gate dielectric layers ~108, 128, 248, 278, 348, 378, 448, 478, 548, 578, 648 , 678, 748, 778, 848, 878; first metal parts ~ 250, 280, 350, 380, 450, 480, 550, 580, 650, 680; | second metal parts ~ 252, 282, 352, 382, 452, 482, 552, 582, 652, 682; gate metal telluride ~ 114, 134, 254, 284, 354, 384, 454, 484, 554, 584, 654, 684, 754, 784, 854, 884; Source metal halides ~116, 136, 256, 28 6, 356, 386, 456, 486, 556, 586 '656, 686, 756, 786, 856, 886; bungee metal telluride ~ 118, 138, 258, 288, 358, 388, 458, 488, 558, 588, 658, 688, 758, 788, 858, 888; contact etch stop layer ~ 112, 132, 260, 290, 360, 390, 460, 490, 560, 590, 660, 690, 760, 790; 硬 hard cover Curtain ~ 449, 479; third metal part ~ 553, 583, 653, 683; ion implantation mask ~ 765; first layer dielectric layer ~ 862; brother one contact money to stop layer ~ 863; second floor Dielectric layer ~ 864; Di two contact money to stop the layer ~ 865; third layer dielectric layer ~ 866.

0503-A31625TWF 35

Claims (1)

1267951 X. Patent application scope: 1. A semiconductor device comprising: a substrate having a first active region and a second active region; and a plurality of first metal halide patterns formed by a first metal halide Located in the first active region; a plurality of second metal halide patterns formed by a second metal germanide in the second active region, wherein the second metal germanide is different from the first a metal telluride, and at least one of the metal telluride-based alloy telluride; and an etch stop layer covering at least one active region of the first active region and the second active region. 2. The semiconductor device of claim 1, wherein the first active region comprises an N-type metal oxide semiconductor (NM〇s), and the second active region comprises a p-type gold oxide Semi-transistor (PMOS). 3. The semiconductor device of claim 1, wherein the etch stop layer has a first stress in the first active region and a second stress in the second active region. 4. The semiconductor device of claim 3, wherein the first stress is a tensile stress and the second stress is a compressive stress. 5. The semiconductor device of claim 4, wherein the tensile stress is greater than 1 〇 9 Pascal. 6. For example, the cap device patent 4th reincarnation device, the brain device should be 1 〇 9 kPa (pascal) 〇 7 対 专利 专利 专利 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体The self-nitrogen-containing material is selected as an oxygen-containing material, and combinations thereof. The U-reduction of the first embodiment of the cast body H-ray lining =, the valve from the nitrogen cut, cut, fine, - Gona (10)-k) material has a k value of at least 10, and its composition. 9. The semiconductor guide according to __ i, further comprising a contact pattern, 0503-A31625TWF 36 1267951 being formed in at least one opening, wherein the at least one opening extends through the etch stop layer to reach At least one metal ruthenium pattern of the first metal ruthenium pattern and the second metal ruthenium pattern. 10. The semiconductor device of claim 1, wherein at least one of the first metal ruthenium compound and the second metal ruthenium compound comprises a single metal ruthenium compound. The semiconductor device according to claim 1, wherein the first metallization and the second metal halide comprise a material selected from the group consisting of nickel antimonide, cobalt telluride, tungsten antimonide, and antimony telluride. , bismuth platinum, bismuth bait, bismuth palladium and combinations thereof. The semiconductor device of claim 1, wherein the first active region and the second active region comprise a gate dielectric layer pattern. 〃13. The semiconductor device according to claim π, wherein the gate dielectric layer pattern comprises a material selected from the group consisting of oxidative dream, nitrogen cut, nitrogen oxynitride, high dielectric value (five) or Materials and compositions thereof. 14. The semiconductor device of the full-time gf 13, wherein the high dielectric value (higli_k) material has a dielectric constant of at least 1 〇. 15. The semiconductor device of claim 13, wherein the high dielectric value (high_k) material comprises a material selected from the group consisting of metal oxides, metal nitrides, metal halides, and transition metal oxides. , transition metal nitride, transition metallazine, metal oxynitride, metal aluminate, strontium ruthenate, strontium aluminate, strontium dioxide (Hf〇2), cerium oxide (Zr〇2), nitrogen Yttrium oxide (ZrOxNy), Hb〇xNy, HfSix〇y, UrSixOy, HfSix〇yNz, Al2O3 , Dioxin (Ti〇2), pentoxide (Ta2〇5), antimony trioxide (LaA), bismuth dioxide (Ce〇2), Shixi acid (Bl4Si2012), oxidized town (W03), Yttrium oxide (γ2〇3), barium aluminate (LaAi〇3), barium titanate (Bai_xSrxTi〇3), barium titanate (BaTi〇3), wrong acid (pbZr〇3), group acid sharpness ( PbScZTal-z〇3, abbreviated as PST), zinc citrate (pbZnzNM_z〇3, abbreviated as pzN), hammered titanium oxalate (PbZK) 3-PbTi03, referred to as PZT), oxidized to (ugly gz _z〇3, referred to as 0503-A31625TWF 37 1267951 PMN) and combinations thereof. The first active region and the semiconductor device second active region as described in claim 1 include a gate electrode.半. The device according to claim 16, wherein the gate electrode-material is selected from the group consisting of a stone material, a material containing a metal, a metal-containing material and a composition thereof. 18. The semiconductor device according to claim 17, wherein the electrode assembly comprises a material selected from the group consisting of polycrystalline, polycrystalline, metal, metal, metal nitride, metal Oxides and compositions thereof. The semiconductor device of claim 1, wherein at least the main active area and the second active H-belt comprise a raised source and a drain. 20. The semiconductor device of claim j, wherein the first active region and the active region of the active region comprise a fin structure field effect transistor (FinFET) structure. The semiconductor device of claim 2, wherein the substrate comprises a mono-element semiconductor. The semiconductor device of claim 21, wherein the elemental semiconductor comprises a material selected from the group consisting of germanium and germanium. The semiconductor device of claim 1, wherein the substrate comprises a compound semiconductor. The semiconductor device of claim 1, wherein the substrate comprises an alloy semiconductor. 25. The semiconductor device of claim 24, wherein the alloy semiconductor comprises a material selected from the group consisting of germanium containing materials, germanium containing materials, and carbonaceous materials. 26. The semiconductor device of claim 25, wherein the alloy semiconductor system comprises Jane. The semiconductor device of claim 1, wherein the substrate comprises a gradual structure of 0503-A31625TWF 38 1267951. /8. For example, the patent device of the patent shed is the semiconductor device of the lion, wherein the substrate comprises a silicon on insulator (SOI) structure. 29. The semiconductor device of claim 28, wherein the cast overlying insulating layer structure comprises a germanium overlying insulating layer pattern. 30. A method of fabricating a semiconductor device, comprising: providing a substrate having a -first active region and a second active region, wherein the first active region and the second silk region respectively comprise a -metal Wei and 1 two gold shots; forming a side stop layer having a -th stress to cover the crane-main secret active region; forming a mask layer on the first active region; then ion implantation is performed to stop the etching The layer; and then removing the mask layer. 31. The method of making a semi-conducting method for the semi-conducting of the patent application 30, the money-stopping layer-containing process, which is selected from the chemical deposition method (PVD). Fly-phase continuation (CVD) and physical gas phase 32_ as described in the scope of claim 3 () of the patent application, in which the first active [upper/in-cover layer, The inclusion-resist layer is included. The fourth method of forming a semiconductor device in the first active region comprises: providing a substrate, having a first active region and a second component, the second active and the second active Forming gold on the region; selectively removing the first gold handle from the second main impurity; forming a first metal layer on the first active region and the second active region (4) The younger brother & and the second active virtue form a metal halide in the basket; and • U such as: S°° and the second active region form an etch stop. 34. The method of manufacturing a vestibule layer garment according to claim 33, wherein the forming of the 0503-A31625TWF 39 1267951 / the first metal layer, the second metal layer, and the silver stop layer comprises a process It is selected from chemical vapor deposition (CVD) and physical vapor deposition (pVD). ^ ... 35 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 After the first master of the machine-covering layer, the second active_ion implanted the side stop layer. 36. A method of fabricating a semiconductor device, comprising: providing a substrate having a first active region and a second active region; forming an N-type MOS transistor in the first active region (NM〇) s), and forming a -P type MOS transistor (PM 〇s) in the ruthenium active region; forming a _th dielectric layer on the first active region and the second active region; Forming a first dielectric layer on the first active region; forming a first-metal layer on the first active region and the second active region; forming a plurality of first metal halide patterns in the first active region; Forming a tensile stress residual stop layer on the first active region and the second main secret; forming a third dielectric layer on the first silk region and the second main secret; moving from the second active region In addition to the second dielectric layer, the tensile stress side stop layer and the first | dielectric layer; forming a second metal layer on the first active region and the second active region; Forming a plurality of second metallization patterns; forming a compressive stress engraving stop layer on the Xuantin active region and the second active region; Forming a third dielectric layer on the first-wire region and the second active region; and planarizing the first active region and the second active region. The method of fabricating a semiconductor device according to claim 36, wherein the planarizing the active region and the second active region comprise a chemical mechanical planarization (CM?) process. 38. The method of fabricating a semiconductor device according to claim 5, wherein the flattening active region and the eleven active region comprise: removing the third from the second active region; the dielectric layer 0503-A31625TWF 40 1267951 and the second etch stop layer. The method of manufacturing a semiconductor device according to claim 5, wherein the flattening filament-active region and the second main secret system comprise: removing the second dielectric from the second main secret portion Floor. 1# 4〇·If applying for the manufacturing method of the transfer of the Wei, the metal layer, the second metal layer, the first stop layer, the second engraving stop layer, The first dielectric layer, the second dielectric layer and the third dielectric layer comprise a process of using a process: a selective phase deposition (CVD) method and a physical vapor deposition method (pvD). ). , 41. A method of fabricating a semiconductor device, comprising: providing a substrate having a -first active region and a second active region, wherein the first active region and the second primary secret system respectively comprise - a gold emitter a region and a second gold chevron region. an active side stop layer having a -th stress covering the first active region and the second forming a -first rhyme stop layer in the first active region, having - the first stress - forming a second side stop layer in the second active region, having - a second: force · forming a dielectric layer to cover the first active region and the second primary having a stop layer and the second side stop layer; and the plurality of contact holes formed by the pair of holes, through the dielectric layer, and through the two side stop layers, the substrate. The side stop layer and the plurality of contact holes of the semiconductor device according to the invention of claim 4 include the dielectric layer. The plurality of contact holes of the semiconductor device according to claim 41, wherein the first etch stop layer is etched and the etch stop layer is formed. Inscribed stop layer at least one of 0503-A31625TWF 41