1261675 玖、發明說明： 一、 發明所屬之技術領域 本黍明係關於一種晶體振盪器，特別係關於一種可自广 校準之晶體振盖器，其可縮短成品之檢測時間以降低整: 測試成本。 a 二、 先前技術 晶體振盪器一般係應用於需要穩定輸出頻率之電子產品 中，例如仃動電話機等移動式通信電子產品。此類晶體振 盪器大多採用頻率在1GMHz左右之AT截斷（Ατ_石英 片作為振動源來構成振盧電路。由於該截斷石英片之 幸則出頻率會ρ思其週圍纟溫度而改變，因此實作上必須設計 一種溫度補償電路以消除該Ατ截斷石英片之輸出頻率的 變異。 圖1例7F — AT截斷石英片之輸出頻率對週圍溫度之關 係圖。如圖1所示’該Ατ截斷石英片之輸出頻率與週圍 溫度大致呈三次曲線關係，例如：。該三 次曲線可分成低溫、中溫及高溫等三個溫度區間。在低溫 度區間（-35 c至約+10°C )中，該曲線包含正斜率之線性區 域及改變斜率極性之非線性區域。在中溫度區間（+1(rc至 + 50C)’孩曲線具有負斜率之線性區域。在高溫度區間（+ 5〇 C至+90 C )，該曲線包含正斜率之線性區域及改變斜率極 性之非線性區域。 圖2係一習知之晶體振盪器丨〇之電路圖。如圖2所示， 該晶體振盥為1 0包含一溫度檢測電路1 2、一振盪電路201261675 玖, invention description: 1. Technical Field of the Invention The present invention relates to a crystal oscillator, in particular to a crystal calibrator that can be self-calibrated, which can shorten the inspection time of the finished product to reduce the whole: test cost . a Second, prior art Crystal oscillators are typically used in electronic products that require a stable output frequency, such as mobile communication electronics such as squeaking telephones. Most of these crystal oscillators use AT cutoff at a frequency of about 1GMHz (Ατ_ quartz plate as a vibration source to form a vibrating circuit. Since the truncated quartz plate is fortunate, the frequency will change depending on the temperature around it, so the implementation A temperature compensation circuit must be designed to eliminate the variation of the output frequency of the Ατ cutoff quartz plate. Figure 1 Example 7F - AT cutoff quartz plate output frequency versus ambient temperature. As shown in Figure 1, 'the Ατ cut off quartz The output frequency is roughly in a cubic relationship with the ambient temperature, for example: The cubic curve can be divided into three temperature ranges of low temperature, medium temperature and high temperature. In the low temperature range (-35 c to about +10 ° C), The curve contains a linear region of positive slope and a non-linear region that changes the polarity of the slope. In the mid-temperature range (+1 (rc to + 50C)' the curve has a linear region with a negative slope. In the high temperature range (+ 5〇C to + 90 C ), the curve contains a linear region of positive slope and a nonlinear region that changes the polarity of the slope. Figure 2 is a circuit diagram of a conventional crystal oscillator, as shown in Figure 2, the crystal oscillator 10 comprises a temperature detecting circuit 12, an oscillating circuit 20
HAHLAHYGV,,1设科技\88〇47\88〇47.DOC 1261675 以及一溫度補償電路40。該振盪電路20包含一 AT截斷石 英片22、一並聯於該AT截斷石英片22之回授電阻24以 及一並聯於該AT截斷石英片22之反相器26。該晶體振盪 器1 0之輸出端28係自該反相器26之輸出側拉出。該振盪 電路20另包含分別電氣連接於該AT截斷石英片22二端 之二直流截斷電容32、34以及二可變電容36、38。該溫 度檢測電路12可利用一熱敏電阻檢測該AT截斷石英片22 週圍之溫度，而該溫度補償電路40則依據來自該溫度檢測 電路12之溫度檢測信號將該振盪電路20之輸出頻率維持 為一預定值。 該溫度補償電路40包含一記憶電路42及一數位/類比轉 換電路44。該記憶電路42 —般係由非揮發性記憶體構成， 用以記憶進行溫度補償所需的補償資料（即用以描述三次 曲線之參數）。該數位/類比轉換電路44則根據該補償資料 及來自該溫度檢測電路12之溫度檢測信號而輸出一控制 電壓，該控制電壓係分別施加於該可變電容36、38之正極 以調整其振盪電容。如此，即可控制該振盪電路20之振盪 頻率，而使得該晶體振盪器10之輸出頻率維持在產品規格 容許之範圍内。 由於該AT截斷石英片22係以機械方式（雷射光）切割而 成，因此每一片AT截斷石英片22之厚度及切割角度並不 完全相同，導致其溫度-頻率特性亦彼此相異。同理，該晶 體振盪器1 〇之電子元件之間亦存在製程漂移所造成之特 性差異。综而言之，該晶體振盪器1 〇彼此之間存在著因製 -6- 1261675 造程序所產生之差異，因此每一晶體振盪器1 〇之溫度-頻 率特性亦不相同，故必須量測每一晶體振盪器1 〇在操作之 溫度區間（高、中、低三個溫度區間）之溫度-頻率特性，並 據以產生溫度補償資料後寫入該記憶電路42中。然而，個 別地量測每一晶體振盪器1 0之溫度-頻率特性是一件相當 耗費時間的工作，導致該晶體振盪器10之整體測試成本急 劇增加。 三、發明内容 本發明之主要目的係提供一種可自行校準之晶體振盪 器，其可縮短成品之檢測時間以降低整體測試成本。 為了達到上述目的，本發明揭示一種可自行校準之晶體 振盪器，其包含一相位比較器、一電氣連接於該相位比較 器之第一輸入端之時脈訊號墊、一電氣連接於該相位比較 器之第二輸入端之振盪元件、一電氣連接於該相位比較器 之輸出端之類比/數位轉換器以及一電氣連接於該類比/數 位轉換器之輸出端之記憶體。該振盪元件係一溫度補償型 振盡元件或一表面聲波振盛元件，而該記憶體係一非揮發 性記憶體。 本發明之可自行校準之晶體振盪器可另包含一設置於該 相位比較器之第一輸入端與該時脈訊號墊間之第一開關、 一設置於該振盪元件與該時脈訊號墊間之第二開關以及一 用以控制該第一開關及該第一開關之邏輯控制元件。當該 晶體振盪器在進行自行校準時，該第二開關係處於關閉狀 態且該第一開關係處於開啟狀態，因此一參考時脈可經由 HAHUXHYGVh1丨朵科技\88047\88047.D〇r 1261675 該時脈訊號墊傳送至該相位比較器之第一輸入端。相對 地，當該晶體振盪器欲輸出一時脈訊號時，該第一開關係 處於關閉狀態且該第二開關係處於開啟狀態，因此該振盪 元件之時脈訊號經溫度補償後可經由該時脈訊號墊而穩定 地輸出。 相較於習知技藝，由於本發明之晶體振盪器在接收到該 校準訊號後即可自行進行校準，因此在並聯複數個晶體振 盪器後一測試機台可同時（平行地）進行溫度校準。如此， 該測試機台所消耗之校準時間係由該複數個晶體振盪器均 分，因而降低每一個晶體振盪器之校準時間以降低其測試 成本。 四、貫施方式 圖3係本發明之可自行校準之晶體振盪器50之示意圖。 如圖3所示，該可自行校準之晶體振盪器50包含一振盪元 件52、一電氣連接於該振盪元件52之積體電路60、一時 脈訊號墊62、一電源墊64、一接地墊66以及一控制墊68。 該振盪元件52可為一溫度補償型振盪元件或一表面聲波 振盛元件。 圖4係本發明之積體電路60之功能方塊圖。如圖4所 示，該積體電路60包含一相位比較器70、一電氣連接於 該相位比較器70之輸出端70C之類比/數位轉換器80以及 一電氣連接於該類比/數位轉換器80之輸出端80C之記憶 體90。該時脈訊號墊62係電氣連接於該相位比較器70之 第一輸入端70A，而該振盪元件52係電氣連接於該相位比HAHLAHYGV,, 1 set technology \88〇47\88〇47.DOC 1261675 and a temperature compensation circuit 40. The oscillating circuit 20 includes an AT cut-off quartz chip 22, a feedback resistor 24 connected in parallel to the AT-cut quartz plate 22, and an inverter 26 connected in parallel to the AT-cut quartz plate 22. The output terminal 28 of the crystal oscillator 10 is pulled out from the output side of the inverter 26. The oscillating circuit 20 further includes two DC blocking capacitors 32, 34 and two variable capacitors 36, 38 electrically connected to the two ends of the AT cut-off quartz plate 22, respectively. The temperature detecting circuit 12 can detect the temperature around the quartz cut-off quartz piece 22 by using a thermistor, and the temperature compensating circuit 40 maintains the output frequency of the oscillating circuit 20 according to the temperature detecting signal from the temperature detecting circuit 12. A predetermined value. The temperature compensation circuit 40 includes a memory circuit 42 and a digital/analog conversion circuit 44. The memory circuit 42 is generally constructed of non-volatile memory for memorizing the compensation data required for temperature compensation (i.e., to describe the parameters of the cubic curve). The digital/analog conversion circuit 44 outputs a control voltage according to the compensation data and the temperature detection signal from the temperature detecting circuit 12, and the control voltages are respectively applied to the positive electrodes of the variable capacitors 36 and 38 to adjust the oscillation capacitance thereof. . Thus, the oscillation frequency of the oscillation circuit 20 can be controlled such that the output frequency of the crystal oscillator 10 is maintained within the range allowed by the product specifications. Since the AT cut-off quartz piece 22 is mechanically cut (laser light), the thickness and cutting angle of each of the AT-cut quartz pieces 22 are not completely the same, resulting in different temperature-frequency characteristics. Similarly, there is a difference in characteristics caused by process drift between the electronic components of the crystal oscillator. In summary, the crystal oscillator 1 〇 has a difference between the -6-1261675 process, so the temperature-frequency characteristics of each crystal oscillator 1 亦 are different, so it must be measured Each crystal oscillator 1 is temperature-frequency characteristic of the operating temperature range (high, medium, and low temperature intervals), and is written into the memory circuit 42 according to the temperature compensation data. However, measuring the temperature-frequency characteristics of each crystal oscillator 10 individually is a rather time consuming task, resulting in a dramatic increase in the overall test cost of the crystal oscillator 10. SUMMARY OF THE INVENTION The primary object of the present invention is to provide a self-calibrating crystal oscillator that reduces the inspection time of the finished product to reduce overall testing costs. In order to achieve the above object, the present invention discloses a self-calibrating crystal oscillator comprising a phase comparator, a clock signal pad electrically connected to a first input end of the phase comparator, and an electrical connection to the phase comparison. An oscillating component of the second input of the device, an analog/digital converter electrically coupled to the output of the phase comparator, and a memory electrically coupled to the output of the analog/digital converter. The oscillating element is a temperature compensated oscillating element or a surface acoustic wave oscillating element, and the memory system is a non-volatile memory. The self-calibrating crystal oscillator of the present invention may further comprise a first switch disposed between the first input end of the phase comparator and the clock signal pad, and disposed between the oscillating element and the clock signal pad a second switch and a logic control element for controlling the first switch and the first switch. When the crystal oscillator is self-calibrating, the second open relationship is in a closed state and the first open relationship is in an open state, so a reference clock can be via HAHUXHYGVh1 technology\88047\88047.D〇r 1261675 The clock signal pad is transmitted to the first input of the phase comparator. In contrast, when the crystal oscillator is to output a clock signal, the first open relationship is in a closed state and the second open relationship is in an open state, so that the clock signal of the oscillating element can be temperature compensated through the clock. The signal pad is output stably. Compared with the prior art, since the crystal oscillator of the present invention can perform self-calibration after receiving the calibration signal, the temperature can be simultaneously (parallelly) calibrated after a plurality of crystal oscillators are connected in parallel. Thus, the calibration time consumed by the test machine is divided by the plurality of crystal oscillators, thereby reducing the calibration time of each crystal oscillator to reduce the test cost. Fourth, the mode of implementation Figure 3 is a schematic diagram of the self-calibrating crystal oscillator 50 of the present invention. As shown in FIG. 3, the self-calibrating crystal oscillator 50 includes an oscillating component 52, an integrated circuit 60 electrically connected to the oscillating component 52, a clock signal pad 62, a power pad 64, and a ground pad 66. And a control pad 68. The oscillating element 52 can be a temperature compensated oscillating element or a surface acoustic wave oscillating element. 4 is a functional block diagram of the integrated circuit 60 of the present invention. As shown in FIG. 4, the integrated circuit 60 includes a phase comparator 70, an analog/digital converter 80 electrically coupled to the output 70C of the phase comparator 70, and an electrical connection to the analog/digital converter 80. The memory 90 of the output terminal 80C. The clock signal pad 62 is electrically connected to the first input end 70A of the phase comparator 70, and the oscillating element 52 is electrically connected to the phase ratio.
l-BHLAHYGW,朵科技\8S047\S8047.DOC 1261675 較器70之第二輸入端70B。該記憶體90係一非揮發性記 憶體。 本發明之積體電路60可另包含一設置於該相位比較器 70之第一輸入端70A與該時脈訊號墊62間之第一開關 72、一設置於該振盪元件52與該時脈訊號墊62間之第二 開關74以及一用以控制該第一開關72及該第二開關74 之邏輯控制元件76，其中該第二開關74之資料流方向相 反於該第一開關72。該邏輯控制元件76運作所需之工作 時脈可由一内建時脈產生器（例如電阻電容時脈產生器）提 供。該積體電路60可另包含一電氣連接該電源墊64及該 邏輯控制元件76之高壓偵測器78。 當該晶體振盪器50在進行自行校準時，該邏輯控制元件 76關閉該第二開關74且開啟該第一開關72。因此一測試 機台可經由該時脈訊號墊62及該第一開關72輸入一參考 時脈至該相位比較器70之第一輸入端70A。該相位比較器 70比較該參考時脈與該振盪元件52之時脈並產生一相位 差訊號（即頻率誤差訊號），而該類比/數位轉換器80則將該 相位差訊號轉換成一數位訊號（溫度補償資料）後由一升壓 電路（pumping circuit)儲存於該記憶體90。 相對地，當該晶體振盪器50欲輸出一時脈訊號時，該邏 輯控制元件76將關閉該第一開關72並開啟該第二開關 74。該數位/類比轉換器82則根據儲存於該記憶體90之溫 度補償資料及來自該溫度檢測器84之溫度檢測信號而輸 出一控制電壓以校準該振盪元件52之時脈，因此該振盪元 H:\HLAHYGV„Y^B:W:ic\88〇47\88047.DOC -9- 1261675 件52之時脈經溫度補償後可經由該第二開關74及該時脈 訊號墊62穩定地輸出。 圖5係本發明之晶體振盪器50之運作流程圖。如圖5 所示，首先檢查該電源電壓是否高於一臨限電壓，其中該 臨限電壓可設成例如120%之電源電壓。若該電源電壓低於 該臨限電壓，該晶體振盪器50係處於正常運作模式並輸出 經溫度補償之時脈訊號。若該電源電壓係高於該臨限電 壓，則檢查環境溫度是否為最後一個校準溫度（一般而言， 晶體振盪器需分別在低溫、中溫、高溫三個溫度區間進行 校準）。若係最後一個校準溫度，則終止校準程序。若不是 最後一個校準溫度，則致能該振盪元件52並自該時脈訊號 墊62輸入一參考時脈。之後，該相位比較器70比較該參 考時脈與該振盪元件52之時脈並產生一相位差訊號（即頻 率誤差訊號）。該類比/數位轉換器80接著將該頻率誤差訊 號轉換成一數位訊號，並經由一升壓電路寫入該記憶體 90。之後，將該振盪元件52關閉並進行下一個溫度之校準。 圖6係本發明之晶體振盪器50之並聯示意圖。由於本發 明之晶體振盪器50在接收到一高於電源電壓120%之電壓 (即校準訊號）後即可自行進行校準，因此可並聯複數個晶 體振盪器50之時脈訊號墊（CLK)62、電源墊（Vdd)64、接地 墊（GND)66及控制墊（PDN)68後再由一測試機台由該時脈 訊號墊62輸入該參考時脈，並經由該電源墊64輸入該校 準訊號以啟動該邏輯控制元件76。之後，每一個晶體振盪 器50之邏輯控制元件76即可自行控制並進行溫度校準程 HAHmHYGVA朵科技\88047\88047.DOC - 1 0 - 1261675 =準亦即’每—個晶體振㈣外係同時（平行地）進行溫度 圖7係本發明之特殊應用積體電路_之功能方塊圖。 :;圖”斤示，該特殊應用積體電路1〇。包含一系統匯流排 • -電氣連接於系統匯流排122之内峨理器⑶、 -電氣連接於該系統匯流排122之系統記憶體126、一時 脈=號墊1〇2、-電氣連接於該時脈訊號#⑽之相位比 U〇、—電風連接於該相位比較器110之輸出端11 oc 之類比/數位轉換器12〇。該類比/數位轉換器⑽亦電氣連 接於該系統匯流排122，以便將其輸出經由該系統匯流排 122傳送至該系統記憶冑m。該特殊應用積體電路⑽ 另包含-設置於該相位比較# UG之第—輸人端應與 該時脈訊號塾102間之第一開關112以及一設置於一外部 振盪元件130與該時脈訊號墊1〇2間之第二開關114。 該特殊應用積體電路100在進行該外部振盛元件13〇之 溫度校準時’ f亥内嵌式處理器124經由該系統匯流排122 傳运控制扣令以關閉該第二開關1 14並開啟該第一開關 112。因此一測試機台可經由該時脈訊號墊丨〇2及該第一開 關II2輸入一參考時脈至該相位比較器11〇之第一輸入端 110A。涊相位比較器11〇比較該參考時脈與該外部振盪元 件130之時脈並產生一相位差訊號（即頻率誤差訊號），而 該類比/數位轉換器i 2 〇則將該頻率誤差訊號轉換成一數位 訊號（溫度補償資料）後經由該系統匯流排122而儲存於該 系統記憶體126。l-BHLAHYGW, Duo Technology \8S047\S8047.DOC 1261675 The second input 70B of the comparator 70. The memory 90 is a non-volatile memory. The integrated circuit 60 of the present invention may further include a first switch 72 disposed between the first input terminal 70A of the phase comparator 70 and the clock signal pad 62, and a clock signal disposed on the oscillating component 52 and the clock signal. A second switch 74 between the pads 62 and a logic control element 76 for controlling the first switch 72 and the second switch 74, wherein the data flow direction of the second switch 74 is opposite to the first switch 72. The operational clock required for operation of the logic control element 76 can be provided by a built-in clock generator (e.g., a resistor-capacitor clock generator). The integrated circuit 60 can further include a high voltage detector 78 electrically coupled to the power pad 64 and the logic control component 76. When the crystal oscillator 50 is self-calibrating, the logic control element 76 turns off the second switch 74 and turns on the first switch 72. Therefore, a test machine can input a reference clock to the first input terminal 70A of the phase comparator 70 via the clock signal pad 62 and the first switch 72. The phase comparator 70 compares the reference clock with the clock of the oscillating element 52 to generate a phase difference signal (ie, a frequency error signal), and the analog/digital converter 80 converts the phase difference signal into a digital signal ( The temperature compensation data is then stored in the memory 90 by a pumping circuit. In contrast, when the crystal oscillator 50 is to output a clock signal, the logic control element 76 will turn off the first switch 72 and turn on the second switch 74. The digital/analog converter 82 outputs a control voltage according to the temperature compensation data stored in the memory 90 and the temperature detection signal from the temperature detector 84 to calibrate the clock of the oscillating element 52. Therefore, the oscillating element H :\HLAHYGV„Y^B:W:ic\88〇47\88047.DOC -9- 1261675 The clock of the 52 is stably outputted via the second switch 74 and the clock signal pad 62 after temperature compensation. 5 is a flow chart showing the operation of the crystal oscillator 50 of the present invention. As shown in FIG. 5, it is first checked whether the power supply voltage is higher than a threshold voltage, wherein the threshold voltage can be set to, for example, a power supply voltage of 120%. The power supply voltage is lower than the threshold voltage, and the crystal oscillator 50 is in a normal operation mode and outputs a temperature compensated clock signal. If the power supply voltage is higher than the threshold voltage, check whether the ambient temperature is the last one. Calibration temperature (generally, the crystal oscillator needs to be calibrated in three temperature ranges: low temperature, medium temperature, and high temperature.) If the last calibration temperature is used, the calibration procedure is terminated. If it is not the last calibration temperature, it is enabled. The oscillating element 52 inputs a reference clock from the clock signal pad 62. Thereafter, the phase comparator 70 compares the reference clock with the clock of the oscillating element 52 and generates a phase difference signal (i.e., a frequency error signal). The analog/digital converter 80 then converts the frequency error signal into a digital signal and writes the memory 90 via a boost circuit. Thereafter, the oscillating element 52 is turned off and the next temperature is calibrated. A parallel schematic diagram of the crystal oscillator 50 of the present invention. Since the crystal oscillator 50 of the present invention can perform self-calibration after receiving a voltage higher than 120% of the power supply voltage (ie, the calibration signal), a plurality of crystal oscillations can be connected in parallel. The clock signal pad (CLK) 62, the power pad (Vdd) 64, the ground pad (GND) 66, and the control pad (PDN) 68 of the device 50 are then input by the test machine from the clock signal pad 62. And inputting the calibration signal via the power pad 64 to activate the logic control component 76. Thereafter, the logic control component 76 of each crystal oscillator 50 can be self-controlled and perform a temperature calibration process HAHmHYGVA Technology \88047\88047.DOC - 1 0 - 1261675 = quasi-that is, 'every crystal oscillator (four) external system simultaneously (parallel) temperature diagram 7 is a functional block diagram of the special application integrated circuit of the present invention. The figure shows that the special application integrated circuit is 1〇. A system bus bar is included: - an internal processor (3) electrically connected to the system bus bar 122, - a system memory 126 electrically connected to the system bus bar 122, a clock = pad 1, 2, - electrically connected to the The phase of the clock signal #(10) is proportional to U〇, and the electric wind is connected to the analog/digital converter 12〇 of the output terminal 11 oc of the phase comparator 110. The analog/digital converter (10) is also electrically coupled to the system bus 122 for transmitting its output to the system memory 胄m via the system bus 122. The special application integrated circuit (10) further includes a first switch 112 disposed between the input end and the clock signal 塾102, and an external oscillating element 130 and the clock. The second switch 114 between the signal pads 1 and 2. The special application integrated circuit 100 performs the temperature calibration of the external oscillating element 13 ' the f-embed processor 124 transmits a control button via the system bus 122 to turn off the second switch 1 14 and turn on The first switch 112. Therefore, a test machine can input a reference clock to the first input terminal 110A of the phase comparator 11 via the clock signal pad 2 and the first switch II2. The phase comparator 11 compares the reference clock with the clock of the external oscillating element 130 and generates a phase difference signal (ie, a frequency error signal), and the analog/digital converter i 2 〇 converts the frequency error signal A digital signal (temperature compensation data) is stored in the system memory 126 via the system bus 122.
HAHU\HYG\tVr^i:科技\88047\88047.DOC 1261675 相對地’該特殊應用積體電路丨〇〇欲輸出一時脈訊號 時’該内嵌式處理器1 24經由該系統匯流排丨22傳送一控 制指令以關閉該第一開關112且開啟該第二開關丨14，並 將儲存於該系統記憶體106之溫度補償資料載入該暫存器 132。該數位/類比轉換器134則根據儲存於該暫存器132 之溫度補償資料及來自該溫度檢測器136之溫度檢測信號 而輸出一控制電壓以校準該外部振盪元件13()之時脈。因 此該外部振盪元件130之時脈經溫度補償後可經由該第二 開關114及該時脈訊號墊1〇2穩定地輸出。 相較於習知技藝，由於本發明之晶體振盪器5〇在接收到 該校準訊號後即可自行進行校準，因此在並聯複數個晶體 振in 50後-測試機台可同時（平行地）進行溫度校準。如 該測試機台所消耗之校準時間係由該複數個晶體振盪 态50均分，因而降低每一個晶體振盪器之校準時間以 降低其測試成本。 务明之技術内容及技術特點巳揭示如上，然而孰悉本 :技術之人士仍可能基於本發明之教示及揭示而作種種不 月離本發明精神之替換及修飾。 此本發明《保護範圍 =限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之中請專利_所涵蓋。 五、圖式簡要說明 圖1例示一 AT截斷石英片之輸 係圖； j阳肩半對週園溫度之關 係一習知之晶體振盪 HAHIAHYGW设科技\88〇47\_47 -12- 1261675 圖3係本發明之晶體振盪器之示意圖； 圖4係本發明之積體電路之功能方塊圖； 圖5係本發明之晶體振盪器之運作流程圖； 圖6係本發明之晶體振盪器之並聯示意圖；以及 圖7係本發明之特殊應用積體電路之功能方塊圖。 六、元件符號說明 10 晶體振盪器 12 溫度檢測電路 20 振盟電路 22 振盪元件 24 電阻 26 反相器 28 輸出端 32、 34直流截斷電容 36、38 可變電容 40 溫度補償電路 42 記憶電路 44 數位/類比轉換電路 50 晶體振盪器 52 振盪元件 60 積體電路 62 時脈訊號墊 64 電源墊 66 接地墊 68 控制塾 70 相位比較器 70Α 第一輸入端 70Β 第二輸入端 70C 輸出端 72 第一開關 74 第二開關 76 邏輯控制元件 78 高壓偵測器 80 類比/數位轉換器 80C 輸出端 82 數位/類比轉換器 84 溫度檢測為 90 記憶體 100 特殊應用積體電路 102 時脈訊號墊 110 相位比較器 1 10Α 第一輸入端 1 10Β 第二輸入端 110C 輸出端 1261675 1 12 第一開關 114 第二開關 120 類比/數位轉換器 122 系統匯流排 124 内嵌式處理器 126 系統記憶體 132 暫存器 134 數位/類比轉換器 136 溫度檢測器 HAHIAHYGV,,1,朵科技\88047\88047.DOC - 14 -HAHU\HYG\tVr^i: Technology\88047\88047.DOC 1261675 Relatively 'This special application integrated circuit 丨〇〇 wants to output a clock signal', the embedded processor 1 24 is connected via the system 丨22 A control command is transmitted to turn off the first switch 112 and turn on the second switch 丨14, and the temperature compensation data stored in the system memory 106 is loaded into the register 132. The digital/analog converter 134 outputs a control voltage based on the temperature compensation data stored in the register 132 and the temperature detection signal from the temperature detector 136 to calibrate the clock of the external oscillating element 13(). Therefore, the clock of the external oscillating component 130 can be stably outputted via the second switch 114 and the clock signal pad 1 经2 after temperature compensation. Compared with the prior art, since the crystal oscillator 5 of the present invention can perform self-calibration after receiving the calibration signal, after the plurality of crystal oscillators 50 are connected in parallel, the test machine can be simultaneously (parallel) Temperature calibration. If the calibration time consumed by the test machine is divided by the plurality of crystal oscillation states 50, the calibration time of each crystal oscillator is lowered to reduce the test cost. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the present invention is limited to those disclosed in the examples, and should include various alternatives and modifications without departing from the invention, and is covered by the following patents. V. Brief Description of the Drawings Figure 1 illustrates the transmission diagram of an AT-cut quartz piece; j-yang shoulder half-to-circumferential temperature relationship. A well-known crystal oscillation HAHIAHYGW set technology\88〇47\_47 -12- 1261675 Figure 3 Figure 4 is a functional block diagram of the integrated circuit of the present invention; Figure 5 is a flow chart of the operation of the crystal oscillator of the present invention; Figure 6 is a schematic diagram of the parallel connection of the crystal oscillator of the present invention; And Figure 7 is a functional block diagram of a special application integrated circuit of the present invention. 6. Description of component symbols 10 Crystal oscillator 12 Temperature detection circuit 20 Zhenmeng circuit 22 Oscillation component 24 Resistor 26 Inverter 28 Output terminal 32, 34 DC blocking capacitor 36, 38 Variable capacitance 40 Temperature compensation circuit 42 Memory circuit 44 Digital / Analog conversion circuit 50 Crystal oscillator 52 Oscillator component 60 Integrated circuit 62 Clock signal pad 64 Power pad 66 Ground pad 68 Control 塾 70 Phase comparator 70 Α First input 70 Β Second input 70C Output 72 First switch 74 Second switch 76 Logic control component 78 High voltage detector 80 Analog/digital converter 80C Output 82 Digital/analog converter 84 Temperature detection is 90 Memory 100 Special application integrated circuit 102 Clock signal pad 110 Phase comparator 1 10Α first input 1 10 Β second input 110C output 1261675 1 12 first switch 114 second switch 120 analog/digital converter 122 system bus 124 embedded processor 126 system memory 132 register 134 Digital / Analog Converter 136 Temperature Detector HAHIAHYGV,, 1, Duo Technology \88047\88047.DOC - 14 -