TWI248614B - Bank control circuit in RAMBUS DRAM and semiconductor memory device thereof - Google Patents

Abstract

A kind of semiconductor memory device for executing the action of an attached storage includes a storage, which is composed of plural memory cells; plural address latching circuits, which are provided commonly for two adjacent storages to receive a global address signal and latch a selected domain address signal; and plural control circuits, which are provided commonly for two adjacent storages to generate the control signal and determine the storage that ought to execute the action.

Description

1248614 ---^^__ V. Description of invention (1) —--- <Scope of invention > · Secret on the memory control circuit of random access memory bank (RAMBUS) DRAM The tea is especially used for a RAMBUS DRAM storage control strip, a control circuit for controlling the memory bank, and a location latch to reduce the circuit area. <Background of invention>

1st chart 7^ A block diagram of a conventional RAMBUS DRAM. It consists of a separate and a lower memory block of the memory bank, and the privacy block 1 0 ' is configured to connect the read and read data of the memory bank. Externally connected series/parallel conversion upper and lower series/parallel shifting parts 1 6 ☆ 1 8 2 or more and lower series/parallel shifting parts 1 6 and 1 8 are received by the intermediary. The output data of the bus output is external, and the write data received from the outside is output to the upper and lower serial/parallel shifting sections 16, and the input/output terminal 2'' and the upper and lower serial/parallel shifts are respectively controlled. The units 16 and 18 use the controller 22. The memory block 10 has 32 memory banks, and each of the upper memory block portion 2 and the lower memory block portion 4 includes 16 banks.

The upper series/parallel shift unit 丨6 converts the 128-bit parallel data RDA_top[127:〇] read by the upper memory block unit 丨2 into 16-bit metadata even RDA-top[7:0], odd number RDA — top[7:〇] is output, and the lower serial/parallel shifting unit 18 converts the 128-bit parallel data RDA_bot [127:0] read by the lower memory block unit 14 into 16 bits. The metadata is evenly RM — b〇t[h 〇], odd RDA-bot[7:0] and output. · The upper and lower series/parallel shifting parts 丨6, 1 8 can be differently

1248614 — V. Description of invention (2) 1. One is to divide the write operation time into a series of 1 2 8 bit % of the series one parallel series of other bits of the series data transformation = the block data read transform. The sub-join of β is always connected to the write data of the two upper bits and 16, 18 simultaneously, and the series/sub-transfer unit 12 and the lower memory block unit 14 are divided into four. The data selected at the upper memory block location is written in the memory block 1 〇. Bran 2 f : 1 〇 is written by the upper position and the lower serial/parallel shifting unit 16 , "When 1818 is in the operation, 2 1 0 receives the read data and transmits it to the output. Knife / /, memory Figure 2 is a diagram of a conventional memory storage device (or lower diagram) installed in the memory block i 4 ) shown in Fig. 1. As shown in the figure, 'traditional memory storage control circuit system The 16 memory storage parts of the dragon (3q<〇>~3〇', · in order to store the upper and lower parts of the number of storage bodies, so that they can be written and J) are stored in the data. Each of the sensing and amplifying parts (4〇<〇>~4〇乍 sensed feeling: the enlarged part (4. <〇>~40<16>) moving drive part (5〇<.>~ 5. <16>); drive = big 〇>, 60 <15 > word line 舆 adverb 'line w „3〇< μ , β η / η, η / ! π:, 丨口Prince line and sub-line drive ", receive the received active signal, precharge signal (Precharge Slgnal), and wide area address signal (Gi〇bai, -

Address Signal), to generate the control corresponding to the address signal storage body:: large drive part, main word line, sub-word line drive part, ° and: 绫 绫 salty amplification control signal, Shi Tong A k ^ ^ 1248614 V. Description of the invention (3) The signal, and the bit line are converted into <. >~7. <15>) Constructed: "empty department and address question lock unit (1) two control unit and address question lock unit (70 <0 >~7〇<15 > . > memory storage unit (30<()> ~3 In the mother a dynamic signal and pre-added signal proudly wide, each day f has a ° when there is a main control part and address flash lock part (7n \ ^ number ^ n%%, the domain position signal of each memory bank Whether it is the position of the Γ 互相 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Department, in the storage body, do; r鸠 maintain the word line changed in the memory lock address (4) domain address (four) is received in the active mode when the nth memory storage (30 < η >) was The wide area address has a third level, and the ("1) memory bank <n >) 3〇<n +1 >) is precharged, and then the (30<n>) is made For example, if the memory storage body 1 (30 <1 >) Ϊ) ' ^^^#ΜΚ30<) and 5 hidden storage 2 ( 30<2>)All 祜 苜 苜 right 储存 storage Κ 3〇 ≪ ! > ) is actuated.) And ', gas has pre-4 electricity / face and then remember < 2 > ) Λ , Λ 1' / # 140 (30 < 0 > } ^ ^ ^ # It2( 30 = 2. >) Until 3 memories 1 (3〇<1>) are not pre-charged

Page 6 1248614 Γ- 丨 1-5, invention description (4) This ΪΓ: This traditional Rafflbus dram storage control department has some shortcomings. For example, there is a question of increasing the layout area due to the address latching portion of each memory. , 卫 1 and <General Theory of Invention> The f π system of the ^^ month was developed to solve the above-mentioned traditional Rambus DRAM storage artifacts. One object of the present invention is to configure a control circuit with an address flash. The memory control circuit of the product and its semiconductor memory element y. In order to achieve the above object, the semi-conducting 本 亍 亍 亍 亍 亍 亍 亍 亍 亍 亍 属 属 属 属 属 属 属 属 属 属 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存 储存Bit 丄:: Wide-area address signal and ask the lock to select the storage and Γΐΐίΐ flash lock circuit, which is characterized by it. ": semiconductor memory element that is a storage object: a piece, also, and a plurality of storage bodies; and in the = ^ by their own memory: number: in the body of the study should be activated which one is determined in the road The characteristics of the 1U storage complex control unit 1 祉 1 port Hu Ya flash lock selected storage page 7 1248614 V, invention description (5) stored area address signal complex address latch circuit; A complex control signal is generated by the combination of the two banks of the respective phases, and it is determined that the complex control/path of which one of the banks should be activated in the number of banks is characterized. In summary, the Rambus DRAM storage of the present invention includes: a plurality of memory storage units for storing data, and a plurality of memory storage units for storing data in the upper part of the storage body for writing in the upper part. The complex sense of the two parts of the oral memory, the amplification drive unit; and the nu*s DRAM including the complex main word line and the sub word line drive unit for driving the memory P ^ U , the sub line and the sub word line, The memory storage unit has one for every two, to connect the control signal and the wide-area address letter. Generating a control located two note = 2 3 ,: sense amplification driving portion body, two main word lines and sub-word line driver j Temple syndrome. The bit line uses the complex control unit and the address latch unit of each signal for its approval. In order to achieve the above, the Rambus DRAM storage of the present invention includes a plurality of memory storage for storing data. a body; one for each of the upper and lower portions of each body portion for writing a complex sense amplifying portion for sensing data; and for controlling the I "amplifying portion for complex sense amplification driving The Rambus of this department has one in every two memory storage units, which is used to drive the complex main word lines and sub-word lines of the word lines and sub-word lines of each body. Each port of the memory storage unit has one for receiving the external signal, the pre-charge signal, and the wide-area address signal.

Page 8 1248614

The system is located in the two main word lines and the sub-words two = and the address flash lock portion, which is characterized by a bit 70, the signal for the table is used for the complex control portion <best embodiment of the preferred embodiment The description of the present invention does not describe in detail the Rai"bus DRAM of the present invention: the storage control circuit and the semiconductor memory device thereof are preferably embodied in the DRAM storage body control. A block diagram of the Rambus gas path in one embodiment.

1 The control circuit includes: n memory banks (1) for storing data. :), in the upper and lower portions of each memory storage unit (130<n>), there are n +1 sensing amplifications for the sensing data when writing and reading operations 〇 <n +1 >) Controlling each of the sense amplifying sections (140 <n +1 >) for n+1 sensing amplification driving sections (15〇<n+1 >), driving each of the brothers n main word lines and sub word line driving units (160 < η >) for the word line and the sub word line of the storage unit (1 30 < n >); and 2 for each of the memory banks Receiving an external active signal, pre-charging a signal, and a wide-area address signal, to generate and control two sensing amplification driving sections located in each of the two memory storage bodies.

Two main word lines and sub word line drive units, and n/2 control units and address latch units for the address line signals (170 < n/2 >). The memory control circuit of the Rambus DRAM of the present invention has two Rams DRAM characteristics (1 3 0 < 0 : 1 > ) The method of the control unit and the address latching unit (丨7 〇<n >).

When: ί system: the active signal and the pre-charge signal belonging to the wide-area signal occur in the second system and the address latching part (170 < η >) to confirm whether the pull-a--1 is its own 2 The address of a memory bank is wide (10) [Ministry Office;: The wide-area address signal selects one control flash lock, and the positive control unit and address are selected for the domain address signal ^ ^ ^ ^ # r ί # ^ ^ ^ ^ ^ ^ ^ ^ ^ 1, ^ The received active signal with pre-charged pre-charge and pre-charge mode actions. Bell Brothers ‘is doing the active part, the control unit selected by the wide-area address signal and the wide-area address signal of the address lock lock to maintain the influence of the second bank. Even if the external wide-area address signal changes, it will not be more approved. The block diagram of the Rambus DRAM storage circuit in another embodiment of the present invention. The control ^ ^ ^ ^ ^ ^ ^ ^ ^ >) upper ίί = 丄); in each memory storage unit (230 < n >) on the 邛 and the lower one each for writing and n + 1 sense amplification section (24〇<Κ action k sensing data Μ24ί) <nu \ u ), controlling each of the sense amplifications: : 2 of 1. +1 sense amplification driver (25 0 < n + 1,), § memory unit (2) G<n>) 2 towels share their Γ^ίΓ^ master, 'spring and sub-line drive unit ( 26〇<η/2>); and memory storage unit (10) <η>) For receiving the charging signal and the wide-area address signal, generating two sensing amplification driving sections and two main word lines and sub-word line driving sections each located in two memory storage pre-stores, 1248614 V. Invention Explanation (8) and 2 brothers recall the n / 2 control units of the signal of the address line of the bank and the address flash lock unit (270 < n/2 >). The memory control circuit of the Rambus DRAM according to the present embodiment uses two Rams DRAM characteristics in which two banks are not simultaneously activated, and two storage units (23 0 < 0: 1 >) are shared. The control unit and the address latch unit (27 0 < n > ) and the one main word line and the sub word line drive unit (2 6 0 < 〇 >). First, 'when the active signal and pre-charge signal belonging to the wide-area signal occur', each control unit and address latch (270 <n >) confirms the received wide-area, whether the address signal is 2 of its own. The address signal of the memory bank. One control unit and address latch ' is selected by = according to the received wide area address signal. Moreover, one control unit and address latch selected by the wide area address signal will correspond to the memory storage body of the wide area address signal received in the two memory storages, and the received active signal and precharge The signal acts as a master mode and a precharge mode. , ^ Furthermore, the control part selected by the wide-area address signal and the address latch 1 ^ internal address flash lock f-channel flash lock active mode when receiving the wide-area bit t, even if the external wide-area bit The address signal changes to maintain the word line in the memory. No more, v#, when =, by receiving the control part and the address request lock part (27〇<n asked 9 wide-area address signal main word line and sub-word line drive part (26〇<; n> 固 固 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , V. DESCRIPTION OF THE INVENTION (9) Various changes are implemented within the scope of the invention. From the above description, it is understood that the memory control circuit of the Rambus DRAM and its semiconductor memory element according to the present invention can be provided from every two banks. A control circuit for each control memory bank is shared with the address latch circuit, thereby achieving an effect of saving circuit area.

Page 12 1248614 Schematic of the diagram The brother 1 is a block diagram of the traditional Rani bus DRAM. Figure 2 is a block diagram of the control circuit of all conventional memory banks in the block of Figure 1. Figure 3 is a block diagram showing the Rambus DRAM bank control circuit in one embodiment of the present invention. Figure 4 is a block diagram showing the Rambus DRAM bank control circuit in another embodiment of the present invention. <Control of Elements and Labels in the Drawings> 130&lt;0&gt;~130&lt;11&gt;, 230&lt;0&gt;~230&lt;n&gt;: Memory storage 26 months and 140&lt;0&gt;~i4〇&lt;n+l&gt; , 240 &lt;0&gt;〜240&lt;n+l&gt; : residual, then enlargement &quot;150&lt;0&gt;~I50&lt;n+1&gt;,250&lt;〇&gt;~250&lt;n+l&gt; : salty, then The amplification drive unit 160&lt;0&gt;~16〇&lt;n&gt;, 260 &lt;0>~260&lt;n/2&gt;: main word line and sub word line drive unit 170 &lt;0 &gt; ~170 &lt;n/2 &gt;, 2 7 0 &lt;〇&gt; ~2 70 &lt;11/2&gt;: control unit and bit, address latch

Page 13

Claims (1)

1248614 VI. Patent Application Range 1. A semiconductor memory device that performs an auxiliary ^~&quot; sub-action, including a complex memory composed of memory cells. In the complex memory, each =, and receives a wide-area address The signal is latched by the two banks that are common to the j:, and the multiple positions are latched. The area address signal of the Tingzhi storage body includes: 2. A semiconductor memory element for performing the operation of the auxiliary storage body, the package, and the plural storage body composed of the single element are stored in the 5 Hz complex storage body, and the 夂 is generated by the beads Control signal, and two a neighbors, shared by two storages, which one of the storage bodies of the complex NC 2 = multiple storage, should be live 3. An implementation of the auxiliary storage move ·, (half' The body memory component comprises a plurality of memory blocks composed of a single memory; in the plurality of memory bodies, each of the two: receiving the wide-area address signal and asking the lock of the storage body to share the 'multiple address flash lock a circuit; and a region address signal of the memory bank, a nickname from each of the two adjacent banks, and a complex control circuit that generates a complex control signal in the plurality of memory banks. Which storage body is tongue-shaped? The storage control circuit of the edited memory includes: a plurality of memory storages for storing data, and a part of each of the memory storage units. 14 pages 1248614 The complex sense amplifying part for sensing data when writing 2 and § buying an action; 6. Patent application range = the complex sense amplifying driving part of each of the sensing amplifying parts; and -&amp; In the Rambus DRAM of the word line and the sub word line for the sub-line and the sub-word line drive unit, the memory bank is shared by two to receive the external control signal = two 3 address signals. The control generates three=two large driving units, two main word lines and sub word line driving units, and bit lines for the two memory banks. The complex control unit of the signal and the address latching unit. 5=· Kind^11113" DRAM storage control circuit includes: a plurality of memory storage units for storing data; one for each of the upper and lower portions of the memory storage unit for writing 2 and reading operations a complex sense amplifier for sensing data; a Rambus DRAM including a complex sense amplifier driver for controlling each of the sense amplifiers: 1 in each of the 5 a plurality of main word lines and sub word line driving units for driving the word lines and the sub word lines of the cryptographic storage &quot;;; and f for each of the two memory storage units for receiving foreign objects , the motion, the 仏 on the 'pre-charge signal, and the wide-area address signal, and the control of each of the two, located in the two memory storage, three sense amplifier drive, one main word · line and Tian Hao word line The drive unit and the complex control unit and the address latch unit for the signal of the bit line. Page 15