TWI246841B - Digital transmission system and method for transmitting digital signals - Google Patents

Abstract

A digital transmission system and method that improves upon the ATSC A/53 HDTV signal transmission standard includes: a first forward error correction (FEC) unit for encoding packets belonging to each of robust and normal data bit streams; a robust processor unit for receiving robust packets comprising priority data and processing the packets for generating the robust bit stream; a trellis encoder unit for producing a stream of trellis encoded data bits corresponding to bits of the normal and robust streams, the encoder employing mapping of encoded data bits of said robust packets into symbols according to one or more symbol mapping schemes; and, an optional second forward error correction (FEC) encoding unit for ensuring backward compatibility with a receiver device by reading in only packets of the robust bit stream and enabling generation of parity bytes only for the robust stream packets; and, a transmitter device for transmitting the robust bit streams in a backwards compatible manner, separately or in conjunction with said normal bit stream over a fixed bandwidth communications channel to a receiver device, wherein an existing receiver device is capable of receiving and processing packets of the robust bit stream as null packets.

Description

1246841

BACKGROUND OF THE INVENTION 1. The present invention relates to a clamp transmission system, which is related to "advanced" Television Systems Committee (ATSC) Digital Television (DTV) Standard (A/53). The present invention describes a method for transmitting a strong bit rate stream in a backwards compatible manner, along with a standard bit rate stream using the ATSC standard. The ATSC standard for high resolution television (HDTV) transmission over terrestrial broadcast channels utilizes a sequence of twelve (12) independent time multiplex trellis encoded signal streams that are modulated at a rate of 10.76 MHz. It is the signal of the eight (8) order residual sideband (VSB) symbol stream. This signal is converted to a six (6) MHz band corresponding to a standard VHF or UHF terrestrial TV channel, which is broadcast on a data rate of 19.39 megabits per second (Mbps). For details on the (ATSC) "Digital TV Standard" and the latest revision A/53, please refer to http://www.atsc.org/. 1 is a block diagram schematically illustrating an exemplary prior art high resolution television (HDTV) transmitter 100. First, the MPEG compatible data packets are randomized in a data random processor 105, and each packet is encoded by forward error correction (FEC) by a Reed Solomon (RS) encoder unit 110. Then, the data packet in the contiguous section of each data block is misplaced by the data misplacer 120, and then the misplaced data packet is further interleaved and encoded by the trellis encoder unit 130. The trellis encoder unit 130 can generate a stream of data symbols each having three (3) bits. One of the three bits is precoded, and the other two bits are generated by a one solid four (4) state trellis encoder. Then map the three (3) bits

wmmM 1246841 (7) to an 8th order symbol. As is well known, the prior art trellis encoder unit 130 contains twelve (12) parallel trellis coded & precoder units to provide twelve iron-coded encoded data sequences. In the multiplexer 140, the symbols of each trellis encoder unit are synchronized with the "segment sync" and "Held sync" sync bit sequences from a sync unit (not shown). 150 phases merged. The preamble insertion unit 160 then inserts the short co-phase preamble signal and is selectively pre-equalized by the filtering means 16 5 . Then, the symbol stream is forked by the V S B1 transformer 17 to perform a residual sideband (VSB) compression carrier modulation process. Finally, the symbol stream is upconverted by the radio frequency (RF) converter 180 to a radio frequency. 2 is a block diagram illustrating an exemplary prior art high resolution television (HDTV) receiver 200. The received RF signal is then down-converted to an intermediate frequency (IF) by the tuner 21 ° and then filtered by the IF filter and detector 220 and converted to digital form. The detected signals are in the form of data symbol streams, each representing a level in the eight (8) hierarchical signal constellation. Next, the signal is supplied to the NTSC rejection filter 23 and the synchronization unit 240. The signal is filtered by the NTSC rejection filter 23 and passed to the equalizer and phase tracker 250 for equalization and phase tracking. Then the 'reconstructed coded data symbols are then decoded by the trellis decoder; 260 is trellis decoded. This decoded data symbol is further misinterpreted by the data demultiplexer 270. This data symbol will then be Reed Solomon decoded by Reed Solomon decoder 280. This will restore the MPEG compatible data packets transmitted by the 传送 transmitter 100. , Ming Ming explained the performance page 12468841 and the existing eight 808-¥83 eight/53 digital TV standard is enough to transmit signals, to overcome many ghosts, noise surges, signal attenuation and interference like ground-based setting methods. The channel corruption problem, indeed, requires two flexible ATSC standards, and can accommodate streaming with various priorities and data rates. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a technique for transmitting a new strong bit stream in conjunction with a standard ATSC bit stream in an ATSC digital bit transmission system, wherein the new bit stream is compared to ATSC. Streaming will have a lower "visible threshold (TOV)" and can therefore be applied to transmit high priority information bits. It is a further object of the present invention to provide an elastic ATSC digital transmission system and method that is backward compatible with existing digital receiver devices. It is yet another object of the present invention to provide an elastic ATSC digital transmission system and method that provides a priority byte generator mechanism that is compatible with existing receiver devices. According to a preferred embodiment of the present invention, there is provided a digital transmission system and method capable of improving ATSC A/53 HDTV signal transmission standards, comprising: - a first forward error correction (FEC) unit, which can be used to belong to each Strong, and normal data bit stream packets are encoded; - a strong processor unit for receiving strong packets containing priority data, and processing the packets to generate the strong bit stream; a trellis encoder unit for generating a stream corresponding to the trellis-encoded data bits of the normal 'and strong 12468841 (4) iaim solid stream elements, the encoder is based on one or more symbolic rules The coded data bit map that is transferred from the strong packet to the symbol; - a selective second forward error correction (FEC) coding unit, by reading only the strong bit stream packet, and can only The strong stream packets are used to generate a bit byte to ensure backward compatibility with a receiver device;

- a transmitter device for transmitting the strong bit streams individually or collectively and in the normal bit stream in a backtrack compatible manner, and transmitting to a receiver on a fixed bandwidth communication channel Apparatus wherein the existing receiver device is capable of receiving and processing the packets of the strong bit stream in accordance with a null packet.

To ensure traceback compatibility with receivers sold by existing manufacturers, a selective non-systematic Reed Solomon encoder can be employed to add the alignment bits to the strong bit_stream packet. Here, the standard 8-VSB bitstream is encoded using the ATSC FEC rule (A/53). Packets transmitted using the new bit stream are ignored by the transport layer decoder of the existing receiver. BRIEF DESCRIPTION OF THE DRAWINGS The details of the present invention will now be described with reference to the accompanying drawings, in which: FIG. 1 illustrates an exemplary high resolution television (HDTV) transmitter block diagram according to the prior art; FIG. 2 illustrates a Exemplary high resolution television (HDTV) receiver block diagram of the art; -10- 1246841 (5) Park mpg FIG. 3 is a high-order diagram of a first embodiment 201 of the improved ATSC standard according to the present invention; FIG. A second embodiment of the improved ATSC standard according to the present invention is a high-order diagram; FIG. 5 is a block diagram showing the trellis coding rule in the transmission system of FIGS. 3 and 4; FIG. 6 is a diagram illustrating the invention according to the present invention. The outer coding circuit of the modified trellis encoder 330 simplifies the block diagram;

Figure 7 is a detailed description of the strong packet dislocation block 400, which shows a dislocation processor 401 and a packet formatter unit 402; Figures 8A and 8B illustrate when MODE = 2 or 3, and respectively, for In the case of NRS=0 (Fig. 8A) and NRS=1 (Fig. 8B), the packet byte is copied into the basic formatter function of two bytes; Figs. 9A and 9B illustrate when MODE=l, and respectively In the case of NRS = 0 (Fig. 9A) and NRS = 1 (Fig. 9B), the elements of an input packet are reassembled into a basic formatter function of two bytes;

Figure 10 illustrates an exemplary "placement and holding" insertion mechanism for an exemplary scenario. The present invention details a new ATSC digital transmission system standard method, which includes a device and method for transmitting a new "strong" bit, stream, in conjunction with a standard ATSC (8-bit) bit stream. The new bit stream will have a lower "visible threshold (TOV)" than the 8-VSB ATSC stream, and thus can be adapted to transmit high priority information bits, which can be U.S. Patent Application Serial No. 10/078,933, the entire disclosure of which is incorporated herein by reference. The entire contents of the text and the disclosures are hereby incorporated by reference in its entirety in its entirety. US010173, the firm's file number 15〇62], the new features include a trade-off mechanism for providing standard bitstream data rates for new-bit stream ruggedness. This mechanism allows new receivers. The device can decode strong Packets, without errors, even in harsh static and dynamic multipath interference environments with reduced CNR and reduced TOV, and further, a mechanism for transmission operations that are compatible with existing digital receiver devices The system can improve the current ATSC digital transmission system standard by providing the elastic transmission rate of "strong and standard" streaming to accommodate a wide range of carrier-to-noise ratios and channel conditions. Figure 3 is a top-level diagram A first embodiment 201 of the enhanced ATSC standard according to the present invention. As shown in FIG. 3, the improved ATSC digital signal transmission standard according to the first embodiment includes a data random processor component 105. First, the input data byte value is changed according to a known virtual random number generation mode. For example, according to the ATSC standard, the data random processor will virtualize all the entry data bytes by a maximum length of 16 隹. The random binary sequence (Prbs) is X〇R, which is initialized at the beginning of a data block. The randomized data output will be followed by the round. To the Reed Solomon (RS) encoder component 11〇, which operates according to the data block size of a 187-bit tuple, and is added to the 'error 1246881 (7) statement that the performance page is 5·%, ' '' ΐ , >,,,, 'ν ί,>匕'' and (-'ν

The corrected 廿(20) RS alignment byte generates an RS block size totaling 207 bytes per data segment. The strong signal star map is then used to post-process these bytes and send them out. In the RS encoding operation, the 207 byte data '' section is input to the new block 115, which contains the strong dislocation, packet formatter, and packet multiplexer elements to further process/reformat these Strong input bytes. The details of the operation of the individual components of the packet formatter block can be found in US Patent Application No. 10/078,933 [US Patent 010, file No. 15062], and the commonly-owned, co-investigated US patent application. No. 10/1 18876 [US010278, Firm File No. 15061], entitled "Package Identification Mechanism for Improved ATSC 8-VSB System at Transmitter and Receiver", citing this article All contents and disclosures are incorporated as a whole in this text. More generally, the strong dislocations, packet formatters, and packet multiplexer elements for reformatting the in-field elements can be responsive to a mode signal 113, indicating whether the incoming azimuth tuple is Both processed (for strong bytes) or unprocessed (for normal bytes). After the strong packet is misplaced in the strong dislocation device, each data byte belonging to the incoming strong bit stream is buffered in the packet formatter device and grouped into a plurality of predefined quantities. That is, a tuple cluster of 207 bytes. In general, for a strong packet, each byte at the output of the packet formatter will have only 4 bits, LSB (6, 4, 2, 0), corresponding to the incoming stream. The other 4 bits of each byte, MSB (7, 5, 3, 1), can be set to any value, the reason of which will be explained in detail later. After the bit 'group' in the packet formatter 117 is -13 - !246841 (8) formatted, the byte belonging to the strong packet is multiplexed with the group of bits belonging to the standard stream. The multiplexed application stream 116 of the strong and standard bytes will then be input to the convolutional misplacer mechanism 12〇, where the data packets in successive sections of each bedding position 4 will be further misplaced, according to The ATSC A/53 standard perturbs the order of the data streams. That is, as described later in detail, the byte associated with each strong or standard packet will be tracked in the current processing control block (not shown). Further, as shown in Fig. 3, a new type of trelUs encoder device 33 is used to encode the misplaced, RS encoded and formatted data bits m. The trellis encoder unit 33 will specifically respond to the mode signal 113 and may interact with the backtracking compatibility bitstream generator component 125 in a manner detailed as described hereinafter. The backtracking compatibility (selective RS encoder) block 丨25, generates an output trellis-encoded data symbol output stream, which has three (3) bits, each of which will be reflected An 8th order symbol. Then, the output symbols of the treins code are transmitted to the multiplexer unit 140, where they will be synchronized with the segment sync (segment sync) and the "station sync" from a sync unit (not shown). Sync)" The sync bit sequence 138 is merged. A preamble signal is then inserted by the preamble insertion unit 160. Then, the symbol stream is streamed to the VSB modulator 170 for residual residual sideband (VSB) compression carrier modulation processing, and finally, the radio frequency (RF) converter 180 up-converts the symbol stream into a radio frequency. Figure 4 is a high level diagram of a second embodiment 300 of an improved ATSC standard in accordance with the present invention. That is, as shown in FIG. 4, the modified ATSC digital television transmission standard according to the second embodiment includes the same functional block as described in FIG. 3, which is a specific functional block of FIG. The front end of system 300 of 4 contains a new block containing "strong" processor elements 205 for processing the strong-packed bytes that are received from an input strong bit stream 207 and their Forwarded to the MPEG multiplexer unit 210, this may additionally receive a byte belonging to the normal (standard) bitstream 208. The multiplexer unit 210 multiplexes the strong and standard packets for input to, for example, a standard data random processor component. The input randomized data is then input to the Reed Solomon (RS) encoder component

110, which is operated, for example, by a data block size of 187 bytes.

It is added to the 廿(20) RS alignment byte for error correction, resulting in an RS block size totaling 207 bytes per data segment. After RS coding, the 207-bit data section 214 is then input to a selective byte scrambling block 215, which will only further process the byte of the strong bit stream, and let the normal The packet is unchanged. The function of the byte scrambling block 215 is to replace the align byte added by the aforementioned RS encoder block 110 with a zero value and to scramble the 207 octets so that the data is passed. After the misplacer, the data of the 184 data bytes generated by the rugged processor (except the header byte) will come before the alignment byte. That is, as seen in Figure 4, the new 'bit tuple block 215 will specifically respond to the mode signal 113, and this indicates whether the in-situ tuple will be processed through this block. That is, as in the first mode depicted in FIG. 3, the data segment of the strong and standard byte 2 16 output from the byte scrambling block 2 15 is then input to the gyroscope mechanism 120. Here, the data in the continuity section of each data field will be further blocked by -15-(10) (10) 1246881, and the data will be streamed according to the ATSC A/53 standard. The order is disturbed. That is, as further detailed in Fig. 4, the misplaced, RS encoded and formatted data bits 217 are encoded by Hantrellis by a new trellis coded volume device 330. That is, as further detailed below, the trellis encoder unit 330 interacts with the traceback compatibility (selective rs encoder) block 125 to produce an output trellis encoded data symbol output stream. The person has three (3) bits, each of which will reflect an eighth-order symbol. Then, the output symbol of the trellis code is transmitted to the multiplexer unit 140' where they will be synchronized with the segment sync (segment sync) and the "station sync" from a sync unit (not shown). Sync)" The sync bit sequence 138 is merged. Then, a preamble signal is inserted by the preamble insertion unit ι6', and then the symbol stream is streamed to the VSB modulator 170 for residual residual sideband (VSB) compression carrier modulation processing, and finally by radio frequency (RF) conversion. The device 180 upconverts the symbol stream to a radio frequency. That is, as shown in Figure 4, the r-strong processor component 2〇5 includes an input for receiving an mpEg data packet 207 to be transmitted by the strong stream. The rugged processor component 2〇5 comprises the following components: a Reed-Solomon processor, followed by a misplacer device, followed by a formatter block 'to form a packet of 188 bytes in length ( MPEG compatible packet) This last block (MPEG packet forming job) will insert redundant bits to form a 184-bit packet 'and then add four (4) MPEG header bits to form a house 188 MPEG packets. The strong packet 206 from the processor block 205 will be multiplexed with the normal packet of the MpEG packet stream 2〇8 to pass through the Mpeg multiplexer device 210 with normal and strong 'solid seals 1246841 〇 1) mmm The ATSC stream 209 of both packets is transmitted. Preferably, the normal stream packet and the strong packet are mutually multiplexed according to a predefined algorithm, and an exemplary algorithm can be as described later in this document. For discussion, and

U.S. Patent Application Serial No. 10/1 1 8876 [US Patent No. 010278, file No. 15061] is hereby incorporated by reference in its entirety herein in A control mechanism is provided to track the type of the packet being transmitted, ie, normal or strong. Thus, as shown in Figures 3 and 4, a normal/strong (N/R) signal is generated in relation to each tuple, and contains a bit 211, which can enhance the ATSC digital signal transmission rule internally. Used to track the progress of the tuples and identify the tuples.

In general, for the ATSC system described with reference to FIG. 4, the strong packet transmission operation requires knowledge of multiplexing processing of the strong packet 206 and the normal packet 208 at the MPEG multiplexer component 210. The way. The way these packets are interposed must be that these packets improve the dynamic and static multipath performance of the receiver device. An exemplary algorithm for leading a strong stream packet and a normal stream packet in the robust processor block 205 can be described with reference to Table 1. This packet insertion algorithm can take advantage of strong packets and capture better and robust receiver design results. A set of strong packets is placed adjacently at the beginning of the MPEG field, and then the remaining packets are interpolated with a predetermined algorithm, as described in Table 1. The first set of packets will help the equalizer to get both static and dynamic channels faster. This strong block insertion algorithm can be implemented before each field is misplaced. According to the exemplary strong package as shown in Table 1 'interpolation -17-1246841 (12) hidden rice r page: ,, algorithm, first will define the following magnitude and noun: one is called the first value of "nrp This value indicates the number of strong segments occupied by strong packets in each field (that is, the number of "strong packets" in a frame); the value of a type called "M" is tight The number of contiguous packet positions occupied by the strong bit stream after synchronization with the block; the character "ΐτ U" indicates a union of two sets; and the "base", which is a truncation indicating a ten nearest value The value is such that the value will be approximated to an integer value. That is, as shown in Table 1, this algorithm involves performing the following evaluation tasks, so as to determine

The location of the strong packet in a meta stream: such as 0 < NRP $ M, Bay Ij strong packet location = {0?15...5NRP-1} 1

For example, M<NRP£floor((3 12-M)/4), Bay 1J strong packet position = {0,l,...,Ml}U{M+4i,i=0,l,..., (NRP- M-1)} as fl〇〇r((312-M)/4) + M<NRP$floor((312-M-2)/4) + fl〇〇

((312-M)/4) + M, then strong packet location = {0,l"..,Ml}U{M+4i,i=0,l,"·,floor((312-M) /4)-1} U{M+2+4i,i=0,l,···,NRP -(floor((312-M)/4) + M)-l}

Such as floor((312M-2)/4) + flooΓ((312-M)/4)+M<NRP:^312, BeimJ strong package position = {0,1,...,Ml}U{M+4i ,i=0,l,···,floor((312_M)/4)-l}U {M+2 + 4i,i = 0,l,...,(fl〇or((312-M- 2)/4)-l}U{M+l+2i,i= 0,1,..., NRP-(M+fl〇or((312-M)/4) + floor((3 12- M-2)/4))-l} (Table 1) -18- 1246841 (13) _____ If yes, in the exemplary implementation for M = 18, the above algorithm will produce the following strong packet placement Algorithm:

Such as 0 < NRP $ 18, Bay | J tamping packet position = {0, 1, ..., NRP-1} 18 mouth 18 < NRPS91, Bay ij strong package position = {0, l, ..., 17} U{18+4i, Bu 0,1,._.,(NRP-19)}

Such as 91<NRPS164, Bellow J

Strong packet location = { 0, 1,..., 1 7 } U { 1 8 + 4i5 i = 0,1,...,72 } U {20+4i,i=0,l,···,NRP - 92} Break 164 < NRP < 312, Bay strong package position = { 0,1,...,1 7 } U { 1 8 + 4 i,i = 0. 1,...,7 2 } U {20+4i,i=05l5 ...,72}U{19+2i,i=0,l,.",NRP-165}

In the first and second embodiments of FIGS. 3 and 4, a backtracking compatibility "alignment byte generator" component 125 (also referred to as a selective non-systematic RS encoder) is provided. The block 125 is read from the trellis decoder. In particular, the block 125 includes a one-bit tuner block and a selective "non-system" RS encoder block from the bit. The group solver block reads a packet and then RS codes to generate the alignment byte. This produces a parity byte that is used for backtracking compatibility only for strong stream packets. The exemplary algorithm used to perform this function can now be as shown in Figure 2: Define a 52 χ 207 array "data__bytes", initialize each variable byte-no, row_no, col_no, row-add to zero, such as byte-no =207* 52 sets read_flag and start_flag to 1, -19- 1246841 (14) «.s) ^ Λ , , and clear description page: t P 2, '' as start_flag=l then every 208 Set the read_flag=l for each byte (for the exception of this rule 'see packet_formatter block description), such as start_flag=l Whenever read_flag is set from the beginning of the packet, the packet is sent out sequentially (row_n0=0), and the message byte (the output of the trellis encoder) is placed in data_bytes [row_no][col_no] as byte_stb (from The trellis encoder signal) = 1 increments byte_no,

Use the following conditional logic to update row_no and col__no variables toques byte-no=207* 52 to 1J byte_no=0; row_add=0; col_no=0; row+no^O; nobe 1J if (byte-no mod 208) = 0 then row_add=(row_add+1) mod 52 ; col_no=row_add ;

Row_no=row_add ; for all other cases co^no^ ( col_no+52) mod 207 ; row-no= (row—no-1) mod 52 ; (Shishirow row-no-1 <0 shell ll will, will Before the 52), go to step 3 (Table 2). For some packets (ie 1 to 7 mod 52), it may be necessary to have previous information about the randomized header bytes, because these are not -20' 1246841 〇 5) mm of the package 'all headers will be available for RS coding. That is, for the group of packets 'being at the output of the gyr-displacer is part of the header byte followed by the alignment of the bit. So 'not to wait for this header header to calculate the 20 alignments, but to use the previous information about the headers (this is the nature of the destiny)' and then take these To calculate the alignment bytes. That is, "Error Control" by Arnold Michelson and Allen Levesque

Techniques for Digital Communication" (John Wiley, NY, 1984), as described in Book B, an (N, K) RS decoder can correct up to (NK)/2 errors or erase fill up (NK) wipes, where N To encode the character length, and K is the message word π length. In general, if there is one wipe and Eb error in the length of a character of length N, then (Ea+2*Eb) is less than or equal to (NK) 'This decoder can completely restore the codeword The element is as follows (1): (Ea+2xEb)$(N - K) (1) where Ea and Eb are the number of wipes and the number of errors in the coded character, respectively. This RS coding property can be utilized to generate 2 对 alignment bytes. Then, 1^20 alignment bit positions are counted as the wipe position of the RS decoder. The calculation procedure for the alignment bit position is similar to the way the packet formatter is ordered. The byte belonging to a packet (zero value at each alignment byte) is passed to the RS decoder as an input code character. When processing the wipe fill, the decoder calculates the byte of the wipe position. These bytes correspond to the 20 alignment bytes. Thus, the "Alignment Bits -21 - (16) 1246841 Generator" block also generates alignment bit position information. The alignment bit and header bytes are always encoded by the standard 8-VBS symbol. The alignment byte and its location information for each packet are then sent to a modified trellis encoder device to map the strong bit groups according to the new symbol mapping rule. It should be understood, however, that for certain packets (i.e., packets 1 through 7), it is necessary to have prior information about the random header bytes, since not all of the header bytes of these packets are available at the time of the RS encoding operation.

The top level operation of this modified trellis encoder device is dominated by the rules set forth in Section 4.2.5 of the ATSC A/53 Transmission Standard. The top-level job is about trellis misplaced jobs, symbol mapping, how to read bits into each trellis encoder, and so on. Normal 8-VSB packets will not be replaced. However, the trellis encoder block according to the ATSC A/53 standard will be modified to perform the following functions: 1) if the byte belongs to a strong bit stream, the precoder is passed; 2) if the byte belongs to The strong bit stream exports each MSB bit, and then sends a new byte to the "byte demodulator" block; 3) reads the alignment from the "byte tuple" block The byte is then encoded using the person (if it is a strong bit stream); and 4) the modified symbol pair is used to map the symbols belonging to the strong bit stream. It should be understood that it is better to map the bit tuples to eight (8) levels. The function of the precoder and the constituent tuples is related to the mode, and will be described later in detail with reference to the modified trellis encoder diagrams of Figs. 5 and 6. In particular, Figure 5 is a block diagram of the trellis coding law 330, and as shown in Figures 3 and -22-1246841 (17): a block diagram of the implementation of the continuation system. For enhanced 8-VSB (E-VSB) or 2-VSB streams, each trellis encoder receives a tuple and only 4 bits (LSB) contain information bits. When the trellis encoder receives a byte belonging to a strong stream, the information bit (LSB, bit (6, 4, 2, 0)) (after encoding the strong mode) is replaced by 乂1. . It then determines the bits to be replaced by X2 to obtain a particular symbol mapping rule. Once X2 and Xi are determined, all bits of a tuple have been determined for subsequent "non-systematic" RS coding jobs. This byte is then passed through the data line 355 to the traceability compatibility bit tuple generator 125 (i.e., "non-systematic" Reed-Solomon encoder). The alignment bits and PID bytes of the "non-systematic" Reed-Solomon encoder are encoded using the 8-乂SB coding rule. The job content of the trellis encoder block 335 above the trellis encoder 330 will now be described with respect to various digital signal modulation modes with reference to FIG. The upper trellis coding block 335, as shown in Figure 6, calculates the precoder 360 input X2 and X! of the standard trellis encoder block 359 to achieve the desired symbol mapping or coding law. For example, these encoding laws are standard 8-VSB, (enhanced) E-VSB and 2-VSB and "8/2" control bits 353, which are provided to indicate the correct encoding (symbol mapping rule). The output bits of this block are grouped into individual bytes and will eventually be fed to the "non-systematic" RS-coded block for the work of the alignment. The normal/strength control bits 2, 11 required to configure the multiplexers 336a, ..., 336d, are provided by the tracking/control mechanism block as shown in Figures 3 and 4. < -23 - 1246841 (18)

¥明婕明: I is so 'for the normal (standard) 8_VSB symbol mapping mode, the input bit received from the previous misplaced block and input to the trellis encoder 33〇 upper encoder 335 is '2 and X, will be transmitted unchanged to the positive and constant trellis encoder containing precoder 3~50 and encoder 370 unit. This can be achieved by having n/R bits 211 select N multiplexer inputs. The 8/2-bit 353 indicates that when N/R (strongness), the trellies to be applied are further controlled by the pair of rules. For 2-VSB mode and 4_VSB symbol mapping mode, the MSB does not load any information. In order to meet the mapping requirements, the Z2 bit is first calculated, and then the MSB X2 is derived by summing the contents of the precoder memory 363 (Fig. 5) by the modulus 2. A new byte group can be formed from the calculated MSB and the input information bit Xi. The memory component is then updated with Z2. Thus, in this case, the trellis encoding benefit output ^2 and & will be equal to the information bit. That is, the input X2 is calculated so that the precoding output z2 will be equal to the information bit when precoding. Here, this operation is implemented using the upper encoding circuit 335 of Fig. 6. In addition, Xi will be equal to the information bit. These operations, in conjunction with the existing symbol mapping rules provided by the trellis coded symbol map 380, produce symbols from the letters Bu, 7,-5, 5, 7}. Basically this is a 2-VSB signal, because the information bits are transmitted with the sign of this symbol. The real symbol is a valid trellis coded 4th order symbol that can be decoded by an existing trellis decoder. For example, to perform a 2-VSB encoding operation, N/R bit 211 will be set to select the R input, and 8/2 switch 353 will be set to select the "2" input of multiplexers 336a, ..., 336d. For the enhanced 8-VSB (E-VSB) mode, X2 and Χι correspond to the enhancement, and the 1246841 (19) Axe-ft pager (ie, the upper encoder 335) outputs. Here, these bits are used instead of the real input to form a byte. Thus, in this mode, the version of the information encoded by trellis is placed on X to make Z2 equal to the information bits. To this end, the way to calculate this X2 is that when precoding, the information bit is generated. The information bit is also passed through another trellis encoder to generate X]. Overall, for E 8-VSB, the external encoder 335 and the normal trellis encoder 359 would be equal to the 1/3 rate trellis encoder of the higher state (i.e., 16 states). The obtained symbol is an 8th order trellis code

symbol. For enhanced 8-VSB encoding, N/R bit 211 will be set to select the R input, and 8/2 switch 353 will be set to select the "8" input of multiplexers 336a, ..., 336d. In each mode, the symbol-to-rate converter introduces a 12-bit delay.

Regarding the function of reading the alignment byte from the byte demultiplexer, this will only be implemented when NRS = 1 (i.e., the implementation of a non-systematic RS coding job). The behavior of this functional unit is the same for different modes. The trellis encoder 330 retrieves the location information of the pair of bits from the pair of bitstream generators 125 for each of the packets. The trellis encoder 330 can then determine if a particular contiguous tuple to be encoded belongs to the set of aligned tuples of the group. If the byte is indeed a set of strong concatenated bit tuples, a tuple is read from the byte decipherer and used to encode the trellis instead. Here, the original encoding and mapping rules are always used to map the symbols generated from the alignment bits to the eight (8) levels. 〃 -25 - 1246841 (20)

Hill, continuation page and more particularly, the alignment "position-hold" is interposed by the packet formatter component of the transmission system of Figures 3 and 4. Figure 7 illustrates the strong packet processor block 400 in more detail, which includes a second misplacer 401, a packet 'cell unit 402, and a normal/strong multiplexer (N/R MUX) 405. Preferably, the strong packet misplacer 401 is only a misplaced strong package. The packet formatter 402 will process the strong packets according to whether a "non-systematic" RS encoder is used to ensure backward compatibility with existing receivers. If NRS = 1, then a "non-systematic" RS encoder is used, and the packet formatter 402 reads 184 bytes from the misplacer and splits the bytes into two 184. A byte block. In general, only 4 bits in each strong byte, LSB, (6, 4, 2, 0), correspond to the incoming stream. The other 4 bits in each strong byte, MSB (7, 5, 3, 1), can be set to any value. After the packet is split, three random null packet ID (or three NULL PID) bytes are then inserted into the beginning of each of the two 184 byte length data blocks. Then, 廿 (20) "position-hold" bit bytes are added to each data block to generate a 207-bit packet. When these 207 bytes are generated, these 184 bytes containing the information stream and 20 "location-hold" bit bytes are rearranged by the standard 8-VSB data misplacer. After that, these 20 bytes will appear at the end of these 184 bits containing information; At this stage, the values of these 20 bytes are set to zero. This approach, incorporated to ensure backwards compatibility with existing receivers, reduces the effective data rate because 23 bytes (20 alignment bytes and 3 | headers) must be added on a packet-by-packet basis. 26- 1246841 (21) mmm byte). The result is a reduction of about 12% in payload. If NRS=0 has been determined, Bayi 1J does not use a "non-systematic" RS encoder. In this case, packet formatter 402 reads 207 bytes from the misplacer and splits the bytes into two 207-bit 'packets. In general, there are only 4 bits in each tuple, LSB (6, 4, 2, 0), which corresponds to the incoming stream. The other 4 bits of each tuple, MSB (7, 5, 3, 1), can be set to any value. In both cases, it should be understood that the strong/normal packet MUX 405 is a packet (207 octets) hierarchical multiplexer. This allows multiplex processing of strong and normal packets on a one-by-one basis. The function of the packet formatter is determined by the MODE and NRS parameters. If NRS=0, the packet formatter basically performs the function of byte, copy or bit reorganization. If BRS = 1, this will hold the π extra header and the alignment byte at the π position. Table 3 summarizes the packet formatter functions for different combinations of MODE and NRS parameters. NRS MODE Input packet number Output packet number Function 0 2, 3 1 2 Byte copy 0 1 2 2 Rearrange bit 1 2, 3 4 9 Byte copy, insert "position hold" 1 1 8 9 Rearrange the bit and insert the “Position Hold” Table 3 where the “MODE” parameter includes the strong packet specification and is used to identify the strong packet format; and, as mentioned above, the “NRS” parameter indicates whether the non-systematic RS is not used. The encoder (when NRS = 0), for example, generates a strong packet that is encoded by the FEC block into two symbol segments, or is it 1246881 (22) Description of the invention: !,, say two, .... The non-systematic RS encoder (when NRS = 1) shall be used, for example to generate a set of strong packets encoded as FEC blocks into nine packet segments. According to the MODE parameter, it is better to use two bits to identify the four possible modes: Print as MODE 00 means no strong H] packet to be transmitted standard stream; MODE 01 means an H-VSB stream; MODE 10 Indicates a 4-VSB stream; and MODE 11 represents a virtual 2-VSB stream. If MODE=00, other parameters can be omitted.

In more detail, the packet formatter block 402 includes three functional units: 1) a basic formatter, 2) a parity byte position calculator; and 3) a "position buffer" interposer. That is, as shown in FIGS. 8A and 8B, when MODE=2 or 3, and respectively for NRS=0 (FIG. 8A) and NRS=1 (FIG. $B), MODE=2 or 3's the basic formatter The packet 411 bytes are copied into two bytes 412a and 412b. If MODE = 1, that is, as shown in Figures 9A and 9B, and NRS = 0 (Figure 9A) and NRS = 1 (Figure 9B), the basic format will rearrange the elements of the input packet. The bit rearrangement is performed in the H-VSB mode to ensure, for example, that the bit 415 belonging to the "strong stream" will always enter the MSB bit position, and the bit 417 belonging to the "post stream" The LSB bit locations of the re-formatted packets 418a, 418b will always be entered, as shown in Figures 9A and 9B. That is, as described above, the packet formatter unit 402 of Figure 7 will include a pair of "positional gripper" interposer functions. The alignment "Position Holder" interposer block is only used when NRS = 1 (i.e., when an additional alignment bit generator is used). This will be inserted into each of the eight (8) packets by placing the "positional hold" of three (3) header bytes and 廿 (2〇) alignment bytes. Take -28- 1246841 (23) mwmwrn wide s <. f t.· ^ %<svxv. ·· «· , <,,> Pack: Mei:i:※:i suspect:!: Fiber collar: i-face S tear machine? · 爹嫩嫩知热微 Specially converts eight (8) packets into nine (9) packets. The header byte will always be placed at positions 0, 1, and 2 within each packet and scrambled. When constructed, the location of the byte corresponding to the location of the alignment byte may be first filled with a zero value. All other remaining byte locations can be filled in sequence with the speaking bit tuple. Figure 10 illustrates an alignment "location reservation" mechanism for an exemplary scenario (NRS = 1). The basic formatter converts a 207-byte data packet 450 into 414 bytes (i.e., equals two (2) packets). The reserved bit positions 460a, 460b, and 460c for each packet are determined according to the following equation (2): m = (52 * n + (k mod 52)) mod 207 (2)

Where m is the number of output bytes and η is the number of input bytes, that is, n=0 to 206, and k=0 to 311 corresponds to the number of packets. To ensure that the 20-bit byte locations for each packet will always correspond to the last 20 bytes of the packet, the m-values of the alignment byte locations can be calculated for only n=187 to 206 (these The η value will correspond to the last 20 bytes of a packet). That is, in an example, the input of k=0 and 187 to 206 will give the position of the bit byte of the packet 0 to 202, 47, 99, 151, 203, 48, 100, 152, 204-, 49, 101. , 153, 205, 50, 102, 154, 206, 51, 103, 155. This means that the alignment byte ΡΒ0 should be placed at position 202 within packet 0 so that its position will be at 1 87 within packet 0 after being misplaced. Similarly, the alignment bit ΡΒ1 must be placed at position 47 and so on. It has been observed that for some packets, the alignment byte will either fall within the packet header position (m=0, 1 and/or 2), ie m should not equal 0, 1 or 2, which This is because the first three positions of the packet are reserved for three null values 'header -29-1246841 (24). To avoid this situation, it is necessary to increase the range of η by the number of alignment bytes (i.e., up to three) that fall within the range of the header position. Thus, when calculating 20 m values for different packets, it can be observed that when k mod 52 = 1 -TB, some of these m values will be 0, 1, and/or 2. For example, when k mod 52 = 0, it can be observed that no m value will fall within the header byte location. In this case, all 20 m values will be set to the parity bit position. When k mod 52 == 1, it can be observed that one of the calculated m values will be 0 (and this is the header byte). In this situation,

The range of η is extended by 1, so that η becomes 1 8 6 - 2 0 6 . In this way, 21 m values are calculated and discarded by m in the position of the header byte.

value. The remaining 20 m values are set to the parity bit f and the location of the register. When k mod 52 = 2, it can be observed that two of the calculated values of m will be exactly 0 and 1 (and this is the header byte). In this case, the range of η is extended by 2 so that η now becomes 185-206. Thus, 22 m values (20+2 extra) are calculated and discarded by m values that fall within the position of the header tuple. The remaining 20 m values are set to the bit byte location. Table 4 now lists the number of packets for all other exceptions. The table also lists the additional m numbers to be calculated. The number of packets mod 52 needs to be calculated from the range of the number of m η 0 0 187- 206 1 1 186- 206 2 2 185 - 206 3 3 184-206 4 3 184-206 -30- 1246841 _____ (25) 5 3 184 - 206 6 2 185 - 206 7 1 186 - 206 8-51 0 , 187-206 Table 4 In particular, as shown in Figure 10, since each packet 450 contains 207 bytes, the basic formatter will split this Into two new packets 4 5 1 , 4 5 2, each containing 207 packets. The alignment position register insertion mechanism executed by the packet formatter specially processes each new packet 45 1 , 452 to include 20 alignment bits in the misplaced positions 460a, 460b, ..., etc. And 3 header bytes 454. Thus, from the new packets 451, 452, the packet formatter will generate new packets 45 Γ, 452', thereby accommodating all alignment and header bits. Thus, the new 207-bit tuple packet 45 contains 184, 203, 20-bit location reservations and 3 null header bits 454. That is, as shown in FIG. 10, this means that an original data packet 450 will be mapped to three new packets 451', 452' and a third 453, the first two being completely filled, and the third party 453 'It will only be partially filled in. Before a data byte is inserted into the new packet 451, 452', 453', the location is checked to see if it belongs to a pair of bytes. If the location does not correspond to the location of any of the alignment bytes, the data packet will be placed at that location. If the location does belong to the location of an alignment byte, the location of the byte is skipped and the next location of the byte is checked. Repeat this process until all the bytes are placed in the new packet. As a result of this conversion, each of the nine output packets will include 92 bytes from the input packet (i.e., input packet 450). In a specific embodiment, when NRS = 1 - 31 - 1246841 (26) WMmm I A Ήϋυ *, , the minimum granularity selected for NRP is 9 segments. When the randomized processor reads in the data, 4 of the 9 packet blocks will contain the information byte, while the remaining 5 packets contain no information. The packet formatter expands the information in the four packets to nine packets via the aforementioned procedure. This ensures that the rate of payload data that is more than necessary is not taken up.

In accordance with the novel proposed technique of the present invention, a number of bits must be transmitted to a receiver device so that the receiver can decode the correct transmission mode. This mode typically contains the number of strong packets, modulation patterns, and redundancy levels that are interpolated for trellis encoding operations. This information can be transmitted in the reserved bit portion of the field sync section 138. In particular, in order to effectively detect the transmitted information, it is necessary to add additional coding bits. According to a preferred embodiment, the code of the spread spectrum type can be used to encode the information into N bits, as described below.

For example, bit 1 can be encoded as b, where b = { 1 1 0 0 1 1 0 0}. In this example, N=8. Then, bit 0 can be encoded as { 1 1 1 1 1 1 1 1} xor b, resulting in { 0 0 1 1 0 0 1 1}. Each bit is encoded this way and inserted in this field sync. Thus, at the HDTV receiver, a standard correction algorithm can be employed to detect the transmitted bits. This coding technique provides a way to detect information bits by using simple coding hardware under extremely severe interference conditions. The proposed DTV system will need to transmit a few bits. For example, 2 bits to represent the modulation type, 1 bit to represent trellis coding redundancy, 4 bits to represent the number of strong packets in each field, and 1 bit 'to $-32 - 1246841 (27)

WmnmWM

Reed- Solomon information. A total of 8 bits need to be transmitted in this example. If each bit is encoded into 8 bits, a total of 64 bits (i.e., 82) will be required in a field sync segment. Since this occupies most of the reserved bits in the data segment sync, one way to reduce the number of bits occupied by these bits is that the coded bits can be divided into two groups, each containing a 32-bit length. Then one of the groups will be sent when the job is transferred in the even field (that is, when the middle PN63 of the A53 ATSC standard is not reversed), and the other 32 bits will be sent when the odd field is transmitted (ie, When the middle PN63 is reversed). In this way, the existing field synchronization sequence structure can be utilized to reduce the number of bits needed to be transmitted per block. Another alternative technique may require the addition of one (1) coded bit carried by the unit and carrying the type information. In this way, the group of bits does not need to be tied to the field synchronization pattern.

While the invention has been described as being the preferred embodiment of the present invention, it is understood that various modifications and changes may be made in the form and details without departing from the spirit of the invention. Accordingly, it is intended that the present invention be construed as being limited by the scope of the invention Schematic Representation Symbol Description Component Number Chinese 100 Prior Art High Resolution Television (HDTV) Transmitter 105 Data Random Processor 110 ReedSolomon (RS) Encoder Unit • 33 - (28) (28)丨 晶 财 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶Encoder unit synchronization bit sequence multiplexer synchronization bit sequence preamble insertion unit filter device VSB modulator, radio frequency (RF) upstream converter prior art high resolution television (HDTV) receiver strong packet data packet standard bit string Stream AT SC Streaming - Tuner Bits Bits Scrambling Blocks Data Bits IF Filters and Detectors NTSC Filter Synchronization Units • 34- 1246841 (29) 250 Equalizers and Phase Trackers 260 trellis Decoder unit 270 data de-interleaver 2~B0 Reed Solom η η decoder 330 trellis encoder 335 external coding circuit 336a-336d multiplexer 353 8/2 control bit 355 data line 3 59 standard trelli s encoder block 360 precoder 363 content 370 encoder 3 80 symbol mapper 400 strong packet misplacer block 40 1 misplacer 402 packet formatter unit 405 normal / rugged multiplexer 412a-412b bit Group 4 15 Bits 4 1 7 Bits 418a-418b Bytes 450 Data Packets 45 1 Packets is·!

-35- 1246841 (30) Invention report page 452 Packet 45 1、4 5 3 ′ Packet 454 Header byte 4—6 0 a - 4 6 0 c Reserved position of the alignment byte -36-

Claims (1)

1246 material! Patent application No. 1121622... I am replacing this (June 94) — '.. _.:::.., picking up, applying for patent range 1. A digital signal for transmitting encoded data packets Transmission systems (201, 300) that contain a strong packet that is normally transmitted and that contains information transmitted over a strong bit stream, the system comprising: a first forward error correction (FEC) Unit (110), which can be used to encode packets belonging to each of the strong and normal data bit streams; - a strong processor unit (115, 205) for receiving each strong packet (207) containing priority data, And processing the packets to generate the strong bit stream; - a trellis encoder unit (330) for generating a stream corresponding to the trellis encoded data bits of the normal and strong stream elements, The apparatus (380) used by the encoder is a coded data bit map for mapping from a strong packet to a symbol (R) according to one or more symbol handling rules; - a selective second forward error correction ( FEC) coding unit (125), By reading only the strong bit_stream packet, and only for the 'strong stream packet to generate the bit byte, ensuring backward compatibility with a receiver device; and - a transmitter device (160, 170, 180), in a backwards compatible manner, the strong bit dream streams are individually or collectively streamed and streamed to the normal bit, and transmitted to a fixed frequency bandwidth communication channel The receiver device (200), - wherein the existing receiver device (200) is capable of receiving and processing the packets of the strong bit symplectic stream according to a null value ί $月正κ: II packet. 2. The digital signal transmission system (300, 400) of claim 1, wherein the receiver device comprises a new receiver device capable of receiving and at a lower T0V than the standard bit stream , to handle the packet of the strong bit contention. 3. The digital signal transmission system of claim 1, wherein the strong processor unit (115, 205, 400) for processing the strong package comprises: a receiving device (401) for receiving the strong packets And misregistering each of the strong packets of the input bit stream; and a packet formatter unit (402) for using the symbol mapping rules for the strong packets and selecting whether to have the existing receiver device Backtracking compatibility to process the strong packet (450); the formatter device (402) includes means for reading the strong bit group (411) from the strong dislocation device and generating two or more corresponding to each strong packet (450) The device of the data block (412a, 412b) facilitates the robust coding operation within the trellis encoder unit. 4. The digital signal transmission system of claim 3, wherein the packet formatter (402) further comprises: a arranging device for arranging information bits in each of the strong octets to the two or more data The least significant bit (LSB) position in the block (412a, 412b) to facilitate the encoding operation in the trellis encoder unit, wherein the remaining bits in the most significant bit (MSB) position will be more year-old) Positive replacement The order is determined according to the rules of the adopted symbols. 5. The digital signal transmission system of claim 4, wherein the packet formatter further comprises an insertion device for inserting a plurality of position reservation bytes at each of the two or more data blocks ( 460a, 460b), when selected to ensure traceback compatibility, the location reserved byte can be used to ultimately receive the alignment byte provided by the second FEC encoding unit (125). 6. The digital signal transmission system of claim 5, wherein the packet formatter (402) further comprises an insertion device for inserting three header bytes (454) into each data block. Identifying the packet at the receiver device, wherein each location reserved byte includes a pre-calibrated location within each of the two or more data blocks (451, 452) to ultimately receive the three headers Bytes. 7. The digital signal transmission system of claim 5, wherein the position reserved bytes are inserted in a position including a byte position spread over the entire data block (451, 452). Or more than one location, and one or more of the location reserved bytes in the data block, the location is located in such a way that when misplaced, the button can be obtained at the end of the packet The result of the alignment of the alignment byte of the contiguous byte location. 8. The digital signal transmission system of claim 6, further comprising a bit byte generator device (125) for selecting trellis for strong packets when selected to ensure backward compatibility The byte obtained after the encoding operation is decoded, and the generator further takes Correcting (more) replacing the alignment bit position information (460a, 460b, 460c) of each strong packet, generating the alignment byte from the second FEC unit, and placing the alignment byte Placed in the position of the holder in the strong package. 9. The digital signal transmission system of claim 1, wherein the multiplexer device (405, 210) is further included to multiplex the normal stream packet and the strong packet according to a predefined algorithm. 10. The digital signal transmission system of claim 1, wherein the one or more mapping rules (370, 380) comprise selecting one of the following groups: a virtual 2_VSB symbol mapping rule, 4-VSB The symbol mapping principle and H-VSB mapping to Fabe, J. 11. The digital signal transmission system of claim 1, wherein the alignment byte is mapped to one of the 8-VSB classes, according to the Advanced Television Systems Committee (ATSC) standard 8-VSB Bit stream standard. 12. A method of transmitting a digital signal (201, 300), the digital signal comprising encoded data packets comprising a normal packet of normal transmission and a strong packet containing information transmitted by the strong bit stream, The method comprises: a) encoding, in a first forward error correction (FEC) unit (110), packets belonging to each of the strong and normal data bit streams; b) receiving each strong packet containing priority data And processing the packets to generate the strong bit stream (115, 205); c) generating a stream (330) corresponding to the trellis encoded data bits of the normal and strong stream elements, and One or more symbols ^1246841 The law of response, the trellis coded data bits of the strong packet are mapped to symbols; d) in a second forward error correction (FEC) coding unit (125), by reading only the strong bit string Streaming packets, and only those strong_stream packets to generate alignment bytes, selectively ensuring backward compatibility with a receiver device; and e) on a fixed bandwidth communication channel Passing the strong bit stream (160, 170, 180) to a receiver device, one of the existing receivers, in a backtracking compatible manner, individually or collectively and in the normal bit stream The device (200) is capable of receiving and processing the packets of the strong bit stream in accordance with a null packet. 13. The method of transmitting a digital signal according to claim 12, wherein the receiver device comprises a new receiver device capable of receiving and processing the strong bit in accordance with a TOV that is lower than a standard bit stream The metadata stream is packetized. 14. The method of transmitting a digital signal according to claim 12, wherein the step of processing the strong packet (400) comprises: - receiving the strong packet and misplace an input bit stream (400) Decapsulating; and - formatting the strong packets (402) according to a symbol mapping rule (380) for the strong packets, selecting whether to have backward compatibility with a receiver device, wherein the format The step of decoding includes reading the strong bit groups (411, 450) from the misplacer and generating two or more data blocks (412a, 412b) corresponding to the respective strong packets to facilitate 1246881 A strong coding job within the trellis encoder unit. 15. The method of transmitting a digital signal according to claim 14 of the patent scope, wherein the packet formatting step further comprises: arranging information bits in each strong byte to be the lowest in the two or more data blocks; Bit (LSB) position to facilitate the step of encoding the trellis encoder unit, and sequentially determine the remaining bits in the most significant bit (MSB) position according to the symbol mapping rule of the taken line . 16. The method of transmitting a digital signal according to claim 14, wherein the packet formatting step further comprises inserting a plurality of location reserved bytes (460a, 460b, 460c) in the two or more data. Steps at locations within blocks (451, 452', 453') that are ultimately received by the second FEC when selectively ensuring traceback compatibility The alignment bit groups provided by the coding unit. 17. The method of transmitting a digital signal according to claim 16 wherein the packet formatting step further comprises inserting three header bytes (454) into each data block (451, 452', 453). , in the receiver; setting the step of identifying the packet, wherein each location reserved byte includes a pre-calibrated location within each of the two or more data blocks to ultimately receive the three Header byte. 18. The method of transmitting a digital signal according to claim 16 wherein the plurality of location reserved bytes are interpolated to one or more locations comprising a byte group spread over the entire data block. Multiple locations, and the location reserved bytes are one or more within the data block The positioning manner of the multiple positions is such that, after being misplaced, the alignment result of the alignment bit group according to the position of the contiguous byte group can be obtained at the end of the packet in the subsequent misplacement step. 19. The method of transmitting a digital signal according to claim 17 of the patent application, further comprising the steps of: - When selected to ensure traceback compatibility, the byte obtained after the trellis encoding operation for the strong packet can be de-proposed, - the position information of the alignment bit of each strong packet is obtained, - The alignment byte is generated from the second FEC unit, and the alignment byte is placed at a location buffer location within the strong packet. 20. The method of transmitting a digital signal according to claim 12, further comprising multiplexing (210, 405) a normal rate stream packet and a strong packet according to a predefined algorithm. 21. The method of transmitting a digital signal according to claim 12, wherein the strong packet trellis encoded data bit is transferred to a symbol; the step comprises using one or more selected from the following group The law of mapping (370, 380): the virtual 2-VSB symbol mapping rule, the 4-VSB symbol mapping rule and the H-VSB mapping rule. 22. A high resolution digital television signal transmission system (201, 300) operable to transmit encoded MPEG compatible data packets received by a digital television receiving device, the packets comprising normal packets transmitted as normal, and containing A strong packet of information transmitted by a strong bit_stream, which The system includes - a first forward error correction (FEC) unit (110), which can be used to format packets belonging to each of the strong and normal data bits; - a strong processor unit (115, 205), Used to receive each strong packet (207) containing priority data, and to process the packets to generate the strong bit stream; a trellis encoder unit (330) for generating a stream corresponding to the trellis encoded data bits of the normal and strong stream elements, the apparatus (380) used by the encoder to More symbolic response law is transmitted from the strong packet to the coded data bit map of the symbol, a selective second forward error correction (FEC) coding unit (125), by reading only the strong bit stream Encapsulating, and capable of generating a parity byte only for the strong stream packets, ensuring backward compatibility with a receiver device; - a digital television signal transmitter device (160, 170, 180) for streaming the strong bit streams individually or collectively and in the normal bit stream in a backtrack compatible manner, while at a fixed The bandwidth communication channel is transmitted to a receiver device (200), and - a device for transmitting a bit received by the receiver device, wherein the information is included to enable the receiver to map according to the symbol used To correctly decode the strong packets, wherein the existing receiver device (200) is capable of receiving and processing the packets of the strong bit_stream according to the null packet, and a new receiver 1246841 ai 〇. ] 夂q m n positive replacement page I The device is capable of receiving and processing the strong bit stream packets in a TOV that is lower than the standard bit stream. 23. The high resolution digital television signal transmission system (201, 300) of claim 22, wherein the transmitted bits received by the receiver device (200) comprise a plurality of information bits, which are based on strong packets The number, modulation, and redundancy levels interpolated for trellis coding are used to describe the digital signal transmission mode. 24. The high resolution digital television signal transmission system of claim 22, wherein the transmitted information bits are spread-spectrum coded prior to transmission, and the bit lines that are encoded for transmission are The reserved bit portion within the data field sync segment (138). 25. The high resolution digital television signal transmission system of claim 22, wherein the mode information bit represents a symbol mapping technique applied to the strong packet, the symbol mapping technology (370, 380) may include One of the 2-VSB, 4-VSB, and H-VSB symbol mapping modes is selected, and whether the selective second FEC encoding unit is utilized.