TWI246651B - An enhanced general input/output architecture and related methods for establishing virtual channels therein - Google Patents

Abstract

A point-to-point interconnection and communication architecture, protocol and related methods are presented. A method for enhancing an input/output bus comprising: receiving information for transmission to an external agent through a general input/output bus; and dynamically allocating a subset of a total bandwidth available over the general input/output bus as a virtual channel to enable transmission of the information to the communicatively coupled component.

Description

1246651 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case No. 6/314, 7〇8 or the title is a high-speed point-to-point interconnection and the priority of the communication architecture, agreements and related methods. The provisional application is by Ajan〇vlc. And others apply on August 26, 2, and are assigned to the assignee of this application. The present invention is generally related to the general output-in-bus-bar architecture, and more specifically the present invention relates to a high-speed point-to-point interconnection and communication architecture 'agreement and related methods. The background of the computer ^ Computer equipment, such as computer systems, servers, network switches and routers, wireless communication devices and the like are generally composed of a number of different components. Such components typically include a processor, microcontroller or other control system, a memory system, input and output interfaces, and the like. In order to facilitate communication between such components, computer equipment has long relied on a body-use input/output (GI〇) busbar to enable different components of the computer system to be connected to each other to support the numerous applications provided by such devices. . One of the most common of these traditional GIO bus architectures is the interconnection of peripheral 7C components, or the P C busbar architecture. This pc is a busbar standard (the peripheral components interconnected on December 18, 1998) (p(:I) local busbar specification revision 2.2) defines a chip, expansion board for interconnecting a computer device in any form. And processor/memory subsystems -6-1246651 (2) I send a multi-station parallel busbar architecture on the continuation page. The contents of this PCI local bus standard have been explicitly incorporated herein by reference. Used. Although the traditional PCI bus has a data flow of 13 3 megabits per second (ie, 3 3 bits per 3 3 MHz), the PCI 2.2 standard allows each pin connected in parallel to reach every 3 3 3 megahertz of 6 4 bits, resulting in a theoretical data flow of just over 1 billion bits per second. In this regard, the data traffic provided by such traditional multi-station PCI bus architectures is by far Sufficient bandwidth has been provided to accommodate the internal communication needs of even the most advanced computer equipment (eg, micro-powered servo equipment, network equipment, etc.). However, processing power at current processing speeds exceeding the 1 GHz threshold The upgrade, combined with the extensive scheduling of multi-frequency Internet access, has made the traditional GIO architecture such as the PCI bus. Architecture a bottleneck in this type of computer equipment. Another limitation related to the traditional GIO architecture is It is generally not suitable for operation/processing, etc. (or time-dependent) data strings. An example of such an isochronous data string is a multimedia data string that requires an isochronous transfer device to ensure data consumption and reception. The data is as fast as possible, and the audio portion and the video portion are synchronized. The traditional GI 0 architecture processes data asynchronously or at random intervals as allowed by the bandwidth. Unsynchronized processing of such isochronous data can result in misalignment Audio and video, and as a result, specific providers of isochronous multimedia have the habit of prioritizing specific data on other materials, such as prioritizing audio data on video data, allowing at least the last user Receive a fairly stable audio signal string (ie, not interrupted) so that it can enjoy the songs that have been serialized, understand the story, etc. 1246651 (5) The artist should understand that one or more of the elements of the present invention may be suitably included in hardware, software, a propagated signal, or a combination thereof. All references in this specification to ''an embodiment' The ''an embodiment'' description is intended to indicate that a particular feature, structure, or characteristic described in connection with this embodiment is included in at least one embodiment of the invention. The use of the terms "or" or "an embodiment" may not necessarily be the same as the same embodiment. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Before the EGIO interconnects the architecture and the details of the communication protocol, it is helpful to introduce the components of the vocabulary that will be used in this detailed description: • Notification: Use EGIO flow control to refer to a process controlled by using one of the EGIO protocols. A receiver that updates information to convey information about the effectiveness of its process control credits; • Completion: A site addressed by a request Logic device; • Completer identification (ID): - one or more of the bus identifier (eg, number) of the completer, the device identifier, and a function identifier uniquely identifying the finisher of the request A combination; • Completion: A reference to a sequence used to terminate, or partially terminate, a completion. According to one example, one conforms to a previous requirement, and in some cases the completion contains data; • Configuration space · one of the four address spaces within the EGIO architecture. Installing a device with a packet having a configuration space address; • Component · a physical device (ie, located in a single packet); -10 - 1246651 (βΛ I send a sequel to the sequel • Data link layer · · located in the transaction The middle layer of the EGIO architecture between the layer (top) and the physical layer (bottom); • DLLP: the data link layer packet is a packet generated in the data link layer to support the link management function; • Downlink: reference to a component correlation The process of location, or information leaving the host bridge; • Endpoint: an EGIO device with one 〇〇h type of configuration space header; • Flow control: one for transmitting receive buffer information from a receiver to a transmission To prevent receiving buffer overflows and to allow transmitters to include ordering rules; • Flow Control Packet (FCP): - used to transfer flow control information from one transaction layer in one component to one transaction in another Layered transaction layer packet (TLP); • Function: identifies a separate part of a multifunction device by a unique function identifier (eg, a function number) in the configuration space; : Defines the I/O interconnection structure implemented in this EGIO architecture. A layer is characterized by a single host bridge that matches the link closest to the counting device (such as the host CPU); • Hierarchy area: use one to get more than one EGIO The interface host bridge divides an EGIO hierarchy into multiple partition blocks, wherein such partition blocks are referenced as a hierarchical region; • Host bridge: connects a host CPU complex to one or more EGIO links; Space: One of the four address spaces of this EGI〇 architecture; 1246651 m I invention. Saying the continuation page • Line: a set of differential signal pairs of a physical link, one pair for transmission, and one pair for Receive. One N interface consists of N lines; • Link: a pair of simplex communication paths between two components; a collection of two ports (one transmission and one reception) and their interconnected lines; Busbar: a logical connection in a collection of devices having the same number of busses in the configuration space;

• Logic device: an element of an EGIO architecture that responds to a unique device identifier in the configuration space; • Memory space: one of the four address blanks of the EGIO architecture; • Information: one has an information space type Packet; • Information space: one of the four address spaces of this EGIO architecture. Containing a special period as defined in P C I as a collection of information spaces, thus providing an interface with legacy devices;

• Legacy software model: software model for a legacy device that must be initialized, discovered, installed, and used (eg, in an EGIO that interacts with legacy devices to facilitate the inclusion of PCI software models in legacy bridge machines); • Physical layer: The communication medium between the two components is directly connected to the layer of the EGIO architecture; • 埠: an interface that is combined with a component, located between the component and an EGIO link; • Receiver: the component that receives the packet information through a link is Receiver (sometimes referred to as a target); • Requirement: A packet used to start a sequence is referenced as a requirement. A requirement includes some opcodes, and sometimes includes address and length, data -12 - 1246651 (8) I _ say _ continuation page or other information; • Requirement: a logic device that first introduces a sequence into the EGIO area; • Require Identification (ID): A combination that uniquely identifies one or more of the bus identifier (eg, bus number), device identifier, and a function identifier of one of the requestors. In most cases, an EGIO bridge or switch will be required to pass from one to the other without modifying the requestor. In addition to an EGIO bus, a bridge from a busbar should generally store this requestor identification for use when establishing a completion for the request; • Sequence: a single request and zero or more related ones The requestor performs the completion of a single logical transformation; • Sequence Identification (ID): - A combination of one or more of a signature identified by the requestor, wherein the combination is uniquely identified as part of a common sequence Requirements and completion; • Separate transaction: ·- A single logical transformation containing an initial transaction (separation requirement), where this tag (completer or bridge), initially one or more in this completion (or bridge) After the transaction (separation is completed), it is terminated by a separate response, so that the read data (if it is readable) or a completion message is returned to the requester; • Symbol: a quantity of 10 bits is generated as 8-bit/10-bit encoded result; • symbol time: the time period required to place a symbol on a line; • mark · a number assigned by the requestor to a known sequence, Distinguish from other sequences (IDs) that are part of the sequence identification; 1246651 (7) send. 諕 諕 • • Transaction layer packet: TLP is a packet generated in the transaction layer to deliver a request or completion; Trading layer: The outermost (topmost) layer of this EGIO architecture, operating on the level of transactions (eg, read, write, etc.); • Transaction Descriptor: A component of a package header, except for the address And the nature of a transaction is described in addition to the length and type; and an exemplary electronic device. FIG. 1 is a simplified electronic device including an enhanced general-purpose input-output (EGIO) bus bar architecture, protocol, and related methods as illustrated by the present invention. Block diagram of device 1 0 0. In accordance with the example illustrated in Figure 1, the electronic device 100 is depicted as including one or more of the processors 102, a host bridge 104, switches 108, and endpoints 10 10, each connected together as shown. In accordance with the teachings of the present invention, at least one or more of the host bridge 104, switch 108, and endpoint 1 10 have an EGIO communication interface 106 to facilitate one or more aspects of the present invention. As noted, each of the components 102, 104, 108, and 110 is communicatively coupled to at least one other component via a communication link 112 that communicates through the EGIO interface 106 to support one or more EGIO communication channels. As mentioned above, the electronic device 100 is intended to represent various traditional and non-traditional computer systems, servers, network switches, network routers, wireless communication user units, wireless communication telephone construction components, personal digital assistance, and solid One or more of the header, or any of the electrical devices, may benefit from communication resources introduced through the EGIO interworking architecture, communication protocols, or related methods described herein. In accordance with the example illustrated in Figure 1, the electronic device 1000 has one or more processors - 1 0 2 of the -14 - 1246651-description page (10). As used herein, processor 102 controls one or more aspects of the functionality of this electronic device 100. In this regard, processor 102 typically represents any and all of the control logic including, but not limited to, a microprocessor, a programmable logic device (PLD), a programmable logic array (PLA), an application. One or more of a special integrated circuit (ASIC), a microcontroller, and the like. Host bridge 104 provides a communication interface between processor 102 and/or a processor/memory complex and one or more other components 108, 110 of the EGIO architecture of the electronic device, and as such In fact, it is also the foundation of this EGIO architecture hierarchy. As used herein, a host bridge 1 〇 4 is referenced to a logical entity of the EGIO hierarchy, which is closest to a host controller, a memory controller hub, a 10 control hub, or any of the above. Combinations, or some combination of wafer collection/CPU components (ie, located in a computer system environment). In this regard, although as a single unit as illustrated in Figure 1, host bridge 104 may suitably be considered a single logical entity that may suitably have multiple physical elements. According to the example illustrated in Figure 1, host bridge 1 〇 4 and one or more EGIO interfaces 106 are placed together to facilitate communication with other peripheral devices, such as switch 1 〇 8, endpoint 1 1 0 and Repatriation bridges 1 1 4 or 1 16 that are not explicitly stated. According to one implementation, each EGIO interface 106. represents a different EGIO hierarchy. In this regard, the implementation illustrated in Figure 1 represents a host bridge 1 0 4 having three (3) hierarchical regions. It should be noted that although described as including a demultiplexed EGIO interface 106, it is desirable to have a single interface 106 with multiple channels to provide alternate implementation of communication with multiple devices. -15 - 1246651 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 According to one implementation, a switch 108 identifies the closest bridge to the host bridge, and all other ports are one of the next ports (i.e., one interface or interface 106). In accordance with one implementation, switch 1 0 8 appears to be a configuration software (e.g., legacy configuration software) as a P C I to P C I bridge, and a P C I bridge device for routing transactions.

In the content of the switch 1 0 8 , the transaction that equals the same transaction for both the receiving and the transmitting is defined as the downlink. In accordance with an implementation, switch 1 支持 8 supports all types of routing of transaction layer packets (TLPs), except for any one of the other transactions related to a locked transaction sequence. In this regard, all broadcast messages should normally be routed from the receiver to all other ports on switch 108. A transaction layer packet that cannot be routed to a switch should be terminated as a TLP that is not supported by switch 1 〇 8. Unless a modification is required to comply with a different protocol of a required transport (e.g., a transport port incorporating a legacy bridge 1 14 , 1 16 ), switch 1 0 8 typically does not convert the transaction layer packet (TLP) from receiving to The transfer will be modified later. It should be understood that the switch 1 0 8 represents other devices, and in this regard, the type and type of traffic are not known at all. In accordance with an implementation that will be described in detail below, the flow control and data integration perspectives of the present invention are based on a linked implementation rather than an endpoint-to-endpoint. Therefore, in accordance with this type of implementation, a switch 1 0 8 is added to the agreement for process control and data integration. In order to incorporate flow control, switch 108 maintains a separate flow control for each port to improve the performance characteristics of this switch 108. Similarly, by using the following TN - 1246651, the description of the sequel (12) describes the detection of the TLP error detection device to input the TLP of the switch, and the switch 1 0 8 supports data integration processing according to a link basis. . According to an implementation, a lower string of switches 1 〇 8 is allowed to form a new E GI 〇 hierarchical region.

Next, with respect to Figure 1, an endpoint 1 1 定义 is defined as any device having a type 〇 十六 hexadecimal (0 Oh) configuration space header. Endpoint device 110 may be a requestor or a EGIO semantic transaction completer representing itself or on behalf of one other non-EGIO device. Examples of such endpoints 1 1 0 include (but are not limited to) EGIO compliant graphical devices, EGIO compliant memory controllers, and/or implementations between EGIO and some, for example, a universal continuous bus (USB), Ethernet And a device connected to one of the other interfaces similar thereto. Unlike a legacy bridge 114, 116, which will be described in more detail below, as an endpoint for a non-EGIO compliant device, 110 may not be able to properly provide complete software that supports such non-EGIO compliant devices. Although a device that connects a host processor complex 102 to an EGIO architecture is considered a host bridge 1 〇 4, it may be exactly the same device type as the other endpoints 1 1 0, this endpoint i 1 0 is set in the EGIO architecture that can only be identified by its position on the processor complex 102. According to the description of the present invention, the endpoint 1 1 〇 can be merged into one or more of the three types. (1) Legacy and EGIO compliant endpoints, (2) legacy endpoints, and (3) EGIO compliant endpoints, each with different rules of operation in the EGIO architecture. As described above, the EGIO acknowledgment endpoint 1 I 0 is identified from the legacy endpoint (eg, 18, 120), where an EGIO endpoint 1 1 0 will have a type 0 0 h configuration space -17 - send _ continuation Page 1246651 (13) Head. Any of these endpoints (1 1 0, 1 1 8 and 1 2 0) supports a completion. Such endpoints are allowed to generate configuration requirements and may either leave the endpoint or be an EGIO-requested endpoint, but this classification may adhere to the following additional rules. Legacy endpoints (e.g., 118, 120) are allowed as a completer and allow 10 requests to be generated. If the legacy software support requires it, the legacy endpoint (118, 120) is allowed to act as a completer to generate the lock. The legacy endpoint typically does not issue a lock request. The EGIO appoints that the endpoint 1 1 0 is generally not used as a completer; and does not generate 10 requirements. EGIO Endpoint 1 10 is not required as a Completion and is not required as a Requirer to generate a lock. EGIO/to legacy bridges 114, 116 define endpoint 1 10, an important software support for legacy devices (118, 120), such as physical support, that is coupled to this EGIO architecture. In this regard, the bridges 114, 116 generally have an upper _ 埠 (but there may be a lot of J 许多 埠 (but only one). According to this legacy soft lock requirements. A legacy bridge 114, 116 an application chain to support process control, and support EGIO architecture and data integration rules, which will be explained in more detail below. As used herein, the use of link 1 1 2 is representative of any medium It includes (but is not limited to) copper wire, optical wire, wireless communication-infrared communication link, and the like. According to a Fan- EG10 link 1 1 2 is a different pair of series lines, a pair of each send and receive communication In order to provide a requirement for the full duplex communication function to be classified as a proper support to support a request, there is a requirement to be fixed. Poetry I 0 requires support to be locked including complete soft, one legacy >), its package The model support should be controlled according to the flow of a communication channel, example implementation, self-support transmission support. Root 1246651

瞵 瞵 V V V (14) This link provides a scalable continuous clock frequency with an initial (basic) operating frequency of 2.5 GHz. The interface width in each direction can be scaled by the xl, x2, x4, x8, xl2, xl6, x32 physical lines. As described in more detail below and below, the EGIO link 112 can suitably support multiple virtual channels between devices to provide access to one or more virtual analog channels, such as a channel for audio and One channel is used for the communication of non-stop communication of isochronous traffic between such devices. EXAMPLE EGIO INTERFACE ARCHITECTURE Figure 2 is an illustration of an exemplary EGI interface 160 architecture used by one or more components of an electronic device to facilitate communication between such components, in accordance with an exemplary embodiment of the present invention. In accordance with the example depicted in FIG. 2, the EGI interface J06 can be suitably represented as a protocol stack including a transaction layer 202, a data link layer 604, and a physical layer 208. As shown, this physical link layer interface includes a logical sub-block 2 1 Ό and a physical sub-block, and as shown, the various portions thereof will be explained in more detail below. Transaction Layer • In accordance with the teachings of the present invention, transaction layer 202 provides an interface between the EGI0 architecture and a device core. In this regard, one of the transaction layer 202's primary responsibility is to assemble and tear down packets (ie, transaction layer packets or TLPs) for one or more logical gamma devices within a host device (or medium). The address space, the transaction layer type, and the use of transactions form the basis for information conversion between an initial medium and a target medium. According to an exemplary embodiment, four address meta-frames are defined within the innovative EGI0 architecture, including, for example, a configuration address space, a memory address 2 -19 - 1246651, and a continuation page (15). An input-input address space, and an information-address space, each of which has its own specific purpose. The memory space (76 6) transaction includes one or more of the read request and the write request to convert the data to a location corresponding to a memory or to convert data from a location corresponding to a memory. Memory space transactions can use two different address forms, such as a short address form (such as a 32-bit address) or a long address form (such as a 64-bit long). The conventional read, modify, and write sequences are provided in accordance with an exemplary embodiment of the EGIO architecture using a lock agreement semantics (i.e., one of the media can appropriately lock access to the modified memory space). More specifically, the following string locks are allowed in accordance with specific device rules (bridges, switches, endpoints, legacy bridges). As noted above, such locking semantics are supported in legacy device support. The I 0 space (7 0 4 ) transaction is used to access an input memory corresponding to an I 0 address space (for example, a 16-bit I 〇 address space). For example, the Intel processor-specific processor 1 〇 2 and other instructions based on this processor contain n 10 definitions. Therefore, 102 transactions include read requests and write requests to convert data to a 10 corresponding location or to convert data from a corresponding address. The configuration space (702) transaction is the configuration space used to access this EGI0 device. Transactions for this configuration space include read requirements and write requirements. A conventional processor like this does not generally include an original configuration space, which is corresponding to a device compatible with a conventional PCI configuration space access device (for example, using a CFC/CFC8 PCI configuration device# 1). Alternately, a memory distortion device can be suitably used to access the configuration space. 1246651 Summary of Invention (continued) (16) Define information space (708) transactions (or information only) to support intra-band communication through the interface 169 between EGIO media. Since the legacy processor does not include support for the original information space, it can be started through the EGIO medium between the EGIO interfaces 106. According to an example implementation, a conventional "sideband" signal such as an interrupt and power management requirement is implemented as information to reduce the number of pins that need to support such legacy signal ^. Some processors and P I buss contain a "special cycle" concept, which also corresponds to the information in the EGIO interface 106. According to an embodiment, the information is generally divided into two types: standard information and sales restriction information. In accordance with the illustrated exemplary embodiment, the standard information includes a general purpose information group and a system management information group. The general purpose information may be a single target information or a broadcast/multicast information. The system management information group may be appropriately composed of one or more of interrupt control information, power management information, order control original words, and error signals, and an example thereof will be described below.

In accordance with an example implementation, general purpose information includes information for support of locked transactions. Implemented in accordance with this example, which illustrates an unlocked message, wherein the switch (e.g., 1 0 8) should generally pass the unlocked message through any of the participating transactions. An endpoint device (e.g., 1 10, 1, 18, 120) that receives an unlocked message when unlocked will ignore this information. Otherwise, the locked device will be unlocked according to the reception of a non-locking message. In accordance with an example implementation, the system management information group contains special information for ordering and synchronizing information in order. This type of information is a piece of protection information that is used to impose strict ordering rules on transactions that are generated using components that receive the EGIO architecture. According to one implementation, this type of protection information can only be used on the Internet -21 - 1246651

(π) The selected secondary set of components, such as endpoints, reactions. In addition to the foregoing, information representative of a correctable error, an uncorrectable error, and an irreversible error is also considered in advance, such as by using a trailing error prequel.

According to one aspect of the invention, as described above, the system management information group provides a signal that utilizes in-band information to cause an interrupt. According to an implementation, the ASSERT JNTx/DEASSERT_INTx message is passed in, wherein the release of the affirmative interrupt information is transmitted to the processor complex through the host bridge 1 〇 4. In accordance with the illustrated example, the usage rules for the ASSERT_INTx/DEASSERT_INTx information pair reflect the ASSERTJNTx/DEASSERTJNTx information for the PCI INTx# signal found in the PCI specification above. From either device, each transmission to ASSERT_INTx should generally have a corresponding transmission of DEASSERT_INTx. For a particular "x" (A, B, C, or D), a DEASSERT_INTx should generally have an ASSERT_INTx transfer before the transfer. The switch should normally route the ASSERTJNTx/DEASSERTJNTx message to the host bridge 104, where the host bridge should normally Track ASSERT_INTx/DEASSERT_INTx information to generate virtual interrupt signals and correspond to these signals to the system interrupt source. In addition to the general purpose and system management information group, the EGIO architecture also establishes a standard architecture in which core logic (such as chipset) vendors Vendor-qualified information that is itself compliant with the specific operational requirements of its platform can be defined. This architecture is established through a common information profile, in which the code defining the vendor-qualified information is defined as "preserved π." Transaction Descriptor A Transaction Descriptor is a device used to transfer transaction information from the origin to the point of service and back. It provides an extendable device for providing a -22 - 1246651 sequel (18) to provide a general interconnection of new types of emerging applications. In this regard, the transaction descriptor supports the identification of transactions within the system, the modification of the default transaction sequence, and the combination of transactions with virtual channels using virtual channel ID devices. A graphical illustration of a transaction descriptor is related to Figure 3. Turning to Figure 3, an illustration of a data telegram containing an example transaction descriptor is depicted in accordance with the teachings of the present invention. In accordance with the teachings of the present invention, a transaction descriptor 300 containing a global identifier field 3 2, an attribute field 3 06 and a virtual channel identifier field 3 0 6 is described. In the example implementation described, the global identifier field 3 0 2 containing a local transaction identifier field 308 and a source identifier field 3 1 0 is described. • Global Transaction Identifier 3 0 2 As used herein, the Global Transaction Idicate is unique to all major requirements. In accordance with the example illustrated in Figure 3, the global transaction identifier 3 0 2 is composed of two secondary fields: a local transaction identifier field 3 0 8 and a source identification field 3 1 0. According to one implementation, the local transaction identifier field 3 0 8 is an octet field generated by each requestor and is unique to all major requirements for the completion of the requestor. This source identifier uniquely identifies an EGIO medium with an EGIO hierarchy. Thus, this local transaction identifier field provides a global identification and source ID for a transaction within a hierarchical region. According to one implementation, this local transaction identifier 308 allows for the request/complete reachable reverse order from one of the requirements to be processed (the order rules will be explained in more detail below). For example, reading one of the sources can produce readings A 1 and A2. The target medium serving these read requests is first sent back as a complete request for the A2 transaction ID, followed by a return to completion as -23 · 1246651 (19) A 1. In the completion of the package header, the local transaction I D information will be traded. Devices of this type are particularly useful for devices that use distributed memory systems because they allow them to be processed in a more efficient manner. Note that support for the completion of such violations will be ensured for completion. As described above on the buffer space 1, since the EGIO switch 1 0 8 is not an endpoint (ie, only the perfect endpoint is passed), it does not need to reserve buffer space. A single read requirement can result in a lot of completion. Up to the next is the completion of a single read requirement. This can be supported by providing the original part of the package header (ie, completing the header). According to an example implementation, the source identifier field 3 1 0 contains a value that is unique to each logical EGIO device. The EGIO device may suitably include multiple logic devices. The value is divided during the penetration mode to the standard PCI bus arrangement. The source ID data line is internally and independently established using, for example, the information available at the time of accessing the device in the initial configuration and the internal EGIO device, such as a device number and a number, which is generated from the EGIO. The configuration is generated during the period of the device used in the PCI configuration. As for the latest switching devices, such devices will need to re-record the number of sinks and streams on this bit cycle to start the SHPC soft. According to one of the EGIO architectures, a physical component can be identified. It is important to identify the processing read. Please assume that a read first allocation is issued. If the request is completed to the order of return, the address of the complete completion of the seal is flat. The attention of a single unit is configured to match the number of bus numbers of the source ID number. According to a real-time use of one phase, the latest connection and the wearing of the various body stacks suitably contain -24 - 1246651 resignation (20) one or more logic devices (or media). The various logic devices are assigned to match the configuration period for which the number of devices is aligned, i.e., the concept of the number of devices incorporated within the logic device. According to one implementation, up to sixteen logical devices are allowed within a single physical component. Each of such logic devices may suitably include one or more string actuators, for example up to a maximum of sixteen. Thus, a single physical component can suitably include up to 256 string actuators.

Transactions marked with different source identifiers belong to the EGI output (10) source, so the ideas that can be arranged in order are handled independently of each other. For tripartite and equivalent transactions, if necessary, use a protection order to control the original words to force them in order. As used herein, the Global Transaction Identifier field 3 0 2 of the Transaction Descriptor 300 supports at least one set of the following rules: (a) Marking each required requirement with a Global Transaction ID (GTID) ;

(b) Generally, a unique GTID should be assigned to each major mandatory requirement starting with a medium, (c) Non-required completion requirements do not use this GTID's local trading ID field 3 0 8, and this local The transaction ID field is considered reserved; (d) The target does not modify this requirement GTID under any circumstances, and only repeats it in the header of a completed packet for all completions related to this requirement, where the initiator Use this GTID to match this to the original requirements. • Attribute Field 3 0 4 As used herein, attribute field 3 04 illustrates the characteristics of the transaction and the closing of the invention (21). In this regard, this attribute field 3 0 4 is additional information for providing modifications that allow for the processing of fixed values within the transaction. These modifications apply to different perspectives of transaction processing within the system, such as hardware coherence management (such as reconnaissance attributes) and prioritization. An example form of this attribute field 3 0 4 is represented by the subfield 3 1 2 to 3 1 8 . As shown, the attribute field 3 0 4 includes a prioritized secondary field 3 1 2 . An initializer can be used to modify this prioritized secondary field to assign a prioritization to the transaction. In an example implementation, by way of example, the type or quality of a service or a medium service feature may be combined with this prioritization within the field. 3 1 2 to affect the processing of other system components. Keep the reserved attribute field 3 1 4 as a future, or sell limited use. The reserved attribute field can be used to implement a possible usage model using prioritization or privacy attributes, and the order attribute field 3 1 6 provides any information that conveys the order type of the order of the default order in the same order plane (where the order surface contains The initial traffic by the host processor (102) and the I〇 device with its corresponding source ID). According to an example implementation, a ''0' order attribute indicates the applicable default order order rule, where a "factory" order attribute indicates an arbitrary order in which the write can pass the write in the same direction, and the read is completed. Writes can be passed in the same direction. The device using random order semantics is mainly used to remove data and transactions having a fixed order of information for reading/writing status information. Use the Scouting Property Field 3 1 8 to provide a fast buffer storage area that can be modified to modify the coherency management rules of the same value in the same sequence. -26 - 1246651 Send a description (2) Any information about the type of pervasive management One of the sequence faces contains the initial traffic by a host processor 102 and I 0 with its corresponding source ID. According to an example, a “reconnaissance attribute field 3 1 8 value conforms to a default value fast-- ^ rush storage area coherence management structure, in which the transaction is investigated to implement hardware level fast buffer storage area coherence. In respect, the value of the reconnaissance attribute field 3 1 8 " 1 '' aborts the cached coherent management structure of this default value, and does not detect transactions. More specifically, the accessed material is not non-storage, or its coherence is managed by software. Lu Virtual Channel ID Field 306 As used herein, virtual channel ID field 3 0 6 identifies a transaction-dependent independent virtual channel. According to an embodiment, the virtual channel identifier (VCID) is a four-bit field that allows identification of up to sixteen virtual channels (V C) based on a pre-transaction. An example of a VC ID definition is provided in Table I below:

VCID VC name usage model 0000 default value channel general purpose traffic 0001 isochronous channel This channel is used to transmit 10 traffic, which has the following requirements: (a) does not detect 10 traffic to allow limited service timing; and (b) use The quality of an X/T contract control service (where χ = amount of data, and τ = time) 0010-1111 Reserved future use form I: Virtual channel ID code -27 - 1246651 Issue. Ming Ming performance page (23) Virtual Channels In accordance with an aspect of the present invention, the transaction layer 202 of the EGIO interface 106 can establish one or more virtual channels within the bandwidth of the communication link 112. The virtual channel (VC) perspective of the present invention described above is used to define an independent and logical communication interface within a single entity EGIO link 112. In this regard, the use of independent VCs for traffic can benefit from different processing procedures and service prioritization. By way of example, a defined quality of service is required to ensure that the X number of data that has been converted during the time period T corresponds to an isochronous (time-dependent) virtual channel. Transactions corresponding to different virtual channels may not have any order requirements related to each other. That is, virtual channel operations are independent logical interfaces with different process control rules and choices. Regarding the initial traffic by the host processor 102, the virtual channel can be controlled in the required order according to the default ordering device rules, or can be completely processed in reverse order. According to an example implementation, V C includes the following two types of traffic, general purpose, traffic, and isochronous traffic. That is, in accordance with this example implementation, two types of virtual channels are described: (1) general purpose I Ο virtual channels, and (2) isochronous virtual channels. As used herein, transaction layer 202 maintains independent flow control for each of one or more channels actively supported by the component. As used herein, all EGI(R) compliant components should generally support a general type I virtual channel, such as virtual channel 0, where there is no required order relationship between different virtual channels of this type. With a default value, VC 0 is used for general purpose I〇 traffic, while VC 1 is allocated to handle isochronous traffic. In the alternate -28-1246651 continuation page (24) In practice, any virtual channel can be assigned to handle isochronous traffic. Description 1 Description of the EGIO concept for a multi-channel, independent, manageable virtual channel in Figure 4.

Turning to Figure 4, an illustration of an exemplary EGIO link 1 1 2 containing multiple virtual channels (V C ) is depicted in accordance with one aspect of the present invention. In accordance with the illustrative example of FIG. 4, an EGIO link 112 is included that includes multiple virtual channels 402, 404 established between EGIO interfaces 106. According to an example implementation, the virtual channel 4 0 2 is illustrated, indicating traffic from multiple sources 4 06 A to N, and at least distinguished by its source ID. As described, the virtual imaginary channel 420 is established without the order requirements between transactions from different sources (e.g., media, interfaces, etc.).

Similarly, the description includes virtual channels 4 from multiple source multiple transactions 408 A through N (where, each transaction is represented by at least one source ID. According to the example, transactions from source ID 0 406A are strongly ordered, Otherwise, it is modified by the attribute field of the transaction header 306, and the transaction from source 408N does not describe such an order rule. The following Figure 10 is an example method for establishing and managing a virtual channel. It is easier to process all the responses in order, but the transaction layer 202 attempts to improve the results by allowing the transactions to be reordered. To simplify this reordering, the transaction layer 202 "marks" the transaction. That is, according to an embodiment, the transaction Layer 2 0 2 adds a transaction descriptor to each packet, causing elements within the EGIO architecture to be optimized (eg, by reordering) its transmission time without losing track of the order in which the original processing packets were processed. The class transaction descriptor is used to simplify the routing through the EGIO interface hierarchy and the completion of the -29 - 1246651 _ _ _ continuation (25) packet routing. The innovative view of this EG]0 interconnect architecture and protocol is that it provides reverse-order communication to increase data sinking by reducing idle or wait states. In this regard, transaction layer 2 0 2 uses one. The group specification defines the order requirements for EGIO transactions. The transaction order requirements are defined to ensure proper software operation, the soft system is designed to support the manufacturer and consumer order model, and at the same time allows for different order models (eg for graphical addition) Any order of application) improves the transaction processing flexibility of the application. The following describes the order requirements for two different types of models, a single order surface model and a multiple order plane model. • Basic transaction order - single "order surface" The model assumes that two components are connected through an EGIO architecture similar to the EGIO architecture of Figure 1: a memory control hub that provides an interface to a host processor and a memory subsystem, and an interface that provides a 10 to 10 system. I〇 control hub. Both hubs contain internal trains that handle inbound and outbound traffic, and this is simple. All I 〇 traffic in the model corresponds to a single “order surface”. (Please note that the Transaction Descriptor Source ID information provides a unique identification for each medium within an EGIO hierarchy. Please note the I corresponding to this source ID. 〇 Traffic can convey different transaction order attributes.) Define the order rules for this system configuration between the initial traffic and the initial traffic of the host. From this, the perspective I 0 traffic and initial traffic corresponding to a source ID The host processor represents traffic implemented within a single "sequence plane." An example of such a transaction order rule for Form II is provided below. This -30- 1246651 _ (26) Invention says _ continued on the table The defined rules apply to all transaction types in the EGIO system with memory, I〇, configuration and information. In Table II below, the column represents the first of the two transactions and the column represents the second. The table item indicates the order relationship between the two transactions. The table items are defined as follows: • Yes - generally should allow the second transaction to cross the first transaction to avoid a pause. (When a blockade occurs, the second transaction is required to cross the first. Generally, fairness should be known to avoid shortage.) • Yes/No - No requirement. The first transaction can optionally cross the second transaction or be blocked by it. • No - generally should not allow the second transaction to cross the first transaction. This is to maintain the same order. Columns crossed the bar? WR_Req (no need to be %) (column 2) RDReq (column 3) WRReq (need to be completed) (column 4) RD a Comp. (column 5) WR_Comp. (column 6) WR_Req no need to complete (column A) no a. No b. Yes Yes/No Yes/No RD A Req (column B) No a. No b. Yes / No Yes / No Yes / No Yes / No WRReq (Needs Complete) (Column C) No Yes / No C. No d. Yes / No Yes / No Yes / No RD_Comp. (Column D) No Yes Yes a. No b. Yes / No Yes / No WR - Comp. (Column E) Yes / No Yes Yes / No Yes / No Form Π : Transaction Order and Pause Avoidance for Single Order - 31 - 1246651 Sending Instructions (27) Column: Column ID Table II Description of Item A2 A published memory write request (WR_REQ) — Generally, there should be no more published memory write requirements. A3 should generally allow a published memory write request to cross the read request to avoid stalls. A4 a. Generally, a published memory WR_REQ should not be allowed to pass over a memory WR_REQ having a property to be completed. b. General should allow a published memory WRJRJEQ to cross 1〇 with configuration requirements to avoid stalls. A5, A6 does not require a published memory WR_REQ to be completed. In order to allow this flexibility when the suspension is still guaranteed, the EGI0 Agreement provides the medium for acceptance of the guarantee. B2, C2 These requirements cannot cross a published memory WR_REQ to maintain a constant write order that requires support for the manufacturer/consumer usage model. B3 a. In a basic implementation (ie, processing that is not in reverse order) does not allow reading requests to cross each other. b. In an alternate implementation, read requests are allowed to cross each other. Transaction identification is necessary to provide such functionality. A B4, C3 allows different types of requirements to be blocked or crossed each other. _ B5, B6, C5, C6 allow these requirements to be blocked or overfilled. D2 read completion cannot cross a published memory WRJReq (to maintain a constant write order). _ D3, D4, E3, E4 - —— -- ________ - ___* — Generally, it should be allowed to complete the non-publishing requirements to avoid a pause. / D5 a. In a basic implementation, reading completion is not allowed to cross each other; b. In an alternate implementation, reading completion is allowed to cross each other. In addition, it is appropriate to require the identification of a constant transaction. / E6 allows these to be done across each other. It is important to use a transaction ID to maintain the tracking transaction. / D6, E5 Different types of completion can cross each other. E2 allows the published memory WR_REQ to block write completion or allow write completion to complete the published memory WRJIEQ. Such write transactions actually move in the opposite direction and therefore do not have an order relationship. 1246651 i_ (28) I send _ sequel to the continuation page • Advanced trading second - "multi-faceted" transaction order model The previous part defines the order rules within a single "order plane". As mentioned above, EGIO interconnection architecture and communication The agreement uses a unique transaction descriptor device to correlate additional information with a transaction to support more complex order relationships. The fields within the transaction descriptor allow for the creation of multiple "order faces" that are based on an I 0 traffic order perspective. In terms of each other, each "order face" is a queue/buffer logic that conforms to a specific 10 device (specified by a unique source ID) and the host processor's queue/buffer logic that carries the initial traffic. The composition is generally defined only in this order between the faces π. The rules that support the manufacturer/consumer use model and prevent pauses defined in the previous section are used to separate the "order faces" from other ''sequences''. For example, the completion of the reading for the initial requirement by the "face" may be sufficient for the completion of the reading of the initial requirements of the ''face'. However, the reading for the face is completed and used for the face. The reading of Μ is not enough to allocate the initial published memory from the host. Although the use of the corresponding device allows multiple multiplexed faces, you can “disassemble some or all of the sequence faces together to simplify this implementation” ( That is, combining a number of independently controlled buffers/FIFOs into a single entity). When all the faces are removed together, the Transaction Descriptor Source ID device is only used to assist in the routing of the transaction, and is not used to relax the order of the 10 separate columns of traffic. In addition to the foregoing, the transaction description apparatus provides an order of defaults within a single order plane that modifies a use order attribute. Therefore, the modification can be controlled in accordance with the advance transaction. Transaction Level Agreement Packet Format -33 - 1246651 (29) Send;, Chain. Continued Page · As explained above, this innovative EGIO architecture uses a package base protocol to change the information between the transaction layers of two devices communicating with each other. This EGIO architecture generally supports memory, configuration, configuration, and information transaction types. General use requirements or completion of the package to deliver such transactions^ which only use the completed package when requested, that is, to return the data or to approve the receipt of a transaction.

With respect to Figure 6, an illustration of an example transaction layer agreement is depicted in accordance with the teachings of the present invention. Performed in accordance with the illustrative example of FIG. 6, a T L P header 600 containing a field, a type field, an extended type/extended length (ET/EL) field, and a length field is described. Please note that some T L P contain information as determined by the format of the location specified in the header. No T L P should contain more than the limit set by MAX-PAYLOAD-SIZE. According to an example implementation, the T L P data is a naturally arranged four-bit element and is incremented by a four-bit double character (DW). As used herein, the Form (FMT) field illustrates the form of T L P according to the following definition:

• 000 - 2DW head, no data • 00 1 - 3DW head, no data • 0 1 0 - 4DW head, no data • 10 1 - 3DW head, with information • 1 10 - 4DW head, with information • All other coded TYPE fields are reserved to indicate the type code used within this TLP. According to one implementation, the form [2: 0] and the type [3: 0] should generally be decoded to determine the T L P form. According to an implementation, use the value in type [3: 0] to determine whether to use the extension -34 - 1246651 _ (30) I to indicate the continuation type / extended length field to extend the type field or length field. The ET/EL field is typically only used to extend the length field with memory type read requirements.

The length field provides an indication of the length of the payload, again in the increment D W : 0000 0000 - 1DW 0000 000 1 = 2DW

1 1 1 1 1 1 1 1 - 256DW

A summary of at least one sub-set of an example T L P transaction type is provided in the following Table IV for its corresponding header form and a description:

TLP Type FMT [2:0] Type [3:0] Extension Type [1:0] Description Initial Process Control Information (FCP) 000 0000 00 Initial Process Control Information Update Process Control Information (FCP) 000 0001 00 Update Process Control Information Memory Read Requirement (MRd) 001 010 1001 E19E18 Memory Read Requirement for Extended Type of Length [9:8] / Extended Length Field Memory Predicate Requirements - Locked (MRdLK) 001 010 1011 00 Memory Requirement - Locked Memory Write Requirement - Published (MWR) 101 110 0001 00 Memory Write Requirement - Published 10 Read Requirement (IORd) 001 1010 00 10 Read Requirement 10 Write Requirement (IOWr) 101 1010 00 10 Write Requirement Configuration Read Type 0 (CfgRdO) 001 1010 01 Configuration Read Type 0 Configuration Write Type 0 (CfgWrO) 101 1010 01 Configuration Write Type 0 Configuration Read Type l (CfgRdl) 001 1010 11 Configuration Read Type 1 Configuration Write Type 1 (CfgWrl) 101 1010 11 Configure Write Type ί -35 - 1246651 Send Eagle says the continuation page (31)

Information Request (Msg) 010 011s2 slsO Information Requirement - The subfield s[2:0] specifies the information for a group. According to an implementation, the information field is decoded to determine the information request (MsgD) 110 011s2 slsO having the data required to complete a request. The information request - the secondary field s [2:0] describes the information of a group. According to the implementation of 'decoding this information field to determine the information required to complete the specific cycle if required to complete (MsgCR) 010 llls2 slsO need to complete the data request - subfield s [2:0] to explain a group of information. According to an implementation, the information field is decoded to determine a specific period of information required to complete the data (MsgDCR) 110 llls2 slsO has the information required for data completion - the secondary field s [2:0] describes the information of a group. Based on an implementation, this particular periodic field is determined to determine a particular period. Undocumented Completion (CPL) 001 0100 00 Completion of no data - except for successful completion, for 10 and configuration write completion, some information is completed, and the memory with completion status is completed. Completion of the data (CplD) 101 0100 00 with the completion of the data - for memory, 10, and configuration read completion, and some information is completed. Completion for locked memory read (CplDLk) 101 001 01 for locked memory read - otherwise as CplD

Additional details regarding requirements and completion are provided in Annex A, the contents of which are incorporated herein by reference. One of the limitations of process control that is generally associated with traditional process control structures is that it counters the problem that should occur, rather than first reducing the occurrence of such problems. opportunity. For example, in a conventional PC I system, a transmitter will transmit information to a receiver before it receives a message to suspend or terminate transmission before further notice. This type of requirement can then occur after the requirement to retransmit the packet at a known point in the transmission. Those skilled in the art should be aware that this method of reaction can result in a wasteful cycle and is inefficient in this regard. To cope with this limitation, the transaction layer 202 of the EGI interface 106 includes a flow control device that reduces the chance of an excessive state occurring, and also provides a pre-linked order for the virtual channel established between the initiator and the finisher. Support for the rules. In accordance with an aspect of the present invention, a flow control "credit" concept is referenced in which a receiver shares information about (a) the size of the buffer (within credit), and (b) has one for The currently available buffer space of one of the various virtual channels established between the transmitter and the receiver (ie, based on the full virtual channel). This allows the transaction layer 2 0 2 of the transmitter to maintain a transparent virtual channel. An estimate of the available buffer space (eg, available credits) allocated to the transmission, and if it determines that the transmission would cause an excess condition in the receive buffer, it can adjust its transmission through each virtual channel in advance. In one aspect of the invention, the transaction layer 202 references flow control to prevent overshoot of the receiver buffer and to comply with the order rules described above. In accordance with an implementation, the flow control device of the transaction layer 202 is used by a requestor to track one Accessing the queue or buffer space available in the EGIO link 1 1 2 medium. As used herein, flow control does not mean that a request has reached its maximum The finalizer. -37 - 1246651 Inventor's Note Continued (33)

In accordance with the teachings of the present invention, flow control is orthogonal to the data integration means for performing a reliable exchange of information between the transmitter and the receiver. That is, since the data integration device guarantees retransmission to correct corrupted and lost packets, the flow control can treat the flow of the transaction layer packet (T L P ) information from the receiver to the transmitter as perfect. As used herein, this process controls a virtual channel that contains EGIO links 112. In this regard, each virtual channel supported by the receiver will be reacted in the Process Control Credit (FCC) notified by a receiver. In accordance with the teachings of the present invention, flow control is performed by transaction layer 220 that cooperates with data link layer 220. To easily describe the description of this process control device, the following types of packet information are distinguished: (a) Published Requirements Header (PRH) (b) Requested Data Sheet (PRD) (c) Non-published Required Head (NPRH) (d) Non-published Request Information (NPRD)

(e) Read, Write, and Information Completion Header (CPLH) (f) Read and Information Completion Data (CPLD) As mentioned above, the unit of measurement within the EGIO implementation of the preemptive process control is a process control credit. (FCC). According to one implementation, a process control signal is 16 bytes for data. Regarding the stall, the unit for the process control credit is a header. As mentioned above, each virtual channel has independent process control. For each virtual channel, an identifier different from the tracking credit is maintained for the above type of packet information ((a)-(f) as shown above). According to the example described, the transmission of the packet is processed according to the following content control flow -38-1246651 (34) With: - Memory /10/ configuration read requirements: 1 NPRH unit - Memory write request: 1 PRH + nPRD unit (where η is the size of the data payload, for example, the length of the data divided by the size of the process control unit (such as 16 bytes)

- 10/Configuration Write Requirements·· 1 NPRH + 1 NPRD - Information Requirement: According to the information at least 1 PRH and / or 1 NPRH units - complete with data: 1 CPLH + nCPLD units (where η is the size of the data divided Control the size of the data unit by process, for example, 1 6 bytes)

- No data completion: 1 CPLH There are three concept registers for each type of information being tracked, each with eight? The retention bit width is used to monitor the credits used (in the transmitter), the credit limit (within the transmitter), and the credit assigned (within the receiver). This credit consumption register includes the total count of the flow control unit modules 2 5 6 consumed from the beginning. After the initial, all credit consumption registers are set to zero (0) and incremented as the transaction layer delivers the information to the data link layer. The size of the increment is related to the number of credits consumed by the information delivered. According to one implementation, when the maximum total is reached or exceeded (e.g., all 1's), the counter is rotated to zero. According to one implementation, this counter is maintained using an unsigned 8-bit module. The credit limit register contains a limit on the maximum number of process control units that can be consumed. After the interface is initially initialized, the scratchpad is set to all zeros and set to the value indicated in the flow control update information for information reception (described above). 1246651 j__ (35) j Invention Description Continued The credit allocation register maintains the total count of credits granted to the transmitter from the beginning. This count is initially set according to the buffer size and the receiver allocation method. This value can be appropriately included in the flow control update information. This value is incremented when the receiver transaction layer removes processed information from its receive buffer. The size of the increment is related to the size of the available space. According to one embodiment, the receiver should normally initially set the credit assigned to the value equal to or greater than: -PRH: 1 flow control unit (FCU); -PRD: FCU is equal to the maximum possible setting of the maximum payload size of the device,

- NPRH : 1 FCU -NPRD ·· FCU is equal to the maximum possible setting of the maximum payload size of the device, - Switching device: 1 FCU; - Switching device - CPLD: FCU is equal to the maximum possible setting of the maximum payload size of the device, or The device will always generate the maximum read request, whichever is smaller; - Root & Endpoint Device - CPLH or CPLD: 25 5 FCU (all 1's), considered by the transmitter to be an infinite number, Therefore, it will never be adjusted. In accordance with this implementation, a receiver typically does not set a credit allocation register value greater than 127 FCUs for any credit type. Instead of maintaining a credit allocation according to the following equation, a transmitter can dynamically calculate the credit allocation instead of maintaining the credit allocation register using the above counter method: -40 - 1246651 (36) C _A 2 (Recently received transmission credit Units) Seven (available receive buffer space) As mentioned above, a transmitter implements this concept register (credit use, credit limit) for each virtual channel that the transmitter will use. Similarly, the receiver implements this concept register (credit allocation) for each virtual channel held by this receiver 1. In order to preemptively prohibit the transmission of information that causes the receiving buffer to be excessive if the information is transmitted, if the credit consumption count plus the number of credit units regarding the information to be transmitted is less than or equal to the credit limit value, a transmitter is allowed to transmit one. Type of information. When a transmitter receives the flow control information indicating the completion of non-infinite credit (ie <255 FCUs) (CPL), the transmitter will complete according to the available credit adjustments. Explain that when credit is used and returned, information from different transactions is not mixed within one credit. Similarly, when credit usage and return are stated, the headers and information from a transaction are never mixed within a credit. Therefore, when some packets are locked from transmission due to lack of process control credits, the transmitter will follow the order rules when deciding which type of packet should be allowed to bypass the "delayed" packet. The return of a transaction control letter for a transaction cannot be interpreted as the transaction has been completed or system visibility is achieved. An information signal interrupt (MSI) that uses a memory write request semantics is considered as another memory write. If a subsequent F C update message (from the receiver) indicates a credit limit value that is lower than the initial indication, the transmitter should take care of this new lower limit and may provide a notification error as appropriate. According to the flow control device described herein, if a receiver receives more information than its allocated credit (beyond the allocated credit), the receiver will indicate a receiver overdue error to the reverse transmitter, and to cause this Excessive seal 1246651 _ 峨 (37) package initial data link level retry requirements. • Process Control Packet (F C P)

According to one implementation, communication between devices using Flow Control Packets (F C P ) must maintain the flow control information of the scratchpad. According to one embodiment, the flow control packet contains two DW header forms and transmits information for a particular virtual channel for six credit registers maintained by the flow control logic for each V C's receive transaction layer. In accordance with the teachings of the present invention, there are two types of F C P : initial F C P and updated F C P , as illustrated in FIG.

As described above, an initial FCP 602 is issued after the initial transaction layer. After the initial transaction layer, the update FCP 604 is used to update the information in the scratchpad. The receipt of an initial F C P during normal operation can result in a reset of the local flow control device and an initial F C P transmission. The content of an initial F C P includes at least one secondary set of notified credits for each PRH, PRD, NPRH, NPRD, CPH, CPD, and a channel ID (e.g., a virtual channel to which F C information applies). The form of an updated F C P is similar to the form of the initial F C P . Please note that although the F C header does not include the length field to share the other transaction layer packet header form, the size of the packet is clear because there is no additional D W data associated with this packet. Error Prequel Unlike the traditional error premature device, the EGIO architecture relies on tail information, which is attached to a telegram that is identified as incomplete for some of the reasons described below. According to an example implementation, transaction layer 202 uses one of several known error detection techniques, such as cyclic residual detection (CRC) error control and the like. -42 - 1246651 Summary of Invention (continued) (38) According to one implementation, in order to promote the error preamble feature, the EGIO architecture uses a "tail" & is attached to the TLP that transmits the known bad data. It may be possible to use the tail error before the transmission. Example: Example #1: A read from the main memory encounters an uncorrected ECC error example #2: — The same error on the PCI is written to the main memory example # 3 : — Internal data buffer or fast buffer The data integration error in the storage area. According to an example, the error preamble is only used to read the completed data or write the data. That is, when an error occurs in the management fee related to the data telegram, such as an error in the header (for example, A phase, address/instruction, etc. is generally not used. In this case, since a real target cannot be clearly identified, it is generally impossible to forward the request or completion of the header, so Such false preambles may suitably cause a direct or side effect, such as data corruption, system failure, etc. According to one embodiment, the error preamble is used to transmit the system. , the propagation of the error of the system diagnosis. The error pre-transmission does not use the data link layer retry, so only the TLP error detection device (such as the loop residual detection (CRC), etc.) will retry when there is a transmission error on the EGIO link 11 2 The TLP with the tail is terminated. Therefore, this tail will eventually cause the requesting starter to reissue it (on the above transaction level) or take some other action. As used in this article, all EGIO receivers ( The TLP termination with a tail can be handled if it is set in the EGI interface. The addition of a trailer support in a transmitter is selective (and thus compatible with legacy devices). Switch 1 0 8 routing A tail with the rest of the TL P. Has the same -43 - 1246651? Say. Continued page (39) The host bridge supported by the route 1 0 4 will generally route the tail with the rest of the TLP. Mark, but not so required. Error prequel is generally applicable to a write request (published or unpublished) or a read completed data. The transmitter is known to include bad data TLP should be this tail end According to an example implementation, a tail is composed of two DWs, where the byte [7: 5] is all zeros (for example, 0 0 0 ), and the bits [4: 1] are all ones ( For example, 111 1 ), while all other bits are reserved. An EGIO receiver will consider all the data in the TLP terminated with a tail error. If the error preamble is applied, the receiver will cause all data from the indicated TLP to be marked. For the bad toxic "). In the trading layer, an analyzer will generally analyze the end of the entire TLP and immediately detect the subsequent data to see if the data is complete. The data link is wide 2 0 4 As described above, the data link layer 220 of Fig. 2 is used as an intermediate layer between the transaction layer 2 0 2 and the solid layer 2 0 6 . The primary responsibility of this data link layer 2 0 4 is to provide a reliable means for exchanging transaction layer packets (T L P ) between two elements on an EGIO link 112. The data plane of the data link layer 2 0 4 accepts a TLP combined by the transaction layer 202, implements a packet sequence identifier (eg, an identification number), calculates and implements an error detection code (eg, a C RC code), and The modified TLP is presented to the physical layer 206 by one or more of the virtual channels established within the bandwidth of the EGIO link 112. The receiving data link layer 204 is responsible for detecting the integration of the received TLP (e.g., using a C RC device, etc.) and for disassembling the T L P that is integrated positively detected to the transaction layer 204 for forwarding to the device core. -44 - 1246651 _ (40) Send a description of the continuation page The services provided by the data link layer 2 0 4 generally include data exchange, error detection and retry, initial and power management services, and data link layer communication services. The various service series provided in each of the foregoing categories are as follows. Data exchange service - accepting TLP for transmission from the transport layer - accepting TLP from the physical layer and transmitting it to the receiving layer error detection & retry - TLP sequence and CRC generation - for data Linked layer retry of transmitted TLP storage - data integration detection

- Approved 'Signal and Retry DLLP - Errors for Error Reporting and Recording Devices - Linked Approval Signal Pause Timer Initial and Power Management Services - Track Link Status and Transfer Active/Reset/Off Status to Transaction Layer Data Link layer intercommunication services - for link management functions including error detection and retry - transition between data link layers of two directly connected components - not exposed to the transaction layer as used in the E GI 0 interface 1 0 6 The data link layer 2 0 4 is shown as a news conduit with various latency to the transaction layer 2 0 2 . Input Transfer Data All information on the link layer will be displayed later on the output of the Receive Link layer -45 - 1246651 _ (41) Send Grasshopper_ Continued. This latency will depend on factors including catheter delivery latency, the width and operating frequency of the junction 112, the transmission of communication signals through the medium, and the delay caused by data link layer retry. Due to these delays, the transport data link layer can use the backward pressure to transmit the transaction layer 202, and the receive data link layer transmits the presence or absence of valid information to the receive transaction layer 202. According to an implementation, the data link layer 204 tracks the EGIO. Link the status of 1 1 2 . In this regard, the DLL 204 communicates with the transaction 202 and the physical layer 206, and performs link management through the physical layer 206. According to one implementation, the data link layer contains a link control and management state machine to perform such management tasks. The status of this machine is described as follows: Example DLL link status: • Connected, Down (LD) - Entity layer reports that the link is inoperative or unconnected • Link Initial (LI) - Entity Layer Report Link is operational And positive initialization • Link Active (LA) - Standard operating mode. Link ActDefer (LAD) - Standard operation interrupt, the physical layer tries to restart the corresponding management rules for each state (refer to Figure 8): • Link Down (LD) After the component is reset, the initial state is after retrying to LD: - Reset all data link layer status information to the default value at -46 - 1246651 _ (42) When you report the continuation page LD: - Do not use TLP information and transactions Or physical layer exchange - does not exchange DLLP information with the physical layer - does not generate or accept DLLPs if left to LI:

- The indication from the transaction layer indicates that the link is not incomplete by SW • Link Initial (LI) at LI: - Do not exchange TLP information with the transaction or entity layer - Do not exchange DLLP information with the physical layer 'Do not generate or Accept DLLPs If you leave to LA: - The indication from the physical layer shows that the link training succeeds if you leave to LD: - The indication from the physical layer shows that the link training failed • Link Active (LA) When the link is active: - TLP information and transactions and Entity Layer Exchange - Exchange DLLP information with the physical layer - Generate and accept DLLPs If left to link ActDefer: - Instruction from the data link layer retry management device - 47 - 1246651 瞵 瞵 _ Continuation (43) Display required link training Or if the physical layer reports that the retraining is in progress. • Link ActDefer (LAD) When linking ActDefer: - Do not exchange TLP information with transaction or entity layer - Do not exchange DLLP information with entity layer - Do not generate or accept DLLPs If leaving to link active: - Indication from entity layer Training has been successful if left to link down: - indication from the physical layer shows training failure data integration as used in this article, data link layer packets (DLLPs) are used to support the EGIO link data integration architecture. In this regard, according to an implementation, the EGIO architecture provides the following DLLPs to support linked data integration management: • Endorsement signal DLLP: TLP sequence number J-approval signal - used to indicate the successful reception of some number of TLPs • Negative acknowledgement signal DLLP : TLP sequence number negative acknowledgement signal - used to indicate a data link layer retry • acknowledge signal pause DLLP: indicates the number of recently transmitted sequences - some forms used to detect TLP loss, as described above, transaction layer 2 0 2 provides TLP The boundary information is given to the data link layer 2 04, causing the DLL 204 to apply the sequence number and the loop residual detection (CRC) error 1246461 (44) detection to Τ L Ρ. According to an example implementation, the receiving data link layer utilizes the number of detected sequences, C R C, and any error indication from the receiving entity layer to validate the received T L Ρ. In the case of an error in a T L ,, the data link layer is retried for recovery. • CRC, sequence number, and retry management (transmitter) for conceptual "counters" and, flags, "description" used to determine TL ρ C RC and sequence number and support data link layer retry The device is as follows: CRC and sequence number rules (transmitter) • Use the following 8-bit counter: 〇TRANS-SEQ - store the number of sequences that are ready for transmission • set to all 0s in the link down state, • In increments after each TLP transmission • When at all ''1's), the quantity causes a repayment to all, 〇,, . . . No 疋 DLLP reception causes the value to be set back to the sequence indicated in the negative DLLp Count ACKD_SEQ - Stores the sequence number approval signal in the most recently received link to the link approval signal DLLP. • Sets the number of sequences to all τ in the link down state to all, 1, and octaves. l ρ 〇 counter 1 RANS - SEQ stores this number TRA If TRANS SEQ is equal to (ACKD - SEQ-1) modulo 256, the transmitter should generally not transmit another TLP until an acknowledgement signal DLLp updates ACkd_SEQ causative mud (TRANS-SEQ =ACKD_SEQ-1) modulo 25 6 No longer true. -49 - 1246651 发? Nickel Continuation (45) I take TRANS_SEQ for TLP, using:

〇 Waiting for a single byte value in advance to the TLP 〇 Waiting for a single reserved byte to the TLP in advance • Calculating a 32-bit CRC for use with the TLP of the following algorithm and appending to the TLP's tail end The polynomial is 〇x〇4Cl 1DB7

- The same CRC-32 used by Ethernet is used for calculations:

1) The initial value calculated by CRC-32 is the DW formed by waiting for 24 "0"s to the number of sequences in advance. 2) Using the DW from the byte 0 containing the header to the last DW of this TLP in order from the transaction layer Each DW of the TLP is calculated by the succession C RC

3) Complement the bit sequence calculated from this and the result is TLP CRC 4) CRC DW is attached to the tail end of this TLP

• The copy of the transmitted TLP should normally be stored in the data link layer retry buffer. • When an acknowledgement signal DLLP is received by another device: 载入 Load the ACKD_SEQ 〇 retry buffer with the value specified in this DLLP. The sequence number eliminates the TLP: • from the previous value of ACKD_SEQ+1 • to the new value of ACKD_SEQ • When a negative acknowledgement signal DLLP is received by other elements on the link: 〇 If a TLP is currently being converted to the physical layer, this conversion Continue to 〇〇 - 1246651 嗯 - - (46) Complete the conversion of this TLP until the following steps are completed. The additional TLP is not taken from the transaction layer. The retry buffer eliminates the TLP with the number of sequences in the range. • ACKD_SEQ+1 The previous value • the value stated in the number field of the negative acknowledgement signal sequence of the negative acknowledgement signal DLLP

All remaining TLPs in the retry buffer are redisplayed to the physical layer for retransmission in the original order. • Note that this will include all TLPs with the number of sequences in the range: 否定Negative acknowledgement signal DLLP + 1 Negatively recognize the value of the value 〇TRANS_SEQ-1 in the field of the signal sequence. • If there is no TLP remaining in the retry buffer, the negative acknowledgement signal DLLP is wrong.

〇 According to the error tracking and recording items, the negative acknowledgement signal DLLP of this error should generally be recorded. The transmitter does not require further action. • CRC and serial number (receiver) Similarly, the conceptual “counter” and • For the flag, the device used to detect the TLP CRC and sequence number and support the data link layer retry is as follows: • Use the following 8-bit counter: oNEXT_RCV_SEQ - store the expected sequence for the next TLP | J number • In the link down state set to all '' 0" • 1 increment for each accepted TLP, or by accepting a TLP to clear -51 - 1246651 _ (47) send _ continuation page DLLR_IN_PROGRESS flag test When the ticket (in the description of the breach) • Each time the value is loaded (the number of transmission sequences + 1), the receipt of a connection layer DLLPJLDLLR_IN_PROGRESS flag is cleared. 〇 If the value of NEXT_RCV_SEQ is different from the value specified by a received TLP Or a loss of synchronization of the sequence number between the transmitter and the receiver when the ACKP is suspended by an acknowledgement signal; in this case: • If the DLLR_IN_PROGRESS flag is set,

〇Reset DLLR_IN_PROGRESS flag 传送"Transfer bad DLLR DLLP" error to error record/tracking 之一 注意 : 此 此 此 DLL DLLR DLLP (negative acknowledgement signal) is transmitted in error mode If DLLR_IN_PROGRESS flag is not set,

〇Set the DLLR_IN_PROGRESS flag and initially negate the approval signal DLLP

〇Please note: This indication has lost a T L P • Use the following 3-bit counter: oDLLRR_C〇UNT—Calculate the number of times DLLR DLLP was issued during a specified time period

• Set to b'OOO in the link down state • For each negative acknowledgement signal DLLP issued in increments of 1 • When the count reaches b'100: 〇 Link control state machine moves from link active to link ActDefer 〇 then heavy Set DLLRR COUNT to b'000 -52 - 1246651 ι_ (48) I send. Say. Continuation page. If DLLRR-COUNT is not equal to b'OOO, every 2 5 6 symbols will be determined by 1 :: B'000 saturation • Use the following flags:

oDLLR_IN_PROGRESS • The setting/clearing system is described below

When setting DLLR_IN_PR〇GRESS, Yi J divides all received TLPs (until receiving the TLP indicated by DLLR DLLP)

When DLLR_IN_PROGRESS is cleared, the detection as described below has been received ^ TLP • For a TLP to be accepted, the following conditions should generally be true: 〇 The number of received TLP sequences is equal to NEXT_RCV_SEQ 〇 The entity has not yet indicated any of the reception of the TLP Error oTLP CRC check J does not indicate an error • When accepting a TLP:

Forward the transaction layer of this T L P to the receiving transaction layer. If set, clear the DLLR_IN_PROGRESS flag 〇 increment NEXT_RCV_SEQ • When a T L P is not accepted:

〇 Set the DLLR_IN_PROGRESS flag to transmit a negative acknowledgement signal DLLP • The acknowledgement signal/negative acknowledgement signal sequence number field should generally contain a value (NEXT_RCV_SEQ-1) • Negative acknowledgement/: The word type (NT) field should normally indicate a negative acknowledgement signal - 53 - 1246651 ι_ (49) I send the reason for the continuation page:

〇b'00 -甴 entity layer identification reception error 〇b'01 -TLP CRC detection failure 〇b'10 - sequence number error 〇b' 11 - identification by the physical layer error frame • Receiver should generally not be allowed to receive The transmission of the CRC to the negative acknowledgement signal of a TLP exceeds 1023 symbol times, as measured from the component 〇. Note: NEXT_RCV_SEQ is not incremented. • If the receiving data link layer is not successfully received within 5 1 2 symbols. This negative acknowledgement signal DLLP is repeated after negating the excess TLP after the acknowledgement signal DLLP. 〇If you have not received the excess TLP after trying four times, the receiver will: • Enter the link that links the ActDefer state and is initially retrained by the physical layer • Indicates that a major error occurred to the error tracking and logging • Data link layer approval signal DLLP Generally, it should be transmitted when the following conditions are true: 〇 Data link control and management status The machine is in the active state of the link 〇 has accepted the TLP, but has not been approved by transmitting an acknowledgement signal DLLP, since the last approval signal DLLP After 5 1 2 symbol times or more • The data link layer approval signal DLLP can be transmitted more frequently than required. • The data link layer approval signal DLLP indicates the value in the number field of the approved signal sequence (NEXT_RCV_SEQ-1) • The approval signal pause device - 54 - 1246651 (50) mmmm. Consider the case where the link 1 1 2 misses a TLP and the receiver does not detect the presence of the TLP. Since the number of T L P sequences will not match the number of sequences expected on the receiver, the lost T L P will be detected when a subsequent T L P is transmitted. However, the transport data link layer 240 cannot generally limit the time that will be presented to the next T L P from the transport transport layer. The acknowledge signal pause device allows the transmitter to limit the time it takes for the receiver to detect the loss of the TLP. Recognize Signal Pause Device Rules • If the transmit retry buffer contains a TLP that has not been received by the acknowledge signal DLLP, and if no T L P or link DLLP is transmitted during a period of more than 1,024 symbols, an acknowledge signal should normally be transmitted to suspend DLLP. • After an acknowledgement signal suspends the transmission of the DLLP, the data link layer typically does not pass through any of the TLPs to the physical layer for transmission before receiving an acknowledgement signal DLLP from the elements on the other side of the link.

〇If the acknowledge signal DLLP is not received within a period of more than 1023 symbols, the acknowledge signal is again transmitted. The DLL is suspended. - In the case where the acknowledge signal DLLP is not received, there are four successful transmissions of the 1024 symbol after the acknowledgement signal is suspended. Number • Enter a link that links the ActDefer state and is initially retrained by the physical layer • Indicates the occurrence of a major error to error tracking and logging. Entity Layer 206 Please continue to refer to Figure 2, which depicts the physical layer 206. As used herein, this physical layer 206 insulates the transaction 202 from the data link 204 layer from the signal technology used to link the data exchange. According to the example illustrated in Figure 2, the actual -55 - 1246651 _ continuation page (5 〇 layer is separated into logic 2 0 8 and entity 2 1 0 function sub-block. As used in this article, the logical sub-region Block 2 0 8 is responsible for the "digit" function of this physical layer 2 0 6. In this regard, logical sub-block 2 0 8 has two main areas: one ready for transmission by entity sub-block 2 1 0 The transmission part of the output information, and a receiver part that identifies and prepares the received information before transmitting the received information to the connection layer 204. The logical sub-block 2 0 8 is coordinated with the physical sub-block 2 1 0 The control and management functions of the physical layer 206 are commanded by the logical sub-block 208. The EGIO architecture uses an 8-bit/10-bit transmission code. With this structure, the octet features are respectively corresponding to a four-bit code group and three bits and four bits of a six-bit code group. These code groups are linked to form a 1 0 The symbol of the bit. The 8-bit/10-bit encoding structure used by the EGIO architecture provides special Symbols, which are different from the data symbols used to represent features. These special symbols are used in the following various link management devices. Special symbols are also used to design DLLP and TLP, using clear special symbols to allow quick and easy The two types of packets are distinguished. The physical sub-block 2 1 0 includes a transmitter and a receiver. The symbol is provided by the logical sub-block 2 0 8 to the transmitter, which is connected in series and transmitted to the link 1 1 2 Providing a continuous symbol from the link 1 1 2 to the receiver, which converts the received signal into a one-bit _, which is de-coupled and supplied to the logical sub-block together with a symbol clock recovered from the continuous__ of the input 2 0 8. It should be understood that, as used herein, EGIO link 1 1 2 may suitably represent any type of communication - 56 - 1246651 _ (52) send a description of the continuation medium, which includes an electrical communication link, a An optical communication link, an RF communication link, an infrared communication link, a wireless communication link, and the like. In this regard, the transmitter containing the physical sub-block 2 1 0 of the physical layer 206 is (or )receive Each of the above for one or more of the communication link. Examples of communication media

Figure 5 is a block diagram depicting an exemplary communication medium containing at least one set of features in accordance with the present invention, in accordance with an exemplary embodiment of the present invention. According to the example illustrated in FIG. 5, the description of the communication medium 500 includes control logic 052, an EGIO communication transmitter 504, a memory space 506 for the data structure, and any one or more applications 5 0 8. As used herein, control logic 502 provides a source of processing to each of one or more of EGIO communication transmitters 504 for selectively implementing one of the present invention.

Or more opinions. In this regard, the control logic 5 0.2 is for representing a microprocessor, a microcontroller, a finite state, a programmable logic device, a programmable gate array, or performing control logic upon execution as described above. One or more of a functional content. The EGIO communication transmitter 504 includes a transaction layer interface 202, a data link layer interface 204, and a physical layer including a logical sub-block 208 and a physical sub-block 210 for engaging the communication medium 500 and an EGIO connection 112. One or more of the interfaces 206. As used herein, the elements of EGIO communication transmitter 504 perform similar (if not identical) functions as described above. According to the example illustrated in Figure 5, the description of the communication medium 500 includes the data link -57 - 1246651 _ (53) I 吗 伽 续 5 5 Ο 6. As described in more detail below with respect to FIG. 7, the data structure 506 may suitably include a memory space, an I 〇 space, a configuration space, and an information space used by the communication transmitter 504 to facilitate communication between electronic device devices. . As used herein, application 508 is used to represent any of a variety of applications that are selectively performed by communication engine 500 to perform EGIO communication protocols and related management functions. Example Data Structure Turning to Figure 7, an illustration of one or more data structures used by the EGIO interface 106 is described in accordance with an implementation of the present invention. More specifically, with regard to the example implementation illustrated in Figure 7, four (4) address spaces are defined for use in the EGIO architecture: configuration space 7 1 0, I Ο space 7 2 0, memory space 7 3 0 and information Space 7 4 0. As shown, the configuration space 710 includes a header field 7 1 2 that traverses the EGIO category to which a host device (eg, an endpoint, etc.) belongs. Each of these types of address spaces performs its individual functions as described above. Having described the architecture and protocol elements associated with Figures 1 through 8 of the present invention above, reference is now made to Figure 10, which depicts a flow chart of an exemplary method for managing an entity communication source of the enhanced general input and output architecture. . Turning now to Figure 10, a flow diagram of an exemplary method of managing one or more virtual channels within an entity source of a reinforced generic input-in connection is depicted in accordance with an exemplary embodiment of the present invention. According to the example illustrated in Figure 10, the method begins with block 1 0 0 2, where an EGIO interface 106 receives information for transmission to another component. In accordance with an example, a transaction layer 202 of an EGIO interface 106 receives the information from a processing medium within a host component. -58 - 1246651 Summary of Invention (5) Within block 1004, the EGIO interface 106 determines whether the received information is associated with an established virtual channel, or whether a new virtual channel is required. According to one implementation, transaction layer 202 uses such sources and destinations to identify such information to make such decisions. If the transaction layer 202 in block 1004 identifies that the information is associated with an existing virtual channel, the transaction layer 202 generates a transaction layer packet (TLP) for the appropriate virtual channel to convey this through the physical layer 206. Receiving information to the appropriate virtual channel, the entity for block 1006 typically outputs the transmission on the source. If the information in block 1004 requires a new virtual channel to be suggested, then transaction layer 202 makes another decision regarding the type of virtual channel required by block 1008. According to an example implementation, the transaction layer 202 determines the decision based at least in part on the content of the received information. As described above, according to an example implementation, the EGIO architecture supports multiple types of selected virtual channels based on the quality of the service requirements for the information to be communicated. In this regard, the transaction layer 202 determines whether the received information is time-dependent (isochronous), and if so, establishes one or more isochronous virtual channels to support such information. transmission. According to one embodiment, the type of content is determined by analyzing the content itself or by the type of media (e.g., the type of application) that transmitted the content to the transaction layer. In block 10 12, the EGIO interface 106 creates a virtual channel with independent flow control and order rules that pass through the physical source of the EGIO link 112 to transfer information to another element. More specifically, as described above, the transaction layer 202 generates a transaction layer packet representing the virtual channel type, as transmitted through the data link layer 204 to the entity for routing to the EGIO link 1 1 2 - 59 - 1246651 Bun said _ continued (55) The physical layer on the medium 2 0 6. In accordance with the teachings of the present invention, as described above, the transaction layer 202 maintains separate flow control and order rules for each virtual channel established by the transaction layer 202. In this regard, an architecture, protocol, and related method for establishing and managing multiple virtual channels within the entity source of the EGIO Link 112 has been described. Alternating embodiment

9 is a block diagram of a storage medium having stored thereon a plurality of commands including one or more aspects of implementing an EGIO interconnection protocol and a communication protocol in accordance with another embodiment of the present invention. command. In general, Figure 9 depicts a mechanically accessible medium/device 900 having content stored therein that includes an innovative EGIO interface that implements the present invention when executed by an access machine. At least one collection of 1 0 6 .

As used herein, mechanically accessible medium 900 is used to represent any of such media known to those skilled in the art, such as a variable memory device, a non-volatile memory device, Magnetic storage media, optical storage media, propagating signals, and the like. Similarly, executable commands are used to reflect any of a number of software languages known in the art, such as C++, video programming languages, Hypertext Markup Language (HTML), Java, Extensible Markup Language (XML). And similar to it. In addition, it should be understood that the media 9 〇 〇 does not need to be set up with any host system. That is, the medium 900 may suitably exist in a communication connection-execution system or a remote server accessible by an execution system. Therefore, since alternate storage media and software embodiments are contemplated within the spirit and scope of the present invention, the software of Figure 9 will be considered for illustrative purposes. -60 - 1246651 _ (^56) Send a description of the margin page

The present invention has been described in the detailed description of the specification and the description of the invention, and the invention is not limited to the specific features or steps described. Step. Rather, the specific features and steps disclosed are merely illustrative of the implementation of the claimed invention. It will be apparent, however, that various modifications and changes can be made thereto without departing from the spirit and scope of the invention. Therefore, the specification and drawings are to be considered as illustrative and not limiting. This description and the summary of the invention are not intended to be exhaustive or limiting of the invention. The names used in the following claims should not be used to limit the invention in the specific embodiments disclosed herein. Rather, the scope of the invention is to be fully determined by the scope of the appended claims, which In accordance with the foregoing, the following is the scope of patent application:

-61 -

Claims (1)

[24] Patent Application No. 1122495 Patent Application Replacement of Chinese Patent Application (November 1993) Niu L· :Λ- ... i, Ji: Pick up, apply for patent scope 1. A method of strengthening the input and output bus, The method includes: receiving information through the general output into the bus to transmit to an external medium; and dynamically allocating the set of available total bandwidths on the general output into the bus as a virtual channel for starting the information Transfer to the component of the communication link. 2. The method of claim 1, wherein the method further comprises: identifying a type of virtual channel, whereby the information transmission is initiated based at least in part on the content of the received information. 3. As in the method of claim 2, identifying one of the types of virtual channels includes: determining whether the received information includes isochronous content; and, if available, establishing an isochronous virtual channel to help isochronous Transmission of sexual content. 4. The method of applying for the third paragraph of the patent scope includes: Establishing a general-purpose input into the virtual channel to facilitate the transmission of non-isochronous content. 5. The method of claim 3, wherein the isochronous virtual channel is not retrieved to begin a decisive service timing. 6. The method of claim 3, wherein the isochronous virtual channel is constructed with the expected quality of the service established between the information transmitter and a receiver. 7. If you apply for the method of the scope of the special benefit, the service is expected The quality of 1246651 is quantified by a period of information transmission. 8. If the method of claim 3 is applied, the medium-term content is time dependent. 9. The method of claim 1 of the patent scope further includes: establishing an additional virtual channel within the general general input/output bus width to initiate the communication of information. 10. The method of claim 1, wherein the virtual channel is one of a plurality of virtual channels established on a general output bus, wherein the state of each virtual channel is independently managed. 11. The method of claim 1, wherein the independent management of the virtual channel comprises: independently managing flow control for each of the one or more established virtual channels. 12- The method of claim 11, wherein the independent management of the virtual channel status comprises: The order rules for each of one or more established virtual channels are managed independently. 13. The method of claim 11, wherein the independent management for each of the one or more virtual channels is performed in a transaction layer connected to one of the devices of the general output bus. 14. The method of claim 1, wherein each of the one or more virtual channels share a source of physical communication that is generally output to the bus. 15. The method of claim 14 of the patent scope further includes: dynamically allocating the realities according to the requirements of the channel virtual channel to start communication 1246651 Body bandwidth is given to any of the virtual channels. 16. The method of claim 15, wherein the dynamic allocation of the physical bandwidth to each of the one or more virtual channels is performed by a physical layer connecting the devices generally connected to the bus. 17. A method of enhancing the output into the bus, including: Establishing a virtual channel dedicated to transferring information between two media via zero or more components, wherein the virtual channel is established and managed according to each link between individual components; and relative to the output Any additional virtual channel established within one of the total bandwidths of the incoming bus, independently managing a state of the virtual channel, wherein the general output inbound bus is coupled to the components. 18. The method of claim 17, wherein the method further comprises: identifying an appropriate type of virtual channel through which information is initially transmitted based at least in part on the content of the information. 19. For the method of claim 18, identifying one of the types of virtual channels includes: determining whether the received information includes isochronous content; and, if available, establishing an isochronous virtual channel to assist The transmission of time-sensitive content. 20. The method of claim 19, further comprising: establishing a general input virtual channel to facilitate the transmission of non-isochronous content. 21. The method of claim 19, wherein the isochronous virtual channel is not retrieved to begin a decisive service timing. 1246651 22. The method of claim 19, wherein the isochronous virtual channel is established with the expected quality of service established between the information transmitter and a receiver. 23. The method of claim 19, wherein the isochronous content is time dependent. 24. The method of applying for the patent scope, item 17, also includes: An additional virtual channel is established within all of the general input and output bus widths to begin communication of information. 25. The method of claim 18, wherein the virtual channel is one of up to a plurality of virtual channels established on the general output bus, wherein the state of each virtual channel is independently managed. 26. The method of claim 25, wherein the independent management of virtual channels includes: Process control for each of one or more established virtual channels is managed independently. 27. The method of claim 26, wherein the independent management of the virtual channel status comprises: independently managing order rules for each of the one or more established virtual channels. 28. As in the method of claim 27, wherein the other rules within the virtual channel, the order rules define whether the packets of the information can be processed in reverse order. 29. The method of claim 25, wherein the virtual channel status The independent management of 1246651 includes: Independently managing the order rules for each of one or more established virtual channels. 30. The method of claim 25, wherein the independent management for each of the one or more virtual channels is performed in a transaction layer connected to one of the devices generally connected to the bus. 31. The method of claim 17, wherein each of the one or more virtual channels shares a physical communication source of a general input bus. 32. The method of claim 17 of the patent scope further includes: dynamically allocating the physical bandwidth to any of the virtual channels as required to initiate communication through the virtual channel. 33. The method of claim 3, wherein the dynamic allocation of the physical bandwidth to each of the one or more virtual channels is performed by a physical layer connecting the devices generally connected to the bus. 34. A computer device for enhancing input and output into a busbar, comprising: - a general output busbar; and two or more components, each of which is in communication with the general output, wherein one or more of the components include An enhanced general output interface is used to create a virtual channel that dynamically shares the physical source of this general output into the bus to initiate the communication of information between two or more components. 35. If the computer device of the patent application No. 34 is applied, the enhanced general input and output interface includes: 1246651 A transaction layer for receiving information from one or more processing media within a component and establishing one or more virtual channels for communicating information from one or more processing media to one or more external media. 36. The computer device of claim 35, wherein the transaction layer independently manages a state in which each of the established virtual channels is related to each other. 37. The computer device of claim 35, wherein the transaction layer selects a type of virtual channel from the plurality of virtual channels based at least in part on the content of the information received from the medium. 38. The computer device of claim 37, wherein the virtual channel type comprises a general output virtual channel type and a first-time virtual channel type. 39. For a computer device as claimed in claim 3, wherein the general input to virtual channel type is a default virtual channel type. 40. The computer device of claim 3, wherein the isochronous virtual channel type is retained to facilitate isochronous communication between the media on the general output and the bus. 41. The computer device of claim 40, wherein the isochronous information includes time-dependent content. 42. For the computer device of patent application No. 41, the enhanced general output interface: a physical link layer that responds to the transaction layer to manage access to the entity's general output into the bus source to one or more Establishing a virtual channel that is received at least in part for receiving through the virtual channel 1246651 The time of transmission of information. 43. The computer device of claim 4, wherein the entity link layer prioritizes the distribution of the general output to the source of the information about the isochronous virtual channel over the information about the general output to the virtual channel. . 44. If the computer device of claim 35 is applied for, the enhanced general input and output interface includes: a physical link layer, which responds to the transaction layer for managing access to the entity's general output into the bus source to one or more established virtual channels, at least in part for receiving through the virtual channel for transmission The time of the information. 45. The computer device of claim 4, wherein the entity connection layer is at least partially based on the virtual channel type to dynamically allocate the entity to each of the established virtual channels. 46. The computer device of claim 45, wherein the entity link layer prioritizes the allocation of the source to the bus source that is generally passed to the isochronous virtual channel that is generally output to the virtual channel. 47. The computer device of claim 46, wherein the physical link layer utilizes information in a transaction layer packet on the virtual channel regarding the received information for transmission to identify the virtual channel type. 1246651 Patent application No. 091122495 Chinese pattern replacement page (August, 1994) 1000 10