Α7 Β7 1240372 i、發明説明（i) 本發明是有關於鑲嵌式内連線結構（damascene imerconnect structure)的製程技術，且特別是有關於一種 鑲嵌式内連線之自對準護層的製作方法。 隨著積體電路日趨精密與複雜化，為了能夠在有限 的晶片表面上製作足夠的金屬内連線，目前大多採用多 層内連線（multi-level interconnects)的立體架構方式，以 完成各個元件的連接，並以内金屬介電層（IMD ·· Imer_ Metal Dielectrics)來作為隔離各金屬内連線之介電材 料；而至於上下層内連線之間，則透過接觸 或介層窗（via)之金屬插塞來作電性連接。 在傳統内連線的製程中，由於接觸窗構造與導線圖 案係分別製作而成，因此需要個別的沈積與定義圖案程 序，使得整個製程步驟極其繁複，在當前電路設計日'益 複雜化的趨勢下，將增加製作都時間與成本，不利於生 產線上的應用。 士為克服上述困難，目前另發展出一種鑲嵌式内連線 、、口 構（damascene interconnect structure),係在基底的介電 經满部中央標準局員Η消費合作社印t 層上，先行製作出具有介層窗與内連線圖案之凹槽，然 後再以一導電層填滿介層窗和内連線圖案凹槽，同時製 作出接觸插塞與内連線結構，達到簡化製程步驟的效 ，。為二進一步說明，以下將配合第1今圖至第1G圖之 °’J面二思圖，說明習知鑲嵌式内連線結構的製作方法。 有丰2照第1A圖’首先提供一石夕基底100，其上形成 -疋件如電晶體或電容等（未顯示），接著再依習知 A7 B7 1240372 五、發明説明（2) 的半導體製程形成一肉八 , ’丨電層（ILD : Inter-LayerΑ7 Β7 1240372 i. Description of the invention (i) The present invention relates to a process technology of a damascene imerconnect structure, and in particular relates to a method for manufacturing a self-aligned protective layer of a damascene imerconnect structure. . With the increasing precision and complexity of integrated circuits, in order to be able to produce sufficient metal interconnects on a limited surface of a chip, a multi-level interconnects three-dimensional architecture is currently used to complete the components. Connection, and the inner metal dielectric layer (IMD ·· Imer_ Metal Dielectrics) as the dielectric material to isolate the metal interconnects; as for the upper and lower interconnects, through the contact or the dielectric window (via) Metal plug for electrical connection. In the traditional interconnection process, because the contact window structure and the wire pattern are made separately, individual deposition and definition pattern procedures are required, making the entire process step extremely complicated, and it is becoming more and more complicated in the current circuit design day. Next, it will increase the production time and cost, which is not conducive to the application on the production line. In order to overcome the above-mentioned difficulties, another type of mosaic interconnect structure (damascene interconnect structure) has been developed. It is firstly produced on the printed layer of the Consumer Cooperatives Co. The recesses of the interlayer window and the interconnect pattern are then filled with a conductive layer to fill the interlayer window and the interconnect pattern groove. At the same time, the contact plug and the interconnect structure are fabricated to achieve the effect of simplifying the process steps. . For further explanation, the following will describe the manufacturing method of the conventional mosaic interconnect structure with the ° 'J plane second thoughts of Figures 1 to 1G. Youfeng 2 according to FIG. 1A. 'A stone evening substrate 100 is first provided on which-a piece such as a transistor or a capacitor (not shown) is formed, and then according to the conventional A7 B7 1240372 5. Semiconductor process of the invention description (2) Forming a flesh, '丨 Electrical layer (ILD: Inter-Layer
Dielect⑽）11G，心_半導 層金屬㈣線120，例如一I呂金屬層。 下 接著，在内介電居11π & 層110與下層金屬内連線120的表 面上’依序覆蓋絕緣層130、氣化石夕層14〇、及絕緣層 、中，鼠化石夕層140是作為钮刻終止層，其與絕緣 層30 150 σ為層間介電層，如多重内連線之内金屬 介電層（IMD)135，-般層間介電層係採用低介電係數之 氧化物質。 接下來參照第1B圖，以微影成像與蚀刻程序，在絕 緣層150上定義出内連線凹槽16〇，以露出欲形成内連 線構造的區域。之後，施行另一次微影成像與钱刻程序， 逐-蝕刻氮化矽層140與絕緣層13〇至露出下層金屬内 連線120為止，以便在内連線凹槽16〇的下方形成介層 窗170，如第1C圖所示。 之後，請參照第1D圖，先在基底上沈積一擴散阻障 層（bamerlayer)i75，例如Ti/TiN阻障層。然後再以電鍍 或沈積的程序，形成一導電金屬層18〇，填滿介層窗17〇 和内連線凹槽160，並且延伸覆蓋在絕緣層15〇的表面 上’其中導電金屬層180的材質，可以是銅、金、銘、 銀等金屬材料。之後，再以回蝕刻或化學、機械研磨（CMp) 將絕緣層150上方的阻障層175和導電金屬層18〇去除， 即可得到一鑲嵌式内連線結構。 在上述鑲嵌式内連線結構的製程中，由於已先在介 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、11 經滴部中央標準局員工消費合作社印顰 1240372 A7 "~~ ---~___________ B7 五、發明説明（3 ) - 電層中形成内連線凹槽與介層洞，因此後續的金屬内連 線與接觸插塞便可以同時形成其中，不僅具有簡化製程 V驟的效果，也可改善傳統中因金屬導線與接觸插塞材 質不同所導致黏著性不佳的問題；尤其是使用銅金屬的 鑲嵌式内連線，不僅可達到内連線的縮小化並且可減少 RC時間延遲，因此已成為現今多重内連線主要的發展趨 勢。 為了使導電金屬能完全填入僅有次微米大小的溝槽 及介層窗，目前所發展出的有機金屬化學氣相沈積法 (M〇_CVD)及電鍍沈積法（electroplating depositon)，已可 達到極佳的階梯覆蓋效果。然而，欲將此一製程作廣泛 的應用之前，仍有部份問題亟待謀求改善之策。以下請 繼續參照第1E圖至第1G圖之說明。 經漓部中央標準局員工消費合作社印裝 第1E圖所示，為第id圖之導電金屬180進行化學 機械研磨時的剖面圖。在研磨進行時，由於晶圓上圖案 的密度不同，因此每個區域的研磨速率也不盡相同，例 如在空曠區（open area)上的金屬層180a，由於研磨速度 較慢’經常在其他區域以研磨完畢之後仍有金屬殘留， 因此需要以過度研磨（over polishing)將之去除，但如此一 來又會使圖案區域的内連線180b因過度研磨而造成如第 1F圖所示的碟狀凹陷（dishing)，甚至造#絕緣層175的 磨損。 請繼續參照第1G圖’在完成内連線的製作後，接下 尚須沈積一材質為氮化矽的護層190，以及另一層内金 5 本紙張尺度適用中國國家標準（CNS )八4規格（210X 297公釐） 1240372 Μ ~_ __ Β7 五、發明説明（4) ~ ' - 屬’I包層（IMD)195，以繼續後序的多重内連線製程。其 中氮化石夕層190通常是利用電漿CVD法（PE-Cvd)，以Dielect⑽) 11G, a core-semiconductor layer metal wire 120, for example, a metal layer. Next, the surfaces of the inner dielectric layer 11π & layer 110 and the lower metal interconnect 120 are sequentially covered with the insulating layer 130, the gasification layer 140, and the insulation layer 140. As the button stop layer, it and the insulating layer 30 150 σ are interlayer dielectric layers, such as the inner metal dielectric layer (IMD) 135 of the multiple interconnects, the general interlayer dielectric layer is an oxidizing material with a low dielectric constant. . Next, referring to FIG. 1B, the lithography imaging and etching procedures are used to define interconnecting grooves 160 on the insulating layer 150 to expose the area where the interconnect structure is to be formed. After that, another lithography imaging and money engraving procedure is performed, and the silicon nitride layer 140 and the insulating layer 13 are etched one by one until the lower metal interconnect 120 is exposed, so as to form a dielectric layer under the interconnect wiring groove 160. The window 170 is shown in FIG. 1C. After that, please refer to FIG. 1D, first deposit a diffusion barrier layer (bamerlayer) i75, such as a Ti / TiN barrier layer, on the substrate. Then a plating or deposition process is performed to form a conductive metal layer 18o, which fills the vias 17o and interconnecting grooves 160, and extends to cover the surface of the insulating layer 15 ′, where the conductive metal layer 180 The material can be metal materials such as copper, gold, inscription, and silver. After that, the barrier layer 175 and the conductive metal layer 180 above the insulating layer 150 are removed by etch-back or chemical and mechanical polishing (CMp) to obtain a mosaic interconnect structure. In the manufacturing process of the above-mentioned inlaid interconnect structure, the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) has been applied to the paper size (please read the precautions on the back before filling this page), 11 By the Ministry of Standards Bureau Consumer Standards Cooperative Seal 1240372 A7 " ~~ --- ~ ___________ B7 V. Description of the Invention (3)-Interconnection grooves and interlayer holes are formed in the electrical layer, so subsequent metal The connection and contact plug can be formed at the same time, which not only has the effect of simplifying the process V step, but also can improve the problem of poor adhesion caused by the different materials of the metal wire and the contact plug in the traditional; especially the copper metal Mosaic interconnects can not only reduce the interconnect size but also reduce the RC time delay, so it has become the main development trend of multiple interconnects today. In order to allow conductive metals to completely fill trenches and interlayer windows with sub-micron dimensions, the organic metal chemical vapor deposition method (Mo_CVD) and electroplating depositon have been developed. Achieve excellent step coverage. However, before this process can be widely used, there are still some problems that need to be improved. Please continue to refer to the description of Figures 1E to 1G below. It is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Lithology. Figure 1E is a cross-sectional view of the conductive metal 180 in Figure id when it is subjected to chemical mechanical polishing. During the polishing process, the polishing rate of each area is different due to the different density of the patterns on the wafer. For example, the metal layer 180a on the open area has a slower polishing speed because it is often in other areas. After the polishing is completed, there is still metal remaining, so it needs to be removed by over polishing, but this will cause the interconnection 180b in the pattern area to cause a dish-like shape as shown in Figure 1F due to excessive polishing. Dishing or even abrasion of the # insulating layer 175. Please continue to refer to Figure 1G. After the production of the interconnects is completed, a protective layer 190 made of silicon nitride and another layer of internal gold must be deposited. 5 This paper is applicable to the Chinese National Standard (CNS) 8-4. Specifications (210X 297 mm) 1240372 Μ ~ _ __ Β7 V. Description of the invention (4) ~ '-belongs to' I cladding (IMD) 195 to continue the subsequent multiple interconnection process. Among them, the nitrided layer 190 is usually made by plasma CVD (PE-Cvd) to
SiIVNH3為反應氣體進行沈積，然而在進行此步驟時， 金屬銅會反應成氧化鋼造成阻值上昇，再加上所形成的 氧化銅是料關时式成長，不僅形成在銅線的上表 面，也會形成在冑電層的内部，更嚴重影響到内連線金 屬的品質。 胃有鑑於此，本發明的主要目的就是為了解決上述問 題，而提供一種鑲嵌式内連線之自對準護層㈣卜响⑽ passivation)的製作方法，以取代傳統的氮化矽護層。 為達上述目的，本發明提供一種鑲嵌式内連線之自 對準護層的製作方法，係在完成金屬層的研磨後（參照第 1F圖），另外再沈積一層銅合金（c〇pperai1〇y)，此合金層 經過研磨後，便會自動殘留在導線上方的凹陷區域。在 後序沈積内金屬介電層（IMD)時，這些殘留的銅合金便會 在原處（in-S1tu)自行氧化成一具有阻絕效果的金屬氧化 層，而保護其下之金屬導線。 經¾•部中*標準局員工消費合作社印製 詳而言之，本發明之方法包括下列步驟··（a)提供一 覆蓋有介電層之半導體基底，此介電層經過定義後具有 一鑲嵌式内連線溝槽；（b)形成一導電層於此介電層上， 並填入上述鑲嵌式内連線溝槽；（c)以令學機械研磨法 (CMP)去除該介電層上之導電層，並使内連線溝槽中之導 電層因過度研磨而產生凹陷（dishing) ; (d)沈積一銅合金 層於介電層上與導電層上；其中上述含銅合金可為銅_鉻 6 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 1240372 A7 B7 經滴部中央標準局員Jr消費合作社印f. 五、發明説明（5 ) 合金、銅-錳合金、或銅-鈦合金；（e)以化學機械研磨法 去除介電層上之銅合金層，而使銅合金自行殘留在該導 電層上之凹陷區域；以及（f)氧化上述銅合金，以在導電 層上形成具有阻絕效果之金屬氧化物。 上述中，鑲嵌式内連線溝槽通常包括一内連線凹槽 以及位於該凹槽下方之介層窗，用以露出下層内連線； 上述之介電層，通常包括堆疊的氧化矽層/氮化矽層/氧化 矽層；而在步驟（b)沈積導電層之前，通常會先沈積一阻 障層於基底既有之輪廓上。此外，步驟（f)通常可藉由内 金屬介電層（IMD)的沈積過程順便將銅合金氧化，但也可 利用熱爐管進行額外的回火程序（annealing)而將之氧 化° 為讓本發明之上述和其他目的、特徵、和優點能更 月”、、員易樓下文特舉一較佳實施例，並配合所附圖式， 作詳細說明如下： 圖式之簡 第1A〜1G圖為一系列剖面圖，用以說明習知製作鑲 嵌式内連線的流程。 第2A〜2H圖為一系列剖面圖，用以說明本發明一較 佳實施例製作鑲嵌式内連線的流程。 符號說明 100〜基底；110〜内介電層；12〇〜下層金屬内連 線’ 130〜絕緣層；140〜氮化矽層；150〜絕緣層；135〜 内金屬；丨電層；160〜内連線凹槽；170〜介層窗；175〜 (請先閱讀背面之注意事項再填寫本頁} -裝 、11 k 、紙張尺 關 1240372 經滴部中央標準局工消費合作社印梦 Α7 Β7SiIVNH3 is deposited as a reactive gas. However, during this step, copper metal will react to oxidized steel and increase the resistance value. In addition, the formed copper oxide is grown in a time-dependent manner, and is not only formed on the upper surface of the copper wire. It will also form inside the galvanic layer, which will seriously affect the quality of the interconnect metal. In view of this, the main purpose of the present invention is to solve the above-mentioned problems, and to provide a method for manufacturing a self-aligned protective layer passivation of a mosaic interconnect to replace the traditional silicon nitride protective layer. In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a self-aligned protective layer of a mosaic type interconnect, which is after depositing a metal layer (refer to FIG. 1F) and depositing another layer of copper alloy (copperai1). y) After the alloy layer is ground, it will automatically remain in the recessed area above the wire. In the subsequent deposition of the internal metal dielectric layer (IMD), these remaining copper alloys will oxidize in-situ to a metal oxide layer with a barrier effect, protecting the underlying metal wires. Printed by the Ministry of Standards and Consumers Cooperative of the Bureau of Standards. In detail, the method of the present invention includes the following steps: (a) providing a semiconductor substrate covered with a dielectric layer, which is defined to have a Mosaic interconnecting trenches; (b) forming a conductive layer on this dielectric layer and filling the aforementioned mosaic interconnecting trenches; (c) removing the dielectric by CMP A conductive layer on the layer and causing the conductive layer in the interconnect trenches to be dulled due to excessive grinding; (d) depositing a copper alloy layer on the dielectric layer and the conductive layer; wherein the above-mentioned copper-containing alloy May be copper_chrome 6 This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) 1240372 A7 B7 Printed by Jr Consumer Cooperative of Central Standards Bureau of the Ministry of Distillation f. V. Description of invention (5) Alloy, copper- Manganese alloy or copper-titanium alloy; (e) removing the copper alloy layer on the dielectric layer by chemical mechanical polishing, so that the copper alloy remains on the recessed area of the conductive layer by itself; and (f) oxidizing the copper alloy To form a metal oxide with a barrier effect on the conductive layerIn the above, the inlaid interconnect wiring trench usually includes an interconnect wiring groove and a dielectric window below the groove to expose the underlying interconnect; the above-mentioned dielectric layer usually includes a stacked silicon oxide layer / Silicon nitride layer / silicon oxide layer; before the conductive layer is deposited in step (b), a barrier layer is usually deposited on the existing contour of the substrate. In addition, step (f) can usually oxidize the copper alloy by the deposition process of the inner metal dielectric layer (IMD), but it can also be oxidized by using an additional annealing process using the furnace tube. The above and other objects, features, and advantages of the present invention can be further improved. ", Yuan Yi Building exemplifies a preferred embodiment, and in conjunction with the accompanying drawings, the detailed description is as follows: The figure is a series of cross-sectional views, which are used to explain the process of making inlay interconnects. Figures 2A to 2H are a series of cross-sectional views, which are used to illustrate the process of making inlay interconnects in a preferred embodiment of the present invention. Symbol description 100 ~ substrate; 110 ~ inner dielectric layer; 12 ~ lower metal interconnects 130 ~ insulating layer; 140 ~ silicon nitride layer; 150 ~ insulating layer; 135 ~ inner metal; 丨 electric layer; 160 ~ Inner wiring groove; 170 ~ Interlayer window; 175 ~ (Please read the precautions on the back before filling out this page} -Installation, 11k, paper rule off 1240372 Jing Dian Central Standard Bureau Industrial Consumer Cooperative Co., Ltd. Yinmeng Α7 Β7
五、發明説明（I 擴散阻障層；180〜導電金屬層；190〜氮化矽護層； 195〜内金屬介電層；200〜基底；21〇〜内介電層；220〜 下層金屬内連線；230〜絕緣層；240〜氮化矽層；25〇〜 、、、邑緣層，23 5〜内金屬介電層，260〜内連線凹槽；270〜 介層窗；275〜擴散阻障層；280〜導電金屬層；29〇〜銅 5金層，300〜内金屬介電層。 首先請參照第2Α圖，首先提供一半導體基底， 例如一矽基底，在基底上可以形成任何所需的半導體元 件’但為了方便起見，此處僅顯示一平整的基底。 其次在該基底200上形成一覆蓋半導體元件之介電 層 210,以作為内介電層（ILD : Inter_LayerDielectHcs” 其材質例如是硼磷矽玻璃（BPSG)。接著，在内介電層21〇 表面形成一下層内連線，例如形成一具有輪廓深度之金 屬層，用為金屬内連線220，此金屬層可為鎢、鋁、鋁 石夕銅合金、或|g銅合金。 接著，在内介電層210與下層金屬内連線12〇的表 面上，依序覆蓋絕緣層230、氮化矽層240、及絕緣層 250。其中，氮化矽層240是作為蝕刻終止層，其與絕緣 層230、250合為層間介電層，如多重内連線之内金屬 介電層（IMD)235，一般層間介電層係採、用低介電係數之 氧化物質，以避免層間介電層因RC延遲時間而減緩積體 電路裝置之操作速度，例如以矽甲烷為主反應物，並藉 高密度電漿化學氣相沈積法（HDP-CVD)所形成之氧化 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、1Τ 1/ 1240372 A7 ----一__________ B7 五、發明説明（7 ) —' ~~~ ^ —- ^或是以四乙氧基料/臭氧（TE㈣〇3)為主反應物，並 藉化學氣相沈積法所形成之氧化層。 接下來參照f 2B圖所示，以微影成像與钮刻程序， 在絕緣層250上定義出内連線凹槽26()，以露出欲形成 内連線構造的區域。之後，施行另—次微影成像與姓刻 程序’逐-姑刻氮化石夕層240與絕緣層23〇至露出下層 金屬内連線220為止，以便在内連線凹槽26〇的下方形 成介層窗270,如第2C圖所示。至此，已完成鎮嵌式内/ 連線的圖案定義。 之後，請參照第2D圖，先在基底上沈積一擴散阻障 層（barrier layer)275，例如Ti/TiN阻障層。然後再以電鍍 或沈積的程序，形成一導電金屬層28〇，填滿介層窗27〇 和内連線凹槽260，並且延伸覆蓋在絕緣層25〇的表面 上。在本實施例中導電金屬層280所用的材質為金屬銅， 可利用PVD或CVD法先在基底既有之輪廊上沈積一晶 種層（seed layer)後，再利用電鍍的方式於晶種層上沈積 一銅導電層。 經满部中次標準局員工消費合作社印f 請參照第2E圖，按習知方式以化學機械研磨將絕緣 層250上方的阻障層275和導電金屬層28〇去除，以形成 一鑲嵌式内連線結構，並使該内連線溝槽中之導電層因 過度研磨而產生凹陷（dishing)，如圖中y〇a所示。 接著參照第2F圖，進行本發明之關鍵步驟；沈積一 銅合金層290於絕緣層250上與導電層28如上，然後再 利用一次化學機械研磨進行平坦化，將絕緣層25〇以上 9 本紙張尺度適用中國國家標準（CNS ) A4規格（2】0x 297公楚） 1240372 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（8 ) 之銅合金層290去除’藉此使銅合金自動殘留於導電層 280a上之凹陷區域，如第2g圖之290a所示。應注意的 是，由於所沈積之銅合金層290的輪廓深度（t〇p〇graphy) 較為平坦，再加上銅合金層290的材質又較導電層280 (通常為銅線）堅硬，因此經過化學機械研磨後可得到一平 坦的表面，不至於有凹陷（dishing)的情形產生。 在上述中所沈積之銅合金290，例如可以是銅·鉻合 金、銅-錳合金、銅-鈦合金、或是包含有上述合金之金屬 材貝。由於這些合金可形成自由能（free energy : △ G)比 氧化銅（CuO)低的金屬氧化物如氧化鉻（Cr2〇3)、氧化鈦 (Τι〇2)、氧化錳（Mn〇)等，因此在進行熱處理時，會先形 成上述氧化物而非形成氧化銅；此外，相較於氧化銅不 規則的生長方式，這些金屬氧化物（氧化鉻、氧化鈦、氧 化錳）會均勻的長在合金層的上表面，而成為一自我保護 層（self-passivati〇n)以防止底下的金屬繼續氧化，因此達 到保護金屬内連線的阻絕效果。 請參照第2H圖，根據本發明之較佳實施例，上述銅 合金290a可藉由後序介電層的沈積過程順便將之氧化， 因此在生成内金屬介電層（IMD)300的同時，亦形成了自 對準護層，而防止底下的金屬内連線遭到破壞。此外， 熟習此技藝者亦可利用額外的一次熱處繆來進行氧化， 例如可利用熱爐管施行回火製程（annealing)來生成具有 阻絕作用的自對準護層。 由以上說明可知，本發明之方法係利用一層銅合 本紙張尺度適用巾gjg[家標率（CNS ) M規格（2IGX 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、11 1240372 A7 __________ B7 五、發明説明（9) 配合化學機械研磨的平坦化製程，以將此銅合金填入導 線上的凹陷（dishing)區域，而這些銅合金在後序沈積内金 屬介電層（IMD)時，便可在原處（in_situ)自行氧化成一自 對準護層。根據上述，該方法具有下列優點： 1·可減少内連線金屬因為化學機械研磨所造成之不 良影響。 2·不需製作額外的護層（如習知的氮化矽護層），直接 沈積内金屬介電層（IMD)即可在内連導線上方自動形成 自對準護層。 3·不需沈積氮化矽，可避免金屬銅線與NHySiH4反 應成氧化銅。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明 之精神和範圍内，當可作各種之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為 (請先閱讀背面之注意事項再填寫本頁) ,裝- 經满部中夾標準局負工消費合作社印f- 適 尺 張 紙 i本 準 標 家V. Description of the Invention (I Diffusion barrier layer; 180 ~ conductive metal layer; 190 ~ silicon nitride protective layer; 195 ~ inner metal dielectric layer; 200 ~ substrate; 21〇 ~ inner dielectric layer; 220 ~ lower metal Wiring; 230 ~ Insulation layer; 240 ~ Silicon nitride layer; 25 ~~, ~, rim margin layer, 23 ~ 5 inner metal dielectric layer, 260 ~ interconnect wire groove; 270 ~ interlayer window; 275 ~ Diffusion barrier layer; 280 to conductive metal layer; 29 to copper 5 gold layer, 300 to inner metal dielectric layer. Please first refer to FIG. 2A, first provide a semiconductor substrate, such as a silicon substrate, which can be formed on the substrate Any desired semiconductor element ', but for convenience, only a flat substrate is shown here. Next, a dielectric layer 210 covering the semiconductor element is formed on the substrate 200 as an internal dielectric layer (ILD: Inter_LayerDielectHcs " Its material is, for example, borophosphosilicate glass (BPSG). Next, a lower layer interconnect is formed on the surface of the inner dielectric layer 21, for example, a metal layer having a contour depth is used as the metal interconnect 220. This metal layer Can be tungsten, aluminum, bauxite copper alloy, or Next, on the surface of the inner dielectric layer 210 and the underlying metal interconnect 120, the insulating layer 230, the silicon nitride layer 240, and the insulating layer 250 are sequentially covered. The silicon nitride layer 240 is used as an etching stopper. Layer, which is an interlayer dielectric layer with the insulating layers 230 and 250, such as the inner metal dielectric layer (IMD) 235 with multiple interconnects. Generally, the interlayer dielectric layer is made of an oxidizing substance with a low dielectric constant. Prevent the interlayer dielectric layer from slowing down the operation speed of integrated circuit devices due to RC delay time, such as silicon dioxide as the main reactant, and oxidized paper formed by high-density plasma chemical vapor deposition (HDP-CVD) Standards are applicable to Chinese National Standards (CNS) Λ4 specifications (210X 297 mm) (Please read the precautions on the back before filling this page), 1T 1/1240372 A7 ---- 一 __________ B7 V. Description of the invention (7) — '~~~ ^ —- ^ Or an oxide layer formed by using tetraethoxy material / ozone (TE㈣03) as the main reactant and formed by chemical vapor deposition. Next, refer to f 2B. Using the lithography imaging and button-engraving procedures to define the interconnecting grooves 26 () on the insulating layer 250, The area where the interconnection structure is to be formed is exposed. After that, another lithography imaging and engraving procedure is performed, one by one, the nitride layer 240 and the insulating layer 23 are etched until the lower metal interconnection 220 is exposed, so that An interlayer window 270 is formed below the interconnecting groove 260, as shown in FIG. 2C. At this point, the pattern definition of the embedded interconnect / connecting line has been completed. After that, please refer to FIG. 2D to deposit on the substrate first. A diffusion barrier layer 275, such as a Ti / TiN barrier layer. Then, a conductive metal layer 28 is formed by a process of electroplating or deposition, which fills the via window 27o and the interconnect groove 260, and extends to cover the surface of the insulating layer 25o. In this embodiment, the conductive metal layer 280 is made of copper metal. PVD or CVD can be used to deposit a seed layer on the existing perimeter of the substrate, and then use electroplating to seed the seed layer. A copper conductive layer is deposited on the layer. Please refer to Figure 2E, and remove the barrier layer 275 and conductive metal layer 28 above the insulating layer 250 by chemical mechanical polishing according to the conventional method. The wiring structure causes the conductive layer in the interconnect wiring trenches to ditch due to excessive grinding, as shown in FIG. Next, referring to FIG. 2F, the key steps of the present invention are performed; a copper alloy layer 290 is deposited on the insulating layer 250 and the conductive layer 28 as above, and then chemical mechanical polishing is used for planarization, and the insulating layer is more than 25 and 9 papers Standards are applicable to Chinese National Standard (CNS) A4 specifications (2) 0x 297 Gongchu. 1240372 Printed by A7 B7, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (8) The copper alloy layer 290 is removed. The recessed area automatically left on the conductive layer 280a is shown in Figure 290a of Figure 2g. It should be noted that, because the depth of outline (topography) of the deposited copper alloy layer 290 is relatively flat, and the material of the copper alloy layer 290 is harder than the conductive layer 280 (usually a copper wire), After the chemical mechanical polishing, a flat surface can be obtained, so that there is no dishing. The copper alloy 290 deposited in the above may be, for example, a copper-chromium alloy, a copper-manganese alloy, a copper-titanium alloy, or a metal material containing the above alloy. Because these alloys can form metal oxides with lower free energy (ΔG) than copper oxide (CuO), such as chromium oxide (Cr203), titanium oxide (Ti2), manganese oxide (Mn0), etc., Therefore, during the heat treatment, the above oxides will be formed instead of copper oxides. In addition, compared to the irregular growth method of copper oxides, these metal oxides (chromium oxide, titanium oxide, manganese oxide) will grow uniformly. The upper surface of the alloy layer becomes a self-passivating layer to prevent the underlying metal from continuing to oxidize, thereby achieving the barrier effect of protecting the metal interconnects. Please refer to FIG. 2H. According to a preferred embodiment of the present invention, the above-mentioned copper alloy 290a can be oxidized by the subsequent deposition process of the dielectric layer. Therefore, while generating the internal metal dielectric layer (IMD) 300, A self-aligned protective layer is also formed to prevent damage to the underlying metal interconnects. In addition, those skilled in the art can also use an additional heat treatment to perform oxidation. For example, an annealing process can be performed using a hot furnace tube to generate a self-aligned protective layer with a barrier effect. As can be seen from the above description, the method of the present invention uses a layer of copper-coated paper for gjg [house standard rate (CNS) M specification (2IGX 297 mm) (please read the precautions on the back before filling out this page), 11 1240372 A7 __________ B7 V. Description of the invention (9) Cooperating with the chemical mechanical polishing planarization process to fill this copper alloy into the recessed area on the wire, and these copper alloys subsequently deposit an internal metal dielectric layer ( IMD), it can be self-oxidized into a self-aligned protective layer in situ. According to the above, this method has the following advantages: 1. It can reduce the adverse effects caused by the chemical mechanical polishing of the interconnect metal. 2. No additional protective layer is needed (such as the conventional silicon nitride protective layer), and the inner metal dielectric layer (IMD) can be directly deposited to automatically form a self-aligned protective layer over the interconnect wires. 3. There is no need to deposit silicon nitride, which can avoid the reaction of metal copper wire and NHySiH4 to copper oxide. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention should be defined as the scope of the attached patent application (please read the precautions on the back before filling this page). i standard bidder
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