TWI220944B - Cache controller unit architecture and applied method - Google Patents

Abstract

A cache controller unit (CCU) architecture with dirty line write-back auto-adjustment, suitable for high performance microprocessor systems with write-back cache memory. The CCU architecture includes a cache data control unit to access data between a cache memory and a CPU, a tag compare unit to compare an address sent by the CPU and a tag address sent by a tag memory and thus produce a cache hit signal, and a CCU state machine to control the data access direction of the cache data control and produce corresponding operations according to the tag compare result.

Description

1220944 V. Description of the invention (1) -------- The technical field to which the invention belongs ... The present invention relates to a cache memory control for a high-efficiency microprocessor system having a write-back cache memory Unit architecture. More particularly, the present invention is directed to providing an operating method for a cache memory controller unit (ccu) to improve cache memory execution efficiency when writing back to a dirty cache line. ~ Prior technology Most efficient microprocessor systems today use different memory levels. A cache memory is arranged at a level closest to the core of the central processing unit (cpu), and most of them are high-speed static random access memory 9 (sram). The cache memory is usually on the same chip as the CPU core, so it can operate synchronously with the CPU at the same clock rate. At the lower level, there is a main memory two, which is composed of the entire physical memory space that the CPU can use. Main memory, e.g., dynamic random access memory (CD ^ "), is usually not in the chip, and it is slower and cheaper. Also, in the main memory, there will be ... a small part of the memory position i. When CPUY stores the data address in cache memory (this is called the hit state)? ί ί access 1 cache memory for access, therefore, the CPU will not delay the schedule. However, when the address of the data accessed by the CPU is not fast, it must go to the main memory: it will take a long time. That is, in this example, the CPU must be paused to wait for data from the main memory 1-ί:: ΐ: In the beneficial system, the main memory can also be accessed by /. For example, various input / output (10) devices or direct memory

1220944 V. Description of the invention (2) The above WT cache memory However, because it always affects the CPU, this method is only the main memory (DMA) master device. The cache memory must maintain the consistency of the cache data gate, and the main memory should contain the same backup as the data in the cache memory. There are two ways to make the data in the main memory the same as the data in the cache memory. One is the direct write (WT) cache memory method. That is, when the data to be written is in the cache memory, the CPU writes the f data into the cache memory and the main memory at the same time. In this way, the main memory always contains the same data as the data in the cache memory. The physical structure is easier to design and easier to maintain consistency. It needs to be written to the main memory with slower execution speed. Another method is to write back (WB) data to the cache memory when it is in the cache memory, and the changed data will not be written into the main memory first. Write > data to main memory to maintain data consistency. Changed or pi-dirty "cache columns" (that is, dirty columns) must be updated when the loss caused by reading causes the dirty columns to be replaced. In the above situation, the original data must be re-cached Before the row data is replaced, the original dirty row data is read from the cache memory and placed in the main memory. This will cause two consecutive operations: write the dirty row data from the cache memory 'Into main memory' and read new cache rows and data from main memory and write to cache memory. To this end, the CPU must be suspended during the above operations, resulting in a reduction in execution efficiency. For A common solution to the above problem is to use a write buffer or register between the cache memory and the main memory to temporarily store the dirty column data and the address (hereinafter referred to as Replaced columns). Figure 1

0697-9048TW (N1); P2〇02.〇54; SUe ptd Page 6 1220944 V. Description of the Invention (3) is a block diagram of a typical microprocessor system with cache memory. Fig. 2 is an operation flowchart of Fig. 1. In Figure 1, this system includes a CPU 11, a tag memory 1, 2, a cache memory 1, 3, a cache memory control unit (CCU) 14, a main memory 15, and a memory control. Controller (MEMC) 16, a bus interface unit (BI U) 17 with a write buffer 17 1, and a system bus 18. As shown in Figures 1 and 2, when the CPU 11 wants to access the data in the memory, it will issue a read / write command and the address to be stored to the CCU 14 (S1). At this time, ecu 14 compares this address with the contents of tag memory 12 to check whether this address exists in the cache memory (S2). The above memory 12 includes the high address bits of each cache row in the cache memory, and some control bits that may include each cache row. For example, it indicates that Data are valid valid bits' and dirty bits indicating that the data on the cache line has been changed. If the above-mentioned check finds the required address, the data will be read from the cache memory 13 to the CPU 11 (read operation) or written from the CPU to the cache memory lj (write operation) (S3). If the address is not in the cache memory, it means that the required data is in the main memory 丨 5. At this time, ccu 丨 4 must redirect the access work to BIU 17 to access and connect to the system bus 18 Those devices: especially the memory controller i 6 which is responsible for accessing the main memory. BIU 17 usually contains a house of lambda bees: ^ 口 口 1R λα ^ 缓冲 入 Buffering benefit 171 to save the data and address written to the main memory, so as to maintain and cache one or two hours of memory information, ccu 14 pairs βΐυ π issues a -fill request, and the W- $ substitution column is dirty or clean (S5). If the above replaced column is dirty, it means that ecu 1 4 has to be $ 丨 phen 1 4 and 4 to the write buffer.

1220944 V. Description of the invention (4)-Until the current dirty column information can be filled (S6). Then, ccu H puts the dirty column information into the write buffer UKS7) and waits for the first request of BIU 17 ', so as to continue the operation of the CPU 11 (S9). ^ The above operation may produce a worst case scenario as shown in Figure 3. That is, when a lost state occurs, within the write buffer and buffer]

17 When the data written in the buffer 171 has not yet been transferred to the main memory, it is shown as a solid line A in FIG. 3. Because, before the BIU will serve is :: falling;,-, / backup Lexun is filled and written to the buffer 1 7 1 headroom (such as Chu 3 drawing line C), so this will also affect c ς Invention Content] Enforcement Efficiency. Therefore, one object of the present invention is to provide a cache memory for a high-efficiency microprocessor system for a right-storage memory. ^ Cache structure, which can reduce the time required for the early memory of the cache memory controller and the like. . The need for a write buffer for disaster relief Another object of the present invention is to provide an operation method for a specific high-efficiency microprocessor system. Write = The buffer improves the efficiency of cache memory when writing back. Imagination 'whereby the present invention provides a cache memory controller unit Galluri / 22, material control early 70, in order to access a cache memory and-φ blood processing early to (CPU) data; a Center comparison, M comparison, above

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1220944 V. Description of the invention (6) The filled address is set to the current lost column address; check whether the replaced column is a distinguished column; when the replaced column is not a dirty column, set the dirty flag as inactive; when When the replaced column is dirty, check whether the write buffer is clear; when the write buffer is not clear, set the dirty flag to the action state to place the replaced column later Into the write buffer, and release the cache memory controller unit (CCU) and central processing unit (CPU) without waiting for the write buffer headroom; when the write buffer headroom, After the replacement column is placed in the write buffer, the dirty flag is set to an inactive state; and the first in a new cache column transmitted by the cache memory controller unit according to the full buffer capture A data block that continues the operation of the central processing unit. Embodiments Throughout the text, similar functional elements are represented by the same symbols. A cache can be subdivided into several levels. For example, the L1 (level 1) cache is the closest to C P U and the fastest. l 2 (Layer 2) Cache Memory is the next level, which is slower than L1 but larger in capacity. The invention is a general principle and can be applied to any cache level memory. However, for ease of explanation ', the following description assumes that the cache memory consists of only one hierarchy. _ δ — When the cached state of body loss occurs, a column of data must be read from the main memory and placed in the cache memory. When a loss occurs, a basic unit of data, usually composed of multiple CPU blocks, is read from the main memory.

0697-9048TWF (N1); P2002-054; SUE.p t d ^ 20944

For example, if one of the following is used: directly corresponds to the address type cache memory structure, a row of data therein is only allocated at a specific position in the cache memory; the η-way cache type cache memory structure, a row in it The data can be arranged in one of the n positions of the cache memory; or a row of data in the fully-combined cache memory structure can be arranged at any position in the cache memory. Figure 4 shows a block diagram of a cache memory controller unit (ecu) according to the present invention. In FIG. 4, the CCU unit 41 includes a cache data control unit 411, a tag comparison unit 412, a filling buffer 413, and a CCU state machine 414. In addition to the CCU unit 41, the microprocessor system also includes a CPU 11, a cache memory 3, a tag memory 1 2 and a write buffer 1 7 1 as shown in FIG. 1. Bus Interface Unit (BIU) 17. As shown in FIG. 4, the unit 412 is a combined logic for comparing the address output (CPU_addr) of the CPU 11 and the tag address of the tag memory 12 (Tag-addr). Tag address rotation (Tag — addr) also contains a valid bit to indicate that the corresponding cache row contains valid data, and a habit bit to indicate that the corresponding cache row has been modified. If CPU —addr = Tag_addr and the logic value of the valid bit is true ’, a Η I τ signal is sent to the state machine 414. The state machine 414 as the control core of the CCU 41 instructs the element 411 to read data from the cache A memory 1 3 to the CPU 1 1 (read operation) or write lean data from the CPU 1 1 to the cache memory 1 3 (write operation). If the H 丨 τ signal is not active, that is, on the contrary, for example, a read loss signal is actuated, the state machine 414 issues a Fill_req signal to request the BIU 17 to grab a new

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The office bit is " 1 "), then these five, invention description (8) cache column. If it is replaced as a dirty column (at this time, the dirty columns must be updated into the main memory (Figure 1) to maintain the consistency of the cache memory. In this situation, the state machine 4144 issues a Wri at the same time. te a req signal to BIU 1 7 to write the data WB-data on the dirty column from the cache memory 1 3 into the write buffer when writing the buffer 1 71 headroom (WB_empty = l) 1 71. After BIU 1 7 fetches the data on the new cache line, it will put the data F i 1 1-da ta into the filling buffer 4 1 3. Then, the data in the filling buffer will be It is sent to the CPU 11 so that the CPU can continue to execute the next instruction operation. Fig. 5 is an example of filling the buffer structure according to the present invention. As shown in Fig. 5, the above structure includes a filling address column to store the missing columns. Address °,, and, many data word columns to store a row of data to be fetched. In this example, a cache line contains 4 CPU words. It should be noted that the two examples described are only used The description is not for limitation. Figures 6a and 6b are operation flowcharts according to Figure 4 of the present invention. As shown in Figures 6a and 6b, when the CPU issues When reading or writing the signal (S1), c⑶ checks the current cache state (S2). If it is a cache hit, ccu accesses the data from the cache memory (S3), and the CPU continues to operate without delay. If ^ cache is lost, ecu then checks the bit dirty flag d 丨 rty_H No (S4) 'that is,' checks if dirty_nag = 1, where d_lrty_fUg is a status bit, which is used by ccu to indicate because Whether the previous dirty column has been replaced in the write buffer. If dirty-f lag = i 'the CCU must wait until the write is slow. When the write buffer is clear, the CCU issues a M tc) meaning K fills requirements to BIU to request

41220944 V. Description of the invention (9) When the above-mentioned dirty memory is read by the autonomous memory, a new cache is issued, which is produced by the "lost time", and the filling is not completed at this time. Self-contained before the step. Then, the cache column address is currently replaced, which is 0 in the figure (S11). State), the CCU is empty again, and di rty_ enters the write buffer to stop the operation to wait for empty. After the above di rty_f1ag block data is filled, it is passed to grab a new cache line, and at the same time, it is saved in the cache memory. List to write buffer (S6). When dirty_flag is inactive, the request is filled to the B I U to request the above list to be fetched from the autonomous memory (S7). Note that the dirty columns read in step 86 are the dirty columns of the previous life, not the dirty columns generated by the current loss. The data in the buffer is placed in cache memory (g 8). Note The data in the full buffer is the data read by the previous loss, and the data of the new cache line. Because the main memory and the system sink are relatively slow, the data on the new cache is now being processed by 311] in steps S6 and S8. The address used to access the cache is to lose the row address and data. The CCU updates the filled address column in the filled buffer with the current missing column address (ie, new) to replace the previous missing column address (s 9) and checks whether the column is dirty (S1 0). If the replaced column is not a dirty column (also clean), you do not need to update and set the right replaced column as a dirty column (that is, the dirty status in the figure. Check whether the write buffer is Headroom (s 1 2). If the net flag is not set to i (si 3), so that the above-mentioned dirty lister can be used later, so the ccu and CTU resources can be released first without writing to the buffer temporarily. Headroom. Conversely, if the write buffer is a net replaced column, it is placed in the write buffer (s 丨 4) and set to 0 (S15). Then, ccu waits for the first person in the missing column to fill the buffer ( S1 6). The first block of data is received and sent to the CPU, so that the CPU can continue to operate (S17).

1220944 V. The remaining words in the description of the invention (ίο) can be filled into the fill buffer after the CPU continues to operate. The foregoing flow is clearly shown in FIG. 7, in which, when the CCU issues a fill request in the fetching lost column cycle, the CPU continues to operate by setting dirty_flag = 1. Therefore, the CPU operation is not delayed because the write buffer is not cleared. Note that from steps 36 to 816, the BIU is fetching missing columns (new cache columns) from the main memory, and because the main memory and system buses are relatively slow, bottlenecks usually occur at BIU grabs the missing columns, instead of (; (^) in steps S6 to 3116 to perform the task. Note that each time a cycle in Figure 6 is executed, only one of steps S6 or 31 4 will be executed. If step 34 is executed, the write buffer will not be cleared. Therefore, when the CCU state machine jumps to step S12, it will then execute step S13 instead of step S14 '. Then, jump from step si3 to step without waiting Write buffer headroom to put dirty columns into the write buffer. The above action of putting into the write buffer will be delayed until the ccu jumps to the next-person and fetches the missing step S4, Execution. At this time, because step S13 performed by the previous loss, the dirty_flag action is performed. In the present invention, cm may still have to wait for the write buffer clearance of step S5. However, compared with the car, I know the technology, This possibility is very small, because lost in the previous ^ The time between the loss and the loss can be used by the BIU to clear the write buffer. The two important moments when putting a dirty column into the write buffer are at step% and when a loss occurs, the present invention will be based on The write buffer is crying: the shape actively chooses to put dirty columns into the write buffer. This achieves the goal of optimizing CPU efficiency. Although the invention has been disclosed above in a preferred embodiment, its Not used

Page 14 1220944 V. Description of the invention (11) To limit the present invention, anyone who is familiar with this technology can make changes and retouches without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be considered The attached application patent shall prevail.

0697 -9048TWF (N1); P2002-054; SUE.ptd Page 15 1220944 The diagram briefly explains the advantages of the invention, μ, +, the above and other objects, features, and advantages. Example, and in conjunction with the attached drawings, make a detailed description as follows: Μ 八 作 bang The first picture shows a JL female 10. System • Block diagram of a conventional microprocessor with cache memory, w shows the second diagram Figure 1 shows the operation flowchart of Figure 1; Figure 3 shows the cache memory controller in Figure 1-a series of operating cache memory controller units

Fig. 4 shows a block diagram according to the present invention; X Fig. 5 shows an example of filling a buffer according to the present invention. Fig. 6a and 6b show a complete operation flow according to the present invention. Figures A and 7 show operation diagrams of the cache memory controller in Figure 4 of the present invention. Queue [Symbol Description] 11 ~ Central Processing Unit (CPU) 1 2 ~ Tag Memory-13 ~ Cache 3 Cache Memory 1 4, 4 Cache Controller Unit ( ccu) 15 ~ main memory 16 ~ memory controller (MEMC) 1 7 ~ bus interface unit (BIU) 4 1220944 simple illustration 1 8 system bus (systembus) 171 ~ write buffer (Write buffer) 411 & cache data control unit 412 ~ tag comparison is simple and flat 70Qtag compare unit) ^ ~ fill buffer · state of cache memory controller unit Machine (CCU SM)

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Claims (1)

1220944 6. Scope of patent application • A type with a dirty line θ S 士 田 # Memory controller unit plus #. Cache 1 of the wither and withdrawal # (U) Zhu structure, suitable for a write-back Fast &# & Egypt round a memory, a central processing unit (CPU) and a bus interface sheet containing a ^, stage punch = write ^ should have the line ⑷rty iine) write back ^ The architecture of the processing unit of the controller includes: · The Shaanxi 圮 memory system processing Ϊ Ϊ shell material control unit, Xiao Yi to access the cache memory above the knife * Central processing data between the early 7G; L k body and Secondary standard 蕺 comparison unit, used to compare the central address output and a single bit hit signal of the hidden memory position 70 迗; U 铩 wears the address output 'to generate—Quick M: cache memory controller unit state machine Use the comparison and results to control the cache f ^ The above salary flag is set and the write buffer is cleared ": =: if-if the dirty flag is not set, issue-fill the write Row; 丨 the surface must use * to find the bus interface unit to grab a new i ^ bus assembly, or, if the write buffer The operation of the central processing unit is based on the operation of the central processing unit so that one is taken to be dirty; the standard is continued and the new dirty row is filled; a buffer is filled to store the bus interface. The information provided to the cache memory controller 7 is for use ..., the information includes one of the missing two; :: big state machine operation; 2. the application of the patent scope of the i item has a dirty column Ui site. Write the auto-adjusted cache memory controller unit ([⑶] shelf 1 ne) back to the frame, where, 0697-9048TWF (N1); P2002-054; SUE.ptd Page 18 1220944 VI. Patent application scope j Filling the buffer includes a row of addresses 櫊 to store a lost row address, and L ^ material block for storage Relevant data of the lost column captured by the central processing unit. 3. Shi Shenyue's Patent Scope Item 1 has a cache memory controller unit (ccu) architecture with automatic adjustment of the dirty line and the automatic adjustment. In the bean, the effective position of the person is displayed as a private cache. Included in the list, the office's Fanfan 'is used to show that the corresponding cache line has been modified by the dirty line (dirty line) and the cache memory controller unit (ccu) has been corrected in the third patent area. Among them, the corresponding cache column is the dirty column or the new cache column. Recording, 5-line writing (dirty line) write-back auto-adjustment-cache processing unit (CPU), and containing-ticket weaving memory, one I (BIU) from the ancient to the last one into the confluence of Ling Chongyi The interface interface is issued for the hit + + e + system. The method includes the following steps: f Field issues a fetch or a falcon or loss event; Λ write ... Check if the current cache line is a cache Hit the plant, and the item that produced a hole material will be accessed from it. The beru fetched from the memory is a cached lost plant. This item is issued when the dirty flag is not activated. Fill in :: flag Mark whether to operate the surface unit to request a new column from the bus interface to the bus interface. ^ S β new memory of the main memory; when the write buffer is clear and the discriminating operation is performed, a fill is issued. 0697-9048TWF (N1); P20〇2-〇54; SUE.ptd Page 19 1220944 6. The scope of patent application requires the bus interface unit to request a new row from the main memory and simultaneously lose the previous one. A generated dirty row is read from the write-back cache to the write buffer; the data read from the previous loss is filled from the full buffer into the write-back cache; ^ ^ Update the filled address column in the above filled buffer to-the current missing column address; / check if the column currently being replaced is a dirty column; when the replaced column is not a dirty column, set the dirty flag to No action; when the replaced column is a dirty column, check whether the write buffer is clear; w when the write buffer is not clear, set the dirty flag as an action, so that the replaced column is later Put in the write buffer, so that the cache memory controller unit and the central processing unit can be released without waiting for the buffer to be cleared; when the write buffer is cleared, write in the replaced column After entering the write buffer, set the dirty flag to inactive; '* To the central processing unit' according to the fetched from the buffer filled by the cache control unit where the first data block transmission above a new column in the transfer of the central processing unit continues. 6. Operation method of a cache memory controller unit (CCU) architecture with dirty 1 ine write-back auto-adjustment, such as item 5 in the scope of patent application, " Xuan dirty flag is a state Bit, used by the cache memory controller to indicate whether the dirty row to be replaced because of the previous loss has been replaced ^ 0697-9048TWF (Nl); P2002-054; SUE.ptd Page 20 1ZZUV44 1ZZUV44 6. The patent application scope is included in the write buffer. 7 · If a method for automatic adjustment of monograph is applied, in which the missing column is lost, the current loss is 8 · If a method for automatic adjustment of monograph is applied, in which, The full address block and the multiple memory mentioned above are among the early ones to be captured. The profit range cache is full of buffers. The profit range cache is cached. The data word address is listed in the fifth item of the data. The operator with a dirty une memory controller unit (CCU) structure is as described above. Store the previous address and data separately in different steps. The operation of the fifth line with a dirty line memory controller unit (ecu) architecture The memory controller unit uses the above-mentioned filling buffer with a filling block, which fills more than 4 data in the address column Blocks the central processing unit