TWI220785B - Memory module with directly chip-attaching and method for making thereof - Google Patents
Memory module with directly chip-attaching and method for making thereof Download PDFInfo
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- TWI220785B TWI220785B TW091124413A TW91124413A TWI220785B TW I220785 B TWI220785 B TW I220785B TW 091124413 A TW091124413 A TW 091124413A TW 91124413 A TW91124413 A TW 91124413A TW I220785 B TWI220785 B TW I220785B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Semiconductor Memories (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
1220785 五、發明說明(1) 【發明領域】 本發明係有關於記憶體模組〔memory modu 1 e〕,特 別係有關於一種晶片直接貼附記憶體模組及其製造方法。 【先前技術】 習知記憶體模組之製造方法係區分為三個主要流程, 即記憶體積體電路之記憶體晶圓製作製程、記憶體晶片封 裝製裎與記憶體模組裝配製程,通常係由一晶圓製作廠提 供記憶體晶圓,並進行晶圓測試與雷射修補;之後,由— 晶片封裝廠將由晶圓切割後形成之晶片電性連接至_丨c載 體〔如導線架、電路基板或電路膠膜〕並以樹脂密封之, 形成一記憶體封裝結構,其型式係如薄小尺寸外觀封筆’ 〔Thin Small Outline Package,TS0P〕或球格陣列: 〔Bal 1 Grid Array package,BGA〕等等,並對該—j 裝 封裝結構進行電性測試與/或老化測試〔burn—丨n e己匕體 然後,再由一模組裝配廠將多個記憶體封裝結構 =〕; 記憶體模組基板〔小型印刷電路板〕,構成一記情^ ^ ~ 〔memory module〕,並進行最終產品測試,就此二=組 標準製程而言,每一種記憶體模組之製造需要噔—一習知 同之測試設備’即晶圓測試機台、封裝結構測試ς =不 組測試機台,儘管上述機台均作為測試記憶體之與模 而晶圓測試機台之探測卡〔用以接觸晶圓〕 然 試機台之HI-FIX測試板〔用以接合封裝結構〕盥=了構測 機台之插槽測試板〔用以扣接記憶體模組〕均測試 同,無法整合,在每一種記憶體模組之製造方法;2 力而要使1220785 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a memory module [memory modu 1 e], and particularly relates to a chip directly attached to the memory module and a manufacturing method thereof. [Previous technology] The manufacturing method of the conventional memory module is divided into three main processes, that is, the memory wafer manufacturing process of the memory volume circuit, the memory chip packaging process, and the memory module assembly process. Memory wafers are provided by a wafer fabrication plant, and wafer testing and laser repair are performed. After that,-the wafer packaging plant electrically connects the wafers formed by the wafer dicing to a carrier such as a lead frame, Circuit board or circuit adhesive film] and sealed with resin to form a memory package structure, whose type is such as thin small outline package pen [Thin Small Outline Package, TS0P] or ball grid array: [Bal 1 Grid Array package, BGA] and so on, and perform electrical test and / or aging test on the -j package packaging structure [burn-ne], and then a module assembly factory will pack multiple memory package structures =]; memory The body module substrate [small printed circuit board] constitutes a memory ^ ^ ~ [memory module], and the final product test is performed. As far as the two = group standard processes are concerned, the manufacture of each memory module You need to know the same test equipment, that is, the wafer test machine and the package structure test. The test machine is not set, although the above machines are used as the test card of the test memory and mold. [Used to contact the wafer] However, the HI-FIX test board of the test machine [for joining the packaging structure] = the socket test board of the test machine [for the memory module] are tested the same, Unable to integrate in the manufacturing method of each memory module;
1220785 五、發明說明(2) 用到三種昂貴 且各種不同之 不可諱言 量發展,因此 發,記憶體模 片封裝製程與 中華民國專利 模組及其製程 模組〔D i r e c t 造方法,如第 曰曰 圓」11 「第二次晶圓 測試」1 4之測 圓選擇性切割 該晶片組20係 2 1係形成有凸 之後,執行「 晶片組2 0覆晶 1 8步驟中,由 嫌不足,需要 塊2 2,以穩固 製造方法雖已 測試步驟1 2、 成之晶片組2 0 之測試機台’測試機台之設置成本相當^, 測試將增加測試成本。 地,記憶體模組係朝向低單價與高記憶體容 ,除了高容量高密度記憶體晶圓之持續研 組之製造成本亦應有效降低,特別係針對曰 模組裝配製程之整合與測試成本之降低,在 公報公告第4 7 2 3 7 2號「晶片直接貼附記憶體 」中’其係揭示有一種晶片直接貼附記憶體 ly Chip Attaching memory module 〕之製 1圖所示,首先在晶圓型態依序執行「提供 「第一次晶圓測試」1 2、 「老化測試」J /與 測試」14等步驟,之後,依據r第二次晶/圓 試結果,在「晶圓切割」1 5步驟中,將該晶 為複數個記憶體晶片組2 〇,如第2圖所示, 由複數個並排晶片21所一體構成,該些晶片 塊22,並在「提供記憶體模組基板」1 6步驟 m附晶片組於基板」17步驟,其係將該 接口至该記憶體模組基板30,並在「封裝 於晶片組20與記憶體模組基板30之固定性^乃 ^封裝材料4〇〔 underf iu〕包覆該些凸 敫人^在上述之晶片直接貼附記憶體模組之 二ς =片B封裝製程與模組裝配製程,然而其 盘記悛Ϊ 3 f態之測試’對於由後續作業形 〜體杈、、且基板3〇之電性連接狀況與記憶1220785 V. Description of the invention (2) Three types of expensive and various undeniable developments are used. Therefore, the memory chip packaging process and the Republic of China patent module and its process module [D irect manufacturing method, such as the first "Yuanyuan" 11 "Second wafer test" 1 4 The test circle selectively cuts the wafer group 20 series 2 1 series After forming the convexity, the "chip group 20 flip chip 18" step is performed, which is deemed insufficient, Block 2 2 is required. Although the test step 1 2 of the completed chipset 20 has been tested in a stable manufacturing method, the test machine's setup cost is equivalent ^, and the test will increase the test cost. Ground, the memory module is oriented Low unit price and high memory capacity, in addition to high-capacity and high-density memory wafers, the manufacturing costs of continuous research groups should also be effectively reduced, especially for the reduction of integration and test costs of module assembly processes. 7 2 3 7 2 "Chip directly attached memory" "It is revealed that there is a kind of chip directly attached memory ly Chip Attaching memory module." "Provide the" first wafer test "1 2," aging test "J / and test" 14 steps, after that, according to the second crystal / circle test results, in the "wafer cutting" 1 5 steps, This crystal is formed into a plurality of memory chip groups 20, as shown in FIG. 2, which is integrally composed of a plurality of side-by-side wafers 21, the wafer blocks 22, and “providing a memory module substrate” 16 in step m. Attach the chip set to the substrate "step 17, which is to interface the memory module substrate 30 with the fixation of" packaged in the chip set 20 and the memory module substrate 30 ^ ^ packaging material 4〇 [underf iu] Encapsulate these convex parts ^ The second part of the chip directly attached to the memory module above = chip B packaging process and module assembly process, but its inventory 悛 Ϊ 3 f state test Working shape ~ body frame, and electrical connection status and memory of substrate 30
(I 1220785 五、發明說明(3) --------- 體,組基板30之功能等等,均無法有效檢測,其製造出之 。己丨思體拉組仍有可能為不良,另一需要注意的問題曰 組20之製作,在晶圓製造後,無法完全切割該晶圓,:須 依據測試結果,進行選擇性切割,以製作具有複數個晶片 21 —體之晶片組2〇,每一次的晶圓切割路徑均不相同,切 割之自動化設計比以往的晶圓切割更為複雜而困難,例如 不良晶片21不恰當地分散於該晶圓,將使得一體的晶片組 20不易製#,再者,習知個別晶片具有更大面積之晶片 組20,當貼附該記憶體模組基板3〇時存在著更大之熱變應 力’易於剝離或翹曲。 另’中華民國專利公報公告第4 52320號「覆晶直接承 載(FC-DCA)記憶體模組」專利案中,係揭示有一種晶片直 接貼附冗憶體模組〔DC A memory module〕,其係將複數 個記憶體晶片覆晶接合〔fHp — chip m〇unting〕至一基板 上,f與該基板電性連接,然而晶片與基板係以凸塊接 合’晶片與印刷電路板之基板兩者熱膨脹係數不同,易於 脫離或凸塊斷裂’需要以一填充物〔⑽derfiiiing mater 1 a+1〕塗施於該些晶片與基板之間,以增進晶片在基 板上之Ϊ位性,且在塗施該填充物後,若測得有不良之晶 Ϊί ί針對個別晶片進行修補或替換,一個不良之晶 t ^條記憶體模組之其它良好晶片無法被使用。 【發明目的及概要】 本發明之I i β μ於 祕> Λ ^ 王要目的係在於提供一種晶片直接貼附記憶 體相:組’利用兮p々备掷^ y 尤體板組基板之框座,以供直接貼附晶片(I 1220785 V. Description of the invention (3) --------- The function of the body, the group substrate 30, etc., cannot be effectively detected, and it is manufactured. It is still possible that the think body pull group is bad Another problem that needs attention is the production of group 20. After the wafer is manufactured, the wafer cannot be completely cut. Selective cutting must be performed according to the test results to produce a wafer group 2 with a plurality of wafers 21 〇, each wafer cutting path is different, the automatic design of cutting is more complicated and difficult than conventional wafer cutting. For example, the defective wafer 21 is not properly dispersed on the wafer, which will make the integrated wafer group 20 difficult.制 #, Furthermore, it is known that the individual chip has a larger area of the chipset 20, and when the memory module substrate 30 is attached, there is a greater thermal variable stress 'easy to peel off or warp. Another' In Patent Gazette Bulletin No. 4 52320 "Flip-Chip Direct Carrying (FC-DCA) Memory Module" patent, it is disclosed that a chip is directly attached to a redundant memory module [DC A memory module]. Memory chip flip-chip bonding (fHp chip m〇unting] to a substrate, f is electrically connected to the substrate, but the wafer and the substrate are bonded by bumps 'The thermal expansion coefficient of the wafer and the substrate of the printed circuit board are different, easy to detach or the bump breaks' need to be A filler [⑽derfiiiing mater 1 a + 1] is applied between the wafers and the substrate to improve the position of the wafer on the substrate, and after the filler is applied, if a bad crystal is detected. ί Repairing or replacing individual chips, a bad crystal t ^ memory module and other good chips cannot be used. [Objective and Summary of the Invention] I i β μ of the present invention > Λ ^ Wang Yao Purpose Is to provide a chip directly attached to the memory phase: the group 'use Xi p々 prepare to throw ^ y yuyou board group substrate base for direct chip attachment
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達到整合 封裝與模組裴 之定位 配流程且節省塗膠步驟之 功效。It achieves the integration of packaging and module positioning, and saves the effect of glue application steps.
本發明之^ 體模組,利用—己 的係在於提供一種晶片直接貼附記憶 之定位與替換Ζ心,模組基板之框座,以供直接貼附晶片 曰Μ仍且I 、’使得在模組級測試之後,不良之直接貼附 日日片仍具有可被替換之功效。 本發明之爯一 體模組之製4方二目的係在於提供一種晶片直接貼附記憶 目J; W4在晶圓切割後’將記憶體晶片係直接 :=心己憶體模組基板之框座,並進行至少一次的模組 Α太:W以同時測試晶片與基板,達到降低測試機台設置 成本並減少測試成本之功效。The body module of the present invention is based on the provision of a chip directly attached to the memory for positioning and replacement of the Z core, and the frame base of the module substrate for directly attaching the chip. After module-level testing, bad direct-attached Japanese-Japanese films still have the effect of being replaceable. The purpose of the present invention is to provide a chip directly attached to the memory head J; W4 after the wafer is cut, 'the memory chip is directly: = the frame of the heart module module substrate And at least one module A too: W to test the wafer and the substrate at the same time, to achieve the effect of reducing the cost of test machine setup and reducing the cost of testing.
Μ Μ ^ ^ 1月之另一目的係在於提供一種晶片直接貼附記憶 :、、且之衣造方法’其係在模組基板上測試複數個設於框 ^ f片,在模組級測試後,仍可進行晶片之替換,有效 玉a則端測試與後端測試於模組級測試。 ^依本發明之晶片直接貼附記憶體模組,其係包含有一 6己^體模組基板及複數個直接貼附之記憶體晶片,該記憶 體模組基板係具有一晶片貼附表面,該晶片貼附表面上形 成有複數個框座,該些框座内形成有接觸端,該些記憶體 晶片係個別地設於該記憶體模組基板之框座,每一記憶體 晶片係形成有複數個導接端,如平墊狀或凸起狀,並電性 導接至對應框座之接觸端’較佳地,該記憶體模組基板係 裝設有一定位蓋,如金屬外殼板,該定位蓋係具有壓合 面’如呈凸起平面’其對應於該記憶體模組基板之框座,Μ Μ ^ ^ Another purpose of January is to provide a method for directly attaching memory to a chip :, and the method of making clothes, which is to test a plurality of ^ f pieces on a module substrate and test at the module level. Later, chip replacement can still be performed, and effective jade testing is at the module level. ^ The chip directly attached memory module according to the present invention includes a 6-module module substrate and a plurality of directly attached memory chips. The memory module substrate has a wafer attachment surface. A plurality of frame bases are formed on the wafer attaching surface, and contact ends are formed in the frame bases. The memory chips are individually arranged on the frame base of the memory module substrate, and each memory chip is formed. There are a plurality of lead terminals, such as a flat pad or a convex shape, and are electrically connected to the contact ends of the corresponding frame base. Preferably, the memory module substrate is provided with a positioning cover, such as a metal shell plate The positioning cover has a pressing surface 'such as a convex plane' which corresponds to a frame base of the memory module substrate,
Υί 頁 ' ---~--- 1220785 五、發明說明(5) 以供緊貼固定該些晶片於該些框座 依本發明之晶片直接貼附記憶體模組之製造方法,其 ^ ρΓΪ 體曰3以下步驟:提供一晶圓,該晶圓係具有複數個記憶 二:片;切割該晶圓,以形成複數個個別之記憶體晶片, 母 C憶體晶片係形成有導接端;提供一記憶體模組基 夕 忒5己憶體模組基板係具有一晶片貼附表面,該表面上 ^成有複數個框座,該些框座内形成有接觸端;貼附一預 定數量之該些記憶體晶片至該記憶體模組基板之該些框 座’使得記憶體晶片之導接端係與框座之接觸端相導通; 曰 第=次模組測試在該記憶體模組基板上之該些記憶體 =片’當第一次模組測試時,測得不良之記憶體晶片係能 曰j之,而後,再進行第二次模組測試;較佳地,另包含 有—預燒測試,可於晶圓型態或模組型態實施。 【發明詳細說明】 〜 -月參閱所附圖式,本發明將列舉以下之實施例說明: 依本發明之一具體實施例,如第3及4圖所示,一晶 直#妾貼附記憶體模組係主要包含有一記憶體模組基板丨 及複數個記憶體晶片1 2 〇,其中該些記憶體晶片J 2 〇係可 SJRAM〔同步動態隨機存取記憶體〕、DDR DRAM〔倍動、、 態隨機存取記憶體〕、DDR SDRAM〔同步倍率動態隨機存 取圯憶體〕、Rambus DRAM或f lash〔快閃記憶體〕等 體晶片,在每一記憶體晶片12〇係形成有複數個導接端思 121 ’導接端121可呈平墊狀或凸起狀。而該記憶體模組美 板1 30係為一小型板狀或條狀之印刷電路板,習知係具有土Υί Page '--- ~ --- 1220785 V. Description of the invention (5) A manufacturing method for directly attaching the chips to the frame and directly attaching the memory module according to the wafer of the present invention, which ^ ρΓΪ The following steps are provided in the system: a wafer is provided, the wafer is provided with a plurality of memory two: a slice; the wafer is cut to form a plurality of individual memory wafers, and a mother C memory wafer is formed with a lead end; Provide a memory module. The base module of the 5th memory module module has a wafer attachment surface, and a plurality of frame bases are formed on the surface, and a contact end is formed in the frame bases; a predetermined number is attached. The memory chips to the frame bases of the memory module substrate make the lead ends of the memory chip and the contact ends of the frame bases conductive; the first module test is in the memory module. The memory on the substrate = slices. When the first module test, the bad memory chip can be called j, and then the second module test is performed; preferably, another —The burn-in test can be implemented in wafer type or module type. [Detailed description of the invention] With reference to the attached drawings, the present invention will enumerate the following embodiments: According to a specific embodiment of the present invention, as shown in Figures 3 and 4, a crystal straight # 妾 paste memory The body module system mainly includes a memory module substrate 丨 and a plurality of memory chips 1 2 0, among which the memory chips J 2 0 are SJRAM [Synchronous Dynamic Random Access Memory], DDR DRAM [Multiplier , DDR SDRAM], DDR SDRAM [Synchronous Rate Dynamic Random Access Memory], Rambus DRAM or flash [Flash Memory], etc., are formed in each memory chip 120 series The plurality of lead-in ends 121 'The lead-in ends 121 may be flat or convex. The memory module US board 1 30 is a small board-shaped or strip-shaped printed circuit board.
1220785 五、發明說明(6) 複數層電路層〔約4至8層或更多〕,該記憶體模組基板 130之一側邊形成有複數個金手指131〔gold finge]r〕, 以供插置時導接至另一電子元件,如主機板,在本實施例 中’該記憶體模組基板130係為DDR DIMM基板〔Double Data Rate Dual In-line Memory Module 〕,其計有184 個金手指,然而本發明係不局限該記憶體模組基板丨3 〇及 其金手指數量,該記憶體模組基板1 30亦可為SDRAM〔同步 動態隨機存取記得體〕、f 1 ash〔快閃記憶體〕或其它記 憶體模組基板,該記憶體模組基板1 3 〇另在金手指1 3 1之兩 側邊各形成有一扣槽1 3 2,以供插置時之定位及穩固,該 記憶體模組基板1 3 0係具有一晶片貼附表面1 33,該晶片貼 附表面133係形成有複數個框座140,每一框座140係具有 電性接觸端1 4 1,對應於記憶體晶片1 2 〇之導接端1 2 1,且 該些接觸端1 4 1係經由該記憶體模組基板丨3 〇之内部電路連 接至金手指1 3 1,該些框座1 4 0係可為一體形成於該記憶體 模組基板1 3 0之框緣〔銅質〕,或者是另行裝設之塑膠轉 接座、陶瓷轉接座或薄膜轉接座,以供直接貼附時記憶體 晶片1 2 0之定位,故記憶體晶片1 2 〇係定位於該框座J 4 〇, 可不需要封裝材料或填充物,此外,在模組級測試之後, 不良之直接貼附晶片仍具有可被替換,較佳地,該記憶體 模組更包含有一定位蓋1 5 0,如金屬外殼板或塑膠外殼 板,該定位蓋1 5 0係具有壓合面1 5 1,如呈凸起平面,其對 應於該記憶體模組基板1 3 0之框座1 4 0,當以固定栓穿過兮 記憶體模組基板130之結合孔134時,定位蓋丨50係緊密1220785 V. Description of the invention (6) A plurality of circuit layers [about 4 to 8 layers or more], one side of the memory module substrate 130 is formed with a plurality of gold fingers 131 [gold finge] r] for When inserted, it is connected to another electronic component, such as a motherboard. In this embodiment, 'the memory module substrate 130 is a DDR DIMM substrate [Double Data Rate Dual In-line Memory Module], which has 184 Gold finger, however, the present invention does not limit the memory module substrate, the number of gold fingers, and the memory module substrate 1 30 may also be SDRAM [Synchronous Dynamic Random Access Memory], f 1 ash [ Flash memory] or other memory module substrates, the memory module substrate 1 3 0 and a gold finger 1 3 1 on both sides of each side is formed with a buckle slot 1 3 2 for insertion and positioning and Stable, the memory module substrate 1 30 has a wafer attaching surface 1 33, the wafer attaching surface 133 is formed with a plurality of frame bases 140, and each frame base 140 has electrical contact ends 1 4 1 , Corresponding to the lead ends 1 2 1 of the memory chip 1 2 0, and the contact ends 1 4 1 are via The internal circuit of the memory module substrate 丨 3 〇 is connected to the gold finger 1 31, the frame bases 140 can be integrally formed on the frame edge [copper] of the memory module substrate 130 It is a separately installed plastic adapter, ceramic adapter or film adapter for the positioning of the memory chip 1 2 0 when directly attached, so the memory chip 1 2 0 is positioned at the frame J 4 〇, no packaging materials or fillers may be required. In addition, after module-level testing, defective direct-attach chips can still be replaced. Preferably, the memory module further includes a positioning cover 1 50, such as The metal cover plate or the plastic cover plate, the positioning cover 15 0 has a pressing surface 15 1. If it is a convex plane, it corresponds to the frame seat 1 4 0 of the memory module substrate 1 3 0. When the fixing bolt passes through the coupling hole 134 of the memory module substrate 130, the positioning cover 50 is tight
第9頁 1220785 五、發明說明(7) . 合於該記憶體模組基板1 3 0,並以其壓合面1 5 1緊貼固定該 些記憶體晶片1 2 0於該些框座1 4 0,具有穩固記憶體晶片 I 2 0與增進記憶體晶片1 2 0散熱之功效。 本發明之晶片直接貼附記憶體模組之製造方法係用以 \ 製造上述之記憶體模組,如第5圖所示,其步驟係主要包 〜 含有··「提供一晶圓」1 11、 「晶圓切割」11 3、 「提供記 憶體模組基板」11 4、「貼附晶片於基板」11 5與「第一次 模組測試」1 1 6,其中在「提供一晶圓」111之步驟中,係 提供有一晶圓,其具有複數個記憶體晶片,較佳地,在 「提供一晶圓」Π1之步驟後,執行一「預燒測試」11 2, φ 約在1 2 5〜1 5 0 °C溫度環境下,對該晶圓施加一高於記憶體 正常運作之電壓〔-2. 5 V〕,以損壞該晶圓上早期不良之 記憶體晶片,所謂「早期不良之記憶體晶片」係指無法耐 久使用之記憶體晶片,易於半導體產品之保固期間内損 3 壞,應儘可能地於良品中剔除,依「浴缸曲線」理論,經 預燒測試之晶片將可有效減少記憶體之早期故障率,此 外,該「預燒測試」11 2亦可在「貼附晶片於基板」11 5步 驟之後於記憶體模組基板1 3 0上執行,在「晶圓切割」11 3 步驟中,係將該晶圓切離成複數個個別的記憶體晶片 120。 ⑩ 在「提供記憶體模組基板」11 4之步驟中,係提供一 記憶體模組基板1 3 0,在記憶體模組基板1 30之晶片貼附表 面1 3 3係形成有複數個框座1 4 0 ;在「貼附晶片於基板」 _ II 5之步驟中,其係由該晶圓中取得一適當數量的複數個Page 9 1220785 V. Description of the invention (7). The memory module substrate 1 3 0 is attached to the memory module substrate 1 3 1 and the memory chips 1 2 0 are closely fixed to the frame bases 1 2 0. 40, has the effect of stabilizing the memory chip I 2 0 and improving the heat dissipation of the memory chip 120. The manufacturing method of the chip directly attached to the memory module of the present invention is to manufacture the above-mentioned memory module, as shown in FIG. 5, and the steps are mainly packaged to include the "provide a wafer" 1 11 "Wafer dicing" 11 3. "Providing a memory module substrate" 11 4. "Attaching a chip to the substrate" 11 5 and "First module test" 1 1 6 of which, in "Providing a wafer" In step 111, a wafer is provided, which has a plurality of memory chips. Preferably, after the step of "providing a wafer" Π1, a "burn-in test" 11 2 is performed, and φ is about 1 2 In the temperature environment of 5 ~ 150 ° C, a voltage higher than the normal operation of the memory [-2. 5 V] is applied to the wafer to damage the early defective memory chip on the wafer. "Memory chip" refers to a memory chip that cannot be used for a long time, and is easy to be damaged internally during the warranty period of semiconductor products. It should be removed from good products as much as possible. According to the "bath curve" theory, chips that have undergone burn-in test will be able to be used. Effectively reduce the early failure rate of the memory, in addition, the "burn-in The "test" 11 2 can also be performed on the memory module substrate 130 after the "attach the wafer to the substrate" step 11 5. In the "wafer dicing" step 11 3, the wafer is cut into a plurality of numbers. Individual memory chips 120. ⑩ In the steps of “Providing a memory module substrate” 11 4, a memory module substrate 1 3 0 is provided, and a plurality of frames are formed on the wafer attaching surface 1 3 3 of the memory module substrate 1 30. Block 1 40; In the step of "attaching a wafer to a substrate" _ II 5, it is obtained from the wafer a proper number of plural
第10頁 1220785Page 10 1220785
兄憶體晶片120〔如2、4、8、16、32個或其它數量〕,並 貼附於該記憶體模組基板1 3 0之框座丨4 〇,且被該框座丨4 〇 口疋,並使彳于5己憶體晶片1 2 〇之導接端1 2 〇電性導接至框座 1 40之接觸墊1 4 1 ;之後在進行「第一次模組測試」丨丨6之 步驟中’如第6圖所示’其係以一記憶體模組測試機台模 f測試該接合有晶片120之記憶體模組基板丨3〇,該記憶體 模組測試機台係具有一測試基板丨6 〇,當該記憶體模組基 板1 3 0插置於該測試基板1 6 〇之插槽丨6 1,該記憶體模組基 板1 3 0之金手指1 3 1係電性導通至該模組測試機台,以供執 行可整修之模組級測試,此外,除了插槽式測試機台,探 針式測試機台亦可應用以模組級測試該些晶片丨2 〇 ;在 「第一次模組測試」1 1 6時,若測得有不良之記憶體晶 片,則執行「替換晶片」1 1 7步驟,其係依據第一次模組 測试結果’將在該記憶體模組基板1 3 〇框座1 4 〇内之不良記 憶體晶片1 2 0取出,並以另一記憶體晶片取代之,較佳 地’ 5玄用以替換之記憶體晶片係為已知良好晶片〔Κ η 〇 w η Good Die, KGD〕;在「替換晶片」117步驟之後,較佳 地’進行「第二次模組測試」11 8,以該記憶體模組測試 機台模組測試該經過替換後之記憶體模組基板1 30,該記 憶體模組基板1 3 0係結合至測試基板1 7 0之插槽1 71或其它 探針,以確認品質以及供分級判定;最後,進行「裝設定 位蓋」11 9工程,將一定位蓋1 5 0裝設於該記憶體模組基板 1 30,以增進該些記憶體晶片1 20之散熱與穩固性。 因此,依本發明之晶片直接貼附記憶體模組之製造方Brother memory chip 120 (such as 2, 4, 8, 16, 32, or other numbers), and is attached to the frame base of the memory module substrate 130, 4 0, and by the frame base 4 0. Mouth, and make the lead terminal 12 of the memory chip 1 2 0 electrically connect to the contact pad 1 4 1 of the frame base 1 40; and then perform the "first module test" 丨丨 6 steps 'as shown in FIG. 6' is a memory module test machine mold f to test the memory module substrate bonded to the chip 120 丨 30, the memory module test machine There is a test substrate 丨 6 〇, when the memory module substrate 130 is inserted into the test substrate 16 〇 slot 丨 61, the memory module substrate 1300 gold finger 1 3 1 It is electrically connected to the module test machine for performing module-level tests that can be repaired. In addition to the slot-type test machine, the probe-type test machine can also be used to test the chips at the module level.丨 2 〇; In the "first module test" 1 16, if a bad memory chip is measured, then perform the "replacement chip" step 1 1 7 based on the first module test Result 'Remove the bad memory chip 1 2 0 in the memory module substrate 1 3 0 frame 1 4 0 and replace it with another memory chip, preferably the memory of 5' The body chip is a known good chip [K η 〇w η Good Die, KGD]; after the 117 steps of "replace the chip", it is better to 'perform the "second module test" 11 8 to use the memory module Group test machine module tests the replaced memory module substrate 1 30. The memory module substrate 1 30 is connected to the socket 1 71 or other probes of the test substrate 170 to confirm the quality. And for the classification judgment; finally, the "installation cover" 11 9 project is performed, and a positioning cover 150 is installed on the memory module substrate 130 to improve the heat dissipation and stability of the memory chips 120. Sex. Therefore, the manufacturer of the chip directly attached to the memory module according to the present invention
第11頁 1220785 五、發明說明(9) 法係有效整合封裝流程與模組裝配流程,以模組級測試確 保晶片1 2 0、記憶體模組基板1 3 0與上述兩者之間的電性連 接線路等狀態,而且免除了填膠步驟。 本發明之保護範圍當視後附之申請專利範圍所界定者 為準,任何熟知此項技藝者,在不脫離本發明之精神和範 圍内所作之任何變化與修改,均屬於本發明之保護範圍。 ,:ug 幽Page 11 1220785 V. Description of the invention (9) The legal system effectively integrates the packaging process and the module assembly process, and uses module-level testing to ensure the electrical connection between the chip 1 2 0, the memory module substrate 1 3 0 and the above. Sexual connection lines, etc., and eliminate the glue filling step. The protection scope of the present invention shall be determined by the scope of the appended patent application. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. . : Ug
第12頁 1220785 圖式簡單說明 【圖式說明】 第1 圖 • 一 種 習 知 晶 片 直 接 貼 附 記 憶 體 模 組 之 製 造 方 法 圖 第2 圖 • 習 知 晶 片 直 接 貼 附 記 憶 體 模 組 之 截 面 示 意 圖 , ·: 第3 圖 • 依 據 本 發 明 之 一 具 體 實 施 例 5 一 晶 片 直 接 貼 附 記 憶 體 模 組 之 元 件 分 解 示 意 圖 y 第4 圖 • 依 據 本發 明 之 一 具 體 實 施 例 5 該 晶 片 直 接 貼 附 記 憶 體 模 組 之 截 面 圖 第5 圖 • 依 據 本 發 明 之 —- 具 體 實 施 例 5 該 晶 片 直 接 貼 附 記 憶 體 模 組 之 製 造 流 程 圖 j 及 • 第6 圖 • 依 據 本發 明 之 —— 具 體 實 施 例 5 該 晶 片 直 接 貼 附 記 憶 體 模 組 在 次 模 組 測 試 製 造 步 驟 之 截 面 圖 〇 [圖 號 說 明 ] 11 提 供 一 晶 圓 12 第 一 次 晶 圓 測 試 13 老 化 測 言式 14 第 二 次 晶 圓 測 試 15 晶 圓 切 割 16 提 供 記 憶 體 模 組 基 板 17 直 接 貼 附 晶 片 組 於 基 板 18 封 裝 20 晶 片 組 21 晶 片 22 凸 塊 30 模 組 基 板 40 封 裝 材 料 ( i 111 提 供 晶 圓 112 預 燒 測 言式 113 晶 圓 切 割 114 提 供 記 憶 體 模 組 基 板 115 貼 附 晶 片 於 基 板 - 116 第 — 次 模 組 測 言式 117 替 換 晶 片1220785 on page 12 Brief description of the drawings [Illustration of the drawings] Figure 1 • A manufacturing method of a conventional chip directly attached to a memory module Figure 2 • A cross-sectional schematic diagram of a conventional chip directly attached to a memory module, ·: Figure 3 • An exploded view of a chip directly attached to a memory module according to a specific embodiment 5 of the present invention y Figure 4 • According to a specific embodiment 5 of the present invention, the chip is directly attached to a memory module Sectional view of the group Figure 5 • According to the present invention-specific embodiment 5 The manufacturing flow chart of the chip directly attached to the memory module j and • Figure 6 • According to the present invention-specific embodiment 5 The chip A cross-sectional view of a direct-attached memory module in a sub-module test manufacturing step. [Illustration of drawing number] 11 Provide a wafer 12 No. One wafer test 13 Aging test formula 14 Second wafer test 15 Wafer dicing 16 Provide memory module substrate 17 Directly attach the chip group to the substrate 18 Package 20 Chip group 21 Chip 22 Bump 30 Module substrate 40 Packaging material (i 111 provides wafer 112 burn-in test 113 wafer cutting 114 provides memory module substrate 115 attaches the wafer to the substrate-116-second module test 117 replacement wafer
第13頁 1220785Page 13 1220785
第14頁 圖式簡單說明 118 第 二 次 模組 測試 119 裝 設 定 位 蓋 120 晶 片 121 導 接 端 130 記 憶 體 模組 基板 131 金 手 指 132 扣 槽 133 晶 片 貼 附 表面 134 結 合 孔 140 框 座 141 接 觸 端 150 定 位 蓋 151 壓 合 面 160 測 試 基 板 161 插 槽Brief description of drawings on page 14 118 Second module test 119 Mounting cover 120 Chip 121 Leading end 130 Memory module substrate 131 Gold finger 132 Buckle groove 133 Wafer attaching surface 134 Bonding hole 140 Frame base 141 Contact End 150 positioning cover 151 pressing surface 160 test substrate 161 slot
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TW091124413A TWI220785B (en) | 2002-10-18 | 2002-10-18 | Memory module with directly chip-attaching and method for making thereof |
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TW091124413A TWI220785B (en) | 2002-10-18 | 2002-10-18 | Memory module with directly chip-attaching and method for making thereof |
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TWI220785B true TWI220785B (en) | 2004-09-01 |
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