TW591792B - Manufacturing method of trench type capacitor with increasing capacitance value - Google Patents

Abstract

A kind of manufacturing method of trench type capacitor with increasing capacitance value is provided in the present invention. The invention includes the followings: providing a substrate and forming a trench in the substrate; forming a glass doped layer conformally on the sidewall and bottom portion inside the trench, so as to constitute the first opening in the trench; filling a filling layer having a specified height into the first opening through vapor phase deposition method, and using the filling layer as the mask to etch the glass doped layer, so as to generally align the glass doped layer with the filling layer; forming a spacer on the substrate, the glass doped layer, the filling layer and the trench sidewall; making the dopant in the glass doped layer diffuse outwards in the substrate to form an embedded plate; etching back the spacer to form a collar-shaped first separation layer spacer on the trench sidewall; completely etching the filling layer and the glass doped layer; etching the substrate inside the trench to form a bottle-shaped trench; and forming a trench capacitor structure inside the bottle-shaped trench.

Description

591792

[Technical field to which the invention belongs] The present invention relates to a semiconductor process, and in particular, to a method for manufacturing a bottle-shaped trench capacitor with increased capacitance (capaCitance). [Previous technology] The development technology of integrated circuits is changing with each passing day, and its development trend is moving towards powerful functions, reduced size and faster speed. The same is true of the manufacturing technology of dynamic random access memory (DRA M), especially its memory. The increase in capacity is the most important key. θ Most DR AM units today consist of a transistor and a capacitor. As the semiconductor process develops toward reducing the size of semiconductor components to increase the density of components, the memory capacity of DRAM has also increased to more than 51 million bits. Therefore, the base area of memory cells in the memory must be continuously reduced to enable integrated circuit performance. Accommodates a large number of memory cells to increase density. With the increasing requirement of component accumulation, the size of memory cells and transistors needs to be greatly reduced, so that it is possible to produce DRams with higher memory capacity and faster processing speed. However, the traditional stacked capacitor design method will occupy too much chip surface area and cannot meet the above requirements. The use of three-dimensional process technology can greatly reduce the area occupied by transistors and capacitors on the semiconductor substrate. Therefore, the three-dimensional technology has begun to be applied to DRAM processes, such as trench capacitors, which can meet the current requirements. The need for accumulation has greatly improved the shortcomings of conventional semiconductor memory cells, and has become a major trend in the manufacture of semiconductor memory cells at present and in the future. The basic structure of the trench capacitor is a doped silicon substrate.

591792

591792 V. Description of the invention (3) The semiconductor silicon substrate 100 is used to form a buried electrode plate 110 as a lower electrode of a trench capacitor. Please refer to FIG. Among them, the surface area of the buried electrode plate 110, which is used for powering down, is determined by the area of the trench covered by the silicon oxide layer 06, and the area of the trench covered by the silicon oxide layer 106 is controlled by the photoresist 107. The distance between the surface and the upper surface of the semiconductor silicon substrate 100 is 120. Because this method is not easy to maintain the thickness of the photoresist after stripping in each trench, and after the photoresist stripping process, the upper surface of the photoresist in each trench and the buried electrode plate cannot be reached. The predetermined height 丨 〇1, so it is not easy to control the area of the buried electrode plate, please refer to Figure ld. For example, under the design rule of 175 microns, the height difference of the photoresist surface may be as high as 8200 A This phenomenon will seriously affect the area of the buried electrode plate formed later. If the photoresist 108 is too high, the area of the buried electrode plate will be too large. This will cause the electrode and ion doped band (buried The breakdown voltage between (bands) is reduced, and even a short circuit occurs. Conversely, if the height of the photoresist 108 is too low ', the area of the buried electrode plate 110 formed will be too small', which will seriously affect the storage performance of the entire trench capacitor, please refer to FIG. In order to increase the capacitor area, a well-known practice is to form a hemispherical silicon grain (HSG) on the surface of a bottle-shaped trench in a grooved capacitor, as shown in Figure 2a. An emulsion layer 102 and a nitride layer 104 are formed on the semiconductor substrate 100, and a trench 14 is formed deep in the substrate at a predetermined position. Next, a protective layer as shown in Fig. 2a is formed in the upper half of the groove 1440, and then engraved with a surname.

0548-9673TWf (nl); 91276; Phoelip.ptd Page 7 591792 V. Description of the invention (4) The size of the groove is not covered by the protective layer 13 and the lower half forms a bottle shape not shown in the hole diagram. Trench 1 5 〇. Next, as shown in FIG. 2c, the protective layer 130 and the sidewalls and the bottom of the bottle-shaped trench 150 are sequentially formed—Arsenic Doped Silicon Dioxlde Giass; asg ) Layer [M and a tetraethoxy stone yaki (^ 〇 magic layer 134, and then drive (hue m) to form a 2d plate 110 inside the sidewall of the bottle-shaped groove. II electrocardiogram " 2. Please refer to FIG. 26. After removing the doped SiO2 glass layer (ASG) layer 132 and the tetraethoxysilane (TE0s) layer 134, the full-scale layer and the bottle-shaped groove are removed. The side wall and the bottom of the 150 are formed in a hemispherical shape: as described in the second two pounds 6: 1 ... SlUCon "" η; HSG) 190 layers, and lastly not shown in Figure 2f, remove the protective layer Half (HSG) layer 'while remaining on the side wall of the bottle-shaped trench and said layer of spherical silicon grains (HSG). 丨 Working day 7 thousand cuts v Due to the above-mentioned conventional manufacturing process, in the current process window (prOc Wmdow) Under the premise that it is getting smaller and smaller, 'because of the necessary grooves: a doped oxide layer of ceramics is formed in sequence), after the bottle groove is prone to form overhangs in the groove (〇Verhang It is unfavorable to increase the difficulty of the manufacturing process. It is mentioned below: the front capacitor that exhibits the difficulty of the St manufacturing process and improves the stability of the manufacturing process to improve the dynamic surface area and the grooved machine memory technology of the buried electrode plate. :: The characteristics of the body of memory is an important subject in the current dynamic clothing & technology.

[Summary of the Invention] The purpose of the invention is to provide a kind of increased capacitance value: i The manufacturing method of Gu Yi ', in order to simplify the process steps, increase the stability of the yuan, and not increase the process. The complex forward-swing / shaped groove structure and the roughened surface of the capacitor can form a bottle with a lift; ί ni can be in a highly integrated state, which is the force of the power storage valley to maintain good memory Operational Shanghai. To store 2 trenches, you need to increase the depth of the trench, that is, to increase the capacitance to the capacitance-added trench and form-trenches in the above "; Shun; :: substrate, side walls and bottom of the trench to construct θ The second opening is completed; the filling with a specific height is wider than the first opening in the trench, and the filling is performed in the upper layer by the above filling deposition method, so that the glass doped layer and the upper 4 are filled. 2 Etching the above-mentioned broken doped material; compliant formation-spacer layer; roughly cut the filling layer and the sidewall of the groove in the trench If = glass doped layer, dopants in the glass doped layer outward To: = dagger the above-mentioned buried board; etch back the above-mentioned spacer layer to form a second-to form a substrate that is etched into the above-mentioned trench, and divide it: :::-charge; = miscellaneous layer; Inside trench, trench and formation-trench 0548-9673TWf (nl); 91276: Phoelip.ptd 591792 V. Description of the invention (6) A method for manufacturing a trench capacitor with increased capacitance according to the present invention, wherein More intimidating: After forming the trench capacitor structure in the bottle-shaped trench, remove the collar shape A spacer gap wall and forming a collar-shaped insulating layer gap at the original position of the collar-shaped first spacer gap; forming a second conductive layer in a region surrounded by the collar-shaped insulation gap; and forming / The third conductive layer is on the above-mentioned collar-shaped insulating layer and the second conductive layer. According to a preferred embodiment of the present invention, a method for manufacturing a trench-type capacitor with increased capacitance according to the present invention, wherein After forming / the second conductive layer on the collar-shaped insulating layer and the second conductive layer, the method further includes performing a planarization process on the surface of the third conductive layer. According to the present invention, the capacitance value is increased. A trench capacitor manufacturing method, wherein the trench capacitor structure includes a conductive thin layer, a capacitor dielectric layer, and a first conductive layer. The step of forming the trench capacitor structure in the bottle-shaped trench is Including ... forming a conductive thin layer on the surface of the substrate in the bottle-shaped trench, wherein the conductive thin layer forms a lower region of a bottle-shaped trench; forming a capacitor dielectric Layer on the surface of the conductive thin layer; and filling the lower area of the bottle-shaped trench with a first conductive layer. The manufacturing method of the trench capacitor with increased capacitance according to the present invention can also be expressed in another way. 'At least includes the following steps: sequentially forming a first oxide layer and a thallium nitride layer on a surface of a substrate; and then forming a trench in the substrate' penetrating the first oxide layer and the first nitrogen A compound layer, and the surfaces of both sides of the first oxide layer are exposed;

591792 V. Description of the invention (7) Storey households: the exposed two sides of the layer, to form a layer between the above-mentioned oxide layer and the above-mentioned substrate to fill the first opening π, which is the ancient ㈤M #? M m trench. The bottom compliance is formed in the groove ..., == two second openings in the groove; a polycrystalline stone layer is filled in the sowing meat I, so that the polycrystalline silicon layer and the glass The doped layer in the above-mentioned trench ”ί ΐ Yiping®; compliantly formed-nitride spacer layer in the above-mentioned μ μs three glass doped layer, the polycrystalline silicon layer, and the trench side two by annealing treatment To form a buried plate toward the dopants in the above-mentioned glass doped layer, and remove the nitride spacer layer formed on the above-mentioned polycrystalline silicon layer to form a buried plate, so as to form A = on = a compound spacer on the sidewall of the trench; the polycrystalline silicon layer and the glass doped layer are completely removed; the above-mentioned base I in the above trench is formed to form a windscreen structure; In the bottle-shaped trench, an amorphous silicon layer is formed on the surface of the substrate in the bottle-shaped trench, and the upper layer is not :: layer structure A bottle-shaped trench lower region 4; for the above-mentioned amorphous silicon layer =:-f spherical granulation process' makes the amorphous silicon layer in the bottle-shaped trench ㈣ grain layer; forming-the capacitor dielectric layer on the above Hemisphere = Said: A first-conducting layer is filled on the surface of the vertical layer to the above-mentioned bottle shape \ second lower area, the collar-shaped nitride spacer is removed, and a collar-shaped oxide spacer is formed on the collar The original position of the nitride barrier wall, and a second conductive layer = two to = a third conductive layer is formed in the region surrounded by the collar-shaped oxide barrier wall, and a third conductive layer is formed on the collar-shaped insulating layer barrier and the second conductive layer. on.

0548-9673TWf (nl); 91276; Phoelip.ptd page 11 591792 V. Description of the invention (8) In order to make the above-mentioned objects and features of the present invention more comprehensible, the following exemplifies the preferred embodiments and cooperates with the attached The drawings are described in detail as follows: [Performance] The preferred embodiments of the present invention will be described in detail with reference to the drawings: Figures 3a to 3n are drawings that are not according to a preferred embodiment of the present invention. Cross-sectional view of the manufacturing process of a trench capacitor with increased capacitance. First, a substrate 100 is provided. A pad structure including a first oxide layer 102 and a first nitride layer 104 is formed on the surface of the substrate 100, and a trench 140 is formed on the substrate 1 by etching. 〇, penetrates the first oxide 102 layer and the first nitride 104 layer, and exposes both surfaces of the first oxide layer 102, as shown in FIG. 3a. The substrate 10 can be, for example, a P-type silicon substrate, an N-type silicon substrate, or an epitaxial silicon substrate. In the description of the present invention, the term " substrate " includes the components formed on the semiconductor wafer and various coating films covering the wafer. Any desired semiconductor element may have been formed thereon, but here In order to simplify the drawing, it is only represented by a flat substrate. The pad structure is composed of the first oxide layer 〇2 and the first nitride layer 104, and the first oxide layer is formed first. The object layer 1/2 is on the surface of the substrate 100, and then the first nitride layer 104 is formed on the first oxide layer 102. The first oxide layer i02 can be, for example, The oxidized stone layer is formed by, for example, performing a thermal oxidation process at a temperature of 850-950 ° C, or performing atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition ( LPCVD); the first nitrogen

0548-9673TWf (nl); 91276; Phoelip.ptd

Page 12 591792 V. Description of the invention (9) The compound layer is formed by low pressure chemical vapor deposition with a sic mixed gas at 700-800 ° C. Please refer to the figure # 3b, and use an isotropic meal engraving method to remove each part of the first oxide layer 102 from the two sides of the trench 140, so that the first oxide layer 102 A first opening 103 is formed on each side of the groove 14 between the substrate 100 and the substrate 100. The method of isotropically etching the first oxide layer 102 may be a wet etching. For example, the first oxide layer composed of silicon oxide may be etched using an etching chemical hydrofluoric acid (HF). . Next, a second nitride layer is comprehensively deposited on the surfaces of the first nitride layer 104 and the trench 140, and the formed second nitride layer 108 fills the first opening 1o. 3. Please refer to Figure 3c for the results. Then come to 'etch the above-mentioned second nitride layer 08' in order to remove the second nitride layer other than the inside of the first opening 103 03, leaving only the portion filled in the first opening 103 The second nitride layer 108. The above-mentioned step of depositing and filling the second nitride layer 108 into the first opening 03 is referred to as a "nitride & refill step", whereby the "nitride refill step" ", The refilled second nitride layer 108 can be used to protect the first oxide layer 104 which is a pad oxide layer from undercutting in the steps described below (un (ier cut) phenomenon, and thus can have more diversified use options for the chemicals used in the steps described below. The method of etching ^ a nitride layer can be a wet engraving, for example, using HF / e G (Gas gas owing / ethylene glycol) formula solution or hot phosphoric acid (Hs P 〇4) as a solution to leave a second nitride layer composed of silicon nitride 〇 02. Next, please refer to the As shown in Figure 3d, a glass substrate is deposited compliantly.

〇548-9673TWf (nl); 91276; Phoelip.ptd

591792 V. Description of the invention (10) The layer 112 is on the surface of the first nitride layer 104 and the groove 14o, and the glass doped layer 112 is formed in the groove 14 and forms a groove 14 〇a. Then, a filling layer of a predetermined height is deposited by a deposition method in the groove H0a formed in the groove 140 of the above-mentioned glass doped layer 112, which can be, for example, a polycrystalline silicon layer, where the fixed height is It is the depth of a buried plate to be formed next. The glass doped layer can be selected from the group consisting of boron-phosphorus-doped silica glass (BpsG), arsenic-doped silica glass (ASG), phosphorus-doped silica glass (PSG), and boron-doped silica glass (BSG). Among the groups, for example, borosilicate glass (β ^), and the formation method i 疋 is performed by mixing Si H4, B Fs, and% gas, and then performing a chemical vapor deposition step. The method for forming a polycrystalline silicon filling layer of a certain height 4 may include filling the groove 140a formed in the trench by the glass doped layer 112 with the filling layer 114, and then etching back the filling layer. From 114 to the above, the method for forming the filling layer 11 4 can be formed by, for example, synchronously doped low pressure chemical vapor deposition (LPCVD). The reaction gas is "3,

The reaction temperature of Sa and Krypton or AsH3, SiH4 and & is between 500 and 65 (TC).

Next, referring to FIG. 3e, the glass doped layer 112 higher than the predetermined height is removed by etching, so that the filling layer 114 and the glass doped layer 112 form a plane in the trench 140. The method for etching the glass doped layer 112 can be dry etching or wet etching. If it is a dry etching method, the etching method may be, for example, a magnetic field enhanced active ion plasma etching method (MERIE), an electron cyclotron resonance plasma etching method (ECR), or a conventional active ion plasma etching method (RIE). The plasma reaction gas may be, for example, one of six sulfonated sulfur (SFe), oxygen (02), tritium, and hydrogen bromide (HBr).

591792 V. Description of the invention (11) Mixed gas; if it is wet etching, for example, diluted hydrogen fluoride (Dhf) or buffered hydrogen fluoride (BHF) can be used as an etching solution to etch the glass doped as a glass doped layer Π2 glass (Asg). Next, as shown in FIG. 3f, a nitride spacer layer 116 is compliantly formed on the first nitride layer 104, the glass doped layer 112, and the filler layer 114 and the sidewalls of the trench 140. The formation of the nitride spacer layer 116 here has two advantages for the process of increasing the capacitance of the trench capacitor according to the present invention: one is to prevent the doped ions from diffusing to the undoped ones in the subsequent thermal process. The dielectric layer covers the trench 丨 40 in the substrate 100 around the sidewall to ensure that the buried plate 丨 丨 〇 is formed in the desired area; = this is the nitride spacer layer 116 after etching, That is, it can be used as a collar shape, and the nitride spacers 1 1 6a. The above-mentioned nitride spacer layer 6 can be a silicon-containing nitride, such as silicon nitride or silicon oxynitride, which can be made by LPCVD, using MW gas and ammonia gas. (NH3) is a messy body, and a silicon nitride layer as nitride 116 is deposited at an operating temperature of 250 to 400. ^ Continued, please refer to FIG. 3g, the dopants in the doped layer 112 made of annealed ytterbium glass are diffused outward to up to: "㈣η◦ doping (buried plate on the process at local temperature) The glass doped layer 112 is processed at a temperature of 80 0 to 1100 ° C, such as' promote from 0 to 0 'gates,' and other examples. For example, doped ions in the doped layer 112, such as two: 10 minutes, to Change the area of the glass to form-the buried plate 110. "Column around the groove 140 of the degree

Page 15 591792 V. Description of the invention (12) For the receiver, please refer to the figure 3h. You can perform a non-isotropic etching by calling "⑨_⑨" to remove a layer formed on the first nitride layer. And the nitride spacer layer 116 on the filling layer to form a collar-shaped nitride spacer 1 1 6 a. The above-mentioned anisotropic relief may be, for example, a magnetic field enhanced active ion plasma etching method ( MERIE), electron cyclotron resonance plasma etching (fCR), or traditional reactive ion plasma etching (RIE). The plasma reaction gas can be, for example, sulfur hexafluoride (SF6), oxygen (〇2), A mixed gas of chlorine (ci2) and hydrogen bromide ~ (HBr). Next, please refer to Figure 3i to completely remove the glass doped layer 1 12 and the filling layer 11 4 to facilitate bottle connection. The formation of a type trench. The method of removing the filling layer 1-4 may be, for example, wet etching, such as a flushed hydrofluoric acid (buffered oxide etching, BOE) solution Λ: may be wet etching , Such as the use of dilute glass fluoride doped layer hydrogen (BHF) as the last name to etch to etch the arsenic silicon Glass (ASG). Etching the above grooves 140 and 150 to form a bottle-shaped groove 150. The method can be A: 氐 4 substrate 1 00 to form a bottle-shaped groove 1 5 0-7 π σ ”Ma uses the gap between the upper commandment and the 11R, a lice compound 10 4 and the collar-shaped first spacer layer 丄 i 〇a shoulders 7 生 女 ιΐ 翌 # Etching the above, f Μ wide screen, using Dilute the cyanide aqueous solution or acid as the above dilution '::: semiconductor substrate' in the etchant to form a -bottle crack groove 'in the meantime. If the above wet erosion 2 = degree can be ammonia water: water ratio 1: 5 to 1:50, the way to form a bottle-shaped groove is to use acid, then

Page 16 is 792. V. Description of the invention (13) Alcohol (EG), dilute hydrofluoric acid can be, for example, hydrogen fluoride (JJF) / ethyl (DHF) or buffered hydrogen fluoride (BHF) to form the above-mentioned ampoule grooves 150 The method can also perform an oxidation of the bottom substrate 100 for the μ, +, and Sej nj. The bottom substrate 100 is oxidized to form a gas π P for the above-mentioned groove 140 1 00, and the exposed portion is oxidized with a p-knife. Base opening: first: Yan 'and by the first -nitride 104 and the above collar opening> The first spacer layer partition wall u is formed into a bottle-shaped groove mm ϋ Curtain Λ milk, and _ The chemical treatment may be a method of rapid thermal oxidation of hydrofluoric acid (HF dioxinization region). For example, the above-mentioned oxidation region may be etched using HF as an etching solution. As shown in the figure, the conformable formation-the base mi in the amorphous stone layer mi above the first nitride 104 and the bottle-shaped groove-shaped particles i (h. 7 'then' on the then amorphous silicon layer hemisphere = t (hemi-SPheHeal gFain, hsg) is not obvious = half-grain layer 190, redeposition-capacitor medium (above ::: shown) on the above-mentioned hemisphere type stone evening grain layer On the surface, it is thought that & ^ ί Grain layer 190 is formed from one of the subsequent first conductive layers 142 to form I:? The electrical layer (not shown in the figure) is separated. Among the above-mentioned spherical silicon ^ f: In the step of the grain layer 190, the above-mentioned half may also be performed as necessary. 〇 Gas phase doping (sound #) is performed to reduce the buried plate 110 and the hemispherical stone layer 1 With a concentration of 90 ° F, the dielectric layer can also be formed by LPCVD. Its material (〇Nn \ valley nitride dielectric layer, oxide / nitride / oxide 〇), nitride layer / oxide Xi layer (nitride / 〇xide, Ν other similar to this nature.

P.17 591792 V. Description of the invention (14) A >: With reference to FIG. 3k, the hemispherical silicon crystal grains formed on the chaotic 04 and the collar-shaped nitride spacer 1 16a are removed by etching. Layer 190 and the dielectric sound of the capacitor, fill the lower region of the trench 150 with a conductive layer 142 and a conductive layer 142. Among them, the capacitor dielectric method can be wet etching using hydrogen fluoride (HF) / ethylene glycol (EG) as the last name; and the method for etching the hemispherical silicon grain layer 19 can be: using diluted ammonia solution Etching of hemispherical silicon grains. The first and second conductive layers 1 ^ 2 may be polycrystalline silicon, doped polycrystalline silicon, or other conductive materials. Next, referring to FIG. 31, the collar nitride spacer 116a is completely removed by etching, and an oxide spacer layer 118 is conformably deposited on the above structure. Next, the oxide spacer layer 丨 8 is etched, and the oxide spacer layer 1 1 6 formed on the first nitride 104 and the first conductive layer 142 is removed to form a collar-shaped oxide spacer 丨丨 8 a, please refer to Figure 3m for the results. The etching method for removing the collar-shaped nitride spacer 116a may be a wet etching, for example, using a solution of HF / EG (hydrofluoric acid / glycol) formula or hot phosphoric acid (H3p04) as an etching solution The method for forming a collar-shaped oxide spacer 11 8 a may be isotropic etching of the above-mentioned oxide spacer layer 11 8, and the chemical used for the etching may be, for example, a hydrofluoric acid (HF) solution. . Finally, please refer to FIG. 3 η, perform an anisotropic money engraving on the collar-shaped oxide spacer 11 8 a to remove a part of the collar-shaped oxide spacer 118 a, and then follow a known method. The second conductive layer 144 and the third conductive layer 146 are filled in, and the manufacturing process of the trench capacitor with the increased capacitance value according to the present invention is completed. Wherein, the above-mentioned collar-shaped oxide partition wall 1 1 8 a

0548-9673TWf (nl): 91276; Phoelip.ptd page 18 591792 V. Description of the invention (15) The purpose of the directional remnant is to enlarge the opening of the above-mentioned trench to facilitate the formation of subsequent conductive layers. To sum up, compared with the conventional technology, the present invention has several advantages in the method for manufacturing a trench capacitor with increased capacitance. Firstly, the present invention can greatly increase the area of the capacitor, thereby effectively increasing the capacitance value of the capacitor; secondly, through the nitride refilling (ni tr ide ref i 1 1) step in the above method, it can be protected as a pad The first oxide layer of the pad oxide is free from undercuts. This method avoids the problems of the conventional bottle-type trench capacitors, which are difficult to process and easy to cause electrical interference. In addition, the present invention not only has the semi-process complexity that can be structured and can increase the capacitance area, it can also increase the performance of the trench capacitor in the precision period and the bottle-shaped trench structure formed by the dimension can not only effectively increase In the state of the trench capacitance accumulation, the stored operation performance is improved, and it is in line with the needs of the mesh accumulation process. The bottle-shaped groove spherical stone slab grain layer that greatly increases the capacitance, and does not increase the area of the buried board to avoid the control to maintain the stability of the component. According to the present invention, the capacitance of the surface of the rough chain trench is cryotropic, and its surface area enables the device to dynamically and randomly access the memory before the capacity of the capacitor is high enough to maintain the good memory. Anyone who is familiar with this technique and scope can make a variety of more scopes as the attached patent application examples are disclosed above, but it is not used for ☆ 'without departing from the spirit and / or decoration of the present invention, Therefore, those defined in the companion 1 of the present invention shall prevail. 4

591792 Brief description of the drawings Figures 1a to 1e are structural cross-sectional views, which show a manufacturing process of a conventional trench capacitor. Figures 2a to 2f are structural cross-sectional views, which illustrate a conventional manufacturing process of a bottle-type trench capacitor. Figures 3a to 3n are structural cross-sectional views, each showing a method for manufacturing a trench-type capacitor with increased capacitance according to a preferred embodiment of the present invention. [Symbol description] 100 ~ substrate; 10 1 ~ predetermined height of buried electrode plate; 102 ~ first oxide layer; 103 ~ first opening; 104 ~ first nitride layer; 106 ~ Oxide oxide layer; 107 ~ photoresist; I0 8 ~ second nitride layer; II 0 ~ buried plate; 11 2 ~ glass doped layer; 11 4 ~ fill layer; 11 6 ~ nitride spacer layer 11 6a ~ collar nitride spacer; 11 8 ~ oxide spacer; 11 8a ~ collar oxide spacer; 1 2 0 ~ predetermined distance;

0548-9673TWf (nl); 91276; Phoelip.ptd Page 20 591792 Brief description of the drawings 1 3 0 ~ protective layer; 1 3 2 ~ arsenic-doped silica glass layer; 134 ~ tetraethoxysilane (TEOS ) Layer; 140 to groove; 140a to groove formed by glass doped layer; 142 to first conductive layer; 144 to second conductive layer; 146 to third conductive layer; 150 to bottle groove ; And 190 ~ hemispherical silicon grain layer.

0548-9673TWf (nl); 91276; Phoelip.ptd page 21

Claims (1)

/ vz 6. The scope of patent application t A trench capacitor with an increased capacitance value The following steps: The method of table W includes providing a substrate and forming a trench on the substrate.-The compliance of the glass doped layer is formed on the top In order to form the H-port in the above-mentioned trench; the side i and the bottom of the above-mentioned opening are filled with a * impurity layer by vapor deposition, so that the above-mentioned glass doping 2 = the mask is doped and cut; t The impurity layer and the filling layer generally conform to form an interval within the groove. The filling layer and the groove are formed in the wall, the glass doped layer, the glass doped layer, and the glass doped reed φ Shuang & Forming-buried plate; dopants diffuse outward to the above substrate, and the above-mentioned interval ## 成 m is formed on the sidewall of the groove; the first spacer layer of the collar μ gap wall in the trench = removing the filling layer and the above A glass doped layer; forming a trench-like bottom to form a bottle-shaped trench; and: an electric valley as a structure in the bottle-shaped trench. • The method for manufacturing a cap capacitor with an increased capacitance value described in item 1 of the patent application scope, 1+ r is a grooved type bottle-shaped groove added with a compound; more ;: in the formation of the above The trench capacitor structure is formed on the upper interlayer partition wall and forms the original position of the collar-shaped insulating bead-dividing spacer; the second guide is formed in the region surrounded by the collar-shaped insulating layer gap. 0548-9673TWf (nl ); 91276; Phoelip.ptd Page 22, 591792 VI. Patent application electrical layer; and the second conductive third conductive layer on the collar-shaped insulating layer gap wall and the above-mentioned capacitor 3, please refer to the second item in the patent scope造 A method for manufacturing a trench-type opening with a capacitance value, wherein a surface of the third conductive layer is formed on the surface of the third conductive layer and the second conductive layer. After that, it further includes the method of manufacturing an increaser as described in item 3 of the scope of patent application, wherein the flattening process is a system on a chemical tank ^ 5 Manufacturing of Trench Capacitors with Increased Capacitance The method, wherein the second conductive layer and the third conductive layer 4 of polysilicon, respectively, of the doped polycrystalline silicon or other conductive material. 6. The method for manufacturing a trench variable capacitor with an increased capacitance value as described in item 3 of the scope of the patent application, wherein the collar-shaped insulating layer spacer comprises a 7-shell oxide layer. 7 · The method for manufacturing a trench plastic capacitor with increased capacitance as described in item 1 of the scope of patent application, further comprising the following steps: before forming the above trench on the substrate, first forming a first liner stone The underlying cushion layer is on the surface of the substrate: the first formed groove is partially removed and exposed on the exposed surface of the first cushion layer in the substrate, penetrating the first liner layer and the second cushion layer, And the first pads' exposed surfaces on both sides of the first pad layer are exposed; and 0548-9673TWf (nl): 91276; Phoelip.ptd page 23 Application scope of patent —— The above-mentioned first liner layer and the above-mentioned and a brother-dielectric layer are used to fill the openings. Forming-opening, electricity = the capacitance of the booster capacitor as described in item 1 of the patent scope, the electric thin layer, the above-mentioned trench capacitor structure, a capacitor dielectric layer, and a first conductive layer . The system includes a guideline. For example, the 8th in the scope of the patent application + the t capacitor of the $ capacitor. The groove of the capacitor value added by the office _ $ 丨 the Lin Yue! Where the first-conductive layer is 葙It is called crystalline silicon or other conductive materials. It is hard-crystal silicon and doped with φ6 1 ^ · Adding the thunderbolt valley device as described in item 1 of the scope of patent application; The method of punishment and secretion, wherein the step of forming the grooved capacitor-stained-slotted bottle 1 grooves includes: constructing the above-mentioned open conductive thin layer in the bottle-shaped grooves, and the above-mentioned lightning-conducting continuous mammoth paper surface溥 layer constitutes the lower area of a bottle-shaped trench · "formation-capacitor dielectric layer on the above-mentioned conductive thin layer 5-Λ a conductive layer fills the above-mentioned bottle-shaped portion i; and Lei Er • The increased capacitance 2 described in item 8 of the scope of the patent application. The manufacturing method of "electricity", wherein the above-mentioned guide = trench type (hem 1-sdhpr · i two thousand ball type stone 々, pner iCai grain, HSG). On the evening, the grain type electric device is as follows: ^ in the bottle-shaped groove i; :: package; the above-mentioned hemisphere type is formed in the upper groove described and formed-an amorphous silicon layer on the substrate surface in the bottle-shaped groove · On; so that the above bottle 0548-9673TWf (nl); 91276; Phoelip.ptd p.24 The semi-spherical granulation process is performed on the above amorphous silicon layer, 591792 6. The amorphous silicon layer in the patent-type trench forms a hemispherical plastic silicon crystal Granular layer 13. The method for manufacturing a trench-type capacitor with increased capacitance as described in item 12 of the scope of the patent application, further comprising the step of performing a gas phase doping process on the hemispherical silicon grain layer. D14. The method for manufacturing a trench-type capacitor with an increased capacitance value as described in item 7 of the scope of the patent application, wherein the first pad layer is made of oxide. 1 5 · The method for manufacturing a trench-type capacitor with increased capacitance as described in item 7 of the scope of the patent application, wherein the second pad layer is made of a nitride. 1 6. The method for manufacturing a trench capacitor with an increased capacitance value as described in item 1 of the scope of the patent application, wherein the glass doped layer is selected from the group consisting of freely doped side phosphorous silicon glass (BPSG) and doped arsenic silicon. Glass (AsSG), doped glass (PSG) and boron-doped silica glass (BsG). 1 7 · The method for manufacturing a trench-type capacitor with increased capacitance as described in item 7 of the scope of the patent application, wherein the above-mentioned / dielectric layer is a nitride. 1 8 · The method for manufacturing a trench-type capacitor with an increased capacitance as described in item 1 of the scope of the patent application, wherein the spacer layer is a nitride spacer layer. 1 9 · The method for manufacturing a trench-type capacitor with increased capacitance as described in item 1 of the scope of patent application, wherein the method of etching the semiconductor substrate at the bottom of the trench to form a bottle-shaped trench is performed by the second The spacer layer and the spacer of the collar-shaped first spacer layer are etching masks, and the semiconductor substrate at the bottom of the trench is etched with a dilute ammonia solution or acid as an etchant to form a bottle. 0548-9673TWf (nl); 91276; Phoelip.ptd Page 25 ----- ^ ί / 92 VI. Patent Application Type Groove. κ 2 0 · The manufacturing method of a trench-type device for increasing capacitance as described in item 1 of the scope of the patent application, wherein the semiconductor substrate at the bottom of the trench is etched, and the method of forming a bottle-shaped trench includes: ^ Performing an oxidation spot on the semiconductor substrate at the bottom of the trench to partially vaporize the exposed doped region to form a doped oxide region; and a gap between the second pad layer and the collar-shaped first spacer layer The wall is an etched mask to remove the doped oxide region to form a bottle-shaped trench. I 2 1 • The manufacturing method of a trench capacitor with an increased capacitance value as described in item 20 of the scope of the patent application, wherein the doped oxide region is etched by hydrofluoric acid (HF). 2 2. The manufacturing method of the electric valley in the trench for increasing capacitance as described in item 20 of the scope of patent application, wherein the above-mentioned oxidation treatment is rapid thermal oxidation treatment (RTO). ^ > 2 3 · The method for manufacturing a trench-type capacitor with an increased capacitance value as described in item 1 of the patent application range, wherein the filling layer is a polycrystalline silicon layer. 24 · —A method for manufacturing a trench capacitor with increased capacitance, including the following steps: sequentially forming a first oxide layer and a first nitride layer on a surface of a substrate;-forming a trench on the substrate In the first oxide layer, the first nitride layer is penetrated, the first oxygen layer is exposed, and the first oxide layer on both sides of the exposed first oxide layer is removed. Between the layer and the above-mentioned substrate 0548-9673TWf (nl); 91276; Phoelip.ptd page 26 / vz =, patent application scope second nitride layer fills the first opening; a compliance with a broken portion having a first predetermined height is formed in the groove In the upper part, the bottom of the trench is in the above trench; the field is configured to form a second opening in the layer and the second opening ^ 'so that the polycrystalline silicon doped plutonium doped layer conforms in the above trench. A nitride spacer layer is formed in a household, the glass doping >, μ, + ,, _, the first nitride layer, the upper polycrystalline stone layer, and the above-mentioned glass doped layer. It is mixed to form a buried plate; the crop expands outwards to the above-mentioned substrate: ί: the first nitride layer and the above-mentioned nitrogen on the polycrystalline silicon layer are finished: i divided:: t a collar-shaped nitrogen The spacer wall is on the side wall of the trench; Qian Qi: ΐ ΐ set the crystal stone layer and the above-mentioned glass doped layer; forming the above-mentioned substrate to form a bottle-shaped groove; / NEC's container structure on the bottle In the above-mentioned groove: i :: i: Xi layer on the surface of the substrate in the above-mentioned bottle groove, which The Xi layer constitutes the lower area of a bottle-shaped groove; the in! Layer in the groove is subjected to a semi-spherical granulation process, so that the above-mentioned bottle = amorphous stone layer is formed into a hemisphere-shaped stone layer; The dielectric layer of the device is on the surface of the above-mentioned hemispherical stone grain layer. The conductive layer fills the lower area of the bottle-shaped trench. Interstitial soil: the original position of the upper collar-shaped compound spacer; the area surrounded by the above-mentioned oxide spacers forms a second guide. Page 27 0548-9673TWf (nl); 91276; Phoelip.ptd 591792 6. A patented electrical layer; and forming a third conductive layer on the collar insulating layer spacer and the second conductive layer. 2 5 · The method for manufacturing a trench-type f container with an increased capacitance value as described in item 24 of the scope of patent application, wherein a third conductive layer is formed on the collar-shaped insulation, the $ -layer gap wall, and the second After the step on the conductive layer, the method further includes performing a planarization process on the surface of the third conductive layer. • "2 6 · The method for manufacturing a trench capacitor with an increased capacitance value as described in item 25 of the scope of patent application, wherein the planarization process is a chemical polishing method. I "2J. The manufacturing method of increasing the capacitance value of the trench type as described in Item 24 of the scope of the patent application, wherein the first conductive layer, the second conductive layer, and the third conductive layer are polycrystalline silicon, respectively. Doped compound silicon material. To conductive 28. As described in item 24 of the scope of the patent application, to increase the capacitance value, the method of manufacturing the container further includes the above-mentioned hemispherical silicon grain layer. Gas phase doping treatment step. 29. The method for manufacturing a capacitor with increased capacitance as described in item 24 of the scope of the patent application, wherein the glass doped layer is selected from the group consisting of borosilicate silicon glass (BPSG) and arsenic silicon doped glass (AsSG) , Doped glass (PSG) and boron-doped silica glass (BSG). Niu 30. According to the method for manufacturing a capacitor with an increased capacitance value as described in item 24 of the scope of the patent application, the above method is to etch the semiconductor substrate at the bottom of the trench to form a bottle-shaped trench. Second pad ^ and πΐ792 == 形 第 —The spacer of the spacer layer is an etching mask, and the semiconductor substrate at the bottom of the trench is etched by using a dilute ammonia solution < or & L as a coining agent to form a bottle-shaped trench. 4 ^ 1 · The manufacturing method for the galvanic combination of the trench f with an increased capacitance value as described in item 30 of the scope of the patent application, wherein the concentration of the above-mentioned diluted ammonia is ammonia water. The ratio of water is 1: 5 to 1: Between 50 and 50. q " 3 2 · The manufacturing method of a trench ^ capacitor with an increased capacitance value as described in item 30 of the patent application, wherein the acid is fluorinated europium (耵) / ethylene oxide (EG "), Cutie t ; Release hydrogen fluoride (DHF) or buffered hydrogen fluoride (BHF). The manufacturing method of the trench 1 for increasing the capacitance value as described in the scope of the patent application No. 24, wherein the method of etching the semiconductor substrate at the bottom of the trench to form a bottle-shaped trench includes: & The semiconductor substrate at the bottom of the groove is subjected to an oxidation treatment to form a doped oxide region with the doped region exited by the part bj bj; and the remaining rows of the second spacer layer and the collar-shaped first spacer layer spacer wall. D to form a bottle-shaped trench by removing the doped oxide region. ^ t Ϊr, ® ^ 3 a ^ ^ ^^ ^ ^ #: Valley. . The fabrication method &, which is doped with oxidized regions by hydrofluoromanganese (the doped oxide region. 爿 乂 etch__ 35. The method for manufacturing a capacitor and a capacitor according to item 33 of the scope of the patent application, wherein the above-mentioned oxidation treatment is a rapid core treatment (RTO).丨, hot milk