TW591377B - Dual basic input/output system for a computer cross-reference to related applications - Google Patents

Abstract

A computer system has a central processing unit (CPU), and a chipset for supporting the CPU, and a selectable BIOS system. The chipset has a first general purpose input/output (GPIO) register. The selectable BIOS includes a primary and secondary BIOS programs, a timer circuit for generating a delay signal after power-on of the computer system, and a BIOS switching circuit. The primary BIOS program has confirmation code for generating a confirmation signal on the first GPIO register. The BIOS switching circuit shadows the primary or secondary BIOS program into a predetermined address space of the CPU according to the confirmation signal and the delay signal. While the primary BIOS program is shadowed, if the BIOS switching circuit receives the timer delay signal before receiving the BIOS confirmation signal, then the BIOS switching circuit causes the CPU to be reset and shadows the secondary BIOS program.

Description

591377 V. Description of the Invention (l) '------ Field of Invention The present invention provides a basic input / output system (BIOS) architecture of a computer system, especially a package Slc for users to choose. Computer system with basic I / O system programs. Several background descriptions. At present, most computer systems use a central processor unit (CPU) to run a non-volatile memory (non- volat i le memoey) to complete the boot-up action. The basic I / O system program includes, in addition to the basic function support of the driver and operating system of the components in the electrical system, a power on self-test (POST) program and a boot loader program ( bootstrap program). The p0sT program is used to ensure that the basic components in the computer system can work correctly. After executing the POST program, the BIOS program then executes the boot loader. The purpose of running the boot loader is to The supervisory program of the operating system is loaded into the main memory from the disk drive, that is, the startup code is loaded into the main memory to start the operating system. The above-mentioned procedure is the booting procedure of the traditional computer system. In recent years, the new computer system has gradually transferred the B I 0S program to flash read only memory (flash read only memory, flash

Page 5 591377

ROM), the advantage of doing so is that the flash read-only memory BI 0S program is directly reprogrammed, so it can save the user the trouble of jealousy. The program update process is basically similar to the two software Update procedure. However, it makes a lot of users feel 懊 a = In the BIOS update process, if the BI0s is improper] = 疋 = The improperly updated BIOS will lead to the computer system crashing. = The user has to obediently perform the troublesome process of performing a hard ^ replacement on the flash read-only memory. '' In order to solve the above problems, many researchers have proposed many solutions, such as & 6311 ^ 〇 ~ 31 ^ et al.

The invention of Including Corrupt Flash ROM Recovery, which is listed as one of the references by the present invention. The invention of Bealkowski et al. Provides a computer system including a second non-volatile memory element. It can be an erasable and programmable read only memory (EPROM), which is used to store an auxiliary backup BIO S program, which is stored in the flash read-only memory of the computer system. When a problem occurs with the main BI 0S program, the auxiliary backup BI 0S program will replace the main BI 0S program loaded into the address space in the CPU of the computer system, and then execute the auxiliary backup BI 0S program. But the invention of Bealkowski et al. Does not allow users to choose freely

Fifth, the description of the invention (3) The main BIOS program or the address space in the CPU used by the CPU is empty / backup BI 0S program is loaded into the computer system BI 0S program is loaded into the boot process first, the The invention still uses this main processing mode. In the ^ ^ program, in fact, not all cases are suitable for the simple hard system. In the case, because Beal kowski and others tuples, so clever: ":" " ⑽ One of the main BIOS programs must be-two ^ bit, and it is correct, it does not represent the BIOS program ^ ^ = King, so that the main line may be incomplete. Boot the computer. ^ Computer The implementation of the address space in the CPU of the system will of course still lead to the computer system tank, and it will also require tedious hardware maintenance procedures. Summary of the invention Cocoa core, first of all, review and put in place, the second one should be completed, and the central government should provide a solution to the veto. In this film, the content is determined by the basic crystals, and the system is set up. Questions can be selected to access the system and selected directly out of the system. The selector includes input and input for the brain. Bao Dian uses the source of the book to organize the base input into the central tablet. The formula can be based on a basic system, a system with a few cores, and it must be linked to Checking the main input and output of the electrical packager to complete the unified export of the system does not need to be entered in the department. You can enter and exit the brain to send the code to the basic code. It should be clear that this should be avoided. The central aid due to the election can choose the main election round. This decision is for the use of this code.

Page 7 591377 V. Description of the invention (4) The first general-purpose input / output register stylized by the device. The optional basic input / output system of the present invention includes a main basic input / output system program which can be executed by the central processing unit and includes a confirmation code, which is used to generate a first universal input / output stored in the first universal input / output system. Acknowledge signal from the register. The optional basic input / output system further includes a pair of basic input / output system programs which can be executed by the central processing unit and a sequential circuit which is used to generate a delay after the computer system is turned on for a predetermined time A signal and a BI 0S switching circuit for mapping the main basic input / output system program or the secondary basic input / output system program to a predetermined address space in the central processing unit according to the confirmation signal and the delayed signal, Wherein, when the main basic input / output system program is mapped to the predetermined address space, if the BI 0S switching circuit receives the delayed signal before receiving the confirmation signal, the BI 0S switching circuit will cause the central processing unit to Perform a first restart operation, and map the auxiliary basic input / output system program to the predetermined address space, so that the central processing unit can execute the auxiliary basic input / output after the first restart operation System program. Detailed description of the invention Please refer to FIG. 1A. FIG. 1A is a schematic block diagram of a computer system 10 according to one embodiment of the present invention. FIG. 1A does not show all the components of the computer system 10, but only the components related to the present invention. The computer system 10 includes a central processing unit (CPU) 20, an address decoder 3 0 connected to the CPU 20, a memory 40, and a chipset.

591377 V. Description of the invention (5) 60, and a reset circuit 70. The CPU address line 23 transmits a bit address to the address decoder 30, and the address decoder 30 sets the output address of the memory 40 through the bus address line 34 according to the address decoding. Then memory module 40 will transfer the memory data to CPU via data bus 42 according to the memory address set by bus address line 34. The system configuration processing mode described above is basically similar to the conventional technology 'That is, the address decoder 30 is used to map the data of different configuration areas in the memory 40 to the address space in the CPU 20. Especially in the restart operation, when the CPU 20 receives a reset signal 72 from the reset circuit 70, the CPU 20 will try to retrieve its first address according to the starting address of c P u set by the CPU address line 2 3 A work instruction. In a typical 32-bit CPU, the starting address is usually a hexadecimal OxFFFFFFFO, and the starting address is usually a CPU jump instruction. The jump instruction will cause the CPU 20 to follow the CPU address. A predetermined CPU address set on line 23 starts fetching instructions. The predetermined CPU address is determined by the manufacturer of the computer system 10, and the CPU jump instruction is placed in the non-volatile memory 40. In the memory area. Generally, the BIOS program includes the CPU jump instruction. For the purposes of the present invention, the last instruction of the main BIOS program 40p and the last instruction of the sub BIOS program 40s are the CPU jump instructions. With the aid of the information of the predetermined address configuration, the address decoder 3 0 can make the CPU 2 0 choose the main BI OS program 4 0 p or choose the subordinate according to the MH IN IT and BH IN IT lines received from the BIOS switching circuit 50. The BI OS program 4 0 s performs data acquisition. When the M Η I N I T is at a high level and the B Η I N I T is at a low level, the bit

591377 V. Description of the invention (6) The address decoder 30 will cause the main BIOS program 4Op to be mapped to the address space in the predetermined CPU. When the MIMO INIT is low and the BH INIT is high, the address is decoded. The device 30 maps the sub-BIOS program 40s to the address space in the predetermined CPU. For example, according to the CPU jump instruction, if the predetermined CPU address set by the CPU address line 23 is 0x0 0 0F 0 0 0 0, the address decoder 3 4 can be set to make the BIOS program 4 Op or 4 Os. The start instruction is mapped to address 0 X 0 0 0 F 0 0 0 0 according to the two MH IN IT and B Η INIT lines. The execution method of the above B I 0 S mapping function is basically similar to the conventional technique. Chip group 60 is used to provide the bus logic support required by CPU 20. In many designs, address decoder 30 can be a sub-component within chipset β 0, and chipset 60 basically contains a plurality of general purpose A general purpose input / output (GPI0) register. The plurality of GPI0 registers can be programmed by the CPU 20 to transmit the relevant signal values in the computer system 10 to the relevant hardware components. In a preferred embodiment of the present invention, the chipset 60 includes two GPI0 registers: a first GPI0 register gpi (h, which is used to send a confirmation signal 61 to the BIOS switching circuit 50; and A second (^ 10 temporary register GP ^) 2 is used to send a selection signal 62 to bi0 ^ for the circuit 50. The f circuit 80 is used after the computer system 10 is turned on for a predetermined delay time. ， Transferring a delay signal 85 to BI0S switching distance is only used to ensure that the CPU 20 is right after power on ^ ^

.., Π βπ ^ ^ Wind silly has enough time to execute the confirmation code 40 5 in the main β10S program 40ρ, so the computer is ready for testing, nl ^ 4, When setting the length of the predetermined delay time, the designer: at t From the loading of the main BIOS program 40p to the execution of the ^ text to the CPU 20 = speed machine confirmation code 4 0 5

Page 10 591377 V. Description of the invention (7) The intervention execution code that the CPU 2 0 may receive. Generally speaking, the delay time of most computer systems 10 after the computer power is stable is between half a second and one second. between. Figure 1B is a schematic circuit diagram of a sequential circuit 80. As is common in conventional technology, the delay signal line 85 will turn to Micro Motion after a delay time interval determined by the resistor 8 2 and the capacitor 8 4 after the power is turned on. Bit. The BI OS switching circuit 5 is designed to keep the MU INIT signal high and the MINIT signal low after the computer system is turned on. Therefore, the main BIOS program 40P can be mapped to the predetermined CPu 20 The address space is then executed by the CPU 20. Sequential circuit 80 is designed to keep the delay signal 8 5 at a low level within the predetermined delay time after turning on the I machine, and then turn to a high level, and send a delay signal 85 to the B I 0S switching circuit 5. The chipset 60 is designed to ensure that the confirmation signal 6 keeps the S low level after the computer system is turned on. That is, the initial state of the confirmation signal 61 is at the low level. When CPU 2 0 executes the main BIOS program 4Op, the confirmation in the main BIOS program 4Op ^ 4 0 5 will set the G P I 01 register in chipset 60, which will be used to turn the confirmation signal 6 1 to the south level. 'And send a confirmation signal 61 to the BIOS switching circuit 5O. After the computer system 10 is turned on, if the delay signal 8 5 is received by the B I 0 S switching circuit 50 before the confirmation signal 6 1, the B I 0 S switching circuit 50 will set the μ Η I Ν I Τ setting疋 Set the B 位 I Ν Γ to the high level for the low level, and send a reset signal 57 to the reset circuit 70 to reset the CPU 20. Under the condition that the M Η IN IT is low and the B Η I Ν IT is high, the address decoder 30 maps the sub-B I 0 S program 40s into the predetermined address space of the CPU 20, After that, the reset line 72 is no longer active, and the CPU 2 0 starts executing the sub-B I 0 S program 4 0 s. But as

591377 $, Description of the invention (8) If the confirmation signal 6 1 has been received by the BI 0 S switching circuit 50 before the delayed signal 8 5, then the BI 0S switching circuit 5 0 will ignore the effect of the delayed signal 85. , CPU 20 does not need to perform the reset action. Figure 2 shows the flowchart of the BIOS switching circuit 50 operating procedure 1 00. The flowchart 1 00 includes the following detailed working steps: Step 1 01: All such signal lines are set to the default values when the power is turned on. That is, the delay signal line 85 is set to the low level, the GP I 〇1 register is set to make the confirmation signal line 61 to the low level, and the GP I 02 register is set to make the selection signal line 6 2 is to select the main BIOS program 4 Op signal value, and then set the MHIN IT to a high level and the BH INIT to a low level, so that the main BIOS program 4Op can be mapped to the predetermined position of the CPU 20 Address space. Step 102: After the predetermined delay time elapses, the sequential circuit § 〇 will turn the delay signal line 85 to the normal level, and then send a delay signal 8 $ to the BI 0 S switching circuit 50, if it works at this time Normally, the main β I 0 S program 4 0 p will have enough time to execute the confirmation code 4 0 5 to turn the disc recognition signal line 6 1 to a high level, and then send the confirmation signal 6 1 to the B I 0 S switching circuit 5 0. However, if the main β I 〇§ Formula 4 〇ρ is incomplete, the confirmation code 405 will not be executed, and the confirmation signal line 6 1 will remain at a low level, and no confirmation signal 6 1 will be sent to Β I 0S switching circuit 5 〇. A detailed description is provided in the description of the conditions for subsequent virtual selection to switch to the sub-BIOS program 40s. Yiding said another

591377 V. Description of the invention (9) Step 103: If it is confirmed that the signal 61 is received before the delay signal 85, then continue to step 104, otherwise skip to step 107. Step 1 0 4 ·· Confirm that the mapped B I 〇 S program 40 p or 40 s unit is 'so it should remain in the mapped address space of the mapped CPU 20' and the delay signal can be ignored. Step 1 0 5: Check whether the selection signal 6 2 is changed. ′ If there is a change, continue to step 10 6, otherwise return to step 104.

Step 106: If the selected signal 6 2 indicates that the main BI OS program 4 0ρ is selected, then set ΜΗ I Ν I Τ to a high level and set ΒΗ I Ν I Τ to a low level, otherwise M Η I Ν I Τ is set to a low level and B Η I Ν I Τ is set to a high level. The reset signal line 5 7 is used to request the reset circuit 70 to reset the CPU 20. The reset action does not affect the value of the selected signal line 62, the selected main BI OS program 4 0 p or the sub BI OS The program 40 s is therefore mapped into the predetermined address space of the CPU 20 according to the value of the selected signal line 62, and then the selected BI OS program is executed with the CPU reset signal line 72 no longer functioning, and then jumps back Go to step 1 0 4. Step 1 0 7: If it is confirmed that the signal 6 1 is not delayed before the delayed signal 8 5

The BIOS switching circuit 50 receives and the main BIOS program 4Op is incomplete, then ignores the selection line 6 2 and sets MU INIT to a low level and BH INIT to a high level to map the sub BI 0S program 4 〇s To the predetermined address space of the CPU 20, and then use the reset signal line 57 to request the reset circuit 70 to reset the CPU 20. When the mapping process of the sub BIOS program 40s is completed, the CPU 20 is in

Page 13 591377 V. Description of the Invention (ίο) After the reset action, the sub-B I 0 S program is executed for 4 0 s. The procedure of step 106 is to allow the computer system to execute the main b 丨 〇s program 4 Op and the sub BIOS program 40s. This option can be selected by CPU 20 using the GP I 0 2 register to select the signal line 6 The setting of 2 is completed, so the computer system 10 enables a user-selectable B can mode. In step 102, the work of the timing circuit 80 and the BIOs switching circuit 50 is to ensure that when the main BIOS program 40p is incomplete, the computer system 10 can automatically switch to the sub BIOS program 40s, because when the main BIOS program When the program 4 Op is incomplete and is mapped to the predetermined address space of the CPU 20, the CPU 20 will be lacking due to illegal instructions such as infinite lGQP and the machine will have no day-to-day work. At this time, the confirmation code 4 05 cannot be executed, so after this predetermined delay time, the 'computer system 10' will also switch to the sub-Bos program 4 0s. Memory 40 contains both volatile and non-volatile memory. The non-volatile memory in the bean can be flash read-only memory, which is used to store the main BIOS program 40ρ, δ 彳 BIOS program 40s, and plural A Bi0s installation parameter 40v 'These BIOS installation parameters 40 are used to store machine-related information, such as hard disk parameters, date and time data, and bus parameters, etc., and are the main BI 0S program 4 0 p Shared with the sub BI 0S program 40 s. However, it can also be replaced by another possible design, that is, there are two sets of BI0S security parameters, which can be stored in one or more flash read-only memories, one of which is a set of BIOS installation parameters used by the main BIOS program 40p , And the other set of bios installation parameters is specifically for the secondary β I 〇S program 4 0 s, so the main b I 0S program 4 0 p and

Page 14 591377 V. Description of the invention (11) The execution function of the auxiliary B I 0S program 40 s can be completely independent, so the computer system 10 can enable two different machine operation modes. Basically, the main BI 0 S program 4 Ο p and the sub BI 0S program 4 0 s have the codes of the conventional BI 0S program functions, such as the power-on self test (ρ 〇wer-ο nse 1 f -1 est, P 0 ST) code, low-level component support code, boot load code, etc. In addition, the main BI 0S program 4 Ο ρ also includes a confirmation code 4 0 5, a check code 4 0 4, and a selection code 4 0 3 etc. As mentioned above, the execution of the instructions in the confirmation code 405 by the CPU 20 will program the GP 101 register to send a confirmation signal 61 to the bios switching circuit 5. In short, the most important function of executing the confirmation code 4 0 5 is to confirm that the main B I 0 S program 4 0 ρ can work normally, that is, to confirm that the computer system 1 〇 does not need to switch to the sub β I 〇S program 4 0 s. As for the instructions in the CPU 2 0 execution check code 4 04, it is used to check the existence and completeness of the secondary β I 0S program 40 s. The check process f is mainly to perform a check and check of the secondary BIOS program 40s. (Checksum) count ^ and compare 4 check and value etc. with the sign value (signature) 404s = No, etc. The instruction in the selection code 40 3 is used to enable the CPU 20 to use ^ to set one of the parameters 40b in the BIOS installation parameter 40 v, and to set the GP 102 register according to the f-number 40b, so the selection code 4〇 The main function of 3 is to provide the user with the choice of the main B I 0S program 4 0 ρ and the sub B I 0S program 4 0 s. Refer to Figure 3. Figure 3 shows a flowchart of the operation procedure of the first embodiment of the basic input / output system m 6 human selection code 4 0 3 according to the present invention. The process group includes the following detailed working steps: Step 2 0 1 β I 〇s formula 4 〇ρ maps to the predetermined address space of c ρ υ 2 〇

591377

Then, the CPU 20 executes the main BIOS program 4Op. At this time, the BIOS program 4Op will execute many basic startup procedures, such as the f test program, the installation program, etc. All of these processes must be less than the self-executing time 70 The pre-set time delay is set. Step 2 0 2: The CPU 20 executes the confirmation code 4 0 5 to program the gp 1〇1 register r to send a confirmation signal 61 to the BIOS switching circuit 50. Therefore, the situation in step 107 of Figure 2 occurs. In the procedure of step 2 〇1, if the main BIOS program 4Op has detected that an internal error has occurred, it is better not to perform this step 2 〇2 first, but stay at step 2 0 1 'with a circle ^ and wait for β I 〇 § Switching circuit 5 〇 Map the sub-BIOS program 40s to the predetermined address of the CPU 20. Step 203: Check the selection parameter 4 〇b in the BIOS installation parameter 40 v. If the selection parameter 4 0b shows that it needs to switch to the sub-b 〇s program 4 〇s, then continue to step 204, otherwise skip to step 207. Step 2 04: In the case where it is necessary to switch to the auxiliary BIOS program 40, make sure that the BIOS program 40s exists, and check and calculate the auxiliary Mos program 40, to ensure that the checksum value is equal to 圮The number value is 404s. It is important to note that the main BI0s program 4〇σρ must be designed to know that the sub-BIOS program 40S can be found in the CPU address space, and this is also one of the manufacturer's design techniques — 〇 Step 2 0 5: If Result If the secondary BIOS program 40s exists and passes the verification and numerical check tests, then proceed to step 2 06; otherwise, the main B 丨 〇§ process

591377 V. Description of the invention (13) Equation 4 0 p must continue to be executed and skip to step 207.

Step 2 0 6: Set the value of GPI 0 2 so that the value of the selected signal line 6 2 indicates that the sub-BI 0S program 4 0 s is to be executed. This will change the value of the selected signal 6 2 and start the BI 0S switching circuit 5 Step 1 of 0 0 resets CPU 20, the sub-BIOS program 40s is therefore mapped to the predetermined address space of CPU 2 0, and after the GPI 0 2 register is set appropriately, it waits for the reset procedure Its implementation. Step 2 0 7: In the case that the main B I 0S program 4 p must continue to be executed, continue the normal B I 0S # operation until the execution of the startup load code of the operating system is finished. Most BI 0S programs have software installation features, that is, in this POjT program, users can be enabled to change the BIOS installation value 40v and set the BIOS configuration 'main BI OS program 4 0 p and sub BI OS program 4 0 s has this kind of setting function, that is, the function of providing the user to set and store the selection parameter 40b. μ ί Another flowchart of the switching operation procedure for executing the main BI0S program 40p and the sub BI0S program 40s f 丄 ding, and the selection code 4 0 3, the flowchart contains the following detailed work steps:

Step 301 · Map the main BIOS program 4Op to the predetermined address space of the CPU 2 ′, and then the CPU 20 executes the main BIOS program 4〇p. At this time, the main f% formula 4 ο P will perform many basic startup procedures, such as ^, Trial procedures, installation procedures, etc., the order time of all these procedures must be less than the predetermined delay set by the sequential circuit 7 〇

Page 17 591377 V. Description of the invention (14) Time interval. Step 302: Check the selection parameter 40b in the BIOS installation parameter 40v. If the selection parameter 40b shows that it is necessary to switch to the secondary BiOS program 40s, skip to step 305, otherwise continue to step 303. Step 3 Ο 4 Step 3 Ο 5 Step 3 0 3: In the case where the main BI 0 S program 4 0 p needs to be continuously executed, the CPU 2 0 executes the confirmation code 40 5 to program the Gpi〇1 register to send out. The acknowledgment signal 61 goes to the BIOS switching circuit 50, so; ^ The situation in step 107 of Figure 2 is avoided. Continue the normal BIOS # operation until the execution of the startup load code execution operation of the operating system is finished. In the case that it is necessary to switch to the subsidiary BI0S program 40s, ensure that the subsidiary BI 0S program 40s does exist, and perform a calculation on the subsidiary B 丨 〇 雄 7 to ensure that the checksum value is equal to the value of Lu Ji number 40. 4 s. Step 30 6: ^ The sub BI0S program 40 蜣 exists and passes the check code 4 04 and the numerical check test, then continue to execute the step otherwise 'The main BI0S program 40〇 must continue to be checked; ^ 仃, and skip to step 3 0 3. Step 307: Keep the loop waiting state until receiving the second sequence from the sequential circuit 80 and ifsf ϊ 85, at this time the confirmation code 40 5 will not be executed, and the BIOS switching circuit 50 will execute the sub-BIOS program 40s and will be loaded. Enter and execute. That is to say, it is not static in the various description steps of the present invention.

591377

For example, under some special hardware configurations, it is possible to directly program the reset circuit 7 0 to perform the reset action of the CPU 2 0 by using the selection code 403. In this case, When the selection signal 62 is changed, the M0s switching ^ ^ will not generate a reset signal 57 but only wait for the selection code 403 to perform the necessary reset action. As long as the preferred embodiment of the present invention is made a little more, the computer system 10 has functions that can support more and allow, and the user k selects special functions. Under this design, it can further cause the moon b BlfS switching The circuit 50 resets the sequence circuit 80 so that the delay signal 8 & is received after all the reset actions of the executor are received, rather than being received in one ^. In this processing mode, each BI0Sa formula is raised = i = t confirmation code, and the BIOS switching circuit 50 can verify between all 3305 programs until a BI0s program is successfully selected by the BI0s switching circuit 50. The invention can also provide an incomplete BI0 ^ style restoration. Ί Say, if the execution code 404 of the main BIOS program 40p is issued 404 1 program 4 0 _ is incomplete, the check code 4 0 4 can also be made Complete function = BI0S program 4〇p overwrites the human assistant program 40s. At this time, f = $ 2 BI0S program 4s is exactly the same. However, as mentioned earlier, you have a separate set of BIOS installation parameters 40v, so you can still use the same code as the sub-BI0 ^ 4. Here. There are functions that allow the user to provide two independent machine installation states = —, the program of the ancient master B 1 0 S program 4 〇p overwrites the sub BI 0 S program 4 0 s is not a direct copy to complete, The overwrite operation may also be based on

Page 19 591377 V. Description of the invention (16) Overwrite status of many indicators, CPU 20 jump instruction, and BI 0 S installation parameter 40 v access to determine relocation '. However, this overwrite operation is known The scope of technology is not repeated here. In a simple embodiment, suppose a simple copy overwrite operation is performed, so that the main BI 0s program 4 0p is overwritten into the memory configuration area of the sub BI OS program 4 0 s, and a piece of scattered memory is used. The space allocation table or the allocation algorithm can change the predetermined allocation space of the sub BI os program 40 s, and the function of the sub BIOS program 40S can be exactly the same as the main BIOS program 40p. Similarly, the secondary BIOS program 40s can also be provided with a check code similar to the main BI 0 S program 4 0 p. This check code can be used to confirm that the main BI 0S program 4 0p is complete, and when any b I 〇s When the program is detected as incomplete, the check code can also be used to correct the incomplete BI 0g program. As described above, compared with the conventional technology, the present invention provides a sequential circuit and a BI 0S switching circuit, which are used to select an appropriate and complete BIOS program from a plurality of BIOS programs mapped to the CPU of a computer system. Within the predetermined address space. When a mapped BI 0s program cannot work normally, it will not send a confirmation signal to the BI 0s switching circuit, so when the b I 0S switching circuit receives a delayed signal from the sequential circuit, it will Map another BIOS program to replace the currently incomplete BI0S program. In addition, by using the selection parameters in the non-volatile memory, the user can choose the BIOS program to be mapped and ensure that at least one βIOs program can be successfully loaded to start the computer system. In addition, at least one B I 0S program provides a check code, which can be used to check the integrity of other BI 0s programs, so it is possible to avoid loading incomplete Bi 0s programs.

Page 20 591377 V. Description of the invention (17) The above description is only a preferred embodiment of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent. Page 21 11 591377 Brief description of the drawings Brief description of the drawings: Figure 1A is a block diagram of a computer system according to the present invention. Figure 1B is a circuit diagram of a sequential circuit. Fig. 2 is a flowchart of a switching circuit of a basic input / output system according to one of the present invention. Fig. 3 is a flowchart of a first embodiment of the BIOS selection code of the basic input / output system according to the present invention. FIG. 4 is a flowchart of a second embodiment of the BIOS selection code of the basic input / output system according to the present invention. Explanation of Symbols of the Drawings 10 Computer System 20 Central Processing Unit (CPU) 23 CPU Address Line 30 Address Decoder 34 Bus Address Line 40 Speech Memory 40b Selection Parameters 40p Main Basic I / O System 40v Basic I / O System Installation Parameter 40s Sub basic I / O system 42 Data bus 50 Basic I / O system switching circuit 57 Reset signal line 60 Chipset 61 Confirm signal line 62 Select signal line 70 Reset circuit 72 Reset signal line 80 Timing circuit 82 Resistance

Page 22 591377 Simple description of the diagram 84 Capacitor 85 Delay signal line 403 Selection code 404 Check code 404s Mark value 405 Confirmation code 1 page 23

Claims (1)

591377 1 · A selectable basic input / output system (BIOS) for a computer system. The computer system includes: · ,,,,, and β and a central processing unit. unit CPU); a chipset (chipset) is used to support the central processing unit, the Α Japanese chipset includes a first general purpose i npu t / output, GPIO) register; The optional basic I / O system includes: ° 'A main basic I / O system program that can be used by the CPU and includes a confirmation code, which is used to generate a Confirmation signals stored in the ^ line universal input / output register; a pair of basic input / output system programs that can be executed by the central processing unit; a sequential circuit for generating a delayed signal when the computer system is turned on for a predetermined time ; And ^ a B I 0S switching circuit, which is used to shoot the main basic input / output system program or the secondary basic input / output system program according to the confirmation signal and the delay ^ = to the central processing unit A predetermined address space; if x, when the main basic input / output system program is mapped into the predetermined address space, if the β I 0S switching circuit before receiving the confirmation signal = receives the delayed signal, Then, the B0S switching circuit will cause the central processing line to perform a first restart operation, and map the pair of basic output into a system program to the predetermined address space, so that the central processing unit can perform J ^ 591377 6. Scope of patent application The first basic input / output system program is executed after the first restart. 2. If the optional basic input / output system of the first patent application scope, wherein if the BI 0S switching circuit receives the delayed signal after receiving the confirmation signal, the BI 0S switching circuit will not make the central processing The device performs the first restarting action. 3. For example, the optional basic input / output system of the scope of patent application, wherein the time point when the delayed signal is transmitted to the BI 0S switching circuit is appropriately set so that the central processor can transmit the delayed signal. The confirmation code is executed before the BI 0S switching circuit. 4. If the optional basic input / output system of item 3 of the patent application scope, wherein the main basic input / output system program further includes a check code, the central processing unit may execute the check code to check the sub basic output. The integrity of the data entered into the system program. 5. If the optional basic input / output system of item 4 of the patent application scope, the main basic input / output system program also contains a selection code for performing the following steps: call the check code to determine the secondary basic output Whether the input system program exists and is complete; if the pair of basic input / output system programs exists and is complete, before the confirmation code is executed, the calculation operation of the central processor is effectively suspended to wait Page 25 591377 VI. Scope of patent application The delayed signal generated by the sequential circuit; and if the basic input / output system program does not exist or is incomplete, the central processor is caused to execute the confirmation code. 6. If the optional basic input / output system of item 4 of the patent application is applied, the main basic input / output system program further includes a selection code for performing the following steps: call the confirmation code; call the check code to Determine whether the pair of basic input / output system programs exists and is complete; and if the pair of basic input / output system programs exists and is complete, make the central processor perform a second restarting operation and make the BI 0S switching circuit replace the pair The basic input / output system program is mapped into the predetermined address space, so that the central processing unit can execute the secondary basic input / output system program after performing the second reboot operation. 7. If the optional basic input / output system of item 6 of the patent scope is applied, the chipset further includes a second general-purpose input / output register for providing a selection signal to the BI 0S switching circuit and the BI 0S The switching circuit will map the primary basic input / output system program or the secondary basic input / output system program to the predetermined address space after the second restart operation is performed according to the selection signal, and the selection code is further used for Perform the following steps: If the secondary basic input / output system program exists and is complete ^, the second general-purpose input / output register generates the selection signal to select the secondary basic input / output Page 26 591377 VI. Patent Application System Program. 8. If the optional basic input / output system of item 7 of the patent application scope further includes a non-volatile memory for storing a selection parameter, the selection parameter can be adjusted and can be read by the central processing unit. , And the selection code will program the second universal input / output register according to the selection parameter. 9. If the optional basic input / output system of item 4 of the scope of patent application is applied, where the secondary basic input / output system program is incomplete, the check code can be used to make the secondary basic input / output system program be Overwritten by the main basic input / output system program. Page 27