TW569136B - Apparatus and method for conditional instruction execution - Google Patents

Abstract

A conditional execution apparatus in a microprocessor is provided. The conditional execution apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies a condition, where execution of an operation prescribed by the extended instruction depends upon realization of the condition. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for the microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and evaluates the condition. If the condition is not realized, then the extended execution logic precludes execution of the operation.

Description

569136

Description of the Invention (Comparison with Related Applications [0001] This application is based on the following US application number rule i «, the application is May 2002 ^ Priority:" Apparatus and Method for Executing Conditional Instructions ". The name is [0002] This application is the same as the following US patent application in the same application: Its "date" is the same as this application, and has the same applicant and ^ TW SERIAL DOCKET --r --- ~ _ ίΜΛΜ selectively control Device and method for writing back condition code NUMBER 91116957 91116956 NUMBER CNTR: 2176 CNTR: 2188 91116959 CNTR: 2189 mechanism 91116672 CNTR: 2198 Device and method for selectively controlling result write-back (Please read the precautions on the back before filling this page )

VI equipment

nnnn ^ tfJV n «ϋ nn I ϋ ϋ I #. (1) Technical Field of Invention: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs [0003] The present invention is related to the field of microelectronics, especially a method that can perform conditions. Ability to incorporate technology into an existing microprocessor instruction set architecture. (II) Background of the Invention ... [0004] Since its development in the early 1970s, the use of microprocessors has grown exponentially. Since the earliest application in the field of science and technology, 2 paper sizes are now applicable to the Chinese National Standard (CNS) A4 specifications " " (210 x 297 meals) " " A7 ^ —----- 5Z____ 5. Description of the invention (>) Consumer fields that have introduced business from those special fields, such as desktop and laptop computers, video game controllers, and many other common home and business devices. [0005] With the explosive growth in use over the past thirty years, it has also undergone a corresponding improvement in technology, which is characterized by increasing requirements for the following items: faster speeds, more addressing capabilities, Faster memory access, larger operands, more operations (such as floating-point operations, single order multiple data (SIMD), conditional movement, etc.) and additional special operations (such as multimedia operations). This has created amazing technological progress in this field, and has been applied to the design of microprocessors, such as extended pipelining, super-scaiar architecture, cache structure, and out-of-order processing ( (Out-of-flight processing), burst access, branch predication, and speculative exeotion. To put it bluntly, today's microprocessors are surprisingly more complex and powerful than they were 30 years ago. [0006] But unlike many other products, another very important factor has been limited and continues to limit the evolution of microprocessor architectures. Today's microprocessors can be so complicated, and a large part can be attributed to the compatibility of legacy software. In consideration of the market, many manufacturers chose to incorporate new architectural features into the latest microprocessor designs, but at the same time, in these latest products, all of the latest products have been retained to ensure compatibility with the older, so-called "old Have the necessary capabilities for a legacy application. [00〇7] This old software compatibility burden, there is no other place, this paper size applies the Chinese National Standard (CNS) A4 specifications (210 x • U --- ^ ------ phase- Packing --- (Please read the precautions on the back before filling out this page) Order --- Printed by the Consumer Consumption Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 569136 A7

Note 1: Fill in the page I. Please read the booklet on the back _136 r — ^ ___: 5. Description of the invention (ψ); ##) as an operation instruction (such as addition, subtraction, operation element from \ self Memory moved to temporary transfer). After normalization, conditional instructions are processed through the pipeline of H and executed in the operation specified by the conditional instruction to evaluate its test conditions. If the condition evaluation is true (that is, it has been met), the difference is executed and the result is produced. If the condition evaluates to false (that is, not met), the operation is not executed and the conditional instruction is withdrawn. In modern microprocessor pipeline architectures, the conditional execution capability is very useful, because it can avoid the phenomenon of deep pipelines being emptied. For conventional conditional branch instructions used in current applications to change the conditional flow, this phenomenon is the result of incorrect branch prediction. / [0010] Therefore, what we need is a technology that allows conditional execution features to be incorporated into an existing microprocessor instruction set architecture, where the instruction set architecture has a fully occupied opcode structure, and the technology is still retained Compatibility with legacy applications. (3) Brief description of the invention: [0011] Like the other applications mentioned above, the present invention addresses the problems and disadvantages of the above and other conventional technologies. The present invention provides a better technique for expanding the microprocessor's instruction set beyond the existing capabilities to provide complete conditional execution features. In a specific embodiment, a conditional execution device is provided in a microprocessor. The conditional execution device includes a translation logic and an extended execution logic. The translation logic translates an extended instruction into a corresponding micro instruction. The extension refers to 5 paper sizes applicable to China National Standard (CNS) A4 (210 X 297 mm) — rL ------ «-pack --- (Please read the precautions on the back before filling this page} ·. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 569136 A7 V. Description of Invention (f) with -extended prefix and -extended prefix tag (extended prefix tag). The extended prefix specifies a condition, • l · ---% ------- install (please read the precautions on the back before filling this page), and the extended age calculation is a record, and the condition is required It depends. The extended preamble mark indicates the extended preamble, wherein the extended preamble mark is another architecturally designated operation code in the microprocessor instruction set. The extension executes the logic to the translation logic, receives the corresponding command, and evaluates the piece. If the county provides, the ship's extension excludes the execution of the operation. Section 1 [0012] An object of the present invention is to provide an extension of the execution features of the existing microprocessor instruction set to add secrets. The extension mechanism includes-extension instructions,-transitions, and-conditional execution control logic. The extended instruction specifies a sub-set of a plurality of condition codes as a basis for judging a specified operation. The extended instruction includes one of the existing microprocessor instructions, followed by -n-bit extension. The feature preamble set indicates the extended instruction, and the n-bit extended feature preamble indicates the subset. The translator receives the extended instruction, and generates the conditional execution of the specified operation printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs: a piece of lamp control logic is connected to the translator to evaluate the corresponding condition code, and When the subset is full; ^, the specified operation is performed. ° Management-[: = 二: Another—purpose 'is to propose—a kind of existing microprocessing set extension module with an escape tag (⑽pe⑽ and -condition refers to t :. The escape tag is received by the translation logic' And the accompanying part of a pair of private orders is specified-Microprocessor Institute 569136 A7 V. Description of the Invention (G) Extended operation, where the escape mark is the existing micro-point = the binary operation code item. The The condition designates the user as one of the accompanying parts. The condition designation element refers to a condition code state 'which is the basis for judging whether the extended operation is performed.: == The state is sent to a condition execution control Logic, where the conditional order control logic enables / disables the execution of the extended operation. [0014] The present invention re-purposes to provide a method for filling the microprocessor instruction set to provide Programmable conditional execution capability. The method includes providing an extension instruction, the extension instruction includes an extension mark and a condition designation 7L preamble, wherein the extension mark is one of the operation codes of the micro order; Yuan exhaustion and the extended finger; The remaining part specifies an operation to be performed, wherein whether the operation is performed depends on whether the condition specified by the condition designation preamble is satisfied; and the condition code is evaluated to determine whether the condition is satisfied, and if the condition is satisfied, that is, Execution of this difference, if not satisfied, the execution action is excluded. (IV) Illustration of the invention ... [0015] The foregoing and other objects, features, and advantages of the present invention, in cooperation with the following description and accompanying drawings, A better understanding will be obtained: [0016] FIG. 1 is a block diagram of a related art microprocessor instruction format; [0017] FIG. 2 is a table describing how instructions of an instruction set architecture correspond to Figure-Instruction format-The paper size of the byte in the calculation exhaust byte group is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 569136 A7 B7 (7) Logical state; [0018] FIG. 3 is the present invention. [_] FIG. 4 is the-table, a block diagram of the appropriate formula. How do the structural features correspond to -8-bit extension = According to the present invention, extension辑 series State; 'Bit exhaustion in the coded embodiment. [_] Figure 5 is a block diagram illustrating the linear microprocessing H of the present invention; + Zhizhi-& [0021] Figure 6 is the present issue_ _-A block diagram of a specific embodiment; Γ of the coded parts:] Figure 7 is a bar showing the value specified by the extended preamble value of Table 6 [0G23] Figure 8 is a microprocessor feed of Figure 5 [0024] FIG. 9 is a diagram of the extended execution block in the microprocessor of FIG. 5; [0025] FIG. 10 is a table showing the commonly used ιρ—then—this condensed description 'Compare the process of conditional execution with the process of customary execution; and [0026] FIG. Explanation of drawing number: 100 instruction format 102 operation code 200 8-bit operation code figure 101 prefix code 103 address designation element 201 operation code value This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 public love) u — — — — — Nn-(— — 111 — One n «— I! — — — — — (Please read the notes on the back before filling out this page) L · 569136 A7 B7 Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed 5. Description of the invention (") 202 operation code F1H 300 extended instruction format 302 operation code 304 extended instruction mark 400 8-bit preamble figure 500 pipelined microprocessor 301 303 305 401 501 502 instruction cache memory / External memory 503 instruction queue 504 505 extended translation logic 506 507 execution logic 508 600 extended preamble 601 602 condition bit 700 condition field logical state 800 translation stage logic 801 802 machine-specific register 803 804 instruction buffer 805 806 translation controller 807 808 escape instruction detector 809 810 instruction decoder 811 812 micro instruction buffer 813 814 micro op code field 815 816 source stop 817 900 extended execution logic 901 902 micro finger Order register 903 Preamble address designation element Extension preamble architecture feature extraction logic translation logic microinstruction queue extension execution logic standby stop activation status signal extension feature field translation logic disable signal extension preamble decoder Control the read-only memory opcode extension item field. Shelve shift field Operand register opcode extension item field (please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS ) A4 size (210 X 297 mm) 569136 A7

Description of the invention (?) 905 operand register 907 conditional execution control logic 009 arithmetic logic unit 904 remaining fields 906 condition flag register 908 enable signal G0 910 result register 1000 compare IF-THEN -ELSE described the conditional execution process and the flow chart of the work flow (5) Detailed description of the invention: [0027] The following description is' in the-specific embodiment and its necessary conditions It is provided in the context so that those skilled in the art can utilize the present invention. However, 'various modifications to the preferred embodiment will be apparent to those skilled in the art' and the general principles discussed herein can also be applied to other embodiments. For this reason, this post is not limited to the specific embodiments shown and described herein, but has the widest scope consistent with the principles and novel features disclosed herein. [0028] The foregoing has discussed the background of today ’s microprocessors on how to expand their architectural features to surpass the capabilities of related instruction sets. In view of this, a related technology will be discussed in Figures 2 and 2 example of. The discussion here highlights the dilemma that microprocessor designers have been facing. On the one hand, they want to incorporate the latest developed architectural features into the design of the microprocessor. Application capabilities. In the example of Figures 2 to 2, the completely occupied occupancy code diagram has excluded the possibility of adding a new transport code to the example architecture, thus forcing the designer to require a 10-scale national financial standard (CNS) A4 specification. (IlG X 297). «L --- * ----- I ---- I --- Order · --------. (Please read the notes on the back before filling this page ) Printed by the Consumers 'Cooperative of the Ministry of Economic Affairs of the Ministry of Economic Affairs of the People's Republic of China. 569136 V. Invention Description ((If you do n’t choose to include new features, and sacrifice some degree of old software compatibility.'. Or the latest developments in architecture —And give up in order to maintain the slightest point ----------- «-install --- (Please read the precautions on the back before filling this page) The compatibility of the processor with the old application. After the discussion of related technologies, the discussion of the present invention will be provided in Figs. Processor designers have overcome the use of the instruction set architecture that has been fully used. While allowing them to provide conditional execution capabilities, they can also ensure that The compatibility of the old applications of fish. / [G㈣] Miscellaneous _, which is a microprocessor instruction of __ technology, a block diagram of 100. The data items of the instruction equipment of the related technology are as follows, each The items are set to a specific value, which together constitutes a specific instruction of the microprocessor ^ 2. The specific instruction ⑽ instructs to perform a specific operation, such as adding two operands, or moving: Yun ^ from memory to micro The register that handles 一般. Generally; "The operation code item 10 within 7 100 specifies the specific to be executed = 'and the optional address designation meta-item 103 is located after" 02 ". 'Assignment_Nading operation is printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -l · · = 3? Where is the operand located and so on. Instruction format heart 2 ίνΓ members before-operation code 102 plus before Code item 1 {) 1. During the execution of a specific operation specified by Operation Lion I, * code 1 〇1 is used to indicate the scope and architecture characteristics. Generally speaking, the application of these architecture characteristics to any operation code in today The operation specified by 1 (32. For example, 'Ma 101 exists in some Fo using different big heart still rely on financial execution. ^ A paper scale applicable 569136 A7

569136 A7 ---------- B7 V. Description of the invention (| >) 2101. The table 200 maps a specific value of the operation code item 102, for example, 02Η, to a corresponding operation code instruction 201 (ie, instruction 102). In the example of the χ86 opcode diagram, as is well known in the art, the opcode value 14Η is mapped to the x86 Add With Carry (ADC) instruction. This instruction converts an 8-bit direct (inunediate ) Operand is added to the embedded value of the architecture register AL. Those skilled in this field will also find that the aforementioned x86 preamble 1101 (ie, 66H, 67H, 0FH, F0H, F2H, and F3H) is the actual operation code value 201, which is in different contexts. , Specifies that a particular schema extension is to be applied to the operation specified by the subsequent opcode item 102. For example, adding the preamble 0FH before the opcode 14H (normally, the aforementioned ADC opcode) will cause the χ86 processor to execute a "decompress and insert low-compression single-precision floating-point value" (u 叩ack and Interleave L0w Packed Single-Precision Floating-Point Values) operations instead of the original ADC operations. Features such as this x86 example are partially enabled in modern microprocessors. This is because the instruction translation / decoding logic in the microprocessor is sequentially interpreted-the instructions of the project are moved. Therefore, in the past, the use of specific opcode values as the preamble 1-01 in the instruction set architecture allows microprocessor designers to incorporate the miscellaneous features of m into the design of microprocessors compatible with old software. Negative strikes are not performed on legacy programs that are not using those particular opcode states. Example: ^ Weizena opcode GFH has a program that can still be executed on today's microprocessors. And-newer applications, using the calculation code 0 = as the preamble un, you can use Xu = single-instruction multiple data (pass) operation 'conditional movement operation 13 Si 136

Description of the invention (丨 $ L〇〇32) Despite the past — — — — — — — II I · 11 (Please read the notes on the back before filling out this page) as the preamble 1G1 (also available / excessive calculations Code value 201 (command 101) to provide 3_feature mark / index 101 or escape finger function is strong but many fingers ™. In the provision of obstacles:% is q for a very direct reason, and encountered a resistance map The value of 20n has been used up by the extra computational values, that is, all f-calculation exhaustion values of the computational stone horse binary values, * eight, and have been specified architecturally. When all available Vrchen calculations are exhausted, When the item 102 or the preamble item 101 is not displayed, the different code value can be used for recruiting people. This serious problem is that in the current multi-processor architecture, it forces the designer There is a choice between the 'structural characteristics' and the preservation of the compatibility of the old programs. ⑼33] It is worth noting that the instruction 2 shown in Figure 2 is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- l · · 1's t-type representation (ie 124, 186), rather than specifically referring to actual differences (such as carry accumulation, 'Mutual exclusion or). This is because, in some different microprocessor architectures, the fully occupied opcode map has been architecture-excluded, and the possibility of newer progress has been ruled out. The obtained 'is the i-bit operation code item 1Q2, and those skilled in the art will still notice that the specific size of the operation code 102' is caused by the operation code structure 2O () caused by the special occupation. Apart from the problem, the other aspects are not related to the problem itself. Therefore, _complete 6-bit opcode map will have 64 opcodes / preambles that can be architecturally specified, and will not provide usable / redundant The value of the operation code is used as an extension.… [0034] Another method is not to discard the original instruction set and replace it with a new format 100 and operation code map 200, but only to pin the existing operation nose. Code 201 is replaced with a new instruction implication, as shown in the second calculation math -nln ·

569136 Β7

40H to 4FH. With this hybrid technology, microprocessors that conform to the old specifications can be compatible with the old software mode operation. Shooting _ noodles-Qing is interpreted according to the rules of finance, or it can be operated by adding ^^ (enhancedm〇de) Among them, the operation code 40H-4FH is interpreted according to the strengthened architecture rules. This technology does allow the designer to incorporate new features into the design. However, when a microprocessor that conforms to the old specifications operates in enhanced mode, the disadvantages still exist because the micro-processing H mismatches any data that makes the code ready. Program. Therefore, from the standpoint of preserving legacy software compatibility, technology that is compatible with legacy software / enhancement mode is still unacceptable. [_] ㈣ For the complete set of instructions 2GG ', and the space covers all applications running on microprocessors that meet the old specifications, the inventor of this case has noticed that the operation code 2001 And they also observed that although some instructions 202 are structured, they are not used in applications that can be executed by microprocessors. The instruction IF1 202 described in Figure 2 is an example of this phenomenon. In fact, the same calculation exhaustion value 2G2 (ie F1H) is mapped to a valid instruction 202 that is not used in the x86 instruction set architecture. Although the unused χ86 instruction 202 is a valid x86 instruction 202, which instructs to perform a structured operation on the χ86 microprocessor | = said again and again ', but it is not used in any modern Processing | $ runs on the application. This special χ86 instruction 202 is called an electric circuit interruption point (InCircuitEmulati〇nBreakp〇int) (also known as ICE BKPT, the opcode value is truncated). It was previously used exclusively for one kind. It no longer exists Microprocessor simulation device. ICE βκρτ 2〇2 is turned into the program from the circuit __, and the wire is used with the degree of comfort (TΓ National Standard (CNS) A4H ^ 0 χ 297) ----

I ^ ---- i ------- * Installation --- f Please read the notes on the back before filling out this page) 569136 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (〖/) The analog device in the circuit of BKPT 202 no longer exists. Therefore, in the case of χ86, the present inventor has found a tool in a fully occupied instruction set architecture 200 by using an effective but unused operation code 202 to allow the advanced design to be incorporated into the microprocessor design. Without compromising the compatibility of legacy software. In a completely occupied instruction set architecture 200, the present invention uses a structured but unused operation code 200 as an index mark to indicate the next n-bit preamble, so Allows microprocessor designers to incorporate up to 2n of the latest developments in architectural features while retaining full compatibility with all legacy software. [0036] The present invention provides an n-bit condition code designation element preamble to use the concept of pre-exhaustion mark / extended preamble, thus allowing the program to use a routine for operations performed by a microprocessor (Such as addition, subtraction, Brin Yunyi's operation, etc.) stylized, and within the same instruction, specify a condition on which the operation is performed. In a specific embodiment, the condition code state of the microprocessor is stored in a condition code register and is evaluated by Kasaki before the specified operation is executed. If the evaluation result determines that the condition is satisfied, the specified operation is performed. If the condition is not satisfied, the specified operation is not performed. Ming will now discuss with reference to Figures 3-11. [0037] Referring now to FIG. 3, it is a block diagram of an extended instruction format of the present invention. It is very similar to the format discussed in the figure. The swelling makes the format 300 have a variable number of data items 301-305, each-item: set to a specific value, the collection of yarn indulgence processing-specific to Γ 300 . This specific instruction_ instructs the microprocessor to perform a specific operation ^ Add two operands, or move an operand from memory to a micro location = 16 scales are applicable to Chinese national standard ⑽χ 297 in (Please read the back Please fill in this page for the matters needing attention) Packing-OJ .. 569136 Printed by A7 B7, Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs. -In general, the instruction _ executes the specific operation to be performed, and the selected address specification element 2 is located after the operation code 302 to specify the specific operation. How does the addition of 3 and 2 increase? Guan · Zhong 瞀-/ '^ Related additional information, Order 4 shipped, Yun · ^ is located, etc. The instruction f allows the programmer to add a pre-math item _ = 302 before a specific operation specified by -op code 3202, and a light code item = to indicate whether to use the existing architectural features.糸 [[However, the extended instruction of the present invention is the aforementioned = ⑽ 之 -superset (ererset), which has two ^ 304 and 3G5, can be selectively used as an instruction extension item, the page extension instruction details In all the remaining items, before. This $ dagger project _ 3G5 is used to enable / disable multiple conditional execution features: we = some features cannot be used in a completely occupied instruction, optional items 304 and 305 are an extended instruction mark = ^^ 月 > Code 3.5. The extended instruction mark 304 is a microprocessor designation-designated operation code. In the real _86, the ς instruction marks the outline, or the escape mark 3G4, and the _ operation is in paper state = it is the ICE BKPT instruction used earlier. Escape mark 3 3 =: = Preamble 305, extended special focus is behind the altar, in which the extended feature designation element 305 instructs the lion to perform a specified operation. In Finance, the extension instruction mark 304 indicates that a corresponding extension of 30 and the following sections 及-and 305 specify the required conditions of the microprocessor: extension operation. Extension prefix 305, or condition designator, specifies a 17

οι --- b ---- I — Aw · I --- (Please read the precautions on the back before filling this page) · -L. · -111 »This standard is applicable to China National Standard (CNSM4 specification) (21〇297 mm)

569136 5. Description of the invention (β) The status of the code is sent to a condition configured to enable / disable the execution of the extended operation to execute the control logic. [0039] The conditional execution extension technology of the present invention is summarized here. One-time command extensions are configured using an existing instruction set architecture with one opcode / instruction 304 and an n-bit extended feature preamble. The selected opcode instruction is used as an index 304 to indicate that the instruction 300 is a conditional execution instruction 300 (that is, it specifies the conditional execution extension of the microprocessor architecture), and the n-bit feature precedes Code 3305 specifies a subset of the plurality of condition codes as a basis for judging whether or not one of the operations specified by the remaining items of the extended instruction 300 is performed. In a specific embodiment, the extended preamble 305 has an octet size, and a maximum of 256 different subsets of the plurality of condition codes can be specified as a basis for judging an existing instruction set to process an existing instruction. In the embodiment of the n-bit preamble, a maximum of 2 can be specified. Different condition code combinations are used during the conditional execution of a particular operation. [0040] Referring now to FIG. 4, a table 400 shows how a conditional execution extension is mapped to the bit logic state of an 8-bit extended preamble embodiment according to the present invention. Similar to the operation code diagram 200 discussed in FIG. 2, the table 400 in FIG. 4 presents an exemplary 8-bit condition code pre-coding diagram 400, which extends an 8-bit preamble item 305 A maximum of 256 values are associated with a corresponding condition code state 401 (such as E34, E4D, etc.) that conforms to the old specification microprocessor. In a specific embodiment of χ86, the 8-bit extended feature preamble 305 of the present invention is provided for use by extension condition execution designated elements 401 (ie, E00-EFF), and these designated elements 401 are current χ86 instruction set architecture failed to provide. 18 This ^^ degree is applicable to CNS A4 specification (21G X 297 public love) J --- U .------ install --- (Please read the precautions on the back before filling this page ) Order · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 569136 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 V. Description of the Invention (li) [0041] The extended features shown in Figure 4 are based on- The method is expressed rather than specifically referring to the actual features. This is because the technology of the present invention can be applied to various different architecture extensions 401 and specific instruction set architectures. Those familiar with this leading technology will find that there are many different architectural features 401, some of which have been mentioned above, which can be incorporated according to the escape mark 304 / extended preamble 305 technology described here -Existing instruction set. The eight-bit preamble embodiment of FIG. 4 provides a maximum of 256 different features 401, while an n-bit preamble embodiment has a normalized selection of up to 2n different features 401. … [0042] In the embodiments corresponding to the non-type conditions, storage, and representation, these are common to many modern microprocessors, and the conditions can be specified to be equal to zero, not equal to zero, even parity ( ⑽η parity), odd parity (oddparity), minus sign (_), no minus sign, overflow, non-overflow, carry, non-carry, can also specify a combination of the aforementioned conditions, including high In (fine 0 (ie, not rounded and not equal to zero), below (bel0w) or equal (ie, rounded or equal to zero), greater than (ie, not equal to zero and the sign bit is equal to the carry bit), etc.) In the processor, a condition code status item (that is, temporary storage) is configured with a plurality of condition code bits (or flags), where each bit represents whether the most recently generated result has exceeded a certain result boundary bar. ^, Such as generating a carry bit, or a sign bit showing the result system, r ,, :: The state of other conditions is not to limit the scope of the present invention to a specific microprocessor condition code set. The foregoing embodiments Can be used as an example ^ The present invention 'How a conditional preamble 305 is encoded to provide a conditional sub-set to be implemented as a microprocessor that conforms to the old specifications (please read the precautions on the back before filling this page) Binding: 19 569136 A7 B7 5 Explanation of the invention (丨) The basis for judging the operation. Those skilled in the art will notice that the configuration of the special extended condition preamble 3G5 depends on how the condition code in the corresponding microprocessor is represented and stored. [〇〇43] Please refer to the fifth part, which is a block diagram illustrating the pipelined micro-processing It 5GG of the present invention for executing the extension bar ^ execution instruction _. The micro-processor 500 has three distinct stage types: Extraction, translation, and execution. The extraction stage has extraction logic 501, which can fetch instructions from the instruction cache memory 502 or the external memory 502. The extracted instructions are sent to the translator 卩 0 through the instruction side 503. In addition, the translation stage has translation logic [M, connected to a microinstruction sequence 506. The translation logic includes extended translation logic. The execution stage has execution logic 507, which includes extended execution logic 508. [0044 ] Based on this It is clear that during operation, the extraction logic 501 extracts formatted instructions from the instruction cache memory / external memory, and places these instructions in the instruction side according to the order in which they are executed. Then it extracts from the instruction array 503 These instructions are sent to translation logic 5Q4. Translation 5Q4 decodes each incoming instruction _ / decodes into a crane reading instruction system, indicating that the microprocessor 500 executes the instructions indicated by these instructions according to whether the specified conditions are met. According to the present invention, the extended translation logic 505 4 tests those instructions with extended preamble flags and provides translation / decoding for the meta-prefix specified as the corresponding condition. In the -χ86 embodiment, the extended The translation logic 505 group of cancers is to detect the extended preamble mark whose value is F1H, which is χ86, which is the BKPT transport difference code. The microinstruction field is provided in the microinstruction queue 506 to specify the condition code status specified by the extended instruction towel. [0045] Microinstructions are sent from the microinstruction queue 506 to the execution logic

I ZU Paper Size_CNS A4g ^ x 297 meals, 569136

569136 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 -----— B7_ —_ 、 Description of invention (M) The flexibility of application of the invention can be matched with the condition code in the instruction set architecture that considers the adoption Specific way. However, those skilled in the art will recognize that the examples of Figures 6 and 7 do not limit the scope of the present invention to a 4-bit condition designator. [0050] Please refer to FIG. 8, which is a detailed block diagram of the translation stage logic 800 in the microprocessor of FIG. 5. The translation stage logic 800 has an instruction buffer 804, which according to the present invention provides extended conditional execution instructions to the translation logic 8G5. The translation logic 805 is reduced to a machine specific register 802 with an extended characteristic bit 803. The translation logic 805 includes a translation controller 806, which provides a disabling signal 807 to an escape instruction detector 808 and an extended preamble decoder 刖 9. The escape instruction detector 808 is coupled to the extended preamble decoder 809 and an instruction decoder 810. The extended preamble decoder 809 and the instruction decoding logic 810 access a control read-only memory (ROM) 811, which stores a template micro-instruction sequence corresponding to some extended instructions. The translation logic 805 also includes a microinstruction buffer 812, which has an opcode extension field 813, a microop code block 814, a destination block 815, a source field 816, and a shift field 817. . [0051] In operation, during the start-up of the microprocessor, the state of the extension field 803 in the machine-specific register 802 is determined by the signal power-up state 801 to indicate the specific micro-processing. Whether the processor can translate and execute the extended conditional execution instructions of the present invention. In a specific embodiment, the signal 801 is derived from a feature control register (not shown in the figure), and the feature control register reads that 22 paper sizes are configured at the time of manufacture. CNS) A4 specification (210 X 297 mm) ------------- (Please read the precautions on the back before filling this page) A7

569136 fusion, _ "Ufusearray) (nuclear control logic_ controls the instructions extracted from the instruction buffer 8G4, and must implement the translation system or the existing translation rules for interpretation. The improved control features allow for supervision The application (such as Na) enables / = 2 extension execution features of the controller. If the extension execution is disabled, the instructions with the extension code marked operation code status will be translated according to the existing translation \ ". In- x86's frequent _ towel, opcode state F1H is selected as the mark, then the translation rule used by f causes an illegal instruction exception (⑽Ga). Fine, under the extended transfer ^ rule, 'If you meet the post, then Will be detected by the escape instruction side device. The escape instruction detector 8080 will be extended when the extended preamble is decoded and the extension condition after the _translate / decode flag specifies the meta-preamble. Operation 'and enable instruction decoding H 810 when translating / decoding the rest of the extended instruction. Certain specific instructions will result in access to control_811 to obtain the corresponding microinstruction sequence board. Microinstruction buffer 8a12's opcode extension field 813 is The code solution _configuration is used to specify the conditions used to determine whether the specified operation is performed. The other buffer stops 814-817 are configured by the instruction decoder 810. The configured micro instruction 812 is sent To-microinstruction 彳 ning column (not shown in the figure and subsequent execution by the processor. [0052] Please refer to FIG. 9 for a block diagram of the extended execution logic 900 in the microprocessor of FIG. 5. The extended execution Logic 900 has an arithmetic logic unit (ALU) 909, which conforms to Chinese National Standard (CNS) A4 Regulation 4 (210 X 297 public love) through a consistent 23 ^ paper standard

AWI Μ ^ --------- (Please read the notes on the back before filling this page) 569136

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the energy signal GO 908 # is connected to the conditional execution control logic 907. The conditional execution controller 907 accesses the conditional flag storage mechanism ·, or the conditional flag register 9G6. The two operands qPERAND 丨 and · RMD 2 are extracted from the temporary storage το temporary H 9G1 and 905. A microinstruction register 902 provides -microinstructions to the ALU 909 and the conditional execution controller 9Q7. The micro-instruction register has a computing ship extension booth and _ rest 904 ° ALU 909 and is additionally coupled to a result register 91. … [㈣] Operationally, when the chronological execution method is translated into a micro-instruction sequence according to the present invention, the extended micro-instructions and the operands in the temporary registers 901 and 905 are temporarily stored through the micro-age. $ 9 () 2, stationed extended to execute Lai_. If the operation code extension field _ indicates the condition that the wire judges that the remaining operation 904 specifies the operation, the piece execution control logic 907 will execute & Judging the condition is the county true. If the bribe is true, the professional line controller instructs the ALU 909 to perform the specified operation by the signal GO 908, and provides a result to the result temporary storage H_. If the condition is false, the job number GQ_ will not be sent to instruct the ALU 909 to exclude the execution of the operation, so no result is sent to the result register 910. [0054] Please refer to FIG. 10, which shows a table 1000. For the commonly used IF-THEN-ELSE description, compare the conditional execution flow with the conventional execution flow. In the left stop, table 1000 shows a commonly used C language formula, which is used to compare two operands A and B. If A is greater than B: then the computation C is set to 3. If A is not greater than β, the operand c is set to i. This expression is common in many applications. Moreover, this comparative shape (please read the notes on the back before filling out this page) Binding-24 569136 A7 Description of the Invention (Outside) The results are not always predictable. • ^ ---------- * Install --- (Please read the precautions on the back before filling out this page) [0055] The middle column of Form 100 shows a conventional χ86 execution process' Implement the aforementioned C language expression. First, it refers to [A] extracting the operand A from the memory to the temporary register EAX. Next, the instruction CMPEAX, [B] compares the contents of the register EAX with the operand b in the memory. Condition The jump instruction E ELSE checks the status of the condition code generated by the previous comparison instruction. If the condition code shows that the comparison result is less than or equal to, the program flow will branch to the label ELSE and set the operand C to! . Otherwise, the transport element C is set to 3 'and the program flow is guided by a subsequent unconditional jump instruction JMP COMMON, and jumps to the label COMMON before continuing. [0056] In modern deep pipelined microprocessors, if the branch prediction logic incorrectly predicts the result of the conditional jump instruction JLE ELSE, many instructions will be cleared from the instruction pipeline to start executing instructions according to the correct program flow. [0057] The conditional execution flow of the same C language expression is displayed in the right column of the table 1000 to explain how the present invention uses extended instructions to avoid the pipeline being emptied due to incorrect branch prediction results. Compared with the conditional jump instruction (ie E ELSE) and the subsequent unconditional jump instruction (ie JMP COMMON), two extended conditional move instructions (GT.MOV [C], 3 and later le are executed here. MOV [C], l). The execution of the first move instruction depends on the result of the comparison instruction (ie, CMPEAX, [B]). If the result of the comparison is greater than, the first move instruction is executed and the operand c is set to 3. If the comparison result is less than or equal to, the first move instruction is eliminated, and the second move instruction is executed, and the operand C is set to 1. Therefore, this 25 paper standard applies to the Chinese National Standard (CNS) A4 specification (210 X 297 g) 569136 Printed by A7 of the Intellectual Property Bureau Employee Consumer Cooperative of the Ministry of Economic Affairs V. Invention Instructions (v <) The invention's instruction process avoids Wrong branching results in pipelines being emptied. [0058] Please refer to FIG. 11, which is a flowchart illustrating the operation of the method for translating and executing conditional instructions according to the present invention. The flow begins at block 1102, where a program configured to execute a conditional instruction is sent to a microprocessor. Flow then proceeds to block 1104. [0059] In block 1104, the next instruction is fetched from the cache memory / external memory. The flow then proceeds to decision block 1106. [0060] In decision block 1106, the next instruction extracted in block 1104 is checked to determine whether it contains an extended escape tag / code. If not, the flow proceeds to block 1112. If the extended escape code is detected, the flow proceeds to block 1108. [0061] In block 1108, since an extended escape flag has been detected in block 1086, the translation / decoding is performed on an extended preamble to determine the designation on which a corresponding operation relies. Whether the conditions are met. Flow then proceeds to block 1110. [0062] In block 1110, the corresponding stop of a microinstruction sequence is configured to indicate a specified condition specified by the extended preamble. Flow then proceeds to block 1112. [0063] In block 1112, the remaining parts of the instruction (such as the preamble item, the operation code, and the address designator) are translated / decoded to determine the operation to be performed and the attributes of the associated operand. Flow then proceeds to block 714. [0064] In block 1114, the remaining fields of a microinstruction sequence are configured to specify the specified operation and its operand format. The process then proceeds to Fang 26. This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). --- (Please read the precautions on the back before filling out this page) 569136 A7 Printed Invention Note (W) block 1116 by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. ----------- • -install—— (Please read the precautions on the back before filling out this page) [0065] In block 1116, the micro instruction sequence contains the configuration of block 1110. The opcode extension field and the rest of the fields configured in block 1114 are sent to a microinstruction queue for execution by the microprocessor. Flow then proceeds to block 1118. [0066] In block 1118, according to the present invention, the microinstruction sequence is extracted by extended conditional execution logic. The flow then proceeds to block 112. [0067] In block 1120, the extended condition execution logic accesses a condition code storage structure to read the code status corresponding to the condition specified in the extended field of the operation code. The process then proceeds to decision block 1122. [0068] In decision block 1122, the state of the code is evaluated to determine whether the specified condition is met. If so, the flow proceeds to block 1124. If not, the flow proceeds to block 1126, thereby precluding execution of the specified operation. [0069] In block 1124, since the specified condition is true, the specified operation is performed. Flow then proceeds to block 1126. [0070] In block 1126, the method is completed. [0071] Although the present invention and its objects, features, and advantages have been described in detail, 'Other embodiments may also be included in the scope of the present invention. For example, Ming has described the following technology: using the fully occupied instruction set architecture-single-unused opcode status as a flag to indicate the extended feature preamble that follows. However, from the perspective of this issue, Fan = is limited to the command structure that has been completely occupied, and the use of the trigger is early-mark. On the contrary, this day ’s brain covers the instruction set that is not fully mapped, and is used in accordance with China National Standard (CNS) A4 and 21〇χ Norwegian-_ 569136. Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. A7 B7 V. Description of the Invention (β) An embodiment with an operation code and an embodiment marked with more than one instruction. For example, consider an instruction set architecture with no unused opcode states. A specific embodiment of the present invention includes selecting an operation code state as an escape mark, wherein the selection criterion is determined according to market factors. Another specific embodiment includes using a special combination of operation codes as a mark, such as the status of the operation code and the continuous appearance of 7FH. Therefore, the essence of the present invention lies in the use of the -label e sequence, followed by an n-bit extended preamble, which can perform the operation specified by an extended instruction. It depends on whether one of the plurality of conditions is satisfied. [0072] In addition, the present invention has taken the example of a microprocessor having a set of condition codes or flags, the set of condition codes indicates a boundary condition of a previously generated result, including parity, overflow, sign And zero. Although these types of condition indicators are still widely used today, the invention is not limited to application to these types of conditions. For example, another embodiment of the present invention includes other specified conditions, such as the status of the contents of a special register ... Whether a scale or other I / O device uses a towel, is a bankable memory or a cache memory space. and many more. [圆] Furthermore, although the above-mentioned office is used as an example to explain the characteristics and advantages of Ben Yue 2, those skilled in the field can still perceive that the present invention is not limited to the architecture of the microprocessor, but can cover all Talking about forms, such as signal processors, industrial processors (-er), array processors, and other devices. The above-mentioned ones are only the preferred embodiments of Benga, and this month, they are used to limit the scope of the present invention. Da Fan who applied for a special ___ 28 & ruler Cai Guan Jia Pi 1 .___, ------------------ order --------- (please first Read the notes on the back and fill in this page 2_ 569136 A7 _B7__ V. Description of the invention (equal changes and modifications made to the benefit of the scope should still fall within the scope of the patent of the present invention, please ask the reviewers to understand and benefit --------- " Equipment --- (Please read the precautions on the back before filling out this page) Order ·· Printed by the Employees ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 29 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

569136 Shen Qing's patent scope h The conditional execution device in the processor includes: where the extended instruction includes the micro instruction corresponding to the county transfer, one = application preamble 'used to specify-condition, and the extended instruction loses' Depending on the material,-the extended preamble mark is used to indicate the extended preamble, and the extended preamble mark is an instruction code of the microprocessor to another architecturally specified operation code; And,-the extended execution logic is coupled to the translation logic to receive the corresponding microinstruction 'and evaluate the condition. If the condition is not satisfied, the extended execution logic excludes the execution of the operation. 2. The conditional execution device described in item i of the patent application scope, wherein the extension instruction further includes a plurality of items specified by the instruction set according to the architecture. 3. The conditional execution device as described in item 2 of the scope of the patent application, wherein the items specified according to the framework include an -operating code item for specifying the ^ operation. 4. The conditional execution device as described in item J of the patent claim, wherein the extended preamble includes a plurality of bits, and each logic state of the bits corresponds to one of a plurality of result conditions Child collection. 5. The condition execution device as described in item 4 of the scope of the patent application, wherein the result conditions include overflow, carry, equal to zero, below, negative sign, greater than, and less than. b L___ 30 Concentration of this paper: National Standard (CNS) A4 size x 297 mm 569136 A8 B8 C8 D8 6. Application scope of patent 6 · Condition enforcement device as described in item 5 of the scope of application for patent, multiple conditions These are stored in the microprocessor's _flag temporary storage. Among them, 7. The condition execution as described in item 1 of the scope of patent application = theft. The extended preamble contains 8 bits. , 'Where the extension is the conditional execution device described in item 1 of the scope of patent application, and the second instruction set contains the x86 instruction set. 9 、 The eighth means 9 · The conditional execution device described in item 8 of the scope of patent application, and: Extend the preamble mark to include the operation code Fi⑽ ^ of the x86 instruction set. Conditional execution. The corresponding micro-instruction includes a micro-operation code field and ^ 1, the bit.儆 Transportation of different code extensions 11. As the conditional execution execution described in item 10 of the scope of patent application, the extension execution logic uses the micro-operation code extension term to determine the extension execution logic to use the micro-operation. The code field starts with: The operation. 12. The conditional execution device described in item u of the scope of the patent application, the extended execution logic in the basin includes: X a conditional execution implement'_ Cai Qingling, and the execution of the operation is enabled / disabled according to the condition. 13. The conditional execution device as described in item 丨 of the patent application scope, wherein the translation logic includes: escaped command detection logic for extracting the extended preamble flag; and an extended preamble decoding logic , Coupled to the escape instruction detection logic, U's Zhang Chiqian_CNS Standard A4; ίΓ ^ Γ297 Public hair ^ Order --------- (Please read the note on the back first Please fill in this page for further information.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 569136 The scope of the patent application is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs to translate the extended front end and configure a micro-operation code extension term block in the corresponding micro instruction. Specify the condition. 14. The conditional execution device described in item 13 of the scope of patent application, the translation logic further includes: human-instruction decoding logic for configuring other fields in the corresponding micro-instruction 'the butterfly position is based on the The instruction set specifies the operation. For—existing microprocessor instruction sets add an extension mechanism for conditional execution, including: Extended instructions, configured to specify a subset of a plurality of condition codes, and 2-specify whether to determine whether or not an operation is performed. Its central order contains Among the existing micro-instruction set-instructions, which ==-n-bit it extended feature preamble, this instruction. The extension command, and the n-bit it extension feature pre-paid indicates the subset >, a translator configured to receive the extension instruction, and generate-microfinger ^ to guide the specified operation according to the subset Conditional execution-The conditional execution control logic is linked to the condition codes of the set of translations, and _ + # performs the specified operation. When L is offered, execute 16. If the patent application No. 15 instruction further includes: M application mechanism, in which the extended plural instruction parts are configured to specify the specified operation. ___ 32 mechanical scale towel _ home standard ϋ_) Α4 size coffee χ 297 -------------------- ^ ---------. 2 Qingxian (Read the notes on the back and fill out this page) 569136 17. The extension mechanism described in item 16 of the scope of patent application, wherein the instruction parts are formatted according to the existing microprocessor instruction set. 18. The extension mechanism according to item 15 of the scope of patent application, wherein the condition codes include overflow, carry, equal to zero, below, negative sign, parity, greater than, and less than. 19. The extension mechanism described in item 15 of the scope of patent application, wherein the n-bit extended feature preamble includes 8 bits. / 、 20. The extension mechanism described in item 15 of the scope of patent application, wherein the existing microprocessor instruction set is a χ86 microprocessor instruction set. 21 · The extension mechanism described in item 2G of the scope of patent application, wherein the second instruction, the ICE Βκρτ instruction in the instruction set of X86 microprocessor ^ is the operation code 22 · The mechanism described in item 15 of the scope of patent application, 1 The translator includes: 逸 an escape instruction detector to detect the instruction; and an extended preamble decoder to the escape instruction detector to translate the n-bit extension Feature preamble, combined production-the order of the set of instructions-micro-operation fine extensions stop. . Kind of-Existing micro-processing pure order set to supplement the conditional execution ability. Test center order set extension module, including: 'One escape mark' is received by-translation logic, used to indicate-the corresponding instruction attached, partly specified -The microprocessor is going to perform a super-declaration operation where the escape is marked as a first opcode item within the instruction of the existing microprocessor; and this new rule money 33 X 297 mm) (Please read the notes on the back before filling this page) 098899 ABCD 569136 VI. Apply for a conditional designation patent, _ to the escape mark, and the accompanying part of the county-'used to specify-condition code status: The conditional exhaustion state is a basis for judging whether the extended operation is executed, and is sent to an & piece of execution control logic, where the conditional execution control logic enables or disables the execution of the extended operation. 24. The instruction set extension module as described in item 23 of the scope of patent application, wherein the rest of the accompanying part includes-a second opcode item and a plurality of optional address designation meta items. 25. The instruction set extension module according to item 23 of the scope of patent application, wherein the condition designation element includes an 8-bit data item. • The instruction set extension module described in item 23 of the scope of patent application, wherein the existing microprocessor instruction set is an X86 microprocessor instruction set. 27. The instruction set extension module as described in item 26 of the scope of patent application, wherein the first operation code item includes an ICE BKPT operation code item in the instruction set of the X86 microprocessor (that is, operation code F1). 28. The instruction set extension module as described in item 23 of the scope of patent application, wherein the translation logic translates the crane-out mark and the production part into corresponding micro-capsules, and the corresponding micro-instruction instructs an extended execution logic To perform the extended operation. Λ 29. The instruction set extension module described in item 28 of the scope of patent application, wherein the conditional execution control logic evaluates a condition code item to determine whether the condition code status is true, and if the condition code status is false, Then the conditional execution control logic instructs the extended execution logic to exclude the execution of the extended operation 0 ------------ install -------- order --------- ( Please read the notes on the back before filling out this page} Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 569136 Scope of patent application OQ8899 Printed by ABCD Employee Consumer Cooperative of the Ministry of Economic Affairs Intellectual Property Bureau. If the extension of the instruction set described in the scope of patent application is 23, the translation logic contains: ''% One escape mark side logic. Mark and indicate that the translation action of the accompanying part should be based on extended translation conventions; and—decoding logic, _ to the escape mark_ logic, to perform micro-processing based on the conventional microprocessor instruction set convention The translation action of the processor instruction 'and the translation of the corresponding instruction are performed according to the extended translation f rule, so as to enable the extended operation. 31 ·: A method of micro-processing the H instruction set to provide programmable conditional execution capabilities, the method includes: providing two extended instructions, the extended instructions include-an extension mark and a condition-specific meta-prefix 'of which The extension mark is one of the operation codes of the microprocessor instruction set; the condition specifies that the meta-prefix and the rest of the extension instruction refer to two = one operation, where whether the operation is performed is determined; The condition designation meta-prefix specifies-whether the condition is met; and 'Evaluate the condition code item to determine whether the condition is met. If the 32 is satisfied, perform the operation, and if the result is satisfied, exclude the execution action. The method described in item 31 of the declared patent scope, wherein the operations performed include: The first calculation required by Zhong Tao, the first specified action uses the microprocessor to set another different operation code in the set. Benefit exposure ruler (210x297 mm) ------------------- Order --------- (Please read the precautions on the back before filling this page ) 569136 ___ g___ Patent application scope 33. The method described in item 31 of the patent application scope, wherein the action of providing an extended instruction includes the use of a conditional 8-bit predicate. 34. The method as described in item 33 of the scope of patent application, wherein the action of providing an extension means = includes using the different operation code in the instruction set of the x86 microprocessor as the extension mark. 35. The method as described in item 34 of the scope of patent application, wherein the different operation trigger ICEMPT operation code (ie operation code Π) of the instruction set of the microprocessor is used as the extension mark. 36. The method described in item 31 of the scope of patent application, further comprising translating the extended instruction into a micro instruction, wherein the microfinger ζ3 instructs an extended execution logic to determine the condition before executing the calculation: 37 · The actions of the method instruction as described in Applying for Full-time_ 36 items include: Extending in a translation logic to 'detect the extension mark'; and execute the rest of the extension instruction in accordance with the conditions ^ 4 pieces W should be installed -----— Order --------- (Please read the notes on the back before filling out this page) Printed by the Ministry of Economic Affairs and the Intellectual Property Bureau of the People's Republic of China 36 This paper size applies to Chinese national standards ( CNS) A4 specifications (210 ^^^ ·