TW566004B - Phase locked loop for reducing electromagnetic interference - Google Patents

Abstract

A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is a integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

Description

566004 V. Description of the invention (1) Field of the invention The present invention relates to a phase-locked loop (PLL), and more particularly to a phase-locked loop that reduces electromagnetic interference (EMI). Description of Related Technology Phase-locked loop (PLL) in digital systems plays an important role in reducing electromagnetic interference (EMI). Because of advances in technology, digital systems must be able to support high speeds and high densities. The phase-locked loops included in such digital systems are no exception to the trend towards high speeds. However, this digital system and the phase-locked loop may cause electromagnetic interference, which is generated when the energy of the high-frequency signal exceeds a predetermined V reference value, especially the semiconductor device is very sensitive to EM I. ι_ A simple way to reduce EM I is to adjust the frequency with high energy, that is, the reference signal with high power at a certain frequency, to become a frequency signal with low energy. For example, if the frequency of the reference signal is 1 M ， z, then the frequency of the reference signal will be adjusted between 0.999 MHz and 1.0 1 0 Η z at a predetermined cycle. That is to say, the frequency of the phase-locked loop output signal is repeated within a predetermined period, and is adjusted to the frequency signal between the maximum frequency and the minimum frequency allowed by the system using the phase-locked loop output signal. Figure 1 is a graph showing the modulation frequency and modulation rate. Please refer to Figure 1. During the period of 1 / F m, the frequency modulation signal changes between the maximum frequency (1 + δ) F 0 and the minimum frequency (1-5) F 0, where F 0 is the reference frequency. The modulation frequency F m and the frequency change rate 5 can be determined randomly. Preferably, the modulation frequency Fm is between 30KHz and 100KΗζ, and the modulation rate 6 is 4% or less.

10031pif.ptd Page 5 566004

V. Description of the invention (2) Figure 2 illustrates the sine curve shown in (a), whose frequency spectrum is as shown in the modulation signal shown in (b) 'The triangular curve shown in (c) / its frequency spectrum is as ( d) The modulation signal shown in (e) is similar to the shape of Hershey Kises curve of the patent of Lexmark Company, and its frequency spectrum is the modulation signal shown in (f). 〇 口 The modulation signal of the sinusoidal curve shown in (a), its power is too high on both sides as shown in (b), so use a modulation signal with a triangular curve or Hershey Kis s e s curve shape.

A scattered phase locked loop (d i t h e r e d P L L) or spread spectrum clock generator (SSCG) is a device for reducing EM I by adjusting frequency and reducing power gain. S S C G is a patented technology of Le X m a rk company and is called scattered phase locked loop. Its modulation method includes center expansion, upward expansion and downward expansion. ^ Figure 3 shows the # rate spectrum of the scattered phase locked loop corresponding to different expansion methods. 'Figure 3 shows the frequency spectrum of the reference signal and the signal generated by the reference signal modulation results in (a), (c), and (e). The modulation signals are shaped outside (b) (d) and (f). Figures (a) and (b) illustrate the center expansion, Figures (c) and (d) t Erming expand upwards, and Figures (e) and (f) illustrate downward expansion. Please refer to Figure 3, the three expansion methods described above will be described in detail. Φ First of all, in the center expansion method in (a) and (b), the reference signal with narrow frequency range and center high power spike in (a) is tuned to $ # wide frequency range and low power frequency Signal. ~ Second, in the upward expansion method of Figures (c) and (d),

〇〇3lpif ptd Page 6 566004 V. Description of the invention (3) The frequency range and the reference signal of the left high power spike are tuned to a frequency signal with a wide frequency range and low power. Third, in the downward expansion method of (e) and (f), the reference signal with narrow frequency range and right high power spike in (e) is tuned to a frequency signal with wide frequency range and low power . In the past, two methods were used to perform the above expansion. One is to control the least significant bit (LSB) of the divider, and the other is to send a sawtooth wave to the potential of the loop filter and wave filter (1 oop fi 1 ter). . In the first method, the SSCG adopts a read-only memory controller that is recommended by H a r d i η of Le X m a r k Company. In the second method, the pulse wave generator recommended by Neomagic is installed to load the sawtooth wave into the potential of the loop filter. In the case of using a read-only memory controller, the above expansion is performed by the read-only memory encoding. Therefore, the data of the read-only memory must be re-encoded to adjust the output frequency range. In addition, read-only memory can take up a lot of space in semiconductor devices. Installing a pulse wave generator to load the sawtooth wave into the potential of the loop filter will limit the output frequency that can be changed. As a result, a device that is not sensitive to the process, consumes less power, occupies a small amount of layout space, and can flexibly control the modulation frequency and modulation rate is needed. SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a phase-locked loop for reducing electromagnetic interference. The phase-locked loop is not sensitive to the process, consumes low power, occupies a small amount of layout space, and Flexible control of modulation frequency and modulation rate.

10031pif.ptd Page 7 566004 V. Description of the invention (4) The present invention is directed to a phase-locked loop for reducing electromagnetic interference. The phase-locked loop includes a pre-divider for inputting signals to the phase-locked loop. Divide by a predetermined value to generate a reference frequency signal; a phase detector to receive the reference frequency signal and the feedback signal, detect a phase difference between the two signals, and generate a control signal based on the detected phase difference, And a control voltage that outputs the processing result of the control signal generated by a predetermined program; a voltage-controlled oscillator that receives the control voltage and a plurality of switching control signals, and responds to the control voltage to output a first oscillation with a predetermined frequency Signal, and in response to switching the control signal, output a second oscillating signal that is delayed by η times (η is an integer) at the basic delay time of the first oscillating signal; A feedback signal indicating an increase or decrease in the frequency of the first oscillating signal I; a modulation control block for receiving modulation frequency data, modulation rate data, and feedback signals And a second oscillating signal, and output a plurality of switching control signals; and a post-divider for receiving the first oscillating signal, and outputting the signal of the first oscillating signal divided by a predetermined value. A phase-locked loop for reducing electromagnetic interference according to a second embodiment of the present invention includes a phase detection and filtering unit, a voltage-controlled oscillator, a phase inserter, a modulation control block, and a main divider. The phase detection and filtering unit compares the phase of the predetermined reference frequency signal with the phase of the predetermined feedback signal to generate a control voltage whose value changes with the phase difference of the comparison. The voltage-controlled oscillator generates a first oscillating signal having a frequency changing in response to the control voltage, and a first to M-th pulse signal having a frequency changing in response to the control voltage. The phase inserter receives the first to M-th clock signals and cuts the first to M-th clock signals in response to predetermined first to N-th switching control signals.

10031pi f.ptd Page 8 566004 V. Description of the invention (5) The phase difference between two consecutive clock signals and generates a second oscillating signal with a frequency η (η is an integer) times the predetermined basic delay time. The modulation control block receives modulation frequency data, modulation rate data, modulation order data, feedback signal and second oscillating signal to output the first to Nth switching control signals. The main divider receives the second oscillating signal to output a feedback signal for instructing to increase or decrease the frequency of the first oscillating signal. In one embodiment, the basic delay time is obtained by dividing the period of the first oscillation signal by 2N-1, where N is the number of switching control signals. The phase-locked loop may further include a pre-divider and a post-divider. The pre-set divider is used to divide the input signal by a predetermined value to output a reference frequency signal. The post-divider is used to divide the first oscillating signal by a predetermined value, and output a signal as _. The modulation control block may include a modulation frequency control block and a modulation rate control block. The modulation frequency control block outputs a selection signal to select whether to increase or decrease the modulation rate in response to the feedback signal and the modulation frequency data. The modulation rate control block responds to the feedback signal, the modulation rate data, the second oscillation signal, the modulation step data, and the selection signal to output the first to Nth switching control signals. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with preferred embodiments in conjunction with the accompanying drawings as follows: Brief description of the drawing numbers: _401, 1130 pre-divider 4 0 3 phase detector

10031pif.ptd Page 9 566004 V. Description of the invention (6) 405 > 1 110 Voltage controlled oscillator 407 ^ 1 1 25 Main divider 409 > 1 1 20 Modulation control block 41 1 > 1 1 35 Rear Divider 50 1 ^ 1 2 10 Modulation frequency control block 503 ^ 1 220 Modulation rate control block 505 Decision block 601 Ring oscillator 603 Temporary register block 605 Multiple switching switches 1105 Phase detection and filtering and wave unit 1115 Phase Inserter Example According to the present invention 1 is used to reduce the electromagnetic interference (PLL), divide the output signal of the voltage-controlled oscillator (VC0) into multiple signals with phase difference, and combine these signals with phase difference to reduce EI and output Modulate the output signal. FIG. 4 is a block diagram of a phase locked loop for reducing electromagnetic interference (EMI) according to an embodiment of the present invention. As shown in Figure 4, the phase-locked loop to reduce EM I includes a pre-divider 401 (pre-divider), which is used to divide the signal FIN input to the phase-locked loop by a predetermined value to generate a reference frequency signal F. -REF; Phase detector 403, used to receive the reference frequency signal F-REF and the feedback signal F-FEED, detect the phase difference between the two signals, and generate a control signal based on the detected phase difference

10031pif.ptd Page 10 566004 V. Description of Invention (7), output control voltage V-C0N generated as a result of charge pump and loop filter control signal; voltage controlled oscillator (VCO) 4 0 5 for receiving control The voltage V-C0N and the plurality of switching control signals S-C0N, in response to the control voltage V-C0N, output a first oscillating signal F-0SC1 having a predetermined frequency, and in response to the plurality of switching control signals S-C 0 N 'to The output delay is η times (η is an integer) the second oscillating signal F-0SC2 at the basic delay time of the first oscillating signal F-0SC1; the main divider 4 07 is used to receive the second oscillating signal F-0SC2 and output The feedback signal F-FEED instructing to increase or decrease the frequency of the first oscillating signal F-0SC1; the modulation control block 4 0 9 is used to receive the signal which can be stored in a temporary register (not shown) or outside the phase-locked loop Provides the modulation frequency data MFR, the modulation rate data MRR, and the feedback signal F-FEED and the second oscillation signal F-0 SC 2, and outputs a plurality of switching control signals S-C 0 Ν; and post division The receiver 41 1 is configured to receive the first shock signal F-0SC1 and send the first shock signal F- 0SC1 is divided by a predetermined value to output the signal F0UT. Figure 5 is an internal block diagram showing the modulation control block 409 shown in Figure 4. Please refer to FIG. 5. The modulation control block 4 0 9 includes a modulation frequency control block 501 for outputting the first modulation signal in response to the feedback signal F-FEED, the modulation frequency data MFR, and the selection signal SELMUX. F-MODI; Modulation rate control block 503, for responding to the feedback signal F-FEED, the modulation rate data MRR and the first modulation signal F-MODI, outputting the selection signal SELMUX and the second modulation signal F -M0D2; and a decision block 505 for outputting a plurality of switching control signals S-C0N in response to the feedback signal F-FEED, the second oscillation signal F-0SC2, and the second modulation signal F-M0D2.

10031pif ptd Page 11 566004 V. Description of the Invention (8) Figure 6 shows the internal block diagram of the voltage controlled oscillator (VC 0) 4 0 5 shown in Figure 4. As shown in FIG. 6, the voltage-controlled oscillator (VC0) 4 0 5 includes a ring oscillator 601 to output a first oscillatory signal F- having a predetermined frequency in response to the control voltage V-CON. 0SC1, and output multiple modulation and oscillation signals F-0SC1-MOD, leading or delaying the first oscillation signal F-0SC1 divided by the number of switching control signals; time-register block 6 0 3, Includes multiple registers to store multiple modulating and oscillating signals F-0SC1 -MOD; multiple switching switches 6 0 5 for responding to multiple switching control signals S-CON, selecting and switching storage in temporary storage One of the multiple modulating and oscillating signals F-0SC1 -MOD of the block 6 0 3; and an output buffer 6 0 7 for buffering and outputting all the selections of the multiple switching switches 6 0 5 1 changing the switch input Signal FOUT. The present invention will be explained using the upward expansion method as an example. Figure 7 is a timing chart showing a plurality of modulation and oscillation signals F-0SC1-M0D stored in the register block 603 shown in Figure 6. According to Fig. 7, a plurality of modulation oscillation signals f-0 s C 1-M 0 D are delayed by a basic delay time. The basic delay time here can be obtained by dividing the period TF_GSC1 of the first oscillating signal F-0SC1 by the number of multiple switching control signals SCON. For example, suppose the number of switching control signals SCON is 6 The basic delay time is TF_QSC1 X 1/1 6. Figure 8 shows the timing of the first oscillation signal 0SC1, the reference frequency signal F-REF and the feedback signal F — FEED delayed by a predetermined time interval. Figure 0

10031pif ptd Page 12 566004 V. Description of the Invention (9) Please refer to Figures 4 and 8 to describe the relationship between signal generation and signal generation. The phase detector 4 0 3 output corresponds to the control voltage V-C0N between the reference signal F-REF and the feedback signal F-FEED output from the pre-divider 4 0 1 and the voltage-controlled oscillator (VCO) 405 responds. At the control voltage V-C0N, a first oscillating signal F-0SC1 is generated. In addition, the voltage-controlled oscillator (VCO) 4 0 5 responds to multiple switching control signals S-C0N to delay the signal generated by delaying the first oscillatory signal F-0 SC 1 η times the basic delay time (△ t), Select the second-second shock signal F-0SC2. For example, assuming that the second oscillating signal is delayed by 3 times the basic delay time (3At), the main divider 407 uses the second oscillating signal f-number F-0SC2 to generate a feedback signal F-FEED. Figure 8 shows that compared with the reference frequency signal F-RE F, the feedback signal F-FEED is delayed by 3 times the basic delay time (3 △ t). The delay time is equivalent to indicating the phase Y. Zhenying signal F-〇SC 1 frequency command. Figure 9 shows the data bits corresponding to the modulation frequency and modulation rate. FIG. 9 shows the maximum modulation frequency MFMAX and the minimum modulation frequency M F Μ I N and the maximum modulation rate MR M A X and the minimum modulation rate MR MIN. For example, the maximum modulation frequency MFMAX is 4, the minimum modulation frequency MFMIN is 3, the maximum modulation rate MRMAX is 3, and the minimum modulation rate MRMIN is 2. FIG. 10 is a timing chart showing a signal used to reduce the modulation of the phase-locked loop of I according to the present invention. Please refer to FIG. 10. In one cycle of the present invention, the present invention selects 3 feedback signals 3TF_FEED with modulation rate 3, then 4 feedback signals with modulation rate 5, and 3 feedback signals with modulation rate 8 TF_FEED, 3 feedback signals with modulation rate 5 3TF_FEED '4 feedback signals with modulation rate 3 4tf_feed, and 3 feedback signals with modulation rate 0

10031pif.ptd Page 13 566004 V. Description of the invention (ίο) Grant signal 3TF_FEED. In other words, during one week of modulation frequency, 20 feedback signals are included. The modulation rate will be described as follows: First, select / select 3 feedback signals with a modulation rate of 3 (3d t), and then select the 4 feedback signals with a modulation rate (5 dt) higher than the previous 3 2dt feedback signals, the modulation rate of the 3 feedback signals of the third option (8dt) is higher than the modulation rate of the 4 feedback flood signals of the second option 3dt and the 3 feedback signals of the fourth option '(5dt) is lower than the 3 feedback signals 3dt of the second option, the modulation rate (3dt) of the 4 feedback flood signals of the fifth option is lower than the 2dt of the feedback signals of the fourth option, and the sixth r chooses The modulation rate (0dt) of the 3 feedback signals is lower than the 3 feedback signals of the fifth option, 3dt. Regarding the period of the above-mentioned modulation frequency, the sawtooth (or triangle) · rate signal shape can be obtained. The ratio of the minimum frequency signal to the maximum frequency signal is the modulation rate. The period when the minimum frequency signal increases to the maximum frequency signal and then falls back is an indicator representing the modulation frequency. As shown in Figure 9, assuming that the modulation frequency and modulation rate are to be specified, the number of switching control signals S-C0N is 16 and the reference frequency ^ number F-REF is 4MHz, then the modulation rate is 2MΗζ (4ΜΗζ χ 8/16) The modulation frequency is 200KHz (4MHz / 20). The minimum and maximum values prevent the response of the phase-locked loop from distorting the shape of the modulation signal. FIG. 11 is a block diagram showing a phase-locked loop for reducing EM j according to a second embodiment of the present invention, and FIG. 12 is a block diagram showing a modulation control block of FIG. 11. ^

10031pif.ptd Page 14 566004 V. Description of the invention (π) Please refer to Figs. 11 and 12. According to the second embodiment of the present invention, the phase-locked loop for reducing EMI includes a phase detection and filtering unit.丨 〇5, voltage-controlled oscillator 1 1 1 0, phase inserter 1 1 1 5, modulation control block 1 1 2 0, and main divider 1 1 2 5. The phase detection and filtering unit 1 105 compares the phase of the predetermined reference frequency signal F_REF with the phase of the predetermined feedback signal F_FEED to generate a control voltage V_C0N whose value changes with the phase difference. The voltage-controlled oscillator 111 〇 generates a first oscillation signal F_0scl having a frequency that changes in response to the control voltage V-C0N, and first to μ-th clocks having a frequency that changes in response to the control voltage V-C 0 N Signal MULTI-C and MULTI-CM. The phase inserter 1 1 1 5 receives the first to μ clock signals MULTI_C1 ~ MULTI-CM, and responds to the predetermined first to N switching control signals S — C0N1 to S — C0NN to cut the first to The phase difference between two consecutive clock signals of the μ-clock signal MULTI-C1 ~ MULTI-CM, and in addition, the 'phase interpolator 1115 generates a second tremor signal having a frequency which is an integer ^ times the predetermined basic delay time 1? _〇% 2. More specifically, the basic delay time is one of the periods of the first oscillating signal F_0scl divided by 2N-1 'where N is the number of switching control signals. Modulation control block 1 1 2 0 receives modulation frequency data | ^ F r, modulation rate data MRR, modulation order data MSTEP, feedback signal F —FEED and second oscillation signal F-0SC2 to output the first to The Nth switching control signals S_CON1 ~ S_CONN. More specifically, the modulation control block includes a modulation frequency control block.

〇〇3lpi f.ptd 苐 page 15 566004 V. Description of the invention (12) 1 2 1 0 and modulation rate control block 1 2 2 0. The modulation frequency control block 1 21 0 outputs the selection signal SEL_HL to respond to the feedback signal F_FEED and the modulation frequency data MFR. The selection is to increase or decrease the modulation rate. The modulation rate control block 1 2 2 0 responds to the modulation rate data MRR, the second oscillating signal F_0SC2, the modulation order data MSTEP, and the selection signal SEL_HL, and outputs the first to Nth switching control signals S_C0N; 1 ~ S_C0NN. The main divider 1 1 25 receives the second oscillating signal F_0SC2, and outputs it to indicate an increase or decrease, that is, a feedback signal F_FEED that changes the frequency of the first oscillating signal F_0SCI. The phase-locked loop 1 1 0 0 further includes a front divider 1 1 3 0 and a post divider 1 1 35. The pre-divider 1 1 30 divides the input signal F I N by a predetermined value to output a reference frequency signal F_REF, and the post-divider 1 1 35 divides the first oscillating signal F — 0SC1 by a predetermined value to output a signal F — OUT. The operation of the phase-locked loop for reducing the EM I according to the second embodiment of the present invention will be explained with reference to Figs. 11 and 12. According to the second embodiment of the present invention, the phase-locked loop 1 1 0 0 for reducing EM I uses a reference frequency signal F — REF having a relatively high frequency by using the function of the phase inserter 1 1 15. Therefore, the jitter of the phase-locked loop can be reduced. That is, the phase inserter 1 1 1 5 cuts the phase difference between two consecutive clock signals of the first to M clock signals MULTI + C1 ~ MULTI_CM, so When the modulation rate is the same and the number of modulation steps is increased, it is possible to establish a wide frequency band of the phase-locked loop to obtain the desired frequency characteristics. For example, suppose the established modulation rate is 0.5%, so when the output frequency

10031pif.ptd Page 16 566004 V. Description of the invention (13) When the rate is 100MHz, the modulation rate becomes 0.5MΗζ. If the voltage-controlled oscillator 1 1 1 0 only generates 16 clock signals, the following relationship can be established to generate a 0 · 5 Μ Η ζ modulation rate. 1MΗζ (reference frequency signal F — REF) * 8/16 = 0 · 5ΜΗζ 2ΜΗζ (reference frequency signal F — REF) * 4/16 = 0.5MHz 4ΜΗζ (reference frequency signal F — REF) * 2/16 = 0. 5MHz 8MΗζ (reference frequency signal F — REF) * 1/16 = 0 · 5ΜΗζ Here, it is better to increase the reference frequency signal F_REF level so that $ low and $ loop flicker. However, when the reference frequency signal is increased, the number of k-steps decreases from 8 to 4 to 2 to 1, so that the modulation can be weakened. Here 'if the phase inserter Π 1 5 is used to divide the interval between the clock signals of the voltage controlled oscillator 1 1 10 into 10 phases, then 160 phases can be used for modulation, so Establish the following relationships. 4MHz (reference frequency signal F — REF) * 20/160 = 0 · 5ΜΗζ 8ΜΗζ (reference frequency signal F —REF) * 10/160 = 0.5MHz 16MHz (reference frequency signal F —REF) * 5/160 = 0. 5MHz, so, use a reference frequency signal Fref with a relatively high frequency by using a phase inserter 5 to increase the order of modulation. That is, in an actual phase-locked loop having the same modulation rate, when a larger number of modulation steps are provided, a reference signal I? JEF having a higher frequency can be input. Only a few are done 々 Except for the phase inserter 丨 丨 丨 5, the operation of the phase-locked loop shown in Figure 丨 丨 is the same as the operation of the phase-locked loop shown in Figure 4. Therefore, the phase locked loopback

1003lpif.ptd Page 17 566004

The operation of the circuit will focus on the difference from the operation of the phase-locked loop shown in Figure 4. The phase detection and filtering and wave unit 1 1 05 compares the phase of the reference frequency signal ρ REF with the phase of the predetermined feedback signal F —FEED To generate a control voltage V_C0N that varies with the difference. m follows f π m The phase detection and filtering unit 1105 operates as a phase detector and low-pass filter arranged in a phase-locked loop, that is, the phase of the reference F_REF and the predetermined feedback signal F — The difference between the phases of the FEED / b to generate a control voltage V cON whose voltage level changes with the phase difference. The output of the voltage-controlled vibrator 11 i 0 has a first shock signal F_0SC1 whose frequency changes according to the control voltage V — C0N, and the first to M-th MULTI_ (M ~ MULTI CM.) The voltage-controlled shock 1111 includes a ring vibration A container (not shown), which produces a plurality of outputs with phase differences. One of the outputs is a first shock soup that has a frequency that changes with the increase or decrease of the voltage level of the control voltage V-CON. SC1, other outputs are generated as the first to fourth pulses; 震 shock ... MULTI-C1 ~ MULTI-CM. Here the first oscillating signal f — 0SC1 and the first to M-th clock signals MULTI-C1 ~ MULTI-CM The cycle is the same. Because the operation of the ring oscillator is known to those skilled in the art, the description of the voltage controlled oscillator 1110 is omitted. The phase inserter 1 1 1 5 receives the first to M clock signals MULTI-C and MULTI. —CM, and in response to the predetermined first to N-th switching control look-ahead signals S-C0N1 ~ S-C0NN, to cut the first to M-th clock signals MULTI-C1 ~ MULTI-CM between two consecutive clock signals Phase difference, this

10031pi f.ptd Page 18 566004 V. Description of the invention (15) In addition, the phase inserter 1 1 1 5 generates a second oscillating signal F_0SC2 having a frequency of η (η is an integer) times the predetermined basic delay time. The basic delay g is obtained by dividing one period of the first oscillating signal F _ 0 S C 1 by 2N-1, where n is the number of switching control signals. The operation of the phase inserter 1 1 1 5 will be described later. 、 Modulation control block 1 1 2 0 Receives modulation frequency data MFR, modulation rate data MRR, modulation order data MSTEP, feedback signal F —FEED and second seismic profit signal F — 0 SC 2 to output the first To the Nth switching control signal 4 S_C0N1 ~ S-C0NN. Modulation frequency data MFR, modulation rate data MRR, modulation order data MSTEP can be input from the outside or stored in a temporary register (not shown) °. More specifically, the modulation control block 1 1 20 includes the modulation frequency Control block 1 2 1 0 and modulation rate control block 1 2 2 0. Modulation frequency control block 丨 2 丨 〇 Output selection number SEL_HL ′ is used to respond to the feedback signal}? A feed and modulation frequency data MFR, the choice is to increase or decrease the modulation rate. The modulation rate control block 1 2 2 0 responds to the modulation rate data MRR, the second oscillating signal F — OSC2, the modulation order data MSTEP and the selection signal SEL —HL: output 苐 to 苐 N switching control signals S to C 0 N 1 ~ S-C Ο NN. The operation of the modulation control block 1 1 2 0 will be described later. " The main divider 11 25 receives the second oscillating signal F_0SC2 to output a feedback signal F — FEED for instructing to raise or lower the frequency of the first oscillating signal F — OSC1. The operation of the main divider 1125 is the same as that of the main divider 407 in FIG. 4, so the description of the operation of the main divider 1 125 will be omitted. The phase-locked loop 1 1 0 0 further includes a pre-divider 1 3 and a post-division 1135. , °

566004 V. Description of the invention (16) Here 'the front divider 1 1 3 0 divides the input signal ρ IN by a predetermined value to output a reference frequency signal F_REF, and the rear divider 丨 135 divides the first oscillating signal F 0SC 1 is divided by a predetermined value to output a signal f — out. The operations of the pre-divider 1130 and the post-divider 1135 and the pre-divider 4 01 and the post-divider 4 1 1 in FIG. 4 are the same, so the pre-divider 丨 3 〇 and post-divide Operation instructions of the device 1 1 3 5. Figure 13 shows the first to M clock signals and the second oscillating signal waveforms in Figure 11. For example, suppose that M is 4, that is, it is assumed that the voltage-controlled oscillator 1110 outputs four clock signals such as MULTI-Cl, MULTI-C2, MULTI-C3, and MULTI-C4. Here MULTI-Cl, MULTI-C2, MULTI-C3, MULTI-C4 and other four clock signals have the same period. The phase inserter 1 1 1 5 responds to the first to N-th switching control signals S_C 0 N 1 ~ S_C 0 NN to cut, for example, the first and second clock signals MULTI-C1 and MULTI-C2. The phase difference between two consecutive clock signals to generate a plurality of signals. Among them, one of the plurality of signals is generated as a second oscillating signal [0802. The number of the plurality of machine numbers generated by cutting the phase difference between the first and second clock signals ^^^ 丨 and ^^^ is determined by the number of switching control signals S_CON. If the number of switching control signals S-CON is N, the number of the plurality of signals is at most 2n-J. Therefore, 'Equation 1 is used to calculate the basic delay time ldt.

T_CL0CK / (2N-1) ............... where ‘T_CLOCK is the period of the clock signal output by the voltage controlled oscillator 丨 丨 丨 〇.

Page 20 566004 V. Description of the invention (17) 苐 14 shows the first and second tremor signals, reference frequency signals and feedback signal waveforms shown in Figure 11. The phase detection and filtering unit 1 105 generates a control voltage V-C0N corresponding to the phase difference between the phase of the reference frequency signal F — REF and the feedback signal F — FEED, and the voltage-controlled oscillator 11 1 10 responds to the control voltage. The voltage level of v_c〇n increases or decreases to generate the first oscillating signal [_〇8 (: 1. When the control voltage V_C0N increases or decreases, the frequency of the first oscillating signal F_〇SCl also increases. The second oscillating signal F — 0SC2 is in the phase inserter 1 1 1 5 in response to the first to M-th clock signals MULTI_C1 ~ MULTI-CM generated by the voltage-controlled oscillator 1 1 1 0, and the tuning The first to N-th switching control signals S—C0N1 ~ S_C0NN generated by the variable control block 1120 are generated, and the second oscillation signal F_0SC2 can be delayed by n (n is an integer) times the basic delay time ldt. The main divider 1125 responds to The second oscillating signal F_0SC2 generates the feedback signal F — FEED. The main divider 1125 increases or decreases the speed of the feedback signal F-FEED according to the delay time of the second oscillating signal F-0SC2. Therefore, the feedback signal F_FEED will Compared with the reference frequency signal F_REF To increase or decrease the frequency of the first oscillating signal F-0SC1. Please refer to Figure 14 'During the comparison between the reference frequency signal F_REF and the feedback signal F_FEED (i)' The second oscillating signal F-〇SC2 Delaying a basic delay time of 1 dt (ii) and delaying a basic delay time of 1 d (丨 i 丨) ° As a result, the second shock signal F — 0SC2 is compared to the first shock signal F-0SC1 ' A basic delay time of 1 dt twice. Therefore, in response to the second shock signal? -0302's feedback signal

〇031pif-Ptd Page 21 566004 V. Description of the invention (18) F-FEED, self-reference frequency signal F-REF, delayed by a basic delay time of 1 dt twice. Among them, the feedback signal F_FEED is delayed, and the control voltage V_C0N is controlled to increase the frequency of the first oscillating signal F_0SC1. Figure 15 shows the establishment or generation of modulation frequency data, modulation rate data, and modulation order data. Figure 16 shows the adjustment of the second oscillating signal. Modulation frequency data MFR, modulation rate data MRR, and modulation order data MSTEP are stored in a temporary register (not shown). Among them, the modulation frequency can be obtained from the modulation frequency data MFR, because the modulation frequency data mfr is 32, and the modulation conversion rate is 1 / (T_F — REF * 32), where T — F-REF is the reference frequency signal F_REF. cycle. The maximum value of the modulation step data MSTEPMAX and the minimum value MSTEPMIN are both 2, which means that whenever the reference frequency signal ρ ref is generated twice, the modulation rate will change. If the maximum MSTEPMAX of the modulation step data MStep is 3 and the minimum MSTEPMIN is 2, the modulation rate will change when the reference frequency signal F — REF is generated three times, and then when the reference frequency signal F — REF When the clock is generated twice, the rate of adjusting the reputation changes once. The maximum mrmAX of the MRR data is 2 and the minimum mrmin is 1 '. Therefore, the modulation rate will change repeatedly at 2 d t, 1 d t, and 2 d t. Please refer to Figure 16. When the frequency of the reference frequency signal F-REF is generated twice at the first time, the modulation rate will be adjusted by 2dt, and when the frequency of the frequency signal F-REF is For the second time, it is adjusted by 2dt + ldt. When the reference frequency signal F — REF clock, the third time

10031pif.ptd Page 22 566004

V. Description of the invention (19), the modulation rate will be modulated by 2dt + ldt + 2dt when it is generated twice, and when the frequency of the reference frequency signal F_REF is twice when it is generated twice The modulation rate is modulated by 2 dt + 1 dt + 2 dt + 1 dt. Among them, as shown in FIG. 16, the maximum modulation rate is 1 1 dt 'If the phase inserter 1 1 1 5 can generate a signal with a phase difference, it is due to an integer number of N switching control signals 8 _ (: 0 ~, And it is formed by multiplying by the basic delay time of 2N-1. The amount of modulation frequency in Figure 16 can be calculated using Equation 2. Reference frequency signal F —REF * 1 1 / (2N-1) ... ..... (2) Please refer to Equation 2. In order to reduce the amount of modulation frequency, the frequency of the reference frequency signal F — REF must be reduced or the value of 2N-1 must be increased. However, when the frequency of the reference frequency signal increases, the lock The bandwidth of the phase loop can be established at will, and the noise of the output signal F_OUT can be reduced. Therefore, the value of 2N-1 must be increased. Here, the modulation waveforms in Figure 16 are only examples, so in order to maximize the modulation The maximum value MSTEPMAX and the minimum value MSTEPMAX and the minimum value MSTEP of the modulation step data MSTEP must be established with the minimum value. In Figure 16 the maximum value MSTEPMAX and the minimum value MSTEPMIN of the modulation step data MSTEP are established as 1. Therefore, the modulation performance is maximized. Among them, in one period of the modulation frequency, It is 1 / (TF_REF * 32), it needs at least 16 signals with different phases, so the phase inserter 1 1 1 5 must generate more than 16 signals. Therefore, (2N-1) > The equation of 16 where N is the switching control number S_C 0 N 'becomes more than 5. If the voltage-controlled oscillator 111 〇 does not use the phase inserter 111 5 to generate one with different phases

566004 V. Description of the invention (20) Signal, voltage-controlled oscillator 1 1 1 10 requires 8 differential amplifiers. The increase in the number of differential amplifiers results in larger power dissipation and limits the establishment of the frequency bandwidth of the phase-locked loop. The above embodiment is only an example of the present invention, and different phase difference modulation methods can be used according to the similar phase inserter 1 1 1 5. As described above, the phase-locked loop for reducing EMI according to the present invention not only reduces EMI, but also does not require a read-only memory. Therefore, the layout space can be reduced, and a wider frequency range can be obtained. In addition, because the phase difference of the output signal of the voltage-controlled oscillator is controlled by a logic circuit, the phase-locked loop is not sensitive to changes in different processes. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. 9

10031pif.ptd Page 24 566004 Brief description of the diagram Figure 1 shows a diagram of the modulation frequency and modulation rate; Figure 2 shows the shape and spectrum of the modulation signal; Figure 3 shows the corresponding expansion A spectrum of scattered phase-locked loop (PLL) power of the method; FIG. 4 is a block diagram of a phase-locked loop that reduces electromagnetic interference (E M I) according to an embodiment of the present invention; The internal block of the modulation control block shown in the figure-Figure · 'Figure 6 shows the internal block diagram of the voltage-controlled oscillator (VC 0) shown in Figure 4; Figure 7 shows the storage in Figure 6 Timing diagram of multiple modulating and oscillating signals F-0SC1-M0D in the register block shown in the figure; Figure 8 contains the first oscillating signal F-0SC1, the reference frequency signal F — R £ F and a delay of one member Timing chart of feedback signal F-F £ El D in a fixed time interval; Figure 9 shows data bits corresponding to the modulation frequency and modulation rate; Figure 10 shows the method used to reduce E M according to the present invention. Timing diagram of the signal modulated by the phase-locked loop of I; Fig. 11 shows the second phase of the signal according to the present invention. The embodiment is used to reduce the block diagram of the phase-locked loop of EMI; Figure 12 is a block diagram showing the modulation control block of Figure 11; Figure 13 is showing the first to M clock signals and the Figure 11 shows the second oscillating signal waveform; Figure 14 shows the first and second oscillating signals, parameters

10031pif.ptd Page 25 566004 The diagram briefly explains the test frequency signal and feedback signal waveform; Figure 15 shows the generation of modulation frequency data, modulation rate data and modulation order data; and Figure 16 shows Tuning of the second shock signal. «

10031pif.ptd Page 26

Claims (1)

566004 6. Scope of patent application 1. A phase-locked loop for reducing electromagnetic interference, including: a pre-divider, for dividing a signal input to the phase-locked loop by a predetermined value to generate a reference frequency A signal; a phase detector for receiving the reference frequency signal and a feedback signal, detecting a phase difference between the two signals, generating a control signal based on the detected phase difference, and outputting a control signal A control voltage is one of the processing results of the control signal generated by a predetermined program; a voltage-controlled oscillator is used to receive the control voltage and a plurality of switching control signals, and in response to the control voltage, outputs one of a predetermined frequency A first oscillating signal, and a second oscillating signal outputting a delay η times (η is an integer) at one of the basic delay times of the first oscillating signal in response to the switching control signals; a main divider for: Receiving the second oscillating signal and outputting the feedback signal instructing to increase or decrease the frequency of the first oscillating signal; a modulation control block for receiving a frequency modulation Data, a modulation rate data, the feedback signal and the second oscillating signal, and output the switching control signals; and a post-divider for receiving the first oscillating signal and outputting the first oscillating signal Signal divided by a predetermined value. 2. The phase-locked loop as described in item 1 of the scope of the patent application, wherein the basic delay time is obtained by calculating a period of the first oscillating signal divided by the number of the switching ~ control signals. 3. The phase-locked loop as described in item 1 of the scope of patent application, wherein the predetermined procedure of the phase detector means a charge pump and is executed on the control signal 10031pif.ptd Page 27 566004 Sixth, the scope of the patent application One loop is considered. 4. The phase-locked loop as described in item 1 of the scope of patent application, wherein the modulation control block includes: a modulation frequency control block for responding to the feedback signal, the modulation frequency data, and a selection signal, Outputting a first modulation signal; a modulation rate control block for outputting the selection signal and a second modulation-signal in response to the feedback signal, the modulation rate data and the first modulation signal; And a decision block for outputting the switching control signals in response to the feedback signal, the second oscillating signal and the second modulation signal. 5. The phase-locked loop as described in item 1 of the scope of patent application, wherein the electrical φ voltage controlled oscillator includes: a ring oscillator 'for responding to the control voltage and outputting the first oscillation signal having a predetermined frequency And outputting a plurality of modulation vibration signals, the modulation vibration cover signal leading or delaying a period of the first vibration signal divided by the number of the switching control signals; a register block, including A plurality of registers for storing the modulating and oscillating signals; a plurality of switch switches for responding to the switching control signals, selecting and switching one of the modulating and oscillating signals stored in the register box; and An output buffer is used for buffering and outputting the signal input through the selection switch of one of the switching on 1_ off. 6. —A phase-locked loop to reduce electromagnetic interference, including: 10031pif.ptd Page 28 566004 VI. Patent application scope A clock generator block for receiving an input signal, generating a reference frequency signal, generating a control voltage corresponding to a phase difference between the reference frequency signal and a feedback signal In response to the control voltage to generate a first oscillating signal and in response to a plurality of switching control signals to generate a second oscillating delay η times (η is an integer) one of the basic delay times of the first oscillating signal Signals; and a modulation control block for receiving a modulation frequency data, a modulation rate data, the feedback signal and the second oscillation signal, and outputting the switching control signals. 7. The phase-locked loop as described in item 6 of the patent application scope, wherein the basic delay time is obtained by calculating a period of the first oscillating signal divided by the number of the switching _ control signals. 8. The phase-locked loop according to item 6 of the scope of patent application, wherein the modulation control block includes: a modulation frequency control block for responding to the feedback signal, the modulation frequency data, and a selection signal, Outputting a first modulation signal; a modulation rate control block for outputting the selection signal and a second modulation signal in response to the feedback signal, the modulation rate data and the first modulation signal; And a decision block for outputting the switching control signals in response to the feedback signal, the second oscillating signal and the second modulation signal. 9 · The phase-locked loop as described in item 6 of the patent application scope, wherein the clock generator block comprises: a ring oscillator for outputting the first in response to the control voltage 10031pif ptd Page 29 566004 VI. Patent application scope Oscillation signal and multiple modulation oscillation signals. The modulation oscillation signals lead or delay one cycle of the first oscillation signal divided by the number of switching control signals. Time; a register block including a plurality of registers for storing the modulating and oscillating signals; a plurality of switching switches for selecting and switching the stored in the register block according to the switching control signals One of the modulation and oscillation signals; and an output buffer for buffering and outputting a signal inputted by selecting one of the changeover switches. 1 〇. —A phase-locked loop for reducing electromagnetic interference, including: a phase detection and filtering unit for comparing a phase of a predetermined reference frequency signal with a phase of a predetermined feedback signal to generate a control Voltage, the value of the control voltage changes with the phase difference of the comparison; a voltage-controlled oscillator for generating a first oscillating signal having a frequency that changes in response to the control voltage, and having a frequency in response to the control voltage; Changed first to Mth clock signals; a phase inserter for receiving the first to Mth clock signals and cutting the first to Mth response signals in response to predetermined first to Nth switching control signals The phase difference between two consecutive clock signals of the M clock signal and generates a second oscillating signal with a frequency η (η is an integer) times a predetermined basic delay time; a modulation control block for receiving a Modulation frequency data, a modulation rate data, a modulation order data, the feedback signal and the second oscillation signal, 10031pif.ptd Page 30 566004 VI. Patent application scope to output the first to N-th switching control signals; and a main divider to receive the second oscillating signal to output an instruction to raise or lower the The feedback signal of the frequency of the first oscillating signal. 1 1. The phase-locked loop as described in item 10 of the scope of patent application, wherein the basic delay time is obtained by dividing one period of the first oscillating signal by 2N-1, where N is the first to Nth Switch the number of control signals. 12. The phase-locked loop as described in item 10 of the scope of patent application, further comprising:-a pre-divider for dividing an input signal by a predetermined value to output the reference frequency signal; and-a A post-divider is configured to divide the first oscillating signal by a predetermined value to output a signal. a 1 3. The phase-locked loop as described in item 10 of the scope of patent application, wherein the 1 modulation control block includes: a modulation frequency control block for outputting a selection signal, the selection signal being in response to the response The selection signal and the modulation frequency data to select whether to increase or decrease the modulation rate; and a modulation rate control block for responding to the feedback signal, the modulation rate data, the second oscillating signal, the The modulation step data and the selection signal are used to output the first to N-th switching control signals. 10031pif.ptd Page 31