TW543147B - Integrated circuit with self-aligned line and via and manufacturing method therefor - Google Patents

Abstract

An integrated circuit and manufacturing method therefor is provided having a base [12] with a first dielectric layer [14] formed thereon. A second dielectric layer [18] is formed over the first dielectric layer [14]. A third dielectric layer [22] is formed in spaced-apart strips over the second dielectric layer [18]. A first trench opening is formed through the first and second dielectric layers [14] [18] between the spaced-apart strips of the third dielectric layer [22]. A second trench opening is formed contiguously with the first trench opening through the first dielectric layer [14] between the spaced-apart strips of the third dielectric layer [22]. Conductor [34] metals in the trench openings form self-aligned trench interconnects [42].

Description

543147 V. Description of the invention (1) [Field of the invention] The present invention is mainly related to integrated circuits, and more particularly, it relates to wires used in semiconductor elements and interconnections in through holes. [Background Art] Semiconductor technology has been rapidly developed to enable the integration of integrated circuits with more than one million transistors. However, the rapid development of technologies that require such integrated circuits has only just begun to increase rapidly. Technologies such as instant image, high-quality TV, virtual reality, and other scientific and industrial applications are demanding higher speeds, greater functionality, and even faster advancements in ultra-large integrated circuit technology. The need for more functionality requires a significant increase in the number of transistors integrated on a single integrated circuit chip. This requires reducing the size of the transistor and / or having a larger wafer size. As the size of the transistor decreases, the increased density must therefore increase the number of interconnects within the integrated circuit chip. As the number of interconnects increases, the amount of area occupied by the interconnects on the semiconductor wafer becomes relatively large and may offset the area saved by reducing the size of the transistor. The long-term goal of the ultra-large integrated circuit in the semiconductor industry is to achieve the smallest area layout of the interconnects, because the smallest area layout usually provides the best efficiency and economy. In addition, as the number of transistors increases, multiple levels of interconnects between the interconnecting wires and vias (v i a) connecting different levels are necessary.

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The problem of accidentally magnifying the through-holes of the spoiled money in the cleaning solution at a later time will be magnified. via chain) generation -via) overlap and suffering, j l caused by misalignment is a long-term pursuit, but the same as the way to solve these problems has long puzzled those who are familiar with this technique. [Disclosure of Invention] The present invention provides an integrated circuit and a method for manufacturing the integrated circuit. The integrated circuit has a first dielectric layer formed on a substrate. A second dielectric layer on top of the first dielectric layer. A third dielectric layer is formed on the second dielectric layer in spaced-apart strips. A first trench opening is formed through the first and second dielectric layers located between the third dielectric layer and the separating strip. A second trench opening is formed adjacent to the first trench opening through the first dielectric layer between the third dielectric layer and the spaced apart strip. A conductive metal, such as aluminum or aluminum, is accumulated in the trench opening to form a self-aligned trench interconnect. This self-aligned patterning (p a 11 e r n i n g) technique achieves a self-aligned interconnect that avoids misalignment and enhances the ability of the interconnect to perform.

From the following detailed description, combined with the accompanying drawings, it will become apparent to familiarity. 543147 Description of the invention (3) is easy to see. [Best Mode for Carrying Out the Invention] Referring to FIG. 1 ', this figure shows a view of a part of the integrated circuit according to the present invention at an intermediate stage of manufacturing. Integrated circuit interconnects are established on the substrate i 2 'The substrate can be a semiconductor substrate, silicon, dielectric layer, barrier layer or other wires used for silicon-on-insulator (SOI) construction , Through-hole or contactor. The other wire 'through-hole or contactor will be connected to a semiconductor device on, in, or below a semiconductor substrate, insulator silicon, dielectric or barrier layer. In the present invention, the electrical layer 14 has been deposited on the initial blocking layer 15 above the substrate 12. The dielectric layer may be a material having a low dielectric constant such as silicon oxide, silicon nitride, or a dielectric constant of about 3.9 or less. A first blocking layer 16 has also been deposited on the first dielectric layer n and a second dielectric layer 18 has also been deposited on the first blocking layer 16. The proper term "π stop layer" is used here as a convenient consideration, because this sound is used to terminate various etching processes, although it is not necessary to perform this function ^. The stop layer can be, for example, silicon oxide or nitrogen Silicon material. The term Η horizontal (h 〇 ri ζ ο nta 1) π is used to define a conventional plane or surface parallel to the wafer, such as the substrate 2, regardless of the orientation of the wafer. The term "vert i cai" means a direction perpendicular to the horizontal plane just defined. Terms such as "above (0n)", "above", "below ( below "", "side (like sidewall)", "higher (her gher)", "lower (1〇wer)", on, and on the surface (over) "Under (un (jer)" "is based on the horizontal level

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To define. The second stop is mainly used to make the subsequent part of the mask groove partially understandable by the through-hole layers 24 and 4, but it can be any circular shape. Consider the second figure, which shows the layer 22's deposition structure. The protective device was contaminated by the deposition of the photoresist of a low-k dielectric material. Consider Fig. 3, which shows the patterning and removal of the protective dielectric layer 20 after the patterning of Fig. 2. Consider FIG. 4, which shows the uniform photoresist layer patterned by the light f in FIG. 3. The second blocking layer 22 is opened by combining the above moments. The dielectric layer 20, which is familiar with the protection, or any desired shape is exposed, square, or other shapes. The protected dielectric layer 20 and the second dielectric layer 20 are selective and are required to prevent the dielectric material from being exposed to the second barrier layer 22 using the trench and the second barrier layer 22 and exposed to the deposition, Patterning and processing the structure after borrowing 24. The uniform photoresist exposes the protected dielectric layer 20. Those skilled in the art will have the dielectric layer of the second dielectric layer 18 so that the final via can be, refer to Figure 5, which shows that FIG. 4 illustrates a structure in which through holes 26 and 28 are formed by anisotropic etching. The through holes 26 and 28 are etched to pass through the protected dielectric layer 20: the second dielectric layer 18 and reach the first blocking layer 16. Referring to Fig. 6 ', this figure shows the edge formation of Fig. 5 after the uniform photoresist layer 24 is removed in preparation for the formation of the interconnecting wires. 16 and the structure after the second blocking layer 22 is selectively etched. Referring to Fig. 7 ', this figure shows the structure of Fig. 6 after the non-equivalence of the protected dielectric layer 20 is left to expose the second dielectric layer 18. Referring to FIG. 8 ’, the figure shows that FIG. 7 etched through the first blocking layer during etching.

92086.ptd Page 9 543147 V. Description of the invention (5) Reference is made to Figure 9, which shows that Figure 8 reaches the first dielectric layer 18 by removing the exposed second dielectric layer 18 by anisotropic etching. A blocking layer 16 and the first dielectric layer 14 reach the initial blocking layer 15. This step forms the inner connecting wire openings 30 and 32. The openings 30 and 32 accurately intersect the through-hole openings 26 and 28 respectively so that the first dielectric layer 14 and the second dielectric layer are intersected. The widths of the adjacent openings between 18 are exactly the same and self-aligned. Referring to FIG. 10, which shows the structure of FIG. 9 in which the first stop layer 16 and the initial stop layer 15 are etched. The initial stop layer is left to connect to other structures of the integrated circuit, such as a semiconductor transistor or other components (not shown). Reference is made to Fig. 11, which shows the completed internal connection line 10 according to the present invention. The through-hole openings 26 and 28 and the interconnecting conductor openings 3 0 and 32 (see FIG. 10) are filled with conductor metals 34 and 36, respectively, and the through-holes 38 and 40 are connected to the interconnecting wires, respectively. 42 and 44 form an inner line without piping. It should be understood that various conductor metals including aluminum and copper can be used. However, the use of copper requires the deposition of a diffusion barrier. '' Because the via hole layer and the interconnect layer are formed at the same time, the formation method will be described as a dual inlay (Dual iniaid) or a dual damascene (Dual damascene) technology without piping. Reference is made to Figure 12, which shows another embodiment of the interconnect 50 in the intermediate stage of manufacture. In Figure 12, the same steps as shown in Figures 1 to 3 have been completed. The substrate 52 has an initial blocking layer 53 and a first dielectric layer 54 deposited thereon. A first barrier layer 56 is deposited on the first dielectric layer 54 and a second dielectric layer 58 is deposited on the first barrier layer 56. When protecting the dielectric

92086.ptd Page 10 543147 V. Description of the invention (6) The layer 60 is on top of the second dielectric layer 58 with a low dielectric constant. The second blocking layer 62 has been deposited on the second blocking layer 62 and the photoresist layer 64 is combined to protect the dielectric layer 60. Connect the center of 50 in this shape. Refer to Figure 13 for the remainder of the structure. The deep trench dielectric layer 60 and the second dielectric layer electrical layer 54 reach the initial barrier with reference to FIG. 14, which shows the anisotropy of the structured dielectric layer 54 after the dielectric layer 60 is removed. The first stop layer 56 and the initial 56 and the initial stop layer 53 have been etched to form the deep trench wire openings 70 and 72, respectively, so that the adjacent openings between 5 and 8 Refer to Figure 15, which shows the structure after the accumulation. The conductive metal and the deep grooves connected to 84 are double-inlaid or double-embedded. Refer to Figure 16, which shows that the material is selectively deposited on the material. The first product is patterned and processed, exposing the through hole or state, the photoresist and photoresist layer 64 have been sunk so that the deep groove region of the second stop layer overlaps the cover layer 64 to cover the inner display Figure 1 2 passes through the protection 58, the first blocking layer 56 and the first blocking layer 53 at the deep grooves 66 to 69 through the unequal cuts of the remaining grooves 66 to 69. No. 1 3 in the picture. The layer 53 has been stopped by the second removal process. Then through the anisotropy 66 to 67 and 68 to the first dielectric layer, the width is exactly the same, as shown in FIG. 14 where 81 and 74 will be formed. The inner edge of the non-rolled inner interconnection shows another implementation of a photoresist layer and a dielectric layer. The etching 69 intersects 54 and the self metal is borrowed from 50 to complete the wiring. For example, its 64 and the protection 58 and the first are respectively removed to the first barrier layer so as to precisely align the second dielectric layer. The structure of 74 and 76 is formed by the shallow trench 82.

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Page 11 543147 V. Description of the invention (7) Structure with additional dielectric layer on it, the additional dielectric layer is patterned and processed in a conventional manner to form a dielectric spacer 2 3, 2 5, 2 7 and 2 9 ° It will be apparent to those skilled in the art that this spacer will be compatible with the construction described previously to form a piping structure, where the conductive metal is larger than the upper layer than the conductive metal. The lower layer, so that when the self-alignment characteristic is to be maintained, the interconnecting wire will be wider than the width of the through hole by the width of the spacer. Refer to Figure 17 'This figure shows a cross-section view of the 100-degree non-piping through-line of the double-posted or double-embedded technology along the n-th section of the line 17_17. 38 and channel 36 without piping through holes 40. Referring to Figure 18, this figure shows a cross-section view of the internal connection 11 of the double-inlay or double-embedding technology along the section line 18_18 of the completed body in Figure 16 to clearly indicate the through hole 38 smaller than the channel 34 And smaller than the through hole 40 of the channel 36. The dielectric spacers 23, 25, 27, and 29 are used to etch the through holes 38 and 40 'and then remove the spacers. The channels 34 and 36 are then etched without using the dielectric spacers 23, 25, 27, and 29, so the channel will be wider than the width of the via. ^ When the present invention is described in conjunction with a specific best mode, it should be understood that many substitutions, modifications, and alterations will become apparent to those skilled in the art after following the description above. Therefore, the inclusion of such substitutions, modifications and transformations are included in the spirit and scope of the scope of patent application ^ 2 previously proposed in this article or shown in the accompanying drawings ^ contents should be regarded as illustrative and non-limiting Meaning.

543147 Brief description of the drawings [Simplified description of the drawings] FIG. 1 is a view of a part of the integrated circuit according to the present invention in the middle stage of manufacturing; The structure behind the stop layer; Figure 3 is Figure 2. Figure 2 uses a trench mask to pattern the second stop layer and remove a portion of the second stop layer to expose a portion of the second interface. Structure after electrical layer; Figure 4 is the structure of Figure 3 after the photoresist layer is deposited, patterned, and processed using a via mask; Figure 5 is the structure of Figure 4 after the initial stage of etching to form a via Figure 6 is the structure of Figure 5 after removing the photoresist layer; Figure 7 is the structure of Figure 6 after removing the protected dielectric layer to expose the second dielectric layer; Figure 8 FIG. 7 is a structure after etching through the first blocking layer and selectively etching the second blocking layer; FIG. 9 is FIG. 8 illustrating removing the second dielectric layer and reaching the first blocking layer in FIG. 8 And removing the first dielectric layer to reach the initial supporting layer to form a structure where the opening of the interconnecting wire intersects with the opening of the through hole; FIG. 10 is the etching of FIG. 9 The structure after the first barrier layer and the initial barrier layer; FIG. 11 is a complete interconnection line according to the present invention; and FIG. 12 is a view of another embodiment of the interconnection line in the middle stage of manufacturing ,

92086.ptd Page 13 543147 Brief description of the drawings Figure 13 shows the structure of Figure 12 after deep trench etching; Figure 14 shows the structure of the internal connection wire opening and deep groove phase in Figure 13 The structure of the father, FIG. 15 is the structure of FIG. 14 where the conductive metal is deposited to form the interconnection wire and the through hole; FIG. 16 is the illustration of FIG. 3 in another embodiment of the present invention. An additional modification of the dielectric layer deposited on the structure to form a spacer is shown in Figure 11 as a cross-sectional view of Figure 11 along the section line 1 7 -17; Figure 1S) S3 > It is a cross-sectional view of Fig. 16 along the section line 1 8 -18. [Explanation of component symbols] 10 Integrated circuit interconnect 12 > 52 Substrate 14, 54 First _ I dielectric layer 15 ^ 53 Initial stop layer 16 ^ 56 First stop layer 17- 17 ^ 1 8 ~ 18 Section 18 ^ 58 Dielectric layer 20 Dielectric protection layer 11, 62 Second barrier layer 23 > 25 > 27, 29 Di 24, 64 Photoresist layer 26 > 28 > 38 38 40 , 40, through hole 30 > 32 opening 34, 36 conductor metal 42 ^ 44 inner connecting wire 50 inner wiring 60 protective dielectric layer 66 > 67 > 68 69 78 79 ^ 80 > 81 deep trench 70 ^ 72 Openings 82, 84 Shallow grooves 100 Double-bump or double-embedded technology without piping

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Claims (1)

543147 VI. Application Patent Scope 1. A method for manufacturing an integrated circuit, comprising: providing a substrate [1 2]; depositing a first dielectric layer [14] on the surface of the substrate [12]; depositing a second A dielectric layer [18] on the surface of the first dielectric layer [14]; depositing a third dielectric layer [22] on the surface of the second dielectric layer [18]; processing the third dielectric layer [ 22] Opening a first trench portion in the second dielectric layer [18]; depositing a photoresist on the surfaces of the second and third dielectric layers [1 8] [2 2]; processing the photoresist to A second trench portion is opened in the first trench portion of the second dielectric layer [1 8]; the first and second dielectric layers [14] below the second trench portion are removed [ 18] to form a first trench opening; remove the photoresist [2 4]; remove the second dielectric layer [1 8] below the first trench portion to form a second trench opening ; And depositing a conductor [3 4] in the first and second trench openings to form first and second trench interconnects [4 2]. 2. The method for manufacturing an integrated circuit as described in the first item of the patent application scope, wherein: the photoresist [2 4] is included in the first trench portion of the second dielectric layer [1 8] and a third is opened Trench portion; removing the first and second dielectric layers [1 4] [1 8] includes removing the 92086.pid Page 16 ^^ 147 VI. Patent application scope $ Three groove part> gt A third groove is opened =-and the second dielectric layer valve Π8] is shaped to open the hole 3 = limb [34 ] Contains depositing the conductor on the third dielectric layer! • If applied ^ = ΐ2> Interconnect [42] connects the first and third trenches. The method of manufacturing integrated circuits in item 1 of the dry enclosure 'wherein the slotted conductor [34] includes processing a photomask to open the first trench and the conductor [34] is deposited to form an interconnector [ 42] Lian / Leyi groove. The method for manufacturing an integrated circuit including item 1 of the stated patent scope includes ^ depositing the dielectric before depositing the photoresistive second dielectric layer [18] as shown in the patent application scope including 5. · [2 4] A protective layer [20] is on this surface. The method for manufacturing an integrated circuit according to item 1 includes depositing first and second barrier layers [16] [20] on the surfaces of the first and second dielectric layers [14] [18]. 6 · —A kind of integrated circuit, comprising: a substrate [12]; a first dielectric layer [η] on the surface of the substrate [12]; a second on the surface of the first dielectric layer [14] Dielectric layer [i8]. A third dielectric layer [22] formed on the surface of the dielectric layer [18] with spaced apart i bars; here, the three dielectric layers [22] are spaced apart from each other by long bars. Vertically crossing the flute of the first and second dielectric layers [1 4] [1 8], and the city of 0th f is broken 543147 VI. Patent application scope; Between the third dielectric layer [2 2] spaced vertically between the long strips and vertically crossing the first dielectric layer [1 4] and adjacent to the first trench opening A second trench opening; and a conductor [3 4] forming first and second self-aligned trench interconnects [50] in the first and second trench openings. 7. The integrated circuit according to item 6 of the scope of patent application, which includes: vertically spaced between the third dielectric layer [2 2] between the strips and vertically crossing the first and second dielectric layers [1 4] and a third trench opening adjacent to the second trench opening; and wherein: the conductor [3 4] in the first and second trenches is located in the third trench opening . 8. The integrated circuit of item 6 in the scope of patent application, wherein: the conductor [34] includes a portion extending on the surface of the third dielectric layer [22]. 9. The integrated circuit of item 6 in the scope of patent application, wherein: the first trench opening in the second dielectric layer [1 8] is larger than the first opening in the first dielectric layer [1 4] Groove openings. 10. The integrated circuit according to item 6 of the scope of patent application, comprising: a dielectric protective layer [20] provided on the surface of the second dielectric layer [18]. 92086.ptd Page 18