TW540128B - Manufacturing method of X-ray detector array - Google Patents
Manufacturing method of X-ray detector array Download PDFInfo
- Publication number
- TW540128B TW540128B TW091115597A TW91115597A TW540128B TW 540128 B TW540128 B TW 540128B TW 091115597 A TW091115597 A TW 091115597A TW 91115597 A TW91115597 A TW 91115597A TW 540128 B TW540128 B TW 540128B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- gate
- ray detector
- forming
- detector array
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 239000003990 capacitor Substances 0.000 claims abstract description 52
- 238000002161 passivation Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000009413 insulation Methods 0.000 claims abstract description 20
- 239000010409 thin film Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 280
- 239000004020 conductor Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 25
- 238000003860 storage Methods 0.000 claims description 25
- 238000001459 lithography Methods 0.000 claims description 23
- 239000004065 semiconductor Substances 0.000 claims description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 19
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical group [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 7
- 238000000746 purification Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000011521 glass Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 5
- 239000012044 organic layer Substances 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 239000010408 film Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 239000004575 stone Substances 0.000 claims description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims 3
- 229910000831 Steel Inorganic materials 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000010959 steel Substances 0.000 claims 1
- 239000011787 zinc oxide Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 description 11
- 238000005137 deposition process Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000004945 emulsification Methods 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Chemical & Material Sciences (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Materials Engineering (AREA)
- Nanotechnology (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Thin Film Transistor (AREA)
- Light Receiving Elements (AREA)
- Measurement Of Radiation (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
540128 五、發明說明（1) [發明領域] 且 本發明係有關於影像檢測儀（i mager )的製作技術 特別疋有關於一種X光檢測儀陣列（X - r a y d e t e c t 〇 r array)單元的製作方法。 [習知技術說明] 例 係 目前’電子矩陣陣列（electronic matrix array)已 被發現可以應用在X光檢測裝置方面。χ光檢測裝置一般包 括有行位址線（c ο 1 u m n a d d r e s s 1 i n e s )和列位址線（r 〇 w address lines)，而這些行位址線和列位址線係水平地和 垂直地隔離，並且互相地交叉而形成複數個交又 (crossover)部分。關於每個交叉部分係稱為一單元 (element)或一畫素（pixei)。這些單元在許多實例中 如在可以電性地調整的記憶陣列或χ光檢測儀陣列中 用來當作是記憶胞（memory cell)或晝素。 請參閱第1圖，第1圖係顯示將光訊號轉成電子訊號的 一種X光檢測儀陣列之電路佈局圖。χ光檢測儀陣列中^含 有複數個晝素3，並且每個畫素3包含有一薄膜電晶體 3 (TFT)5與一儲存電容7。而每個儲存電容7包含有一電荷收 集電極（charge collector electrode)4 與一晝素電極 11 ’其中該電荷收集電極4係用以當作是上電極Y而該晝 素電極11用以當作是下電極。 ^旦 以下請參見請參閱第2Α、2Β圖，以說明習知之χ光檢 測儀陣列製程。第2 Α圖係顯示習知的χ光檢測儀陣列單元540128 V. Description of the invention (1) [Field of invention] And the present invention relates to the manufacturing technology of the image detector (i mager), particularly to a method for manufacturing an X-raydetector array unit. . [Description of Known Techniques] Example At present, an 'electronic matrix array' has been found to be applicable to X-ray detection devices. The X-ray detection device generally includes row address lines (c ο 1 umnaddress 1 ines) and column address lines (r 〇w address lines), and these row address lines and column address lines are isolated horizontally and vertically And cross each other to form a plurality of crossover parts. Each intersection is called an element or a pixei. These cells are used in many instances as memory cells or x-ray detector arrays that can be electrically adjusted as memory cells or daylight. Please refer to Fig. 1. Fig. 1 shows a circuit layout of an X-ray detector array which converts an optical signal into an electronic signal. The x-ray detector array ^ contains a plurality of day pixels 3, and each pixel 3 includes a thin film transistor 3 (TFT) 5 and a storage capacitor 7. Each storage capacitor 7 includes a charge collector electrode 4 and a day electrode 11 ′, where the charge collection electrode 4 is used as the upper electrode Y and the day electrode 11 is used as Lower electrode. ^ Once, please refer to Figs. 2A and 2B to illustrate the process of the conventional x-ray detector array. Figure 2A shows the conventional X-ray detector array unit
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第4頁0611-7910TWF (N); A02004; Jacky.ptd page 4
540128 五、發明說明（2) ' 的上視圖，第2B圖係顯示第2 A圖的χ光檢測儀陣列單元沿 著C-C’斷線的剖面圖。習知的X光檢測儀陣列單元中，包 含有一基底20 0、一閘極2〇5、一閘極線2〇6、一第_閘極 絕緣層2 1 〇、一下電極（畫素電極）2 1 5、一第二閘極絕緣層 220、一 α-Si 層 225、一 η+α—以層23()、一第一介層洞 235、一源極240、一汲極245、一資料線25〇、一共同線 (common line) 25 5、一平坦化層26〇、一 第二介層洞 265、 一第三介層洞270、一第四介層洞2 75，以及一電荷收集電 極280。另外’符號Cs係表示儲存電容。 為製作上述習知的χ光檢測儀陣列單元，則需要7道微 影#刻步驟（PEP)，亦即需要7個光罩（reticles 〇Γ masks)，其製程略述如下： 第1道微影钱刻步驟：定義閘極2〇5以及閘極線2〇6。 第2道微影钱刻步驟：定義下電極（晝素電極）215。 第3道微影姓刻步驟：定義a—Si層225以及η+ Si層 230，而形成一島狀（island)結構。 第4道微影姓刻步驟：定義第一介層洞235。 第5道微影钱刻步驟：定義源極24〇、汲極245、資料 線250以及共同線255。 第6道微影敍刻步驟··定義第二介層洞2 6 5、第三介層 洞2 7 0以及第四介層洞2 7 5。 第7道微影蝕刻步驟：定義電荷收集電極28〇。 然而’上述習知技術有許多缺點，例如有： (a)由於儲存電容Cs與TFT對於絕緣層特性的需求並不540128 5. Top view of the description of the invention (2) ', FIG. 2B is a cross-sectional view of the χ light detector array unit of FIG. 2A along the line C-C'. The conventional X-ray detector array unit includes a substrate 200, a gate 205, a gate line 206, a first gate insulating layer 2 10, and a lower electrode (pixel electrode). 2 1 5. A second gate insulating layer 220, an α-Si layer 225, an η + α-layer 23 (), a first via 235, a source 240, a drain 245, a Data line 25, a common line 25 5, a planarization layer 26, a second via 265, a third via 270, a fourth via 2 75, and a charge Collecting electrode 280. The symbol Cs indicates a storage capacitor. In order to make the above-mentioned conventional X-ray detector array unit, 7 lithography #etching steps (PEP) are required, that is, 7 photomasks (reticles 〇Γ masks) are required. The process is briefly described as follows: Shadow money engraving steps: define gate 205 and gate line 206. The second lithography step: define the lower electrode (day electrode) 215. The third lithography step is to define the a-Si layer 225 and the η + Si layer 230 to form an island structure. The fourth step of lithography engraving: define the first mesogen hole 235. The 5th lithography money engraving step: define source 24, drain 245, data line 250, and common line 255. 6th lithography narrative step ·· Define the second via hole 2 65, the third via hole 2 700 and the fourth via hole 2 75. 7th lithography etching step: define the charge collection electrode 28. However, the above-mentioned conventional technology has many disadvantages, such as: (a) Because the storage capacitors Cs and TFTs do not require the characteristics of the insulating layer,
540128540128
相同，然而在習知技術中，辟产+ + p ^ 的第二問極絕緣彻卻係：一存層電仏中的介電層㈣ 造成(面b)積1\^_55^無法製作儲存電容Cs ’所以 由：共，同線255下方係與下電極(晝素電極)115電 性連接，所以無法相容灰調微影（gray_toneThe same, however, in the conventional technology, the insulation of the second electrode of + + p ^ is completely: the dielectric layer 仏 in a storage layer 仏 causes (area b) product 1 \ ^ _ 55 ^ cannot be stored. The capacitor Cs' is composed of: in common, the line below 255 is electrically connected to the lower electrode (day element electrode) 115, so it is not compatible with gray tone
Photolithography，亦稱為狹縫（sUt)微影）tft製程。 (d)請參閱第2C圖，當需要保護TFT的通道（channei) 時，則必須在平坦化層260下方形成一純化層29〇，之後進 行一道額外的微影蝕刻步驟，用以去除部分該鈍化層29〇 而形成-介層洞295。士口此，習知技術則共使用 影蝕刻步驟。 [發明概述] 種X光檢測 有鑑於此’本發明之一目的，在於提供一 儀陣列的製程。 本發明之另一目的，在於提供一種可以相容於灰調微 影（gray-tone photo 1 ithography) TFT 製程的X 光檢測儀陣 列的製程。 ' 本發明的又另一目的、，在於提供一種可以增加儲存電 容面積的X光檢測儀陣列的製程。 本發明的再另一目的，在於提供一種具有保護TF丁通 道之鈍化層的X光檢測儀陣列的製程。 ^ 為達上述目的，本發明提供一種X光檢測儀陣列單元Photolithography, also known as sUt tft. (d) Please refer to FIG. 2C. When it is necessary to protect the channel of the TFT (channei), a purification layer 29 must be formed under the planarization layer 260, and then an additional lithography etching step is performed to remove part of the A passivation layer 29 is formed to form a via hole 295. For this reason, the conventional technique uses a shadow etching step. [Summary of the Invention] A kind of X-ray detection In view of this, one of the objectives of the present invention is to provide a process for forming an array. Another object of the present invention is to provide a process of an X-ray detector array compatible with a gray-tone photo 1 ithography TFT process. Another object of the present invention is to provide a manufacturing process of an X-ray detector array which can increase the storage capacitor area. Yet another object of the present invention is to provide a manufacturing process of an X-ray detector array having a passivation layer for protecting a TF channel. ^ In order to achieve the above object, the present invention provides an X-ray detector array unit
540128 五、發明說明（4) 的製程。提供一 橫向延伸的一閘 極，且位在該電 線、該閘極及該 區的該閘極絕緣 線於該閘極絕緣 體島上而構成一 該資料線電性連 該閘極絕緣層上 層於該閘極絕緣 該資料線與該閘 層，而露出該源 上，並填入該第 層洞穿透該平坦 的表面，該第三 面。形成順應性 與該源極電性連 層、該鈍化層與 capaci tor)結構 為使本發明 下文特舉較佳實 下： 基底’ 極線於 晶體區 基底上 層上。 層上， 薄膜電 接。形 ’且覆 層、該 極線上 極的表 一介層 化層， 介層洞 的一第 接。：a： ^ N 該第二 具有一電容區與一電晶體區。形成 該基底上，其中該閘極線包含一閘 内。形成一閘極絕緣層於該閘極 。形成一半導體島於位在該電晶體 形成縱向延伸的一共同線與一資料 並且形成一源極與一汲極於該半導 晶體（TFT)結構，其中該汲極係與 $一第一導體層於位在該電容區的 f該共同線。形成順應性的一鈍化 第一導體層、該薄膜電晶體結構、 形成一第一介層洞穿透該鈍化 面。形成一平坦化層於該鈍化層 洞。形成一第二介層洞及一第三介 其中，該第二介層洞係露出該源極 係露出位在該電容區的該鈍化層表 二導體層於部分該平坦化層上，並 中，位在該電容區的該第一導體 導體層係構成一儲存電容（storage 實施例：540128 Fifth, the process of invention description (4). A laterally extending gate is provided, and the gate insulation line located on the electric wire, the gate, and the area is on the gate insulator island to form a data line electrically connected to the gate insulation layer above the gate insulation layer. The gate electrode insulates the data line from the gate layer, exposes the source, and fills in the first layer hole to penetrate the flat surface and the third surface. Forming a compliant electrical connection layer with the source, the passivation layer, and a capaci tor) structure for the purpose of the present invention are as follows: The substrate's polar line is on the upper layer of the crystal region substrate. On the layer, the film is electrically connected. The shape of the cladding layer, the surface of the epipolar line is an interlayer, and the first hole of the interlayer is connected. : A: ^ N The second has a capacitor region and a transistor region. Formed on the substrate, wherein the gate line includes a gate. A gate insulating layer is formed on the gate. A semiconductor island is formed at the transistor to form a common line and a material extending longitudinally, and a source and a drain are formed in the semi-conducting crystal (TFT) structure, wherein the drain is connected to a first conductor The layer is located at f the common line in the capacitor region. A compliant passivation first conductor layer, the thin film transistor structure is formed, and a first via hole is formed to penetrate the passivation surface. A planarization layer is formed in the passivation layer hole. Forming a second via hole and a third via, the second via hole is exposed, the source electrode is exposed, the passivation layer located in the capacitor region, the second conductor layer is partially on the planarization layer, and The first conductor layer located in the capacitor area constitutes a storage capacitor (storage embodiment:
540128 五、發明說明（5)540128 V. Description of the invention (5)
第1實^;I 請參照第3A〜9A及3B〜9B圖，用以說明本發明第1實施 例之製造流程。其中，第3A〜9A圖係顯示本發明第1實施例 之X光檢測儀陣列單元的製程剖面圖；第3β〜9B圖係顯示本 發明第1實施例之X光檢測儀陣列單元的製程上視圖。其 中’第3Α〜9Α圖係沿著第3Β〜9Β圖中C-C，斷線的剖面圖 首先，請參照第3 A、3Β圖，提供例如是玻璃的一基底 300 其上具有一電容區301與一電晶體區302。然後，進 打一沉積製程與第一道微影蝕刻步驟（PEP—〗）而形成橫向 延伸的一閘極線310於該基底30 0上，其中該閘極線310具 有一凸出部，該凸出部係一閘極3 2 〇，且位在該電晶體區 30 2 内。 沒裡要特別說明的是，雖然第1實施例的閘極3 2 〇是位 於閘極線31G的凸出部，但實際上本發明並不限定閘極3 的位置’例如閘極320可以直接位於閘極線川上。關於閑 ，320直接位於閘極線31〇上之狀況，將於下述之第1實施 例的變化例中予以說明。 第3A、3B圖，形成一閱ϋ _ „ ^ΟΟΛ 取間極絕緣層330於該閘極線310、 該閘極320及該基底3〇〇上。甘士 ^ 〇9n , η ^ ^ ： 其中，該閘極線310與該閘極 3 2 0例如是經由沉積法所形 η上 緣層330例如是經由沉積法2 J屬層：其中’ ”極絕 (SiNx)層或氮氧化;^層>成的-乳化砍層、氮化石夕 ’進行一沉積製程與第二道微影蝕 a〜Si層410與n+ α-Si層420於部分 請參照第4A、4B圖 刻步驟（PEP-II)而形成First Realization ^; I Please refer to FIGS. 3A to 9A and 3B to 9B to illustrate the manufacturing process of the first embodiment of the present invention. Among them, Figures 3A to 9A are cross-sectional views showing the manufacturing process of the X-ray detector array unit of the first embodiment of the present invention; Figures 3β to 9B are showing the manufacturing process of the X-ray detector array unit of the first embodiment of the present invention view. Among them, the 3rd to 9th views are taken along CC in the 3rd to 9th views, and the broken cross-section is shown in the first. Referring to FIGS. 3A and 3B, a substrate 300 such as glass is provided with a capacitor region 301 and A transistor region 302. Then, a deposition process and a first lithography etching step (PEP—) are performed to form a gate line 310 extending laterally on the substrate 300, wherein the gate line 310 has a protrusion, and The protruding part is a gate electrode 3 2 0 and is located in the transistor region 30 2. It should be noted that although the gate electrode 3 2 0 of the first embodiment is a protruding portion located at the gate line 31G, the present invention does not limit the position of the gate electrode 3 ′. For example, the gate electrode 320 may be directly Located on the gate line Chuan. Regarding the idle state, 320 is located directly on the gate line 310, which will be described in a modified example of the first embodiment described below. In FIGS. 3A and 3B, an interlayer insulation layer 330 is formed on the gate line 310, the gate 320, and the substrate 300. Gan Shi ^ 〇9n, η ^ ^: where The gate line 310 and the gate 3 2 0 are formed, for example, by a deposition method, and the upper edge layer 330 is formed by a deposition method, for example, a J-type layer: in which a “SiNx” layer or an oxynitride layer is used. > Formation-emulsification cutting layer, nitride stone y 'to perform a deposition process and a second lithography a ~ Si layer 410 and n + α-Si layer 420. Please refer to the steps in Figure 4A and 4B (PEP- II) to form
〇611-7910TWF(N) ； A02004 ； Jacky.ptd〇611-7910TWF (N); A02004; Jacky.ptd
540128 、發明說明（6) 該閘極絕緣層33 0上，其中該a-Si層410與n+ a-Si層420 係構成位在該電晶體區3 〇 2的一半導體島（α -s i semiconductor island) 〇 請參照第5A、5B圖，先沉積一導體層（未圖示），然後 進行第三道微影蝕刻步驟（PEP-I I I )去除部份該導體層（未 圖示）而形成縱向延伸的一共同線510與一資料線520於該 閘極絕緣層330上，以及形成一源極530與一汲極540於該 a -Si層42 0上。接著，以該源極530與該汲極540為罩 幕，回银部分該η+ α - Si層420而露出部分該a - Si層410的 表面，如此即構成了位在該電晶體區4 〇 2的一薄膜電晶體 (TFT)結構，其中該汲極54〇係與該資料線52〇電性連接。 請參照第6A、6B圖，進行一沉積製程與第四道微影蝕 刻步驟（PEP-IV)而形成一第一導體層610於位在該電容區 3 0 1的該閘極絕緣層3 3 0上，且覆蓋該共同線5 1 〇。其中， 該第一導體層6 1 0例如係由沉積法所形成的銦錫氧化物 (IT0)層或銦鋅氧化物（ιζο)層，用以當作是下電極或書素 電極（pixel electrode) 〇 請參照第7A、7B圖，形成順應性（con formal)的一鈍 化層（passivation layer)710於該閘極絕緣層330、該第 一導體層610、該TFT結構、該資料線520與該閘極線3 1〇 上。然後，進行第五道微影蝕刻步驟（PEP-V)而形成一第 一介層洞（via) 720穿透該鈍化層710，用以露出該源極“ο 的表面。其中，該鈍化層71 0係由沉積法所形成的例如是 氮化石夕（Si Nx)的介電層（dielectric layer)，用以當作儲540128, description of the invention (6) on the gate insulating layer 330, wherein the a-Si layer 410 and the n + a-Si layer 420 form a semiconductor island (α-si semiconductor) located in the transistor region 302 island) 〇 Please refer to Figures 5A and 5B, first deposit a conductor layer (not shown), and then perform a third lithography etching step (PEP-I II) to remove part of the conductor layer (not shown) to form A longitudinally extending common line 510 and a data line 520 are on the gate insulating layer 330, and a source 530 and a drain 540 are formed on the a-Si layer 420. Next, using the source electrode 530 and the drain electrode 540 as a mask, a portion of the η + α-Si layer 420 is returned to the silver portion and a portion of the surface of the a-Si layer 410 is exposed, thus forming the transistor region 4 A thin film transistor (TFT) structure of 〇2, wherein the drain electrode 54 is electrically connected to the data line 52. Referring to FIGS. 6A and 6B, a deposition process and a fourth lithography etching step (PEP-IV) are performed to form a first conductor layer 610 in the gate insulating layer 3 1 in the capacitor region 3 0 1 0 and cover the common line 5 1 0. The first conductor layer 6 1 0 is, for example, an indium tin oxide (IT0) layer or an indium zinc oxide (ιζο) layer formed by a deposition method, and is used as a lower electrode or a pixel electrode. ) 〇 Please refer to FIGS. 7A and 7B to form a conformal passivation layer 710 on the gate insulating layer 330, the first conductor layer 610, the TFT structure, the data line 520 and The gate line is 3 10. Then, a fifth lithography etching step (PEP-V) is performed to form a first via hole 720 penetrating the passivation layer 710 to expose the surface of the source electrode “ο. Among them, the passivation layer 71 0 is a dielectric layer formed by a deposition method, such as Si Nx, for storage.
0611-7910TWF(N) ; A02004 ; Jacky.ptd 第9頁 540128 五、發明說明（7) 存電容Cs中的介電層。 請參照第8A、8B圖，形成一平坦化層（pianarizati〇n layer)810於該純化層710上，並填入該第一介層洞720。 然後，進行第六道微影蝕刻步驟（PEP-VI )而形成一第二介 層洞820及一第三介層洞830穿透該平坦化層81〇，其中， 該第二介層洞820係至少露出該源極53〇的表面，該第三介 層洞8 3 0係露出位在該電容區3 〇 1的該鈍化層71 〇表面。還 有，該平坦化層810例如係由旋塗法（spin c〇ating)所形 成的旋塗式玻璃層（SOG)或有機層（即由「有機平坦化材 料」所組成）。 請參照第9A、9B圖，進行一沉積製程與第七道微影蝕 刻步驟（PEP-V I I )而形成順應性的一第二導體層9丨〇於部分 該平坦化層810上，並與該源極530電性連接。其中，位在 該電容區301的該第一導體層610、該鈍化層71〇/與該第二 導體層910係構成一儲存電容Cs結構。其中，該第二導體 層910例如係由沉積法所形成的銦錫氧化物（IT〇)層或銦 氧化物（ΙΖΟ)層，用以當作是上電極或電荷收集電極 (charge col lector electrode)。 第1實施例之變化例 請參照第9C及9D圖，用以說明本發明第i實施例 化例。第9C圖係顯示本發明第一實施例之變化例的 面圖；第9D圖係顯不第9C圖的上視圖。其中，第9C 、: 著第9D圖中D-D，斷線的剖面圖。在此，相同或類似於^0611-7910TWF (N); A02004; Jacky.ptd Page 9 540128 V. Description of the invention (7) Dielectric layer in storage capacitor Cs. Referring to FIGS. 8A and 8B, a pianarization layer 810 is formed on the purification layer 710, and the first via hole 720 is filled. Then, a sixth lithography etching step (PEP-VI) is performed to form a second via hole 820 and a third via hole 830 to penetrate the planarization layer 810, wherein the second via hole 820 At least the surface of the source electrode 53o is exposed, and the third via 830 is exposed at the surface of the passivation layer 71o located in the capacitor region 301. The planarizing layer 810 is, for example, a spin-on glass layer (SOG) or an organic layer (that is, an organic planarizing material) formed by a spin coating method. Referring to FIGS. 9A and 9B, a deposition process and a seventh lithography etching step (PEP-V II) are performed to form a compliant second conductor layer 9 on a part of the planarization layer 810, and The source electrode 530 is electrically connected. Among them, the first conductor layer 610, the passivation layer 710 / and the second conductor layer 910 located in the capacitor region 301 form a storage capacitor Cs structure. The second conductor layer 910 is, for example, an indium tin oxide (IT0) layer or an indium oxide (IZO) layer formed by a deposition method, and is used as an upper electrode or a charge col lector electrode. ). Modification of the first embodiment Please refer to Figs. 9C and 9D to describe the i-th embodiment of the present invention. Fig. 9C is a plan view showing a modification of the first embodiment of the present invention; Fig. 9D is a top view showing Fig. 9C. Among them, 9C,: D-D in 9D, broken cross-sectional view. Here, the same or similar to ^
540128540128
3 A〜9 A及3B〜9B圖之構成者，將盡量以相同符號來表示。另 外’由於各構成者之材質與前述相同，在此亦不再贅述。 請參照第9C、9D圖，提供例如是玻璃的一基底3〇〇， 其上具有一電容區301與一電晶體區3〇2。然後，形成橫向 延伸的一閘極線31 〇於該基底3 〇 〇上，其中部分該閘極線 3 1 0用以當作是一閘極3 2 0，且位在該電晶體區3 〇 2内。 接著’形成一閘極絕緣層330於該閘極線3 1 〇、該閘極 320及該基底3〇〇上。之後，形成a -Si層410與n+ a -Si層 4 2 0於部分該閘極絕緣層3 3 〇上，其中該α — s i層4 1 0與n+ α -Si層420係構成位在該電晶體區3 0 2的一半導體島（α 一以 serai conductor island)。 接著，形成縱向延伸的一共同線510與一資料線520於 該閘極絕緣層3 3 0上’以及形成一源極5 3 0與一沒極5 4 0於 該n+ a - Si層420上。之後，以該源極530與該汲極540為 罩幕，回蝕部分該η+α-Si層420而露出部分該a—Si層410 的表面，如此即構成了位在該電晶體區4 〇 2的一薄膜電晶 體（TFT)結構，其中該TFT結構係橫躺於該閘極線310上， 且該汲極540係與該資料線520電性連接。 接著，形成一第一導體層610於位在該電容區301的該 閘極絕緣層3 3 0上，且覆蓋該共同線5 1 〇。其中，該第一導 體層610用以當作是下電極或晝素電極（pixei electrode) ° 接著，形成順應性（c ο n f 〇 r m a 1 )的一鈍化層 (passivation layer)710於該閘極絕緣層33 0、該第一導The constituents of 3 A to 9 A and 3B to 9B will be represented by the same symbols as much as possible. In addition, since the materials of the constituents are the same as those described above, they will not be repeated here. Referring to FIGS. 9C and 9D, a substrate 300, such as glass, is provided, which has a capacitor region 301 and a transistor region 302 thereon. Then, a gate line 31 extending laterally is formed on the substrate 300, and part of the gate line 3 1 0 is used as a gate 3 2 0 and is located in the transistor region 3 0. 2 within. Next, a gate insulating layer 330 is formed on the gate line 31, the gate 320, and the substrate 300. After that, an a-Si layer 410 and an n + a-Si layer 4 2 0 are formed on a part of the gate insulating layer 3 3 0, wherein the α-si layer 4 1 0 and the n + α-Si layer 420 are formed at the A semiconductor island of the transistor region 3 02 (α-serai conductor island). Next, a common line 510 and a data line 520 extending vertically are formed on the gate insulating layer 3 3 0 ′, and a source 5 3 0 and a non-electrode 5 4 0 are formed on the n + a-Si layer 420 . Then, using the source electrode 530 and the drain electrode 540 as a mask, etch back part of the η + α-Si layer 420 and expose part of the surface of the a-Si layer 410, so that the transistor region 4 is formed. A thin film transistor (TFT) structure, wherein the TFT structure is lying on the gate line 310, and the drain 540 is electrically connected to the data line 520. Next, a first conductor layer 610 is formed on the gate insulating layer 3 3 0 of the capacitor region 301 and covers the common line 5 1 0. Wherein, the first conductor layer 610 is used as a lower electrode or a pixei electrode. Next, a passivation layer 710 of compliance (c ο nf 〇rma 1) is formed on the gate electrode. Insulation layer 33 0, the first conductor
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第11頁 540128 五、發明說明（9) ---- 體層610、该TFT結構、該資料線52〇與該閘極線31〇上。然 ，進行Μ影蝕刻步驟而形成一第一介層洞（v i a ) 7 2 0穿透 邊鈍化/層710，用以露出該源極53〇的表面。其中，該鈍化 層710係用以當作儲存電容Cs中的介電層。 ^ 接著’形成一平坦化層（planar izat ion layer)81 0於 该鈍化層7 1 0上，並填入該第一介層洞72 〇。然後，進行微 =餘刻步驟而形成一第二介層洞8 2 0，及一第三介層洞8 3 0 穿透該平坦化層81〇，其中，該第二介層洞820,係露出該 源極5 3 0的表面與位在電晶體區3 〇 2之該鈍化層7丨〇的表 面’该第二介層洞8 3 〇係露出位在該電容區3 〇 1的該鈍化層 7 1 0表面。 接著’形成順應性的一第二導體層9丨〇於部分該平坦 化層8 1 0上，並與該源極5 3 〇電性連接。其中，位在該電容 區301的該第一導體層61〇、該鈍化層71〇與該第二導體層 910係構成一儲存電容Cs結構。其中，該第二導體層91〇係 用以當作疋上電極或電荷收集電極（charge collector electrode) 〇 第2實施例 請參照第1 0 A〜1 6 A及1 0 B〜1 6 B圖，用以說明本發明第2 實施例之製造流程。其中，第1 〇A〜1 6A圖係顯示本發明第2 實施例之X光檢測儀陣列單元的製程剖面圖；第1 〇B〜1 6B圖 係顯示本發明第2貫施例之X光檢測儀陣列單元的製程上視 圖。其中，第10A〜16A圖係沿著第ιοΒ〜16B圖中C-C，斷線的0611-7910TWF (N); A02004; Jacky.ptd Page 11 540128 V. Description of the invention (9) ---- The body layer 610, the TFT structure, the data line 52 and the gate line 31. However, a M-etching step is performed to form a first via hole (v i a) 7 2 0 penetrating edge passivation / layer 710 to expose the surface of the source electrode 53. The passivation layer 710 is used as a dielectric layer in the storage capacitor Cs. ^ Next, a planarization layer 81 0 is formed on the passivation layer 7 1 0, and the first via hole 72 0 is filled. Then, a micro = remove step is performed to form a second via hole 8 2 0, and a third via hole 8 3 0 penetrates the planarization layer 810, wherein the second via hole 820 is The surface of the source electrode 5 3 0 and the surface of the passivation layer 7 丨 located in the transistor region 3 〇 2 are exposed. The second interlayer hole 8 3 〇 exposes the passivation located in the capacitor region 301. Layer 7 1 0 surface. Next, a conformable second conductor layer 9 is formed on a part of the planarization layer 8 10 and is electrically connected to the source 5 3 0. Wherein, the first conductor layer 61, the passivation layer 71, and the second conductor layer 910 located in the capacitor region 301 form a storage capacitor Cs structure. Wherein, the second conductive layer 91 is used as an upper electrode or a charge collector electrode. For the second embodiment, please refer to FIGS. 10A to 16A and 10B to 16B. , Used to explain the manufacturing process of the second embodiment of the present invention. Among them, FIGS. 10A to 16A are cross-sectional views showing the manufacturing process of the X-ray detector array unit of the second embodiment of the present invention; and FIGS. 10B to 16B are X-rays showing the second embodiment of the present invention Top view of the process of the detector array unit. Among them, Figures 10A-16A are broken along C-C in Figures ιοΒ ～ 16B.
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第12頁 540128 五、發明說明（10) 剖面圖 首先，請參照第1 〇A、1 〇β圖，提供例如是玻璃的一基 底1000 ’其上具有一電容區1〇〇1與一電晶體區1002。然 後L進行一沉積製程與第一道微影蝕刻步驟（PEP-I )而形 成检向延伸的一閘極線1 0 1 0於該基底1 0 0 0上，其中該閘極 舞1 〇 1 0具有一凸出部，該凸出部係一閘極i 〇 2 〇，且位在該 電晶體區1 〇 〇 2内。其中，該閘極線1 〇丨〇例如係由沉積法所 形成的金屬層。 這裡要特別說明的是，雖然第2實施例的閘極1 〇 2 〇是 位於閘極線1 〇 1 〇的凸出部，但實際上本發明並不限定閘極 1 〇 2 0的位置’例如閘極丨〇 2 〇可以直接位於閘極線丨〇丨〇上。 關於閘極1 020直接位於閘極線1〇1〇上之製程，類似於上述 之第1實施例的變化例，在此不再予以贅述。 苐11 A、11 B圖’形成一閘極絕緣層1 11 〇於該閘極線 1010、該閘極1 020及該基底1 0 0 0上，其中該閘極絕緣層 1110例如是經由沉積法所形成的二氧化矽層、氮化矽 (S1 Nx)層或氮氧化矽層。然後，依序沉積一 —s丨層丨丨2 〇 與一n+ a -Si層11 30於該閘極絕緣層111 〇上。然後，形成 一第一導體層1140於該η+α—Si層1130上，其中該第一導 體層11 4 0例如係由沉積法所形成的金屬層。接著，進行一 >儿積製程與苐一道微影姓刻步驟（p £ p — I I )而形成一灰調 (gray-tone，亦稱為狹縫（si it))光阻圖案！ ！ 50於該第一 導體層1140上。 請參照第12人、126圖，以該灰調光阻圖案115〇為蝕刻0611-7910TWF (N); A02004; Jacky.ptd Page 12 540128 V. Description of the invention (10) Sectional view First, please refer to Figures 10A and 10B. A capacitor region 1001 and a transistor region 1002 are provided. Then L performs a deposition process and the first lithography etching step (PEP-I) to form a gate line 1010 extending in the direction of detection, wherein the gate dance 1 〇1 0 has a protruding portion, the protruding portion is a gate electrode 〇2〇, and is located in the transistor region 002. The gate line 100 is, for example, a metal layer formed by a deposition method. It should be particularly noted here that, although the gate electrode 1 〇 2 0 of the second embodiment is a protruding portion located on the gate line 1 〇 0 〇, the present invention does not limit the position of the gate electrode 〇 2 0 ′ For example, the gate electrode 〇〇２〇 can be directly located on the gate line 丨 〇 丨 〇. The manufacturing process of the gate electrode 1 020 directly on the gate line 1010 is similar to the modified example of the first embodiment described above, and will not be repeated here.苐 11 A, 11 B 'forming a gate insulating layer 1 11 〇 on the gate line 1010, the gate 1 020 and the substrate 1 0 0, wherein the gate insulating layer 1110 is, for example, by a deposition method The formed silicon dioxide layer, silicon nitride (S1 Nx) layer or silicon oxynitride layer. Then, an -s 丨 layer 丨 丨 2 0 and an n + a -Si layer 11 30 are sequentially deposited on the gate insulating layer 111 0. Then, a first conductor layer 1140 is formed on the η + α-Si layer 1130. The first conductor layer 1140 is, for example, a metal layer formed by a deposition method. Then, a > child product process and a photolithography step (p £ p — I I) are performed to form a gray-tone (also known as si it) photoresist pattern! !! 50 on the first conductor layer 1140. Please refer to Figure 12 and Figure 126, and use the gray-tone photoresist pattern 115 as an etch
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第 13 頁 540128 五、發明說明（11) 罩幕’經過數次蝕刻製程，去除部分該第一導體層丨丨4 〇、 該η+α-Si層1130與該a_si層1120，而形成縱向延伸的一 共同線1210於一第一半導體島1 22 0上，以及形成一源極 1230、一没極1240與縱向延伸的一資料線125〇於一第二半 導體島1260上而構成一薄膜電晶體（TFT)結構，其中該汲 極1 240係與該資料線丨25〇電性連接。其中，該第一半導體 島1 220係由剩餘的a—Si層112〇，與n+ “―Si層113〇，所組 成，該第二半導體島丨2 6 〇係由剩餘的α — s丨層丨丨2 〇，，與# a - S i層11 3 0 ’ ’所組成。 請參照第1 3A、1 3B圖，進行一沉積製程與第三道微影 蝕刻步驟（PEP-I II)而形成一第二導體層131〇於位在該電 容區1〇〇1的該閘極絕緣層1110上，且覆蓋該共同線121〇。 其中’該第二導體層丨3丨〇例如係由沉積法所形成的銦錫氧 化物（ITO)層或銦鋅氧化物（IZ0)層，用以當作是下電極或 晝素電極（pixel electrode)。 請參照第14A、14B圖，形成順應性（conf 〇 r m a 1 )的一 鈍化層（pas si vat ion layer ) 1 41 0於該閘極絕緣層111 〇、 該第二導體層1310、該TFT結構、該資料線1 25 0與該閘極 線1 0 1 0上。然後，進行第四道微影蝕刻步驟（pEp_丨v)而形 成一第一介層洞（via)1420穿透該鈍化層1410，用以露出 該源極1 2 3 0的表面。其中，該鈍化層1 41 〇係由沉積法所形 成的例如是氮化矽（SiNx)的介電層（dielectric layer)， 用以當作儲存電容Cs中的介電層。 請參照第1 5 A、1 5 B圖，形成一平坦化層0611-7910TWF (N); A02004; Jacky.ptd Page 13 540128 V. Description of the invention (11) The mask 'after several etching processes to remove part of the first conductor layer 丨 4 〇, the η + α-Si Layer 1130 and the a_si layer 1120 to form a longitudinally extending common line 1210 on a first semiconductor island 1 22 0, and form a source 1230, an electrode 1240 and a longitudinally extending data line 1250 in one A thin film transistor (TFT) structure is formed on the second semiconductor island 1260. The drain electrode 1 240 is electrically connected to the data line 250. Wherein, the first semiconductor island 1 220 is composed of the remaining a-Si layer 1120 and the n + "-Si layer 113o", and the second semiconductor island 2 6 0 is composed of the remaining α-s 丨 layer丨 丨 2 〇, and # a-Si layer 11 3 0 ''. Please refer to Figures 13A, 13B, a deposition process and the third lithography etching step (PEP-I II) and A second conductor layer 131 is formed on the gate insulating layer 1110 located in the capacitor region 1000 and covers the common line 121. Wherein, the second conductor layer 3 is formed by deposition, for example. The indium tin oxide (ITO) layer or indium zinc oxide (IZ0) layer formed by the method is used as the lower electrode or the pixel electrode. Please refer to Figures 14A and 14B for compliance ( conf 〇rma 1) a passivation layer (pas si vat ion layer) 1 41 0 on the gate insulating layer 111 〇, the second conductor layer 1310, the TFT structure, the data line 1 250 and the gate line 1 0 1 0. Then, a fourth lithography etching step (pEp_ 丨 v) is performed to form a first via hole 1420 penetrating the passivation layer 1410 to expose the passivation layer 1410. The surface of the electrode 1 2 3 0. The passivation layer 1 41 0 is a dielectric layer such as silicon nitride (SiNx) formed by a deposition method, and is used as a dielectric in the storage capacitor Cs. Electrical layer. Please refer to Figures 5 A and 15 B to form a planarization layer.
540128 五、發明說明（12) (planarization layer)1510 於該鈍化層 141〇 上，並填入 該第一介層洞1 4 2 0。然後，進行第五道微影蝕刻步驟 (PEP-V)而形成一第二介層洞1520及一第三介層洞1530穿 透該平坦化層1510，其中，該第二介層洞152〇係露出該源 極1 2 3 0的表面，該第三介層洞1 5 3 〇係露出位在該電容區 1 0 0 1的該鈍化層1 4 1 0表面。其中，該平坦化層丨5丨〇例如係 由旋塗法（spin coating)所形成的旋塗式玻璃層（s〇G)或 有機層（即由「有機平坦化材料」所組成）。 請參照第1 6A、1 6B圖，進行一沉積製程與第六道微影 #刻步驟（PEP-V I )而形成順應性的一第三導體層丨6丨〇於部 分該平坦化層1 5 1 0上，並與該源極丨2 3 〇電性連接。其中， 位在該電容區1001的該第二導體層1310、該鈍化層/41〇與 該第三導體層1610係構成一儲存電容Cs結構。其中，該第 三導體層1610例如係由沉積法所形成的銦錫氧化物（IT〇) 層’用以當作是上電極或電荷收集電極（charge col lector electrode) ° [本發明之主要步驟與優點] 本發明之主要步驟包括：形成一閘極於一基底上，該 基底具有一電谷區與一電晶體區。形成一閘極絕緣層於該 閘極及該基底上。形成一矽島於位在該電晶體區的該閘極 絕緣層上。形成一共同線於該閘極絕緣層上，並且形成一 源/汲極於该矽島上而構成一薄膜電晶體（71?了）結構。形成 一晝素電極於位在該電容區的該閘極氧化層上，且覆蓋該540128 V. Description of the invention (12) (planarization layer) 1510 is placed on the passivation layer 1410, and the first via hole 1420 is filled. Then, a fifth lithography etching step (PEP-V) is performed to form a second via hole 1520 and a third via hole 1530 to penetrate the planarization layer 1510, wherein the second via hole 152 is formed. The surface of the source electrode 1230 is exposed, and the third via hole 1530 is exposed at the surface of the passivation layer 1410 located in the capacitor region 1001. The planarizing layer 5 is, for example, a spin-on glass layer (sog) or an organic layer (that is, an organic planarizing material) formed by a spin coating method. Referring to FIGS. 16A and 16B, a deposition process and a sixth lithography #etching step (PEP-V I) are performed to form a conformable third conductor layer. 6 and a part of the planarization layer 1 5 1 0 and is electrically connected to the source 丨 2 3 〇. Wherein, the second conductor layer 1310, the passivation layer / 410 and the third conductor layer 1610 located in the capacitor region 1001 form a storage capacitor Cs structure. The third conductor layer 1610 is, for example, an indium tin oxide (IT0) layer formed by a deposition method, and is used as an upper electrode or a charge col lector electrode. [Main steps of the present invention And advantages] The main steps of the present invention include: forming a gate on a substrate, the substrate having a valley region and a transistor region. A gate insulating layer is formed on the gate and the substrate. A silicon island is formed on the gate insulating layer of the transistor region. A common line is formed on the gate insulating layer, and a source / drain is formed on the silicon island to form a thin film transistor (71?) Structure. Forming a day electrode on the gate oxide layer in the capacitor region, and covering the gate oxide layer
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第 15 頁0611-7910TWF (N); A02004; Jacky.ptd page 15
540128 五、發明說明（13) 共同線。形成順應性的一鈍化層於該閘極氧化層、該晝素 電極與該TFT結構上。形成一第一介層洞穿透該鈍化層， 而露出該源極的表面。形成一平坦化層於該鈍化層上，並 填入該第一介層洞。形成一第二介層洞及一第三介層洞穿 透該平坦化層，其中，該第二介層洞係露出該源極的表 面，、該第^介層洞係露出位在該電容區的該鈍化層表面。 形成一電荷收集電極於部分該平坦化層上，並與該源極 性連接。 如此，經由比較習知技術與本發明，本發明之優點 少有： μ (a) 由於儲存電容Cs .中的介電層71〇， 141〇與打了的 極絕緣層3 3 0， 1 1 1 〇係不同層，所以本發明可以符合儲 電容Cs與TFT對於絕緣層特性的不同需求。 (b) 由於在共同線510，1210上方製作儲存電容Cs， 以本發明可以節省元件面積。 (c) 由於共同線5 1〇， 1210下方並不需要和下電極（全 素電極）610，1310電性連接，所以本發明可以相容灰調 影（gray-tone photolithography，亦稱為狹縫（sli ^ 影）TFT製程，使得本發明僅需六道微影蝕刻步 ^ 少製造成本。 M r^減 1 4 1 0係能夠同時 的保護層，所以 護層而必須增力口 (d)由於本發明製程中的鈍化層71〇, 地當作是儲存電容Cs的介電層與TFT通道 不必像習知般地為了要形成TFT通道的保 一道微影餘刻步驟。540128 V. Description of the invention (13) Common line. A compliant passivation layer is formed on the gate oxide layer, the day electrode and the TFT structure. A first via hole is formed to penetrate the passivation layer and expose the surface of the source electrode. A planarization layer is formed on the passivation layer, and the first via hole is filled. Forming a second via hole and a third via hole penetrating the planarization layer, wherein the second via hole is exposed from the surface of the source electrode, and the third via hole is exposed at the capacitor; Surface of the passivation layer. A charge collection electrode is formed on a part of the planarization layer and is connected to the source. In this way, by comparing the conventional technology with the present invention, the advantages of the present invention are rare: μ (a) due to the dielectric layers 71, 141, and the polarized insulating layer 3 3 0, 1 1 in the storage capacitor Cs. 10 is different layers, so the present invention can meet the different requirements of the storage capacitor Cs and TFT for the characteristics of the insulating layer. (b) Since the storage capacitor Cs is fabricated above the common lines 510 and 1210, the device area can be saved by the present invention. (c) Since the common lines 5 10 and 1210 do not need to be electrically connected to the lower electrodes (all-velocity electrodes) 610 and 1310, the present invention is compatible with gray-tone photolithography (also known as slits) (Sli ^ shadow) TFT process, so that the present invention requires only six lithographic etching steps ^ reduce manufacturing costs. M r ^ minus 1 4 1 0 can be a protective layer at the same time, so the protective layer must be strengthened (d) because In the process of the present invention, the passivation layer 71 is used as the dielectric layer of the storage capacitor Cs and the TFT channel does not need to be a lithography step to form a TFT channel to protect the TFT channel.
540128 五、發明說明（14) 以較佳實施例揭露如上，然其並非用以限定本發明的 範圍，任何熟習此項技藝者，在不脫離本發明之精神和範 圍内，當可做些許的更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。540128 V. Description of the invention (14) The above is disclosed in the preferred embodiment, but it is not intended to limit the scope of the present invention. Any person skilled in the art can do some things without departing from the spirit and scope of the present invention Changes and retouching, so the protection scope of the present invention shall be determined by the scope of the appended patent application.
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第17頁 540128 圖式簡單說明 ^ 第1圖係顯示將光訊號轉成電子訊號的一種X光檢測儀 陣列之電路佈局圖； 第2 A圖係顯示習知的X光檢測儀陣列單元的上視圖； 第2B圖係顯示第2A圖的X光檢測儀陣列單元沿著C-C， 斷線的剖面圖； 第2C圖係顯示習知技術的一缺點圖； 第3 A〜9 A圖係顯示本發明第一實施例的X光檢測儀陣列 單元的製程剖面圖； 第3B〜9B圖係顯示本發明第一實施例的X光檢測儀陣列 單元的製程上視圖； 第9C圖係顯示本發明第一實施例之變化例的製程剖面 圖； 第9D圖係顯示第9C圖的上視圖； 第10A〜16Λ圖係顯示本發明第二實施例的X光檢測儀陣 列單元的製程剖面圖；以及 v p ^ i於明篦-f施例的X光檢測儀陣 第10B〜16B圖係顯示本《月弟一只 列單元的製程上視圖。 α制你士去亦 [註：上述的上視圖係透視圖，以利說▲ 要 部位的相關位置。] 電荷收集電極 擁存電容〜7 ; [圖示符號說明]: 第1圖之圖示符號 畫素〜3 ; 薄膜電晶體〜50611-7910TWF (N); A02004; Jacky.ptd Page 17 540128 Simple illustration ^ Figure 1 shows the circuit layout of an X-ray detector array that converts optical signals into electronic signals; Figure 2 A The top view of the conventional X-ray detector array unit is shown in FIG. 2B, which is a cross-sectional view of the X-ray detector array unit of FIG. 2A along CC and broken lines; FIG. 2C is a disadvantage of the conventional technology. 3A to 9A are sectional views showing the manufacturing process of the X-ray detector array unit according to the first embodiment of the present invention; FIGS. 3B to 9B are the X-ray detector array unit according to the first embodiment of the present invention; Top view of the manufacturing process; FIG. 9C is a process cross-sectional view showing a modification of the first embodiment of the present invention; FIG. 9D is a top view of FIG. 9C; and FIGS. 10A to 16Λ are X of the second embodiment of the present invention A cross-sectional view of the manufacturing process of the photodetector array unit; and Figures 10B-16B of the X-ray detector array in the example of vp ^ i in the Ming-f embodiment show the top view of the manufacturing process of a column unit of the moon brother. Alpha system you go [Note: The above top view is a perspective view, so Eli said that the relevant position of the main part. ] Charge collection electrode Possessing capacitance ~ 7; [Illustrated symbol description]: Symbol shown in Figure 1 Pixels ~ 3; Thin film transistor ~ 5
〇611-7910TWF(N) » A02004 ； Jacky.ptd 第18頁 540128 圖式簡單說明 晝素電極〜11。 第2A〜2C圖之圖示符號 基底〜20 0 ; 閘極〜2 0 5 ; 閘極線〜2 0 6 ; 第一閘極絕緣層〜210 ; 下電極（晝素電極）〜215 ; 第二閘極絕緣層〜2 2 0 ; a -Si 層〜22 5 ； η+ α -Si 層〜2 3 0 ； 第一介層洞〜2 3 5 ; 源極〜2 4 0 ; 汲極〜245 ; 資料線〜2 50 ; 平坦化層〜260 ; 第二介層洞〜265 ; 第三介層洞〜270 ; 第四介層洞〜275 ; 電荷收集電極〜280 ;儲存電容〜Cs ; 鈍化層290; 介層洞295。 電容區〜3 0 1 ; 閘極線〜3 1 0 ; 閘極絕緣層〜3 3 0 n+ CK -Si 層〜420 ·， 資料線〜5 20 ; 沒極5 4 0 ; 第3A〜9A、3B〜9B、9C〜9D圖之圖示符號 基底〜3 0 0 ; 電晶體區〜3 0 2 ; 閘極〜3 2 0 ; α - S i 層〜41 0 ； 共同線〜510 ; 源極5 3 0 ; 下電極（晝素電極）〜610 ; 純化層〜710 ; 第一介層洞〜720〇611-7910TWF (N) »A02004; Jacky.ptd P.18 540128 Schematic description of simple day electrode ~ 11. Figure 2A to 2C. Symbol base ~ 20 0; gate ~ 2 05; gate wire ~ 2 06; first gate insulating layer ~ 210; lower electrode (day electrode) ~ 215; second Gate insulation layer ~ 2 2 0; a -Si layer ~ 22 5; η + α -Si layer ~ 2 3 0; first via hole ~ 2 3 5; source ~ 2 4 0; drain ~ 245; Data line ~ 2 50; planarization layer ~ 260; second via hole ~ 265; third via hole ~ 270; fourth via hole ~ 275; charge collecting electrode ~ 280; storage capacitor ~ Cs; passivation layer 290 Mesoscopic hole 295 .; Capacitance area ~ 3 0 1; Gate line ~ 3 1 0; Gate insulation layer ~ 3 3 0 n + CK -Si layer ~ 420 ·, Data line ~ 5 20; No pole 5 4 0; No. 3A ~ 9A, 3B ~ 9B, 9C ~ 9D diagram symbol base ~ 3 0 0; transistor region ~ 3 2 2; gate ~ 3 2 0; α-S i layer ~ 41 0; common line ~ 510; source 5 3 0; lower electrode (day electrode) ~ 610; purification layer ~ 710; first via hole ~ 720
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第19頁 5401280611-7910TWF (N); A02004; Jacky.ptd page 19 540128
平坦化層〜810， 第二介層洞〜820、820，； 第一"層洞8 3 0 ,上電極（電荷收集電極）〜9 1 0 儲存電容〜Cs。 第10A〜16A、：ίΟΒ〜16B 圖 基底〜1 000 ; 電晶體區〜1 0 0 2 ; 閘極〜1 0 2 0 ; α -S i 層〜11 2 0 ； 第一導體層〜1140 共同線〜1210 ; 源極〜1 230 ; 資料線〜1 25 0 ; 下電極（畫素電極） 夺號 電谷區〜1001 ; 閘極線〜1 〇 1 〇 ; 閘極絕緣層〜1 1 1 〇 ; η+ α -Si 層〜1130 ; ; 灰調光阻圖案1 1 5 0 ; 第一半導體島1 220 ; >及極〜1 2 4 0 ; 第二半導體島〜1260 ; 〜1310 ; 鈍化層〜1 4 1 0 ; 第一介層洞〜1 4 2 0 ; 平坦化層〜1 5 1 0 ; 第二介層洞〜1 5 2 0 ; 第三介層洞〜1 530 ;上電極（電荷收集電極）〜161〇 ; 儲存電容〜Cs。The planarization layer is ~ 810, the second interlayer hole is ~ 820, 820; the first " layer hole is 8 3 0, the upper electrode (charge collecting electrode) is ~ 9 1 0, and the storage capacitor is ~ Cs. 10A ~ 16A ,: ΙΟΒ ~ 16B, drawing base ~ 1 000; transistor region ~ 1 0 2; gate ~ 1 0 2 0; α -S i layer ~ 11 2 0; first conductor layer ~ 1140 common line ~ 1210; source ~ 1 230; data line ~ 1 250; lower electrode (pixel electrode); electric valley area ~ 1001; gate line ~ 1 〇1 〇; gate insulation ~ 1 1 1 〇; η + α-Si layer ~ 1130;; gray-tone photoresist pattern 1150; first semiconductor island 1220; > and poles ~ 1240; second semiconductor island ~ 1260; ~ 1310; passivation layer ~ 1 4 1 0; first vias ~ 1 2 2 0; planarization layers ~ 15 1 0; second vias ~ 15 2 0; third vias ~ 1 530; upper electrode (charge collection Electrode) ~ 161〇; storage capacitor ~ Cs.
0611-7910TWF(N) ； A02004 ； Jacky.ptd 第20頁0611-7910TWF (N); A02004; Jacky.ptd page 20
Claims (1)
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091115597A TW540128B (en) | 2002-07-12 | 2002-07-12 | Manufacturing method of X-ray detector array |
| US10/367,756 US6764900B2 (en) | 2002-07-12 | 2003-02-19 | Method of fabricating an X-ray detector array element |
| KR10-2003-0032457A KR100531047B1 (en) | 2002-07-12 | 2003-05-22 | Method of Fabricating an X-Ray detector array Element |
| JP2003273628A JP4563661B2 (en) | 2002-07-12 | 2003-07-11 | Method for manufacturing an X-ray detection array element |
| US10/790,004 US6949426B2 (en) | 2002-07-12 | 2004-03-02 | Method of fabricating an X-ray detector array element |
| US10/834,867 US7259037B2 (en) | 2002-07-12 | 2004-04-30 | Method of fabricating an X-ray detector array element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091115597A TW540128B (en) | 2002-07-12 | 2002-07-12 | Manufacturing method of X-ray detector array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW540128B true TW540128B (en) | 2003-07-01 |
Family
ID=29580737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW091115597A TW540128B (en) | 2002-07-12 | 2002-07-12 | Manufacturing method of X-ray detector array |
Country Status (4)
| Country | Link |
|---|---|
| US (3) | US6764900B2 (en) |
| JP (1) | JP4563661B2 (en) |
| KR (1) | KR100531047B1 (en) |
| TW (1) | TW540128B (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW540128B (en) * | 2002-07-12 | 2003-07-01 | Hannstar Display Corp | Manufacturing method of X-ray detector array |
| KR100556701B1 (en) * | 2003-10-14 | 2006-03-07 | 엘지.필립스 엘시디 주식회사 | Thin Film Transistor Substrate for Display Device And Method For Fabricating The Same |
| TWI228782B (en) * | 2004-01-19 | 2005-03-01 | Toppoly Optoelectronics Corp | Method of fabricating display panel |
| TWI287869B (en) * | 2005-02-16 | 2007-10-01 | Hannstar Display Corp | Structure and manufacturing method of imager array unit |
| US8053777B2 (en) * | 2005-03-31 | 2011-11-08 | General Electric Company | Thin film transistors for imaging system and method of making the same |
| US7411213B2 (en) * | 2006-04-03 | 2008-08-12 | Chunghwa Picture Tubes, Ltd. | Pixel structure, thin film transistor array substrate and liquid crystal display panel |
| JP4908935B2 (en) * | 2006-06-09 | 2012-04-04 | キヤノン株式会社 | Photoelectric conversion device and imaging system |
| KR101218089B1 (en) * | 2007-12-07 | 2013-01-18 | 엘지디스플레이 주식회사 | Digital x-ray detector and method of fabricating the same |
| JP4844767B2 (en) * | 2008-10-03 | 2011-12-28 | ソニー株式会社 | THIN FILM TRANSISTOR, METHOD FOR PRODUCING THIN FILM TRANSISTOR, AND ELECTRONIC DEVICE |
| KR20100082631A (en) * | 2009-01-09 | 2010-07-19 | 삼성전자주식회사 | X-ray detector and manufacturing method same of |
| KR101094288B1 (en) * | 2010-01-27 | 2011-12-19 | 삼성모바일디스플레이주식회사 | X-ray detector |
| US8537852B2 (en) * | 2010-05-07 | 2013-09-17 | Tyco Electronics Subsea Communications, Llc | Configuration and operation of inverse multiplexing communication system |
| US9275561B2 (en) | 2010-11-09 | 2016-03-01 | Samsung Display Co., Ltd. | Optical adhesive film and flat panel display device having the same |
| CN102403329B (en) * | 2011-11-01 | 2014-12-17 | 上海奕瑞光电子科技有限公司 | Low-temperature polysilicon thin film transistor detector and preparation method thereof |
| TWI451179B (en) * | 2011-11-17 | 2014-09-01 | Au Optronics Corp | Pixel structure and manufacturing method thereof |
| JP5963551B2 (en) | 2012-06-06 | 2016-08-03 | キヤノン株式会社 | Active matrix panel, detection device, and detection system |
| US9935152B2 (en) | 2012-12-27 | 2018-04-03 | General Electric Company | X-ray detector having improved noise performance |
| US8986921B2 (en) * | 2013-01-15 | 2015-03-24 | International Business Machines Corporation | Lithographic material stack including a metal-compound hard mask |
| CN103107135B (en) * | 2013-02-19 | 2016-01-06 | 京东方科技集团股份有限公司 | A kind of manufacture method of array base palte, array base palte and display unit |
| US9780140B2 (en) * | 2013-08-07 | 2017-10-03 | Sharp Kabushiki Kaisha | X-ray image sensor substrate |
| US9917133B2 (en) | 2013-12-12 | 2018-03-13 | General Electric Company | Optoelectronic device with flexible substrate |
| EP3117204B1 (en) | 2014-03-13 | 2021-06-16 | General Electric Company | Curved digital x-ray detector for weld inspection |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4417325A (en) * | 1981-07-13 | 1983-11-22 | Eliyahou Harari | Highly scaleable dynamic ram cell with self-signal amplification |
| US5688709A (en) * | 1996-02-14 | 1997-11-18 | Lsi Logic Corporation | Method for forming composite trench-fin capacitors for DRAMS |
| US6060714A (en) * | 1998-01-23 | 2000-05-09 | Ois Optical Imaging Systems, Inc. | Large area imager with photo-imageable interface barrier layer |
| US6323490B1 (en) * | 1998-03-20 | 2001-11-27 | Kabushiki Kaisha Toshiba | X-ray semiconductor detector |
| US6440814B1 (en) * | 1998-12-30 | 2002-08-27 | Stmicroelectronics, Inc. | Electrostatic discharge protection for sensors |
| US6560217B1 (en) * | 1999-02-25 | 2003-05-06 | 3Com Corporation | Virtual home agent service using software-replicated home agents |
| JP3683463B2 (en) * | 1999-03-11 | 2005-08-17 | シャープ株式会社 | Active matrix substrate, manufacturing method thereof, and image sensor using the substrate |
| JP3469143B2 (en) * | 1999-11-02 | 2003-11-25 | シャープ株式会社 | Active matrix substrate and two-dimensional image detector having the same |
| JP2001177103A (en) * | 1999-12-20 | 2001-06-29 | Sony Corp | Thin film semiconductor device, display device, and method of manufacturing the same |
| KR100477788B1 (en) * | 1999-12-28 | 2005-03-22 | 매그나칩 반도체 유한회사 | Method for fabricating CMOS image sensor having photodiode coupled capacitor |
| KR100630880B1 (en) * | 1999-12-31 | 2006-10-02 | 엘지.필립스 엘시디 주식회사 | X-ray image sensor and a method for fabricating the same |
| KR100344777B1 (en) * | 2000-02-28 | 2002-07-20 | 엘지.필립스 엘시디 주식회사 | method for forming device having a thin film transistor |
| JP2002190598A (en) * | 2000-12-20 | 2002-07-05 | Matsushita Electric Ind Co Ltd | Thin-film transistor array substrate and method of manufacturing the same |
| KR100732877B1 (en) * | 2001-08-21 | 2007-06-27 | 엘지.필립스 엘시디 주식회사 | X-ray detecter and manufacturing method of the same |
| KR100527087B1 (en) * | 2001-12-22 | 2005-11-09 | 비오이 하이디스 테크놀로지 주식회사 | Method of fabricating X-ray detector |
| TW544946B (en) | 2002-07-12 | 2003-08-01 | Hannstar Display Corp | Manufacturing method of X-ray inspecting instrument array unit |
| TW540128B (en) * | 2002-07-12 | 2003-07-01 | Hannstar Display Corp | Manufacturing method of X-ray detector array |
-
2002
- 2002-07-12 TW TW091115597A patent/TW540128B/en not_active IP Right Cessation
-
2003
- 2003-02-19 US US10/367,756 patent/US6764900B2/en not_active Expired - Lifetime
- 2003-05-22 KR KR10-2003-0032457A patent/KR100531047B1/en active IP Right Grant
- 2003-07-11 JP JP2003273628A patent/JP4563661B2/en not_active Expired - Fee Related
-
2004
- 2004-03-02 US US10/790,004 patent/US6949426B2/en not_active Expired - Lifetime
- 2004-04-30 US US10/834,867 patent/US7259037B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR100531047B1 (en) | 2005-11-28 |
| US6949426B2 (en) | 2005-09-27 |
| US20040009621A1 (en) | 2004-01-15 |
| JP2004040115A (en) | 2004-02-05 |
| US6764900B2 (en) | 2004-07-20 |
| KR20040007247A (en) | 2004-01-24 |
| JP4563661B2 (en) | 2010-10-13 |
| US7259037B2 (en) | 2007-08-21 |
| US20040203202A1 (en) | 2004-10-14 |
| US20040166613A1 (en) | 2004-08-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW540128B (en) | Manufacturing method of X-ray detector array | |
| US9761731B2 (en) | Thin film transistor and its manufacturing method, array substrate and its manufacturing method, and display device | |
| CN109360828B (en) | Display substrate, manufacturing method thereof and display device | |
| US6740884B2 (en) | Imaging array and methods for fabricating same | |
| WO2016023294A1 (en) | Array substrate, manufacturing method and display device | |
| TW544946B (en) | Manufacturing method of X-ray inspecting instrument array unit | |
| CN115995470A (en) | Display substrate, manufacturing method thereof and display device | |
| US6777685B2 (en) | Imaging array and methods for fabricating same | |
| JP4600964B2 (en) | Solid-state imager having gated photodiode and method for manufacturing the same | |
| CN110854175B (en) | Array substrate, preparation method thereof and display panel | |
| KR102600693B1 (en) | Apparatus and Manufacturing Method of Thin Film Transistor Array Substrate | |
| CN101118881A (en) | Method for fabricating pixel structure | |
| TW200816490A (en) | Display device and method of manufacturing the display device | |
| CN108550595B (en) | X-ray detector array substrate, manufacturing method thereof and X-ray detector | |
| CN105765709A (en) | Array substrate and preparation method thereof, display panel and display device | |
| CN101197332A (en) | Pixel structure manufacturing method | |
| TW200832696A (en) | Display panel and method for manufacturing thin film transistor substrate thereof | |
| JP4478215B2 (en) | Corrosion resistant imaging device | |
| CN101022093B (en) | Method for producing picture element structure | |
| CN102097390B (en) | Manufacturing method of pixel structure | |
| JP5402211B2 (en) | Method for manufacturing photoelectric conversion device | |
| CN1210561C (en) | Method for making x-ray detector display unit | |
| CN113488543B (en) | Thin film transistor, preparation method thereof and display panel | |
| CN1208616C (en) | Method for making x-ray detector display unit | |
| CN210182385U (en) | Array substrate, touch display panel and touch display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4A | Issue of patent certificate for granted invention patent | ||
| MM4A | Annulment or lapse of patent due to non-payment of fees |