533508 經濟部智¾財是^Μ工消費合作社印製 Λ7 B7五、發明説明（） 5 -1發明領域： 本發明係有關於一種半導體積體電路之結構與製造方 法，特別是有關於一種可防止具有多層重疊導線之層間介 電層發生破裂的結構，以及其製造方法。 5-2發明背景： 隨著積體電路的積集度增高，由單一層的半導體電子 元件與金屬導線，在面對日益複雜的電路設計已經不敷使 用。因此，利用多重内連線（Multilevel Interconnects) 的製程，可以讓電路的佈局由二度空間的平面轉變為立體 的架構，而使得半導體積體電路的體積可以更為縮小。以 0. 2 5 u m的半導體製程為例，為了因應日趨複雜的電路設 計，以及更進一步的縮小積體電路的體積，其電路佈局常 常需要在第一層的電路層上，重複的堆疊許多的金屬導線 層。這樣的金屬導線層往往會累積到五層甚至五層以上的 規模，而面對這樣複雜的積體電路佈局時，則必須遭遇到 一些全新的製程挑戰。 在一般半導體之多重内連線的製程中，當底材 (Substrate)上的電子元件开》成之後，會進一步的於其表 面覆蓋一層介電層（Dielectric Layer)以保護其中的電 子元件並與外界的環境隔絕。接著會在此介電層的某些特 定位置上形成接觸窗（Contact Hole)，以曝露出該電子 (請先閱讀背面之注意事項再填寫本頁 -裝·533508 Intellectual property of the Ministry of Economic Affairs is printed by ^ 7 Industrial Cooperative Cooperative Association Λ7 B7 V. Description of the Invention (1) Field of Invention: The present invention relates to a structure and manufacturing method of a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit. Structure for preventing cracking of interlayer dielectric layer with multiple overlapping wires, and manufacturing method thereof. 5-2 Background of the Invention: As the integration degree of integrated circuits increases, single-layer semiconductor electronic components and metal wires have become inadequate in the face of increasingly complex circuit designs. Therefore, by using the process of multilevel interconnects, the layout of the circuit can be changed from a two-dimensional plane to a three-dimensional structure, so that the volume of the semiconductor integrated circuit can be further reduced. Taking a semiconductor process of 0.2 5 um as an example, in order to cope with increasingly complicated circuit designs and further reduce the size of integrated circuits, its circuit layout often needs to be repeatedly stacked on the first circuit layer. Metal wire layer. Such metal wire layers tend to accumulate to a scale of five or more layers. When facing such a complex integrated circuit layout, it must encounter some new process challenges. In the process of multiple interconnects of general semiconductors, when the electronic components on the substrate are opened, a surface is further covered with a dielectric layer to protect the electronic components and communicate with them. The external environment is isolated. Contact holes will then be formed at certain specific positions of this dielectric layer to expose the electrons (please read the precautions on the back before filling this page -installation ·
、1T 線 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 533508 經濟部智您財4^工//]骨合作社印紫 五、發明説明（） 元件上預定要與外界導通的節點。接著於接觸窗中填滿導 電材料以形成所謂的插塞（P 1 ug )，再於這些插塞之上形 成金屬導線’並以這些導線為基礎進行第二層的電路佈 局。當第二層的電子元件製作完成後，同樣的於其上再沈 積一層界電薄膜以完成第二層的電路架構。同理，此一多 重内連線製程可以依據設計上的要求而重複的向上堆疊， 以完成整個積體電路的結構。 然而當此含有金屬導線的金屬間介電層（I n t e r - M e t a 1 D i e 1 e c t r i c )越堆越高時，常會使得整個結構發生一些缺 陷。第1圖顯示了一個含有多層金屬間介電層之半導體結 構發生裂縫的情形。如圖中所示，一個多層的半導體結構 100，包含有底材102、電子元件層104、第一金屬間介電 層106、第二金屬間介電層108、第三金屬間介電層110, 與第四金屬間介電層11 2。各個金屬間介電層間透過金屬 導線11 4與插塞1 1 6相互通連。當製程中的線寬縮小至一 定程度時（如，0. 2 5 um )，此結構中的金屬間介電層將變 得結為脆弱而容易發生裂缝。一但此結構受到一些外力作 用時，常常會使這些金屬間介電層中發生諸如裂缝1 1 8所 表示的缺陷。而這樣的缺陷將使得製程良率大為降低造成 了大量的製程損失，並大為降低了積體電路的電性、耐用 性以及結構強度。 綜上所述，亟需要發展一種新的製程技術，以克服上 述之多重金屬間介電層結構中所發生的裂縫現象。以期提 高半導體積體電路的製程良率，同時增加其結構與各種材 (請先閲讀背面之注意事項再填寫本頁 裝- 訂 線 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） 533508 五 ___ 經濟部智葱財/1^78(工消費合作社印製 A? B7 昏明説明（） 料性質的可靠度。 5-3發明目的及概述： 本發明之目的為在提供一種應用於半導體積體電路中 的結構，以防止多重内連線中的介電層發生裂缝。 本發明之又一目的在提供一種製程方法，使得所製造 出之具有多層金屬間介電層之半導體結構不會發生裂縫。 本發明之在一目的為透過上述方法與結構的揭露，使 得多重内連線製程中的堆疊層數可以因而提高，製程的線 寬也可以因而縮短。 本發明揭露了一種防止多重金屬間介電層發生裂缝的 結構與方法。此一結構係透過選擇性的各個金屬間介電層 之間，嵌入具有殘留壓縮應力的氧化層，並藉由此一壓縮 應力氧化層所提供的束縛力，而防止半導體結構中的内金 屬應力層中產生裂縫。其中此嵌入的壓縮應力氧化層將不 限於一層，而所應用的多重金屬間介電層之結構，亦不限 於特定的層數。 而此一壓縮應力層的嵌入方法，則可以透過對形成的 金屬間介電層表面進行研磨。當其表面研磨至一定的厚度 時，隨後以電漿化學氣相沈積（PECVD )的製程，於其表面 沈積一層氧化層，並於其製程反應時調整其射頻能量（RF P 〇 w e r )，以得到所需之具有殘留壓縮應力的壓縮應力氧化 層。 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公漦） 533508 A7 B7 五、發明説明（ 5-4圖式簡單說明： 經濟部智慧財/i^g (工消費合作社印製 第 1 1 圖 為 傳 統 上 含 有 多 重 金 屬 間 介 電 層 之 半 導 體 結 構 的 層 間 缺 陷 示 意 圖 〇 第 2A 圖 為 本 發 明 中 多 重 金 屬 間 介 電 層 之 缺 陷 形 成 機 構 示 意 圖 0 第 2B 圖 為 本 發 明 中 多 重 金 屬 間 介 電 層 之 缺 陷 形 成 機 構 示 意 圖 0 第 3A 圖 為 本 發 明 中 多 重 金 屬 間 介 電 層 之 缺 陷 形 成 機 構 示 意 圖 0 第 3B 圖 為 本 發 明 中 多 重 金 屬 間 介 電 層 之 缺 陷 形 成 機 構 示 意 圖 0 第 4 圖 為 本 發 明 中 一 個 具 有 M0S 電 晶 體 之 半 導 體 結 構 截 面 圖 〇 第 5 圖 為 本 發 明 中 具 有 插 塞 與 金 屬 導 電 層 之 半 導 體 結 構 截 面 圖 〇 第 6 圖 為 本 發 明 中 相 鄰 金 屬 層 上 沈 積 金 屬 間 介 電 層 之 截 面 圖 0 第 7 圖 為 本 發 明 中 嵌 入 壓 縮 應 力 層 之 截 面 圖 〇 第 8 圖 為 本 發 明 中 具 有 壓 縮 應 力 層 之 含 有 多 重 金 屬 間 介 電 層 之 半 導 體 結 構 的 之 剖 面 圖 0 5 - 5發明詳細說明： 請 先 閱 讀 背面 意 事 項 再 寫 本 頁 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 533508 Λ7 B7 五、發明説明（） 本發明將首先介紹各種多重金屬間介電層中的裂缝機 構。接著以一個實施例來說明本發明之製造方法及程序。 再以一個較佳的實施例來說明本發明所揭露之用以防止多 重金屬間介電層之裂縫的半導體結構。 參閱第2A、2B圖，顯示了 一種發生於多重金屬間介電 層中的潛在裂縫機構。如第2 A圖中所表示，介電層2 0 2的 表面曝露出了兩條導線2 04a、204b。其中介電層2 0 2可以 是一層位於底材上，用以覆蓋半導體電子元件之内介電 層，也可以是位於此内介電層上方重複堆疊的任何一層的 金屬間介電層。而此介電層2 0 2之介電材料的選用可以依 照不同的製程條件而有所不同，一般常見的介電材料 Si〇2、Si3N4、PSG，與BPSG皆可以依照需作為介電層的材 料。至於導線204a與2 0 4b則作為半導體結構中不同層間 電流溝通的橋樑，多為金屬材質，例如鋁即為其中常見的 金屬導線的材料。 經濟部智总財產钧員工消費合作社印^ 接著覆蓋一層介電層於金屬導線204a、2 04b，以及内 介電層2 0 2的表面。以化學氣相薄膜沈積製程（CMP )為例， 圖中2 0 6顯示了沈積開始時的剖面圖。由於導線2 04a與 2 0 4b的距離相當的靠近，因此當沈積開始進行時，介電材 料會沿著導線2 0 4a與2 0 4b的週邊開始沈積，並依著箭號 2 0 8所指示的方向，向著凹槽的2 1 0中央漸次堆積。 參閱第2B圖，當凹槽210被填滿之後，介電層20 6會 形成如圖中所示大致平坦的結構。然而，填滿凹槽2 1 0的 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） 533508 A 7 H7 五、發明説明（） 過程中，介電材料係由凹槽的週邊區域漸次向中心堆積， 於是在堆積的過程中，兩側的介電材料會向中央相互擠 壓。當沈積完成後即會形成一個如虛線2 1 2所示之具有高 殘留應力的界面。在某些深寬比（Aspect Ratio)很大的 實施例中，此一應力集中界面甚至會形成一塊中空的區 域，而增高了發生破裂的危機。也因著界面21 2，當此半 導體結構受到一些應力作用時，例如進行表面平坦化處理 時，很容易會沿著應力集中界面21 2而發生裂缝。 參閱第3A、3B圖顯示了另一種的潛在裂縫機構。如第 3A圖中所表示的半導體結構，其中包含了介電層302與曝 露於其上的導線304a與3 0 4b。如同前文所述，介電層302 可以是直接沈積於底材上的内介電層，亦可以是重複堆積 於其上的金屬間介電層。接著，於導線3 0 4a、3 0 4b與底材 3 0 2的表面上沈積一層介電材料。第3 A圖顯示了沈積剛開 始時的半導體結構剖面圖。當溝槽3 1 4的深寬比稍微較第 2A、2B圖之實施例為小時，常可以見到另一種形式的應力 集中界面。 如第3 A圖所示，當沈積開始發生時，介電材料會堆積 於導線304a與304b中間之内介電層302的表面以形成如 圖中所示之三角形堆積 3 1 6。同時介電材料亦會沿著導線 3 0 4 a與3 0 4 b的週邊向凹槽3 1 4的内側堆積。由於三角堆 積3 1 6會沿著箭號3 1 0的方向向外擴張，而位於凹槽週邊 的介電材料亦會沿著箭號3 0 8的方向漸次向下向内成長。 因此在沈積介電材料的過程中，即會發生由於沈積界面相 本紙張尺度適用中國國家標準（C’NS ) Λ4規格（210X 297公漦） (請先閱讀背面之注意事項寫本頁) -裝· 、\# 經濟部智慧財4¾¾工消費合作社印製 533508 發明説明 A7 B7 經濟部智慈財/l.^M工消費合作社印製1. The paper size of the 1T line is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 533508 Wisdom of the Ministry of Economic Affairs 4 ^ 工 //] Bone Cooperative Printed Purple 5. Description of the invention () The component is scheduled to communicate with the outside world Node. Then, the contact window is filled with conductive material to form so-called plugs (P 1 ug), and then metal wires are formed on these plugs, and a second layer of circuit layout is performed based on these wires. After the second layer of electronic components is completed, a layer of boundary film is also deposited thereon to complete the circuit structure of the second layer. In the same way, this multi-layer interconnection process can be repeatedly stacked up according to the design requirements to complete the structure of the integrated circuit. However, when this intermetal dielectric layer (I n t e r-Me t a 1 D i e 1 e c t r c) containing metal wires is higher and higher, it often causes some defects in the entire structure. Figure 1 shows a crack in a semiconductor structure containing multiple intermetal dielectric layers. As shown in the figure, a multilayer semiconductor structure 100 includes a substrate 102, an electronic component layer 104, a first intermetal dielectric layer 106, a second intermetal dielectric layer 108, and a third intermetal dielectric layer 110. And the fourth intermetallic dielectric layer 112. The intermetal dielectric layers are in communication with each other through the metal wires 11 4 and the plugs 1 1 6. When the line width in the process is reduced to a certain degree (for example, 0.2 5 um), the intermetallic dielectric layer in this structure will become brittle and prone to cracks. When the structure is subjected to some external force, defects such as those indicated by cracks 1 1 8 often occur in these intermetal dielectric layers. Such defects will greatly reduce the process yield and cause a large number of process losses, and greatly reduce the electrical properties, durability and structural strength of the integrated circuit. In summary, there is an urgent need to develop a new process technology to overcome the crack phenomenon that occurs in the above-mentioned multiple intermetal dielectric layer structure. With a view to improving the process yield of semiconductor integrated circuits, at the same time increasing its structure and various materials (please read the precautions on the back before filling in this page. ) 533508 Five ___ Ministry of Economic Affairs, Zhi Congcai / 1 ^ 78 (printed by the Industrial and Consumer Cooperatives A? B7 dim description () reliability of material properties. 5-3 Purpose and Summary of the Invention: The purpose of the present invention is to provide a A structure applied to a semiconductor integrated circuit to prevent cracks in a dielectric layer in multiple interconnects. Another object of the present invention is to provide a manufacturing method for a semiconductor having a multilayer intermetallic dielectric layer. No cracks will occur in the structure. One object of the present invention is to expose the above methods and structures, so that the number of stacked layers in the multiple interconnect process can be increased, and the line width of the process can be shortened. The present invention discloses a Structure and method for preventing cracks in multiple intermetal dielectric layers. This structure is formed by selective intermetal dielectric layers embedded with residual The compressive stress oxide layer and the binding force provided by the compressive stress oxide layer prevent cracks in the internal metal stress layer in the semiconductor structure. The embedded compressive stress oxide layer will not be limited to one layer, but The structure of the applied multiple intermetal dielectric layer is not limited to a specific number of layers. The embedding method of this compressive stress layer can be performed by grinding the surface of the formed intermetal dielectric layer. When the surface is ground to a certain level Then, a plasma chemical vapor deposition (PECVD) process is used to deposit an oxide layer on the surface, and the radio frequency energy (RF P 0wer) is adjusted during the process reaction to obtain the required residue. The compressive stress oxide layer of compressive stress. The paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X 297 cm) 533508 A7 B7 V. Description of the invention (5-4 Schematic illustration: Ministry of Economic Affairs Smart Money / i ^ g (Printed by Industry and Consumer Cooperatives Figure 11 is a schematic diagram of interlayer defects in a semiconductor structure that traditionally contains multiple intermetal dielectric layers.) Figure 2A is a schematic diagram of a defect formation mechanism of a multiple intermetal dielectric layer in the present invention. 0 Figure 2B is a schematic diagram of a defect formation mechanism of a multiple intermetal dielectric layer in the present invention. 0 Figure 3A is a multiple intermetal dielectric layer in the present invention. Schematic diagram of the defect formation mechanism of the layer 0 FIG. 3B is a schematic diagram of the defect formation mechanism of the multiple intermetallic dielectric layer in the present invention 0 FIG. 4 is a cross-sectional view of a semiconductor structure with a M0S transistor in the present invention. A cross-sectional view of a semiconductor structure having a plug and a metal conductive layer in it. FIG. 6 is a cross-sectional view of an intermetal dielectric layer deposited on an adjacent metal layer in the present invention. 〇 Figure 8 shows the pressure Sectional view of a semiconductor structure containing multiple intermetallic dielectric layers in a stress layer 0 5-5 Detailed description of the invention: Please read the notice on the back before writing this page. This paper applies the Chinese National Standard (CNS) A4 specification (210X297). (Centi) 533508 Λ7 B7 V. Description of the Invention () The present invention will first introduce crack mechanisms in various multi-metal dielectric layers. Next, an embodiment is used to explain the manufacturing method and procedure of the present invention. A preferred embodiment is used to describe the semiconductor structure disclosed in the present invention for preventing cracks in a dielectric layer between multiple metals. Referring to Figures 2A and 2B, a potential crack mechanism occurs in a multiple intermetal dielectric layer. As shown in FIG. 2A, the surface of the dielectric layer 202 exposes two wires 204a and 204b. The dielectric layer 202 may be a dielectric layer on a substrate to cover a semiconductor electronic device, or an intermetallic dielectric layer which is repeatedly stacked on top of this dielectric layer. The selection of the dielectric material of the dielectric layer 202 can be different according to different process conditions. Generally common dielectric materials Si02, Si3N4, PSG, and BPSG can be used as the dielectric layer according to the needs. material. As for the wires 204a and 204b, as bridges for current communication between different layers in a semiconductor structure, most of them are made of metal. For example, aluminum is a common metal wire. The Ministry of Economic Affairs and the Intellectual Property Co., Ltd. employee consumer cooperative seal ^ Then cover a layer of dielectric layer on the surface of the metal wires 204a, 204b, and the internal dielectric layer 202. Taking the chemical vapor thin film deposition process (CMP) as an example, the sectional view at the beginning of deposition is shown in FIG. Since the distance between the wires 2 04a and 20 4b is quite close, when the deposition is started, the dielectric material will be deposited along the periphery of the wires 2 0 4a and 2 0 4b, and indicated by the arrow 2 0 8 Direction, gradually accumulate toward the 2 10 center of the groove. Referring to FIG. 2B, after the groove 210 is filled, the dielectric layer 20 6 will form a substantially flat structure as shown in the figure. However, the size of this paper that fills the groove 2 1 0 is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 533508 A 7 H7 V. Description of the invention () In the process, the dielectric material is defined by the periphery of the groove Areas are gradually stacked toward the center, so during the stacking process, the dielectric materials on both sides will squeeze each other toward the center. When the deposition is complete, an interface with high residual stress is formed as shown by the dotted line 2 1 2. In some embodiments with a large aspect ratio, this stress concentration interface may even form a hollow area, which increases the risk of rupture. Because of the interface 21 2, when the semiconductor structure is subjected to some stress, for example, when the surface is flattened, cracks easily occur along the stress concentration interface 21 2. Refer to Figures 3A and 3B for another potential crack mechanism. The semiconductor structure shown in FIG. 3A includes a dielectric layer 302 and wires 304a and 3 0b exposed thereon. As mentioned above, the dielectric layer 302 may be an internal dielectric layer directly deposited on a substrate, or an intermetallic dielectric layer repeatedly stacked thereon. Next, a layer of dielectric material is deposited on the surfaces of the wires 3 0a, 3 4b and the substrate 3 2. Figure 3A shows a cross-sectional view of the semiconductor structure at the beginning of the deposition. When the aspect ratio of the grooves 3 1 4 is slightly smaller than that of the embodiment of Figs. 2A and 2B, another form of stress concentration interface can often be seen. As shown in FIG. 3A, when the deposition starts, a dielectric material will be deposited on the surface of the inner dielectric layer 302 between the wires 304a and 304b to form a triangular stack 3 1 6 as shown in the figure. At the same time, the dielectric material will also accumulate along the periphery of the wires 3 0 4 a and 3 0 4 b toward the inside of the groove 3 1 4. Since the triangular stack 3 1 6 will expand outward in the direction of the arrow 3 1 0, the dielectric material located around the groove will also gradually grow downward and inward in the direction of the arrow 3 0 8. Therefore, in the process of depositing dielectric materials, it will happen that the paper size of the deposition interface phase applies the Chinese National Standard (C'NS) Λ4 specification (210X 297 cm) (Please read the precautions on the back to write this page)- · ， ## Printed by the Ministry of Economic Affairs and Intellectual Property 4¾¾Printed by Industrial and Consumer Cooperatives 533508 Invention Description A7 B7 Printed by the Ministry of Economics and Intellectual Goods / l. ^ M Industrial Consumer Cooperatives
互擠壓所產生夕* 王之應力集中界面。 口 〇 T) ^ 圖所示，當金屬間介電層3〇β丄 即會形成無圖中 沈積完成之後， 上述的沈積機： 角形處'線312即代表著 積钱構所造成應力集中界面。间從丄 衣者 結構受到一此 门樣的當此半導體 任一側發生笋 力集中界面3 1 2的 又王衣縫。另外要加以說明的是， ^ 主要發生在劁妒^ α〜 上述之破裂機構 牡衣裎中線寬越縮越小，而 再 形下。因此，火 i層越璺越高的情 备上述破裂機構中的金屬缘 相似的半導俨姓 V線製換成其形狀 夺、4構時（如，相鄰的閘極） 結構形狀的44 Μ . 1 』位），也有可能因為 缝。故，=，而產生此中應力集中界面並進而發生裂 :金屬間介電層越叠越高後’半導體結構就越容 二 可—個應力集中的界面並橫跨幾個介電層而產生 裂縫。 口 =下將以一個實施例來介紹本發明之結構的製造過 /閱第4圖，顯示了一個半導體結構的截面圖。半導 體結構戴面40 0包含底材4〇2，與一個位於底材4〇2之上 的MOS電晶體41 2，其中有閘極406、源/汲極404a，與源 /汲極404b。在源/汲極4〇4a的旁邊有一個渠溝（Trench) 4〇8，用以隔絕M0S電晶體4丨2與其他週邊的電子元件相互 干擾與影響。在渠溝408之上有第一金屬層410作為導線 之用。 芩閱第5圖，於底材402、閘極406,與第一金屬層410 的表面覆蓋一層介電材料以形成内介電層512。一般而言， 化學氣相薄膜沈積製程（CVD )，以及其改進製程如，SACVD 本紙悵尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） (請先閱讀背面之注意事項3寫本頁) 裝· 訂 線 533508 A 7 B7 五、發明説明（ 經濟部智慧財是苟資工消骨合作社印製 (Sub-Atmospheric Γνη、 θ ^ ^ ^ ,, ^ 1CLVD)，是目前最常被使用的薄膜沈積 製程方法。至於一些常用的介電材料有Si〇2、 與BPSG，而這些材料都可以依照不同的製程需求加以應 用，本實施例之内介電層512則為SACVD製程所形成之氧 化層。而内介電層512的厚度也隨著不同製程而有所變 化，通常變化的範圍約在3KA〜5KA之間。接著於源/汲極 4〇4a與導線41〇的上方各開一個接觸窗，並於其中填 電材料以形成插塞518、516，使得底材4〇2上的電子元件 可以與外界形成電性連接。-般而言，常用的插塞材料有 多晶石夕⑺〇ySlllC0n)、石夕化轉（TungstenSiHcide)， 以及金屬4 ’至於其他特殊的導電材料亦可以視需求來製 作插基516、518。接著於插塞516、518的上方形成第二 金屬層514及第三金屬@ 5 2 2。纟此一個基本的半導體電 路結構於焉形成。接著，本實例將以區域50 2來說明由此 -基本的半導體結構，繼續往上堆疊半導體圖案的製作程 序。 一第6圖為區域5 0 2的局部放大截面圖。當進行多重内 运線製程時，首先必須在内介電層51 2的上方沈積一層内 至屬"層6 0 2，用以隔絕其下方的電路圖案，使其不會與 其上層將要形成的電路圖案發生干擾。同常此金屬間介電 層6 02可以由化學氣相薄膜沈積製程（)，或是電漿化 學氣相沈積薄膜製程（PECVD )所得到。在本實施例中，金 1間介電層6 0 2則為以PETE0S反應所沈積之氧化層，而其 厚度則約在17KA〜19KA，再以化學機械研磨8KA〜 1〇KA， 本紙張尺度適用中國國家標準（CNS ) Α4規格（2iOX 297公釐） 請 先 閱 讀 背 ιέ 之- 注 意 事 S· 寫 本 頁 裝 訂 線 533508 A7 ________B7 五、發明说明（） ^ 而剩下約8KA〜10KA的厚度。如前文所述，當半導體積集 度提高時，常會伴隨有應力集中界面的產生。如圖中所示 的三角形虛線區域604,即為一種的應力集中界面的形式。 當金屬間介電層6 0 2隨著製程的複雜化而越疊越高時，金 屬間介電層6 02沿著應力及中區域6〇4向兩側裂開的機率 也會隨著大幅升高。 經濟部智慧財/1-局員工消赏合作社印製 參閱第7圖，接著透過化學機械研磨（CMp )製程，將 金屬間介電層6 0 2向下比原來還多研磨約2KA〜4KA的厚 度。此時，金屬間介電層6 0 2的表面將會向下移動至7〇4 處，而此一表面將會切割三角形應力集中界面6〇4的頂 端。再利用電漿化學氣相薄膜沈積製程（pECVD )，於金屬 間介電層60 2的表面704之上沈積一層具有高壓縮應力的 介電層702。而此一壓縮應力介電層7〇2將可以提供金屬 間介電層602 —個如同箭號7〇6表示方向的收縮力量，使 得半導體結構受到外力作用時，例如，各種製程中的表面 平坦化處理，可以被壓縮應力層7〇2所提供之材料中的殘 留壓縮應力，而被緊緊的收聚在原始的結構形狀之下，而 不至於沿著應力集中界面6 0 4而發生裂縫。而此一由p e c V D 製程所沈積的壓縮應力介電層7 0 4，可以依照製程的需要 選擇所需的介電材料，諸如，Si〇2、Si3N4、PSG，與BPSG， 並調整PECVD5中射頻能量（RFPower) —層具有壓縮殘留 應力的介電薄膜7 0 2。在本實施例中，壓縮應力介電薄膜 7 0 2係為透PECVD製程所沈積出的TE0S氧化層，而此一氧 化層的厚度約在2KA〜4KA。而反應時PECVD製程中所設定 533508 A7 --—__ _ΒΊ__ 五、發明説明（） 白白勺，頻能量約在6 0 0W〜8〇〇W之間，在此能量下所沈積出來 1虱化層，大約會具有2E + 9 dyne/cm2〜3E + 9 dyne/cm2的 殘留壓縮應力。 在此 ^例中介紹了一種在單一層的金屬間介電層 上，沈積一層壓縮應力薄膜的製程，以防止此金屬間介電 層中發生裂縫。然而此一壓縮應力薄膜的應用範圍並不僅 止於單一層的金屬間介電層。在多重金屬間介電層的結構 中’金屬間介電層發生裂縫的機會將大為提高，因此可以 將本發明所揭露的壓縮應力薄膜，嵌入各個需要加強的金 屬間介電層之中，以防止半導體結構沿著介電層中的潛在 應力集中界面而發生破裂。以下將就此一在半導體結構上 的應用，以另外一個實施例來說明本發明的精神。 第8圖顯示了一個具有多重金屬間介電層的半導體結 構剖面圖。如圖中所示，底材812之上具有M0S電晶體8〇2、 804 °而M0S電晶體80 2包含閘極802a、源/汲極802b、 8Q2c ’ MOS電晶體804則包含閘極804a、源/汲極804b、 804c °電晶體80 2與804則由渠溝808加以隔絕，而其兩 側則由渠溝8 0 6、8 1 0而加以隔絕。底材8 1 2的上表面則覆 盖了内介電層814,其上則依次為第一金屬間介電層83〇、 第二金屬間介電層832、第三金屬間介電層834，與第四金 屬間介電層836。渠溝808上之金屬層816，透過插塞818 與金屬層820與第一内金屬屬介電層之電路進行電性連 接’而此結構中的各層之間即透過此種插塞與金屬層相連 的結構相互的連通，直達於最上端的金屬層 8 2 2。如前文 本紙张尺^適用( CNS ) Λ4規格（210X297公釐j (請先閲讀背面之注意事項再填寫本頁 -裝· 訂 經濟部智慧財4苟員工>/]骨合作社印製 533508Xi * Wang's stress concentration interface produced by mutual extrusion.口 〇T) ^ As shown in the figure, after the intermetallic dielectric layer 30β 丄 will be formed without deposition, the above-mentioned deposition machine: the corner line 312 represents the stress concentration interface caused by the accumulated money structure . The structure of the fabricator is subject to a gate-like structure, and when the semiconductor shoots occur on either side of the semiconductor, the force-concentrated interface 3 1 2 is again sew. In addition, it should be explained that ^ mainly occurs in jealousy ^ α ~ The above-mentioned rupture mechanism The line width of the middle of the robe is shrinking and shrinking, and then the shape is reduced. Therefore, the higher the fire i layer, the higher the situation. The semiconducting V-line system with similar metal edges in the above rupture mechanism is replaced with its shape and structure (eg, adjacent gates). Μ. 1 ′), may also be due to seams. Therefore, =, and the stress-concentrated interface is generated and cracks occur: the more the intermetallic dielectric layer is stacked, the more the semiconductor structure is more compatible-a stress-concentrated interface and generated across several dielectric layers crack.口 = The structure of the present invention will be described below by way of an example./See FIG. 4, which shows a cross-sectional view of a semiconductor structure. The semiconductor structure wearing surface 400 includes a substrate 402, and a MOS transistor 412 on the substrate 402, which includes a gate 406, a source / drain 404a, and a source / drain 404b. There is a trench 408 next to the source / drain 4104a to isolate the M0S transistor 4 丨 2 from interference and influence from other peripheral electronic components. Above the trench 408 is a first metal layer 410 for conducting wires. Referring to FIG. 5, a surface of the substrate 402, the gate electrode 406, and the first metal layer 410 is covered with a layer of a dielectric material to form an inner dielectric layer 512. Generally speaking, the chemical vapor deposition process (CVD) and its improved processes, such as SACVD, the paper size of the paper applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) (please read the note on the back 3 first) Page) Binding line 533508 A 7 B7 V. Description of invention (Printed by Sub-Atmospheric Γνη, θ ^ ^ ^,, ^ 1CLVD) is the most commonly used at present. Thin film deposition process. As for some commonly used dielectric materials such as SiO2 and BPSG, these materials can be applied according to different process requirements. In this embodiment, the inner dielectric layer 512 is formed by the SACVD process. Oxide layer. The thickness of the inner dielectric layer 512 also varies with different processes, and usually ranges from 3KA to 5KA. Then, the source / drain 4504a and the lead 410 are separated from each other. A contact window is filled with electrical material to form plugs 518, 516, so that the electronic components on the substrate 40 can form an electrical connection with the outside world. In general, polycrystalline stones are commonly used as plug materials. Xi Xi 〇ySlllC0n), Shi Xi Turn (TungstenSiHcide), and a metal 4 'As for other special conductive materials can also be prepared as needed for the group 516, 518 is inserted. A second metal layer 514 and a third metal @ 5 2 2 are formed over the plugs 516 and 518. This basic semiconductor circuit structure is formed in silicon. Next, in this example, the basic semiconductor structure will be described with the area 50 2, and the manufacturing process of stacking the semiconductor patterns on is continued. A sixth figure is a partially enlarged cross-sectional view of the area 50 2. When carrying out multiple internal transport line processes, first a layer of inner layer " layer 6 02 must be deposited above the inner dielectric layer 51 2 to isolate the circuit pattern below it so that it will not form with the upper layer. Interference in circuit patterns. As usual, the intermetallic dielectric layer 602 can be obtained by a chemical vapor deposition process (PECVD) or a plasma CVD process (PECVD). In this embodiment, the dielectric layer 602 of gold 1 is an oxide layer deposited by PETEOS reaction, and its thickness is about 17KA ~ 19KA, and then chemical mechanical polishing 8KA ~ 10KA. Applicable to Chinese National Standard (CNS) Α4 specification (2iOX 297 mm) Please read the back first-note S · write this page gutter 533508 A7 ________B7 5. Invention Description () ^ and the thickness of about 8KA ~ 10KA is left . As mentioned earlier, when the semiconductor concentration increases, it is often accompanied by the generation of a stress-concentrated interface. The triangular dotted area 604 shown in the figure is a form of stress concentration interface. When the intermetallic dielectric layer 62 is stacked higher and higher as the process becomes more complicated, the probability of the intermetallic dielectric layer 602 cracking to both sides along the stress and the middle region 604 will also increase significantly. Rise. The Ministry of Economic Affairs ’s Smart Money / 1-Bureau Consumers Co-operative Cooperative printed it as shown in Figure 7, and then through the chemical mechanical polishing (CMp) process, the intermetallic dielectric layer 6 2 2 was further ground down by about 2KA ~ 4KA thickness. At this time, the surface of the intermetallic dielectric layer 602 will move down to 704, and this surface will cut the top end of the triangular stress concentration interface 604. Then, a plasma chemical vapor thin film deposition process (pECVD) is used to deposit a dielectric layer 702 with a high compressive stress on the surface 704 of the intermetal dielectric layer 60 2. This compressive stress dielectric layer 702 will provide an intermetallic dielectric layer 602—a shrinking force in the direction indicated by the arrow 706. When the semiconductor structure is subjected to external forces, for example, the surface in various processes is flat. Chemical treatment, can be tightly gathered under the original structure shape by the residual compressive stress in the material provided by the compressive stress layer 702, so that cracks do not occur along the stress concentration interface 6 0 4 . The compressive stress dielectric layer 704 deposited by the pec VD process can be selected according to the needs of the process, such as Si02, Si3N4, PSG, and BPSG, and adjust the RF in PECVD5. Energy (RFPower)-a layer of dielectric film 7 2 with compressive residual stress. In this embodiment, the compressive stress dielectric film 702 is a TEOS oxide layer deposited through a PECVD process, and the thickness of this oxide layer is about 2KA to 4KA. The reaction time set in the PECVD process is 533508 A7 ---__ _ΒΊ__ 5. Description of the invention () The frequency energy is about 600W ~ 800W, and a lice formation layer is deposited under this energy. , Will have a residual compressive stress of approximately 2E + 9 dyne / cm2 to 3E + 9 dyne / cm2. In this example, a process of depositing a compressive stress film on a single intermetal dielectric layer to prevent cracks in the intermetal dielectric layer is described. However, the application range of this compressive stress film is not limited to a single interlayer dielectric layer. In the structure of the multiple intermetallic dielectric layer, the chance of cracks occurring in the intermetallic dielectric layer will be greatly improved, so the compressive stress film disclosed in the present invention can be embedded in each intermetallic dielectric layer that needs to be strengthened. This prevents the semiconductor structure from cracking along the potential stress concentration interface in the dielectric layer. In the following, the application of this to a semiconductor structure will be described in another embodiment to illustrate the spirit of the present invention. Figure 8 shows a cross-sectional view of a semiconductor structure with multiple intermetal dielectric layers. As shown in the figure, the substrate 812 has M0S transistor 802, 804 ° and M0S transistor 802 includes a gate 802a, a source / drain 802b, and 8Q2c. The MOS transistor 804 includes a gate 804a, The source / drain 804b, 804c ° transistors 80 2 and 804 are isolated by the trench 808, and the two sides are isolated by the trenches 806, 8 1 0. The upper surface of the substrate 8 1 2 is covered with an internal dielectric layer 814, which is in turn a first intermetal dielectric layer 83, a second intermetal dielectric layer 832, and a third intermetal dielectric layer 834, And a fourth intermetal dielectric layer 836. The metal layer 816 on the trench 808 is electrically connected to the circuit of the first inner metal dielectric layer through the plug 818 and the metal layer 820, and the layers in this structure pass through the plug and the metal layer. The connected structures communicate with each other directly to the uppermost metal layer 8 2 2. As above, this paper rule is applicable (CNS) Λ4 specification (210X297 mmj (please read the precautions on the back before filling in this page-binding and ordering), and printed by Bone Cooperative 533508
PC B7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁 所述，由於此種多重結構，極易使得各個金屬間介電層沿 著潛在的應力集中界面發生裂縫。因此在此一結構中選擇 性的於第二金屬間介電層832與第三内金屬介電834之 間，喪入第一壓縮應力層 824’以及於第三金屬間介電層 834與第四内金屬介電 836之間，嵌入第二壓縮應力層 826。透過第一壓縮應力層824與第二壓縮應力層826所提 供的壓縮應力，將可以緊緊的束缚住此一半導體結構，進 而防止其沿著各個介電層中的應力集中界面裂縫。 此一實施例僅用於說明本發明應用於多重金屬間介電 層之結構中的方法，並不僅限定本發明於此例中的結構。 舉凡各個不同層數所堆疊之半導體結構，皆可應用本發明 所揭露的壓縮應力層以防止裂縫的發生。至於嵌入壓縮應 力層的數目，亦可視製程的需要而加以決定，嵌入的層數 越多，相對的對於裂縫的防止能力也就越高。 本發明以數個較佳實施例說明如上，僅用於藉以幫助 了解本發明之實施，非用以限定本發明之精神，而熟悉此 領域技藝者於領悟本發明之精神後，在不脫離本發明之精 神範圍内，當可做些許更動潤飾及等同之變化替換，其專 利保護範圍當視後附之專利申請範圍及其等同領域而定。 經濟部智慈財產句員工消費合作社印製PC B7 V. Description of the invention () (Please read the notes on the back before filling in this page. Due to this multiple structure, it is easy for cracks to occur along the potential stress concentration interface between the intermetallic dielectric layers. Therefore, in In this structure, the first compressive stress layer 824 'and the third intermetal dielectric layer 834 and the fourth inner metal dielectric 834 are selectively buried between the second intermetal dielectric layer 832 and the third inner metal dielectric 834. Between the metal dielectric 836, a second compressive stress layer 826 is embedded. Through the compressive stress provided by the first compressive stress layer 824 and the second compressive stress layer 826, this semiconductor structure can be tightly bound, thereby preventing it. The stress is concentrated along the interface cracks in each dielectric layer. This embodiment is only used to explain the method of the present invention applied to the structure of the multiple intermetal dielectric layer, and not only limits the structure of the present invention in this example. For semiconductor structures stacked with different numbers of layers, the compressive stress layer disclosed in the present invention can be applied to prevent cracks. As for the number of embedded compressive stress layers, it can also depend on the needs of the process. It is determined that the more the number of embedded layers, the higher the relative ability to prevent cracks. The present invention is described above with several preferred embodiments, and is only used to help understand the implementation of the present invention, not to limit the present invention. The spirit of the invention, and those skilled in the art who understand the spirit of the present invention, without departing from the spirit of the present invention, can make some modifications and equivalent changes. The scope of patent protection shall be regarded as the attached patent. The scope of the application and its equivalent area will be determined.