TW526498B - High integration memory device, memory module mounting the memory device, and control method of the memory module - Google Patents

Abstract

The present invention discloses a high integration memory device, including a package packaging at least two chips, each including a predetermined number of control signal pads; and a predetermined number of control signal applying terminals connected with the predetermined number of the control signal pads.

Description

526498 A7 __ _B7 V. Description of the invention (1) Cross reference This patent application has the advantages of Korean Patent Application No. 2001-1019 filed on January 8, 2001, based on 35 USC. § 119. The patent application is mentioned by way of reference. This is incorporated in its entirety. BACKGROUND OF THE INVENTION The present invention relates to an integrated memory device. In particular, the present invention is directed to a highly integrated memory device with at least two chips built into a package, a memory module installed with the memory device, and the memory. Module control method. Related technical description-A 144-pin / 200-pin pin-on-line memory module installed on a notebook computer motherboard includes: small 〇utHne duai in-line memory module; SODIMM ), With a width of 1.25 inches, a height of 2.66, and a thickness of 0.15 忖; and, a micro dual-row in-line memory module (111 丨 (^ 〇-dual in-line memory module; μ-DIMM), whose width is 1 · 1 8 印 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 咼 1 · 5 忖 and thickness · 15 ··. The size of the memory module is according to the connected electronic device Determined by the Joint Electronic Devices Engineering Council (JEDEC) standard. On this type of memory, up to four 54-pin thin small packages (TSOP) can be installed on its front and back respectively. Type Synchronous Dynamic Random Access Memory (SDRAM). Figures 1 A and 1 B show the front and back configuration plans of a conventional 144-pin / 200-pin memory module, respectively. See Figures 1 A and 1 B, memory module Face 10 includes four memory devices 1 2 -1 to 1 2-4 and back 20. This paper size applies to Chinese national standards (CNS> A4 specification (210X297 mm) 526498 A7 B7 V. Description of the invention (2) It also includes four memory devices 22-1 to 22-4. Although not shown in the figure, signal lines have been arranged on the front 10 and rear 20 of the .1 memory module to connect the memory devices 12-1 to 12 -4 and 22-1 to 22_4 are connected to the pins 14-1, 14_2, 24-1, and 24-2. The connection pins 10-1 on the front 10 and the connection pins 24 on the back 20 -1 and 24-2 are connected to the signal line (not shown) through the slot (not shown) on the motherboard (not shown). Although not shown in the figure, the connection of the memory module Pin configuration includes 12-pin address input pin, 2-pin bank selection signal pin, 64-pin data input / output pin, and 1-pin column address strobe Pin pin, 1-pin row address strobe pin, 1-pin write enable signal pin, 8-pin data input / output mask pin, and a predetermined number of unconnected pin pins. Figure 2 Show A cross-sectional view of a TS0p type sdram installed on the memory shown in Fig. I. As shown in Fig. 2, the memory device includes a package 3 0, a chip 3 2, a lead frame 3 4 -1 and 3 4-2, Welding area 3 6-1 and 3 6-2, insulation material 3 8 _ J and 3 8-2 and bonding wire 4 0-1 and 4 0-2. The wafer 3 2 and the lead frame 3 4-1 and 3 4-2 are separated by the isolation material 38] and 38-2, and the lead frame 34_ 1 and 3 4-2 and the bonding area 3 6-1 and 3 6-2 They are connected to each other via bonding wires 4 0-1 and 4 0 2. Lead frame 34] and 34-2 are used as signal input / output pins. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ---------- (Please read the precautions on the back before filling this page)

1T Fig. 3 shows a plan view of the configuration of the 54 pin with the 〇1 > type SDRAM pin configuration. Pin numbers 1, 14 and 27 indicate the power supply (VDD) pin. Pin numbers 2 8, 4 1 and 5 4 indicate the power supply ground pin. Pins Numbers 3, 9, 4, 3, and 4 9 indicate the data output power pins. Pin numbers 6, 1, 2, 4, 6 and 5 2 indicate the data output power ground pin. Pin No.-5 526498 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (3) Code 16 indicates the socket opening signal (WEB) supply connection. &Quot; a Pin No. 1 7 Grab An unreserved address strobe signal (CASB) is supplied to the pins. The pin number η 俨 indicates that the column address strobe signal (CASB) is supplied to the pin. Pin Number The chip select signal (CSB) supplies the pin pins. Pin numbers 20 and 21 are supplied to the pin in the memory bank selection signal (BA0, BA1). Pin numbers W to 26 and 29 to 36 indicate the addresses (80 to 8 12) to supply pin pins. Pin No. 37 indicates that the timing enable signal (CKE) is supplied to the pin. The pin number η indicates that the system timing signal (CLK) is supplied to the pin. Pin numbers 15 and 39 indicate that the data input / output it cover signals (LDQM, UDQM) are supplied to the pin pins. Pin numbers 2, 4, 5, 7, 8, 10, h, 13, 42, and 45, 47, 48, 50, 51, and 53 indicate the data chip / output signal (DQ0 to DQ15) pins . The pin number 40 indicates that no pin is connected. The chip select signal (CSB) supplied to the chip select signal (CSB) enables the input signal to be input to the previously mentioned except the system timing = signal (CLK) supply pin, the timing enable signal (CKE) Supply pin pins and shell material input / output mask signals (LDQM, UDQM) supply all pin pins except pin I to enable the operation of the memory device. The system timing signal (CLK) supply pin is a pin used to input the clock signal from the motherboard controller. Specifically, the timing on signal (cke) supply pin can be used as a control signal for the power-down mode of a notebook computer that requires low-power module operation. Fig. 4 shows a plan view of a memory device and a control signal line installed in the illustrated memory module. The memory module shown in Figure 4 is a 256μ byte that can install eight 16M × 16-bit memory devices to 12 · 4 and 22-1 to 22_4 (please read the precautions on the back before filling this page). 1T 526498 A7 B7 5. Description of the Invention (4) Memory module. In Figures 1 and 4, similar reference numerals indicate similar parts. The memory devices 12 ″ to 12-4 arranged in a dotted line 10 · are memory devices mounted on the front face 10 of the memory module. Enable the memory device 丨 2-1 to 1 2-4 to respond to the chip select signal (CSBO) and enable the system timing k (CLKO) to respond to the timing on signal (CKEO) to input or output data in response to the system Timing signal (CLKO). At this time, the 16-bit data is input to the memory devices 12-1 to 12-4 or the 16-bit data is output from the memory devices 12-1 to 12-4. Therefore, the 16-bit data is input to the memory device or the self-recall device 1 2- The total data output from 1 to 1 2-4 is 64 bits. The memory devices 224 to 22_4 arranged in the dotted line portion 20f are memory devices mounted on the rear 20 of the memory module. Enable the operation of memory devices 2 2-1 to 2 2-4 in response to the chip select signal (CSB1) and enable the system timing signal (CLK1) in response to the timing on signal (CICE1) to input or output data 'in response to the system timing Signal (CLK1). At this time, 16-bit data is input to the memory devices 22-1 to 22-4 or 16-bit data is output from the memory device. Therefore, input to the memory device 22_1 to 22_4 or self-memory device 2 2-1 to 2 2 -The total output of 4 is 64 bits. The other k-line (not shown in Figure 4) are connected to each other via a universal signal line. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). That is, as shown in Figure 4, four 16Mx 16-bit memory devices are installed on the front 10 and 10 respectively. In the 256M byte memory module on the back 20, the four memory devices on the front 10 and the four memory devices on the back 20 should operate independently of each other to input / output 64-bit data to / from 256M Bit group memory module. As shown in Fig. 4, if the four memory devices installed on the front side ^ 〇 and the four memory devices installed on the back side 20 should be in accordance with the Chinese paper standard (CNS) A4 (210X297 mm) in a paper size that is unique to each other 526498

运作 mode operation, in order to increase the capacity of the memory module, you need to increase the capacity of the installed memory device. For example, in order to configure a 512M-byte memory module, two 16M X 1 6-bit modules should be installed on the front and back of the module. Instead of installing four 16M X 1 6-bit memory device. However, in order to increase the capacity of the memory module, the use of a larger capacity " hidden device will greatly increase the burden on the manufacturer. Furthermore, if the memory operates in the 10,000-type of Figure 4, a memory device with a small capacity is used to configure the Otani! There will be restrictions on the memory module. In order to overcome the problems mentioned above, four memory devices configured by stacking two 32MX 8-bit TS0p packaging methods will be installed on the front 10 and the back 20, so that the memory module can have 512M bits. Tuple capacity. However, since the memory module is configured by stacking two packages, the memory device becomes thicker. In order to overcome the aforementioned problems, a memory module having a highly integrated memory device in which two chips are packaged into one package has been used. a FIG. 5 shows a k / f plan view of a highly integrated memory device in which two chips are packaged into one package. As shown in FIG. 5, the highly integrated memory device includes an upper-layer wafer 5 2 · 丨 and a lower-layer wafer 5 2 _ 2 arranged opposite to each other, and a package 50 that packages the upper-layer wafer 52] and the lower-layer wafer 52-2. The upper wafer 52-1 includes the _th lead frame 54-1 and the second lead frame 54_2, the first isolation material% "and the first isolation material 56-2, the first land 58_ 丨 the second land, and the first Bonding wire 60] and the second bonding wire 60 · 2. The lower layer wafer 52_2 includes a first lead frame 54-3, a second lead frame 54_4, and a first isolation material 5. 3 and No. _ Isolation Material 56_4, No. 1 Welding Area 58_3 and No. 2 Welding Area This paper is suitable for National Standards (CNS) A4 specifications (210 X 297)

Hold

-8- 526498 A7 _______ B7 V. Invention Zhu Ming (6) 5 8-4 and the first bonding wire 60-3 and the second bonding wire 60-4. In the south integrated device of FIG. 5, the first lead frame 5 4-1 of the upper chip 5 2-1 and the first lead frame 5 4 · 2 of the lower chip 5 2-2 are connected to each other, and the upper layer The second lead frame 54-2 of the wafer 5 2-1 and the second lead frame 54_4 of the lower wafer 52-2 are connected to each other. The lead frames 54-1 to 54-4 are respectively connected to a plurality of control signal supply pins of the upper wafer 52 · i and the lower wafer 5 2-2. Although not shown in the figure, the lead frames connected to the plurality of shell input / output pins of the upper wafer 52-1 and the lower wafer 52_2 are not connected to each other and are configured in a mutually independent manner. In other words, except for the lead frames connected to the data input / output pins of the 32M × 8-bit upper chip 52-1 and the lower chip 5 · 2-2, all of the upper chip 52 "and the lower chip 52 · 2 The first and first lead frames are connected to each other. Therefore, the configuration of the high-integration memory device is the same as that shown in FIG. 3. The first lead frame 544 and the second lead frame 5 4-2 shown in FIG. Used as signal input / output pin. Figure 6 shows the 32M X 8-bit 5 4-pin TSOP type SDRAM pin configuration. Figure 6 shows the pin numbers 4, 7, and 10, 15, 40, 42, 45, 48, and 5 1 indicate non-connected (NC) pins. For highly integrated memory devices that do not package the two chips 52-1 and 52-2 into one package 'The connectionless lead frame of chip 5 2 · 1 must be connected to the data input / output (DQ0 to DQ7) lead frame of chip 5 2-2. Therefore, the configuration of the highly integrated memory device and the group shown in FIG. 3 The state is the same, and it becomes 32M χ 8-bit χ 2 SDRAM. In the highly integrated memory device shown in FIG. 5, two chips 5 2-1 will be enabled at the same time. 5 The operation of 2-2 is in response to the chip selection signal and when the system is enabled. -9-Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 526498 A7 ~ --- B7 V. Description of the invention (7) ^ 仏 is opened in response to the timing Signal in order to input 8-bit data to the two chips 52-1 and 52-2 or output 8-bit data from the two chips 52-1 and 52-2 in response to the system timing signal. As described above Because two chips perform I / O at the same time, heat will be generated, which will reduce the performance of the memory device. Figure 7 shows the highly integrated brother memory device shown in Figure 5 installed on the memory module shown in Figure 1. And the plan of the control signal line on the motherboard. The memory module shown in Figure 7 includes two 32M X 8-bit highly integrated memory devices 2_ j to 4 and 22-1 to 22-4 ' Therefore, it has a capacity of 512M bytes. In Figures 1 and 7, 'similar reference numerals indicate similar parts. The highly integrated memory devices arranged in dotted lines Shaofen 1 0' 丨 2 _ 丨 to 丨 2 _ 4 series On the front of the brother memory module 1 0. Enable the highly integrated memory device 丨 2 _ 3 to 1 2 * 4 operation in response Chip select signal (CSBO), and enable system timing signal (CLKO) in response to the timing on signal (CKE0), in order to input or output 32-bit data in response to the system timing signal (CLKO). Furthermore, enable Southern Integration 1 The memory device 1 2 -1 to 1 2-2 operates in response to the chip select signal (CSB1) 'and enables the system timing signal (CLK1) in response to the timing enable signal (CKE1) to input or output 32 bit data, In response to the system timing signal (CLK1). That is, the memory devices 丨 2] to 丨 2 _ 4 are enabled in response to the chip select signal (CSBO) and the timing enable signal (CKE〇), and input or output 64-bit data in response to the system timing signals (CLK0, CLK1 ). The memory devices 2 2 _ 丨 to 2 2 _ 4 arranged in the dotted line 2 0 · are mounted on the back 20 of the memory module. Enabling the operation of the highly integrated memory device 2 2-1 to 2 2 _ 2 in response to the chip selection signal (CSB1), and enabling the system timing letter -10-This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297) f Aw%. Order (Please read the precautions on the back before filling out this page} 526498 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs V. Invention Description (No. 8 (CLKO) in response to the timing opening signal (CKE1), In order to input or output 32-bit data in response to the system timing signal (CLK0). Furthermore, the user owes the operation of the highly integrated memory devices 22 · 3 to 22_4 in response to the chip selection signal (CSB1) and enables the system timing The signal (CLK1) turns on the signal blunt (CKE1) in response to the timing so that 32-bit data can be input or output in response to the signal (CLIO). That is, the highly integrated memory devices 12_f to 12 4 are enabled in response to the chip selection signal (CSB1 ) And timing enable signal (CKEi), and input or output 64-bit data in response to system timing signals (clk〇, CLK1) 〇 However, as mentioned above, the problem with traditional .highly integrated memory devices is that Because two chips will generate heat when performing data input / output at the same time, it will reduce the operating performance of the memory device. Based on the foregoing reasons, there is a need for a highly integrated memory device, which can reduce the The heat generated. In order to overcome the above-mentioned problem, g β β A η tons, a preferred embodiment of the present invention provides a highly integrated memory device with high operation performance. The present invention provides a memory module The memory module can be equipped with a highly integrated memory device with high operating performance. The present invention also provides a method for controlling the memory module, and the Youyi m can be installed with a highly integrated memory device with high operating performance. In order to achieve the foregoing purpose, Tailu Tuyi &, as far as possible, the preferred embodiment provides a corrective ... Jift device, Taonan integrated memory device includes:-a package encapsulating at least rain crystals-tablets' Each of these chips includes a predetermined number of control signals ml af ^ n imi ii --1 li mi l ^ K m (Please read the precautions on the back before filling in this purchase)

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526498 A7 ___ B7 ________ 5. Description of the invention (9) Welding area; and a predetermined number of control signal supply terminals connected to the predetermined number of control signal welding areas. A preferred embodiment of the present invention provides a highly integrated memory device. The highly integrated memory device includes: a package for packaging a first chip and a second chip, wherein each chip includes a predetermined number of control signal supply pads; and A first and a second chip selection signal supply pin, which are respectively connected to the first and second chip signal supply pads of the predetermined number of control signal supply pads to supply the first and second chip Signal of chip operation. A preferred embodiment of the present invention provides a memory module. The memory module includes: a plurality of highly integrated memory devices corresponding to respective chips, and each of the highly integrated memory devices includes: a)-packaging at least two Packaging of wafers' where each wafer includes a predetermined number of control signal pads; and, b) a predetermined number of control signal supply terminals connected to the predetermined number of control signal pads, where a corresponding plurality of The highly integrated memory device chip is responsive to control signals supplied from the predetermined number of control signal supply terminals for inputting and outputting data. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back and fill in this page)

Li A preferred embodiment of the present invention provides a memory module including a plurality of highly integrated memory devices, each of which includes: a)-a package that packages the first and second chips, wherein each chip includes A predetermined number of control signal supply pads; and, b) first and second chip selection signal supply pins connected to the first and second chip signal supplies of the predetermined number of control signal supply pads, respectively Welding area to supply signals to enable the operation of the first and second chips, which will be used separately. -12- This paper size applies Chinese National Standard (CNS) A4 specifications (public i ^ ~~ 526498 V. Invention Explanation (1〇) A plurality of high-integration + > should be to the first chip of the first, in response to-supply or input :: the first chip selection signal of the foot pin should be 愔 I w, — Materials, and will simultaneously enable these multiple high-integration notes 22 :: T second chips, in response to-the second chip selection signal supplied to the second chip ... Output data. Yuekjia specific embodiment further provides a kind of memory module control method '; the memory module includes a complex, solid-state memory device with at least two first and second chips installed, for Receive and output data in response to the first and second control signals located on the upper surface and lower surface of the Θ hidden ω. The party ... has included the following steps: input and output data by simultaneously enabling a plurality of β and other 鬲A first chip of each of the integrated memory devices in response to the first control signal; and inputting and outputting data by simultaneously enabling a second chip of each of the plurality of highly integrated memory devices in response to the Second control signal. Simple diagram. For a better understanding of the present invention and its advantages, please refer to the detailed description of the preferred embodiment illustrated in the accompanying drawings. Similar reference numerals indicate similar parts, and of which: Printed by the Consumer Bureau of the Standards Bureau (please read the precautions on the back before filling out this page) Figure 1 Α and 1B show the front of the traditional 144-pin / 200-pin memory module respectively And the rear configuration plan; Figure 2 shows the TSOP-type SDRAM cross-sectional view; Figure 3 shows the 54-pin TSOP-type SDRAM pin configuration and configuration diagram; I-13 · ΪThe paper size is applicable to China Standard (CNS) A4 size (210X297 mm) " "-Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 526498 A7 ____ B7 V. Description of the invention (η) Figure 4 shows the installation in Figure 1 a and 1 Β Figure 5 shows the plan of the memory device and control signal line of the memory module; Figure 5 shows a cross-section view of a highly integrated memory device in which two chips are packaged into a package; Figure 6 shows a 32M X 8-bit 5 4 pin TSOP type SDRAM pin configuration plan; Figure 7 shows the highly integrated memory device and control signal lines shown in Figure 5 installed in the memory module shown in Figure 1; Figure 8 shows the comparison according to the present invention A plan view of the pin configuration of the highly integrated memory device according to the preferred embodiment; FIG. 9 shows a highly integrated memory device installed in the A memory module shown in FIG. 1 according to a preferred embodiment of the present invention And the plan of the control signal line on the motherboard Figure 1 shows the installation and a square embodiment of FIG. 1 according to a modification not in & lt particular embodiment of the invention; FIG high memory module programming of integrated memory device and a control signal line located on the motherboard. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described by way of preferred embodiments of the invention and with reference to exemplary drawings. FIG. 8 shows a plan view of a pin configuration of a highly integrated memory device according to a preferred embodiment of the present invention. Pin number 丨 5 indicates the chip selection signal (CSB1). Pin number 4 〇 indicates the timing on signal (CKE1). Pin number 19 indicates the chip selection signal (csb〇 supply pin. Pin number 37 indicates the timing on signal (CKE〇) supply pin (please read the note on the back ^ before filling this page)

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526498 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (12). The other pin configuration is the same as that shown in FIG. 6. In a conventional highly integrated memory device, the chip selection signal supply lead frame and the timing enable signal supply lead frame of the two chips are connected to each other. However, in the highly integrated memory device shown in FIG. 8, the chip selection signal supply lead frame and the timing enable signal supply lead frame of the two chips are not connected to each other, but are configured in a mutually independent manner. Furthermore, in a conventional highly integrated memory device, the eight data input / output lead frames of the two chips are not connected to each other, but are configured in a mutually independent manner. However, in the pin configuration of the highly integrated memory device shown in FIG. 8, the eight data input / output lead frames of the two chips are connected to each other. Therefore, the operation of the highly integrated memory device shown in FIG. 8 is enabled in response to the chip select signal (CSB〇), and the system timing signal (CLK) is enabled in response to the timing enable signal (CKE〇) to input data into two Data is output from one of the wafers or from one of the two wafers. Furthermore, the operation of the South integrated memory device is enabled in response to the chip select signal (CSB1), and the system timing signal (CLK) is enabled in response to the timing enable signal (CKE1) to input data to the other of the two chips or from two Output data from one chip. That is, in the highly integrated memory device shown in Fig. 8, two chips in the package can be operated in response to control signals from each other. In the highly integrated memory device shown in FIG. 8, the data input / output lead frames of the two chips are interconnected internally, and 8-bit data input / output pin pins (DQO to DQ7) are externally configured. However, since the highly integrated memory device shown in FIG. 8 has a no connection (> 1 (:) pin, the data input / output pads of the two chips will not be connected to each other in Inshao, as shown in FIG. 8 No connection (Please read the notes on the back before filling out this page)

* 1T such as -15 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 526498 A7 --------- ____B7______ V. Invented Sun and Moon (13) The pin can be connected to the data input / output soldering area of other chips, External configuration 16-bit data input / output pin (DQO to DQ15). Furthermore, if it is not necessary to operate the highly integrated memory device with low power, the timing enable signals (CKE0, CKE1) can be connected to each other to supply the pin pins. FIG. 9 shows a plan view of a highly integrated memory device installed on the memory module shown in FIG. 1 and a control signal line on a motherboard according to a preferred embodiment of the present invention. This memory module has eight 32M X8-bit x2 highly integrated memory devices, so its capacity is 512M bytes. In Figures 1 and 9, similar reference numerals indicate similar parts. The memory devices i 2-1 to 丨 2-4 arranged in a dotted portion 10 0 ′ are memory devices mounted on the front surface 10 of the memory module. Enable the operation of one of each of the highly integrated memory devices 1 2-1 to 1 2-4 in response to the chip select signal (CSB0), and enable the system timing signal (CLK〇) in response to the timing enable signal (CKE0) to Input or output 8-bit data in response to the system timing signal (C LK 0). Furthermore, the operation of each highly integrated memory device 丨 2-1 to 丨 2 _ 4 is enabled in response to the chip select signal (CSB1), and the system timing signal (CLK1) is enabled in response to the timing enable signal (CKE1) for inputting or Output 8-bit data in response to system timing signals (clki). The memory devices 2 2-1 to 2 2-4 arranged in a dotted portion 2 0 1 are memory devices mounted on the back 20 of the memory module. Enable each of the highly integrated memory devices 2 2-1 to 2 2-4 to operate in response to the chip select signal (CSB0), and enable the system timing signal (CLK0) in response to the timing enable signal (CKE0) for input Or output 8-bit data in response to the system timing signal (CLK0). In addition, enable each highly integrated memory device 22-1 to 22- -16-This paper is only Jl applicable to China National Standard (CNS) A4 specifications (210 X297 mm ^ clothing order (please read the precautions on the back before filling This page} 526498 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Description (14) 4 operates in response to the chip select signal (CSB1) and enables the system timing signal (CLK1) in response to the timing on signal (CKE1 ) In order to input or output 8-bit data in response to the system timing signal (CLK1). Replacing the 'chip selection signal (CSBO) and timing enable signal (CKEO) will cause the 6th memory device 12-1 to 12-4 And the upper (or lower) chips of 22-1 to 22-4 operate at the same time, the chip select signal (CSB1) & timing enable signal (ckeo will make the memory devices 12-1 to 12-4 and 22-1 to 22-4 The lower (or upper) chip operates simultaneously. Therefore, 8-bit data is input to the memory devices 12_ 1 to 12-4 and 22-1 to 22-4 or the self-memory devices 12-1 to 12-4 and 22- 1 to 2 2-4 output 8-bit data, therefore-the total data input to or output from the memory module 64-bit. At this time, not only the upper and lower wafers of the memory devices 12-1 to 12-4 and 22-1 to 22-4 will operate simultaneously, but also the upper and lower wafers on the front and back sides will operate separately. Therefore, the problem of reducing the operating performance of the memory module caused by the heat generated when the upper chip and the lower chip are operated at the same time can be improved. FIG. 10 shows the installation of the modified embodiment according to the modified embodiment of the present invention. The high-integrated memory device of the module and the planning diagram of the control signal line located on the motherboard. In the memory module of Figure 10, the system timing signal (CLKO) is supplied to the dotted line 10, which is arranged on the The memory devices 1 2 -1 and 12-2 and the memory devices 22_ι and 22-2 arranged on the dotted portion 20, and the system timing signal (CLK1) is supplied to the memory arranged on the dotted portion 10, Devices 1 2-3 and 1 2-4 and the dotted line 2 〇, the memory devices 2 2-3 and 2 2-4 arranged above. Therefore, the system timing signals (CLK0, 17- National Standard (CNS) A4 Specification (210X 297mm) I Order III n (Please read the notes on the back before filling this page) 526498 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (15) ^ ^ ~ CLK1) Separately supplied to the memory located on the front Device and a memory device located on the back, which can reduce the load of the system timing signal line, thereby speeding up signal transmission. Furthermore, since the upper chip and the lower layer of the memory device do not operate simultaneously, but operate separately, the operation performance can be improved. In the foregoing specific embodiment, the package of the highly integrated memory device has at least two chips. When a highly integrated memory device has three chips in the package, the memory device can be configured in the following ways: a chip selection signal supply pin and two timing enable signal supply pins connected to two chips, and connected to each other Data input / output pin for three chips. In one way, the memory device can be configured in the following ways: three chip selection signal supply pins and three timing enable signal supply pins for three chips are externally configured, and three chips are connected to each other externally. Data input / output pins In the same way, if each of the plurality of highly integrated memory devices on the installed memory module includes three chips, the following methods can be used to configure the memory module: 2 Input data Output data to one or more of each of the three chips of the plurality of highly integrated memory devices, or output data from one or more of the three chips of each of the plurality of highly integrated memory devices in response to two Chip select signal and two timing enable signals 7 or respond to three chip select signals and three timing enable signals. As described above, in the highly integrated memory device according to the preferred embodiment of the present invention, since the chips in the highly integrated memory device are separately operated so that problems caused by heat do not occur, the memory device can be improved. Operational performance. Furthermore, in the memory module installed with the high-coupling 1 memory device according to the preferred embodiment of the present invention, since the highly integrated memory will be operated separately ^ IT (Please read the precautions on the back before filling this page}- 18-526498 A7 B7 V. Description of the invention (16) The chip in the center will not cause problems caused by heat, so the performance of the memory device can be improved. In addition, the chip in the highly integrated memory device will be operated separately. Therefore, in the memory module and the control method according to the preferred embodiments of the present invention, the reliability of the memory module can be improved. Since the chips in the highly integrated memory device are operated separately, the overheating caused by overheating will never occur Question. Although the present invention is described with reference to its preferred embodiments, those skilled in the art should know the forms and details of the foregoing and other changes without departing from the spirit and scope of the present invention. (Please read the precautions on the back before (Fill in this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs -19- This paper size applies to China National Standard (CNS) A4 (210X 297 mm)

Claims (1)

526498 A8 B8 C8 D8 application, patent scope 2 The Ministry of Economic Affairs ’Intellectual Property Bureau employee consumer cooperative prints a highly-integrated memory_, which includes: a package containing at least two, ##, where each chip includes a predetermined number of control signals * drought“ zone; The pre-numbered control number supply terminals are connected to the predetermined number of control signal welding areas. For the device in the scope of the patent application, the pre-number control k-number supply terminals include the chip selection signal supply 'terminal. The signal supply terminal is enabled in a timely manner. For the device in the scope of patent application No. 2, each chip is enabled in response to a chip selection signal supplied to the chip selection signal supply terminal, and a system timing signal is enabled in response to a supply to the device. The timing enable parameter of the timing enable signal supply terminal is used to input or output data in response to the timing signal of the system., ;; 'A highly integrated memory, which includes: ΐ J ”, ---:' One package first And first and second wafers, each of which includes a predetermined number of control signal supply pads; and first and second wafers The selection signal supply pins are respectively connected to the first and second chip signal supply pads of the predetermined number of control signal supply pads to supply signals for enabling the operation of the first and second chips. If the device of the patent application No. 4 is applied, the device further includes: first and second timing enable signal supply pins, which are connected to the first and second timings among the predetermined number of control signal supply pads. The letter No. 1 is supplied to the welding zone to supply the precautions for controlling the supply to the back of the first and second crystals. J Page 1 I-20-This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 mm) 526498 A8 B8 C8 D8 6. Application, Patent Scope System timing signals printed by employees' cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A memory module includes: a plurality of highly integrated memory devices located on an upper surface and a lower surface of the memory module, each of which includes: a) a package encapsulating at least two chips , Each of which includes a predetermined number of control signal pads; and b) a predetermined number of control signal supply terminals, which are connected to the predetermined number of control signal pads, where a corresponding plurality of these are simultaneously enabled Each of the highly integrated memory devices responds to the control signals supplied from the predetermined number of control signal supply terminals in order to input and output data. For example, the module in the sixth scope of the patent application, wherein the memory module is a SODIMM with a width of 1.25 pairs, a southness of 2.66 忖, and a thickness of 15 忖. For example, the module in the sixth scope of the patent application, wherein the pre-quantity control signal supply terminals include a chip selection signal supply terminal and a timing enable signal supply terminal. For example, the module of claim 7 of the patent scope will enable each chip to respond to a chip selection signal corresponding to one of the respective chips supplied to the chip selection signal supply terminal, and enable a system timing signal in response to a supply to The timing enable signal Y ^ of the timing enable signal supply terminal inputs or outputs data in response to the system timing signal. 10 · If the module of the scope of patent application No. 9, the system timing signals are divided into a predetermined number of timing signals, and the predetermined number of timing signals are separately supplied to the memory device on the front and the 6 on the back. 7. 8. · 9. -21 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) _ A8 B8 C8 D8 526498 6. Application, patent scope memory device. 1 1. A memory module comprising: a plurality of south integrated 1 memory devices located on an upper surface and a lower surface of the memory module, each of the highly integrated memory devices includes: a) —package first and A package of second wafers, wherein each wafer includes a predetermined number of control signal supply pads; and b) the first and second wafer selection signal supply pins are connected to the predetermined number of control signal supply pads, respectively Among them, the first and the second chip k $ tiger supply welding area 'are used to supply signals for enabling the operation of the first and second chips, wherein the first of each of the plurality of highly integrated memory devices is enabled respectively. Chip, in response to a first chip selection signal supplied to the first chip signal supply pin, so as to input or output data, and simultaneously enable the second chip of each of the plurality of highly integrated memory devices to Responds to a second chip selection signal supplied to the second chip signal supply pin, so as to input or output data / 1 2 · As the module of the scope of patent application No. 11 Group, wherein the highly integrated memory device further includes first and second timing enable signal supply pins connected to the first and second timing enable signals of the predetermined number of control signal supply pads. The supply pads are used to supply system timing signals for controlling supply to the first and second chips. 13. The module according to item 11 of the patent application scope, wherein the memory module is a SODIMM with a width of 1.25 inches, a height of 2.66 inches, and a thickness of 0.15 inches. 1 4 · —If the module in the scope of patent application No. 11 is used, the memory module has a width of -22- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read the back first Please note this page before filling in this page). I · n · nn nnnnn-OJa n I in 印 Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 526498 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 i ___ D8 VI. Application The patent range is 1.18 inches, height 1.5 inches, and μ-1) IMM with a thickness of 0.15 inches. 15 · If the module in the scope of patent application No. 1 丨, 8-bit data will be input to each of the memory devices or 8-bit data will be output from each of the self-memory devices. The total data output by the memory module is 64 bits. 16. If the module of the scope of patent application No. 12 is used, the first chip of each of the plurality of integrated memory devices will be enabled in response to the first chip selection signal 'enable the system timing signal in response to the The first timing enable signal, so as to input or output data in response to the timing enable signal, and enable the second chip of each of the plurality of highly integrated memory devices in response to the second chip selection signal to enable the system The timing signal is in response to the first timing enabling signal, so that data is input or output in response to the timing enabling signal. 17. · A method for controlling a memory module, the memory module comprising a plurality of highly integrated memory devices mounted with at least two first and second chips for receiving and outputting data in response to the upper surface of the memory and The lower surface of the first and second control signals 'the method includes the following steps: inputting and outputting data' by means of simultaneously enabling the first chip of each of the plurality of highly integrated memory devices in response to the first control operation And inputting and outputting data in a manner of simultaneously enabling the second chip of each of the plurality of highly integrated memory devices in response to the second control signal. 1 8 · —If you apply for the method of item 17 in the scope of patent application, where the memory module has a width of -23-This paper size is applicable to China & quasi (CNS) A4 specifications (21G χ 297 meals) (Please read first (Notes on the reverse side of this page) i: The farmer's book is too customized --------- line k 526498 A8 B8 C8 D8, patent application scope 1.25 inches, height 2.66 pairs and thickness 〇15 忖 3〇1) 1] ^] ^. 19 · The method according to item i 2 of the patent application scope, wherein the memory module is a μ_DIMM with a width of 1.18 nanometers U 忖 and a thickness of 15〇. 20. The method according to item 17 of the patent application park, wherein 8-bit data and a total of 64-bit data are received or output at each of the plurality of high-integration memory devices. (Please read the note on the back first ----- Item X-line on this page Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 24-This paper size applies to China National Standard (CNS) A4 (210 X 297 public love)