TW521189B - System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system - Google Patents

Abstract

A computer system employs virtual channels and allocates different resources to the virtual channels. More particularly, the computer system provides a posted commands virtual channel separate from the non-posted commands virtual channel for routing posted and non-posted commands or requests through coherent and noncoherent fabrics within the computer system. Because separate resources are allocated to the virtual channels in the computer system, posted requests may be allowed to become unordered with other requests from the same source. Implementation of a separate posted commands virtual channel may allow the computer system to maintain compatibility with I/O systems in which posted write requests may become unordered with previous posted requests (e.g., the peripheral component interconnect bus, or PCI). Implementation of the separate posted commands virtual channel thus may assist in providing deadlock-free operation.

Description

521189 A7

[Field of the Invention] The present invention relates to the field of electrical systems and, more specifically, to the routing of data between nodes in a multiprocessor computer system. [Background of the Invention] In general, personal computers (PCs) and other types of computer systems are designed to share a bus system around to access memory. One or more processors and one or more input / output (1/0) devices are connected to the memory via a shared bus. I / O devices can be connected to the shared bus via an I / O bridge that manages the transfer of information between shared buses and ι / 〇 devices, while processors are typically connected directly to the shared bus or via a fast buffer storage system To shared bus. Unfortunately, shared bus systems have several disadvantages. For example, several devices connected to a shared bus cause considerable capacitance to the device on the bus = the drive signal. In addition, several contacts on the shared bus produce signal reflections at high signal frequencies, reducing signal integrity. As a result, the frequency of the signal on the bus is usually kept quite low to maintain the signal integrity to an acceptable level. This relatively low signal frequency reduces the signal bandwidth and limits the performance of devices connected to the bus. The lack of scalability to a larger number of device capacities is another disadvantage of a shared bus system. The usable bandwidth of a shared bus is generally fixed (and may be reduced, if additional devices are added to reduce the signal frequency on the bus). Once the bandwidth requirement of the device connected to the bus (directly or indirectly) exceeds the available bandwidth of the bus, when trying to access the bus, the device will be delayed by _f, and the overall performance of the computer system including the shared bus will be very Possibility of negotiation (21G x 297 ^), coffee

Awl 1 --------- Awl. (Please read the precautions on the back before filling out this page) 521189 B7 V. Description of the invention (2 reduced. Strain / side 'distributed memory system does not have many of the above Disadvantages1 Two computer systems with a decentralized memory system in cattle include several nodes == multiple connected to different memories. Nodes are connected to each other using any two connections. For example, each node of Tian Ni can be, The car can be connected to each other using a dedicated line. Or, a predetermined number of other nodes can be implemented, and each execution can be routed through Xin: Evening, and the first node is routed to a second that is not directly connected to the first: Point: Nodes. Computer systems: and the memory of each node. The two schools are generally distributed. A "node" is a device that can be connected. For example, 'connection can be the basis of a packet. Sending as part of the implementation is sighed to receive a series of packets.-A "request: request packet 'start one point to the target' point: point borrow: publish-each packet of a copy, execute on" order two " -The individual packets, the end. "When _ :: 1 ㈣ 二The receiving node accepts the information transmitted by the packet. The destination is located at the source and destination = f: internally processes the information. Or, the node on the requester-to-destination route can forward the packet and remove it. Initially requesting the outside of the envelope> If you are a parent, you can lead to other types of packets, such as replying, probing, and broadcasting. For example, after receiving the original requested packet, the target: 2 :: = = to other nodes in the processing system. These nodes are widely distributed = reply to the target destination or the requester node. The "4" was generated. The target node 'header 91S90 V. Description of the invention (3) Target node This can be achieved by publishing a distributed memory system that responds to both: points to answer. Different design challenges. For example, Ugly > /, the beginning of the implementation of the challenge section of the iL row system. Therefore: Erzi / The bus system arbitrates the bus participants through the arbitration rules of the bus participants 'initial execution to allow each sink to perform the order of execution. The execution order on the bus indicates that the distributed system' nodes can start at the same time /), the other side 'Points to other nodes. $ 此 # / σ 仃 and use the connection to send the execution to: some execution mechanisms that may have a logical conflict of 1 due to the lack of adjustments, which will run through and may encounter executions involving the same address. Source conflicts (such as slow balance storage space may spread helmets, so 'ensure that information continues to flow smoothly between nodes and conflicts, and its implementation has not been completed, such as' some deadlock' The situation may occur in a known t I / O system, such as a peripheral part connection interface (PCI) I / 0 system. Unless one, and later, write execution-related packets are allowed to surpass others that are not related to post-write execution Other services. In general, when a write request and corresponding data are transmitted by the requester (for example, via a source interface), a post-write execution is considered to be completed by the requester 'and thus, it is effectively completed by the requester Because the requester does not directly detect when the post-write execution is actually completed by the target, more order support for the post-request operation needs to be provided by the hardware. Therefore, when the packet or post-write execution As the packet travels to the target, the requester may issue additional requests and assume that such additional requests will be completed after execution is completed. Sufficient usable hardware is required to support this assumption. This paper size applies Chinese national standards ( CNS) A4 specification (210 x 297 mm) 3 91890 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description (4 In contrast, a "non-post" writes one and one, until the goal (for example, one仃 It is not considered that the requester has completed the non-post-writer execution completion (quote) interface) The non-post-write execution has been completed. The non-post-write execution is issued, for example, ...: the requester receives and explains. Can be subsequently Completed before the implementation of the release. Tian Yue, knowing that the previous implementation has been generated in the computer system of the I / O ::: distributed memory system, and the operation is properly arranged to maintain the consistency and conformity of the memory in the computer system. The operation of the / 0 system may require 1 in the order in which it was generated. For example, 'Memory # # H β Μ 貭 Order Fancheng, in order to maintain the records in the computer system and meet the 1/0 order requirements. Therefore — A computer The system formulates systems and methods to provide post-request—a separate communication channel. Such systems and methods can avoid deadlock situations and also minimize the device (in terms of hardware) to improve the ease of implementation. Summary of the Invention] The present invention provides a computer system that implements a system and method for using virtual channels and allocating different resources to virtual channels. More specifically, the computer system provides a command virtual channel after separation from non-post-command virtual channels. To route requests through the coordination and non-coordination structure in the computer system. Post-write belongs to the post-command virtual channel, and other requests belong to the non-post-command virtual channel. Because individual resources in the computer system are provided to the virtual channel, the post-write can be Allows requests to be made out of order with other requests from the same source. Advantageously, the computer system can be written with the requirements of the previous non-post request. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm).

imr binding --------- AWI · (Please read the notes on the back before filling in this page) 4 91890 Printed clothing by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 91890 521189 A7 ^ ~ —-2Z ____ V. Description of the Invention (5) '-The previous I / O system that has become non-sequential (for example, peripheral component connection interface, or PCI) maintains compatibility, thus avoiding some deadlock that might otherwise occur in the system. Advantageously, by providing a post-command virtual channel, the computer system can provide the required compatibility and provide money operation. The broad and t ′ present invention considers a method of enveloping a plurality of nodes between packets in an electrical system. A post-request packet is received at the first of a plurality of nodes. The first node includes a plurality of packet buffer memories, and each of the buffer memories is assigned to a different one of the plurality of virtual channels. The post-request packet is stored in the post-command buffer memory, which is one of a plurality of packet buffer memories. The post-command buffer memory is dedicated to packets in the post-command virtual channel, which is one of a plurality of virtual channels. In addition, the present invention considers a computer system including a first node and a second node. The first node is set to transmit a post-request packet. Connect to receive a request packet from the first node, the second node contains a plurality of packet buffer memory, this packet buffer contains a post command buffer memory. Each of the plurality of packet buffer memories is assigned to a different one of the plurality of virtual channels, and this virtual channel includes a command virtual channel specified by a command buffer buffer after the command. The second node is set to request a packet after storage in the post-command buffer memory. [Brief description of the drawings] Other objects and advantages of the present invention will be understood after reading the following detailed description and referring to the accompanying drawings. Among them: Fig. 1 is an exemplary embodiment of a computer processing system including a plurality of processing nodes. Block diagram; This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) —--- 5 ----------- jmp installed -------- order- -------- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 91890 521189 V. Description of the invention (6) Figure 2 is the two of Figure 1. Virtual 1U management_point block diagram showing exemplary specific embodiments of communication connections of connected nodes. Figure 3 is a diagram that can be used to deal with irregular coordinated information packets within the system and the system; Fig. 4 is a diagram that can be used to process a demonstration coordination request packet in the + ^ & ^ where-person system. Fig. 5 is a diagram that can be used to process a demonstration coordinated response packet in a sub-system. Figure 6 is a diagram that can be used to process a sample coordination data packet in the sub-system; Figure 7 is a table listing the Used to process different types of coordinated packets in the sub-system; Figure 8 is a block diagram illustrating a pair of virtual channels in the processing system; Figure 9 is a table illustrating a set of exemplary embodiments of virtual channels and their applicable connections Figure 10 is a block diagram of an exemplary embodiment of the processing node of Figure 1, the node contains the packet processing logic; Figure 11 is a block diagram of an exemplary embodiment of the packet processing logic of the node of Figure 10, the packet processing logic contains Data buffer storage slot and reply counter slot; ~ Θ Figure 12 is a block diagram of an exemplary embodiment located in the data buffer storage slot of Figure 11; Figure 13 is located in the reply counter slot of Figure 11 A block diagram of an exemplary embodiment of the location; The scale of this book applies to the Chinese National Standard (CNS) XTiT grid (210 X 297 public love) ----------- Imp t ------ -^ --------- Awl (Please read the notes on the back before filling out this page) Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 521189 V. Description of the invention (7) Brother 14 The picture is the first 〇 Demonstration of the part of the picture used to receive the packet The flowchart of the operation of the example; Figure 15 is the flowchart of the specific embodiment of the logical operation of Figure 10, which is used to process some and _ months of the δ months to find the packet. Fig. 10 is used to ^ a part of the packet processing logic of the reply packet to demonstrate the specific embodiment of the operation flowchart; Fig. 17 is a diagram of Fig. 10 used as 仏 _ part of the packet processing logic to start the packet demonstration Flowchart of the operation of the specific embodiment; Figure 18 is a block diagram showing an exemplary embodiment of a Ufo packet containing a buffer memory release field; Figure 19 is a demonstration of an I / O secondary system For example, the block diagram of this I / O secondary system includes a main bridge and a plurality of μ-points connected by links. It is similar to the connection shown in Figures 1 and 2. Figure 20 is a table illustrating packets used for uncoordinated connections. Define exemplary specific embodiments; (Figure 21 is a diagram of an exemplary non-coordinated request that can be used to process the system; ^ Figure 22 is a diagram of a sample non-coordinated response packet that can be used to process the system; The picture shows 1/0 of the I / O secondary system in Fig. 19 Section f * begin < Block diagram of the specific embodiment of Wei Wei; ^ Fig. 24 is a diagram of the node logic for packet reception in Fig. 23 ~ Dry bucket < Operation flow chart of the non-performing part; Fig. 25 is 24 The paper size of the node logic used to process the request packet is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love ^ — / 91890 890 & & 装 订 订 --- order ----- ------ ^^ 1 (Please read the notes on the back before filling out this page) 521189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 -------— B7_______ V. Description of Invention (8) Fig. 26 is an operation flowchart of the exemplary part of the node logic used to process the reply packet in Fig. 24; Fig. 27 is the operation of the exemplary part of the node logic used to initiate the packet in Fig. 24 Flow chart; and Figure 28 is a table listing exemplary sequence rules that can be implemented by the major bridges of Figure 19. Although the present invention allows different modifications and alternative forms, specific specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. It should be understood that 'however, the accompanying drawings and detailed description are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all the spirit and scope of the invention as defined by the scope of the appended patent application. Modifications here, equivalents and choices. [Detailed Description of the Invention] System Overview A specific embodiment of the computer system 10 is shown with reference to FIG. 1 '. Other specific embodiments of the computer system 10 are possible and considered. In the specific embodiment of FIG. 1, the computer system 10 includes a plurality of processing nodes 12A, 12B, 12C, and 12D, although more or fewer processing nodes may be used. Each processing node is connected to the individual memories 14A to 14D via the memory controllers 16A to 16D included in each individual processing node 2a to 12D. The memory address space of the computer system 10 is distributed throughout the memories 14A to 14D, so that the system 10 has a distributed memory system. In addition, the processing nodes 12A to 12D include interface logic for communication between the processing nodes 12A to 12D. 11 — — — — — — · I ------ Order · -------- f Please read the notes on the back before filling out this page} This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 meals) 8 91890 521189 A7 B7 V. Invention description (9) For example, processing node 12A includes interface logic 18 to communicate with processing node 12b, interface logic 18B communicates with processing node 12c, and a third interface Logic 18C communicates with another processing node (not shown). Similarly, the processing node 12B includes interface logics 18D ′ and 18p; the processing node includes interface logics 18G, 18H, and 181; and the processing node 12D includes interface logics 18J, 18K, and 18L. The processing node 12D is connected to communicate with the I / O bridge 20 via the interface logic i8] L. Other processing nodes can communicate with other 1/0 bridges in a similar manner. The 1/0 bridge 20 is connected to the I / O bus 22. The processing nodes 12A to 12D implement a packet-based two-way connection 24 as communication between the processing nodes. In this specific embodiment, the two-way connection is implemented with a set of one-way = paths (for example, line 24A is used to transmit packets from processing node 12A to processing node 12B 'and line 24B is used to transmit packets from processing node 12β to processing node 12A). The other sets of lines 24c to 24H are used to transfer packets between other processing nodes as illustrated in FIG. Connections can be quickly coordinated in a buffered storage area, as communication between processing nodes (,, coordinated connections, or in a non-coordinated manner, as processing nodes and 1 / 〇 胄 beams ("non-coordinated connections).) In addition, non-coordinated connections It can be implemented with a link chain connection structure between 1/0 devices to replace 1/0 bus 22. The connection of two or more nodes via coordinated connection is called, coordinated structure, and similarly, via non- The connection between two or more nodes that are tuned is called a "non-coordinated connection." It should be noted that a packet to be transmitted by a processing node to another can pass one = multiple intermediate nodes. For example, one by processing The packet sent by node M to point 12D at point P can be processed by processing node or processing node I]., • As shown in Figure 1, any appropriate routing algorithm can be used. ^ Zhang scale suitable grid (210 7 9 91890 521189 A7 B7 V. Description of the invention (10) The memories 14A to 14D may include any suitable memory device. For example, the memories 14A to 14D may include one or more RAMBUS dynamic random access memories (RDRAMs), the same Dynamic random access memory (SDRAMs), static random access memory, etc. As mentioned above, the address space of the computer system 10 is specified throughout the memory 14A to 14D. Each processing node 12A to 12D may contain a memory map Map to determine which address maps to that memory 14A to 14D, and therefore a memory request for a specific address needs to be arranged at one of the processing nodes 12A to 12D and needs to be routed. In a specific embodiment The coherent point of the address in the computer system 10 is the specific memory controllers 16A to 16D connected to the memory storage bytes corresponding to the address. In other words, the memory controllers 16A to 16D are responsible for ensuring each The memory accesses to the corresponding memories 14A to 14D are generated in a coordinated manner in a fast buffer storage area. The memory controller 6 A to 16D may include control circuits to serve as the interface from the memory 14 to the ud. In addition, the memory The body controllers 16A to 16D may include a request sequence to arrange the memory requests. In general, the logic interfaces 18A to 18L may include a buffer memory to receive packets and buffers from a bidirectional connection The packet sent on the connection. The computer system Π) enables the flow control mechanism to send packets. Example 2: The interface logic in each node can store some buffers of each type ... the other end of the communication connection In the interface logic of the receiving node. A node does not transmit packets until the receiving node has an idle buffer memory as a storage packet. When each buffer misstores a packet in the receiving node), the receiving node transmits " This paper size applies ... 10

I 91890 521189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 11 91890 A7 V. Description of the invention (η) to the transmitting node, indicating that the buffer storage has been released. This type of organization is called, "Combined Order Basic" system. Referring to Figure 2, a block diagram illustrating processing nodes 12A and 12β is shown to illustrate an exemplary embodiment of a bidirectional connection 24 among them. Communication connection 24 and other The specific embodiment is possible and considered. In the specific embodiment of FIG. 2, the bidirectional connection 24 includes a unidirectional line 24A and a unidirectional line 24B. The line 24A includes a clock signal line (CLK) 24AA and a control signal line (CTL) 24A through B, and the command / address / data bus (Cad) 24AC. Similarly, the line 24b includes a clock signal line 24ba, a control L line 24BB, and a command / address / data bus 24BC. Clock line Transmits clock signals indicating sample points used to control lines and commands / addresses / data buses. In a specific embodiment, data control bits are located on each edge of the clock signal (ie, rising and falling edges). ) Transmission. Therefore, each clock cycle has two data bits per line. The time used to transmit and transmit one bit per line is called here, the bit time. In the embodiment, each clock cycle includes two bits of 7G time. One packet can transmit two or more bit times. One clock line can be used according to the width of the command / address / data bus. For example Four clock lines can be used for a 32-bit command / address / data bus. The control line indicates whether the data transmitted on the command / address / data bus is the bit time or bit of the control information. Time. The control line will be established to refer to the bit time that does not control the information, and the bit time that is not established to indicate the data. The thick __ ^ shell material can be immediately after the corresponding control information. In a specific paper ruler Money equipment -------- Order --------- AWI (Please read the precautions on the back before filling in this page) Hui 5's Zhang ruler home standard (CNS) A4 specification ⑽ 521189 V. Description of the Invention (12) Embodiment 'Other control information may interrupt the transmission of data. Such interruption can be performed when the control line is established due to the establishment of some bit time of the control line during the transmission of data and the transmission of control information. .Control information for interrupted data is available Do not indicate that the data will be the next. In addition, in a specific embodiment, the control line may not be established to indicate the delay time when transmitting the control information. One of the control lines may instruct the control information to continue later. &Quot; P The order / address / data bus contains a set of lines to transmit data / control bits. In a specific embodiment, the command / address / data bus can include 8, 16, or 32 lines. Depending on the design choice, each Each processing node or bridge can use any of the number of lines supported. Other specific embodiments can support commands / addresses / data buses of other sizes as required. According to a specific embodiment, different signals can be used for commands / addresses / Data bus discharge material pulse. Alternatively, the line can carry valid materials (ie, logic " Γ, which is represented by a low voltage on the line, and logic " expressed by a high voltage) or valid data (where logic " "is on the line j ^ No electricity, and logic "0" is represented by low voltage). Packets transmitted in the computer system 10 may pass through one or more = nodes. For example, 'in line M. Here is the processing section: The packet to processing node 12D can be processed by processing node 12B or processing t 12c (see Figure i. If the processing node is

a ^ The packet can be coordinated to the processing IS point 12B, and the processing node 12B can receive the packet, that is, the processing node 12D. On the other hand, the Yun f packet is forwarded to processing ..., Lang Dian called to send the coordinated packet to the processing point 12C, the processing node, the point can be reached ~ ----- then transfer the packet to 91890

Aw ^ -------- ^ --------- (Please read the notes on the back before filling out this page) 12 521189 A7 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs (13) Transport to processing node 12D. Any suitable packet routing algorithm can be used in the computer system 10. Other embodiments of the computer system 10 may include more or fewer processing nodes i 2 than the embodiment of FIG. 1. The coordinated packets used in the computer system 10 may have different formats and may contain different data. Figures 3 to 6 illustrate the form of untargeted coordinated packets that can be used to process the sub-system u. Figures 3 to 5 illustrate model coordination information, request and reply packets, respectively, and Figure 6 illustrates a model coordination data packet. The info packet carries information about the general operation of the communication connection, such as flow control information, error status, and so on. Requests, and response packets carry control information about execution. Some request and reply packets specify subsequent data packets. The lean packet carries lean information about the execution and response request or reply packets. Other embodiments may use different packet formats. The exemplary packet formats of Figs. 3 to 6 are shown in the contents of bits 7_〇 of the octet, which are transmitted continuously, in bit time, and in parallel. The total amount of time used to transmit each data unit of a packet (such as a byte) is referred to herein as "bit $". Each bit time is part of the period of the CLK signal. For example, in a single period of a signal, The first byte may be transmitted on the rising edge of the CLK signal, and a different byte may be transmitted on the falling edge of the CLK signal. In this case, the bit time is one and a half of the CLK signal period. No bit time is provided in the figure It is reserved for specific packets, or used to transmit specific packets. The fields indicated by the dotted lines indicate optional fields that are not included in all types of packets. Figure 3 shows one of the sub-systems 12 that can be used for processing. Demonstration coordination tm⑽0) Illustration of packet 30. 1nf0 packet 30 contains four bits' paper size applicable to Zhongguan Family Standard (CNS) A4 specifications ⑽χ depending on public love 91890 (Please read the note on the back? Fill in the matter --- ----- Order -------- I ^ _wi. Fill in this page) 13 521189 B7 V. Description of invention (w) Time in one octet coordinated communication call 5: 〇] in the first digit Time (ie, bit.-Two bit command field c figure please The reply packet is transmitted in bit m0). The 4th and 5th parity positions. Apricot from Ding A ^ 3 is similar to the command code encoded in the Aida field. It does not contain bit transmission information in the nearest processing section 4 0 # 30 can be used to Because, and therefore, no need to delay any 9 packets, not in the structure, the packet can be used to transfer the memory to the receiving node. In addition, it has been used to transmit information and release the memory. Other types of information Second, the flow meter draws slow packets and non-operational (NOP) packets, such as the 7th = 3 System Synchronization (SynC) embodiment, the information agreement may require information from the field. In a specific case, it needs to be terminated at its end node. Accept. &Quot; Do not * flow control and follow the packet can be used to process the demonstration coordination request bit in the sub-system 12: Figure No. The request packet 32 contains eight bit time in one eight two :: adjust the communication connection. Request packet 32 It can be used for initial execution (for example, fixed item fetch or write execution), and for those addresses that carry the execution role: seek 'to transmit the request during the completion of the execution. Generally, the request packet instruction will be performed by the end node. Fuck The type of bit identification request in the command field Cmd [5: 0] is transmitted during bit 。. The bit in the source unit field SrcUnit [1: 〇], which contains the value of the source unit in the source node, is also in the bit. Time 〇 Transmission ^ The types of units in the brain system can include memory controllers, fast 2-speed storage areas, processors, etc. Contains the bits in the node field SrcNode [2: 0] that identify the value of the node that started the execution , During the bit time i, the transmission source contains the end point that uniquely identifies the end point value # '° _______ Point field This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm 521189 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by Consumer Cooperative A7 V. Description of Invention (15)

The bits of DestNode [2: 0] are also used to route packets to the destination node during bit time 1. Specialized and available " Dagger 3 to identify the end unit value in the single μ μ point of the receiving envelope. End point of the received packet. End unit unit DestUnitM · Old and young a yuan, also in bit time! During transmission. [_〇] The position of many request packets also includes the source tag field SreT "4.00 yuan at bit time 2, this office _ 士 agl4.〇J's position at time 2 and the source node SrcNode [2: 0] and the source single-point item field and shoulder field SrcUnit [1: 〇], the only packet that can be connected to the packet is a specific implementation of + # to seal the adjacent injury. Bit time 3 can be used for some requests to transmit the least significant bit of the memory address affected by m J for a χ q execution. Bit times 4 to 7 are used to capture the bits of 1,131 and addr [39: 8] in the address field. This address field contains the effective bits of the address affected by the execution> 1. yuan. Some undefined fields in 32 are available. X J is used for various request packets to carry special order information. Figure 5 is an illustration of a sample coordinated response packet 34 that can be used to process the secondary system 12 embedded in the system. The reply packet 34 includes a command field Cmd [5: 0], a destination node field DestNode [2: 〇], and a destination unit field DestUnitH: 〇]. The destination node field DestNode [2: 〇] identifies the destination node of the reply packet (in some cases, this reply packet can be the source node or target node for execution). The destination unit field DestUnit [1: 0] identifies the destination unit in the destination node. Different types of reply packets may contain additional information, for example, a read reply packet may indicate the total number of read data provided in subsequent data packets. The probe response can indicate whether a copy of the requested cache block is reserved by the probe node (using the selective shared bit "Sh" at bit time 3). This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) 91890 Packing -------- Order --------- (Please read the precautions on the back before filling in this (Page) 521189 A7

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I

Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521189 A7 --B7 V. Invention Description (17) Contains information transmitted in bit time 0 and 1 during the connection of eight bits. Similarly, a packet bit time 0 of a 32-bit connection may contain information transmitted during bit-time connections 0 to 3 during an eight-bit connection. The following formulas 1 and 2 illustrate the formation of a 16-bit connection bit time 0 and a 32-bit connection bit time according to the bit time of the 8-bit connection. BT016 [15: 0] = BT18 [7; 〇] I) BT28 [7: 〇] ⑴ BT032 [31: 〇] = BT38 [7: 〇] II BT28 [7; 〇] // BTl8 [7: 〇] // BT08 [7: 0] (2) Figure 7 is Table 38, which lists the different types of coordinated packets that can be used to process the secondary system. Other specific embodiments of the processing subsystem 12 are possible and considered ' and may include other appropriate packet types and command field decoding groups. Table 38 contains the command code block. This command code block contains the content of the command field Cmd [5: 0] for each coordinated command, including the command column for the mnemonic symbol indicating the command, and the packet type block. This packet type block indicates which Coordinated packets 30, 32, and 34 (and data packet 36, specifically specified here) are used in this command. Brief functional descriptions of some commands in Table 38 are provided below. A read execution can use a read (sized) request, a read block (RdBlk) request, a read block sharing (RdBlks) request, or a read block request with a modification (RdBlkMod). .Rea (j (sized) request is used for non-cacheable reading or reading data that is different in size from the fast buffer storage area. The total amount of data to be read is encoded into the Read (Sized) request packet. About fast buffer storage area To read, you can use the RdBlk request, unless: (0 requires a writable copy of the cache area, ----------- install -------- order-- ------- · (Please read the notes on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 (2) 0X 297 mm 17 91 ^ 90 521189 Wisdom of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Property Bureau 91890 A7 B7 V. Description of the invention (1S) In this case, the RdBlkMod request can be used; or (ii) A writeable copy of the fast-buffer storage block is required, but there is no intention to modify the known block In this case, the RdBlkS request can be used. The RdBlkS request can be used to change the Efficiently generate certain kinds of coherent plans (for example, directory-based coherent plans). Generally, for initial execution, the appropriate read request is transmitted from the source node to the one that has the memory corresponding to the cache block. Target node. The memory controller in the target node sends PrObe requests to other nodes in the system to maintain coherence, by changing the state of the cache blocks in those nodes and prompting the nodes containing updated copies of the cache blocks. Send the fast buffer storage block to the source node. Each node that receives the pr0be request sends a probeResp packet to the source node. If the probed node has a modification field that reads data (ie, foul data) 4 This node sends a read response (RdReSpoon) packet and foul data to the source node. The node that sends the foul data also sends a MemCancel reply packet to the target node in an attempt to revoke the request read sent by the target node Data. In addition, the memory controller in the target node uses a lean packet The data is subsequently replied by RdResp〇nse to send a request to read the data. If the source node receives one RdResp〇nse packet from a probed node, the received read data will be used. Otherwise, it will use The data from the node. Once each probe response and read data is received at the source node, the source node sends the source to complete the response packet to the standard. ----- Order --------- AWI (Please read the notes on the back before filling in this page) 521189

The target node is used as confirmation of the termination of execution. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A write execution can use a fixed size write (Wr (sized)) request packet or a victim block (VicBlk) request packet start, and the corresponding data packet follows. The Wr (Sized) request is used for data writes that are not cacheable writers or different from the cache block size. To maintain the consistency of Wr (Sized) requests, the memory controller in the target node sends a PrObe request to every other node in the system. To respond to the PrObe request, each probe node sends a ProbeResp reply packet to the target node. If the probing node stores dirty and poor materials, the probing node responds with RdResponse reply packets and contamination data. In this way, the flash cache block requested by Wr (Sized) is returned to the memory controller and merged with the data provided by Wr (Sized). The memory controller sends a target completion (TgtDone) reply packet to the source node after each probe node receives a probe response to provide confirmation of execution termination. The source node responds with a SrcDone reply packet. The sacrifice cache area block that has been modified by the node and returned to the cache area in the node uses vicBlk to request a packet to be sent back to the memory. VicBlk requested no investigation. Therefore, when the target memory controller is ready to send the victim block data to the memory, the target memory controller sends a TgtDone reply packet to the source node of the victim block. The source node responds with a SrcDone reply packet to indicate that the data needs to be sent, or a MemCancel reply packet to indicate that the data has been invalidated between sending the vicBik request and receiving a TgtDone reply packet (eg, responding to an intervention probe). This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love) 91890 Αν- Μ ^ --------- AWI (Please read the precautions on the back before filling this page) 19 521189 A7

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-a change (Dirty) request packet change can be transmitted by the source node in order to obtain storage by the source node in a non-writeable ^ ^ fast buffer storage block . Executions that start with Changet〇Dirty $ are similar to read operations, except that the target node does not send back poor data. If the source node intends to update the entire cache area 3, a ValidateBIk request is available to obtain write permission for the cache area that is not stored by the source node. In this type of execution, no data is transferred to the source node, but otherwise it is similar to the read execution operation. A target can use a TgtStart response to indicate that execution has begun (for example, scheduling a subsequent execution). A non-operational (Noop) inf packet can be used to transfer flow control information between nodes (for example, buffer storage is idle). A Broadcast request packet can be used to broadcast the message between nodes ... (for example, to interrupt the configuration). After you dare, synchronize the info packets to synchronize node operations (eg, error detection, restart, start, etc.). Table 袼 38 also contains the Virtual Channel (Vehan) column. The vchan block indicates the virtual channel that each packet travels (ie, to which each packet belongs). In this specific embodiment, four virtual channels are defined: a non-post-command (Npc) virtual channel, a post-command (PC) virtual channel, a reply (R) virtual channel, and a probe (p) virtual channel. Virtual legacy Next, referring to Fig. 8, the two virtual channels 40A and 40B and their relationship with the processing nodes 12A to 12D are illustrated graphically. Although only two virtual channels are displayed. 'It is necessary to understand that other specific embodiments of the computer system can be used. I 11 -------- Order -------- I (Please read the precautions on the back before (Fill in this page) This paper size is in accordance with Chinese National Standard (CNS) A4 specification (21,297 mm) 20 91890 521189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description (21) Any appropriate number of virtual channels . -In general, "virtual channel" is a communication channel to carry packets between different nodes. Each virtual channel is independent of the resources of other virtual channels (that is, the packets circulating in the virtual channel are usually not affected by the presence or absence of packets in another virtual channel in terms of actual transmission). Packet root two packet types are assigned to the virtual channel. Packets in the same virtual channel may actually conflict with other transmissions (ie, packets in the same virtual channel may encounter resource conflicts) but will not actually collide with packet transmissions in different virtual channels. Some packets may logically conflict with other packets (that is, one packet may logically conflict with other packets due to agreement reasons, coherence reasons, or other such reasons). If the first packet needs to reach its destination node before the second packet arrives at its destination node due to logical / protocol reasons, the computer system may be deadlocked. If the second packet actually blocks the transmission of the first packet (for example, by Occupy conflicting resources). By allocating the first and second packets to separate virtual channels, and because the transmission medium is implemented in the computer system, the packets in the separated virtual channels cannot block each other's transmission, and a deadlock-free operation can be achieved. It should be noted that packets from different virtual channels will be transmitted on the same physical connection (such as line 24 in Figure 1). However, because the receive buffer = registers are available before transmission, virtual channels will not block each other, even when using this shared resource. Each different packet type (for example, each different command field CMD [5.0]) can be assigned to its virtual channel. However, the hardware that ensures that virtual communications are virtually non-conflicting will increase with the number of virtual channels. For example, in a specific embodiment, an individual memory is allocated to each virtual channel. This paper size is applicable to Zhongguan specifications ⑽x2m) -_-21 9R9〇 I -------- ^ --------- (Please read the precautions on the back before filling this page) 521189

(Please read the phonetic on the back? Matters before filling out this page) -III, Install ----- ^ --------- # II I- 521189 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 5. Description of the Invention (23) The packets of the Tao can be routed separately via the computer system 10. For example, a packet traveling through the first virtual channel, node 12A to node 12D can pass through node 12B 'and a packet traveling through the second virtual channel' from node 12a to node 120 can pass through node 12C. Each node can contain circuitry to ensure that packets on different virtual channels do not actually conflict with each other. In a non-coordinated structure, packets from an I / O node can pass through each other I / O node between the 1/0 node and the main bridge (see Figure 19). Note that the 1/0 node can be connected to the virtual channel in a similar way as shown in Figure 8. In a specific embodiment described in more detail below, the command packet buffer memory is assigned to each virtual channel to buffer packets traveling on the virtual channel. Individual data packet buffers are also allocated to each virtual channel that can carry data packets. Packet buffer storage (each item can contain a significant amount of bit time) and data packet buffer misregisters (which can contain a significant amount of bit time per item to maintain fast buffer storage blocks by separating commands ) Will save buffer memory space while still providing proper data storage. Can implement more people than the data packet buffer storage. Second packet buffer storage (because all data packets have corresponding requests or packets, but not all corresponding requests or reply packets with corresponding data packet management capabilities will be improved and more efficient. The buffer memory space is used in the ground. Figure 9 on the ground is a table 42 illustrating the virtual itit defined according to the specific embodiment of the computer system 10. Other specific embodiments are possible and considered. For the specific embodiment shown, definition four Virtual channels. Packets that belong to the connected virtual channels are shown in Figure 7, and packets that belong to the connected virtual channels are shown in Figure 20. ~ This paper is closed at the time of Guan Jiaxian (CNS) A4 inspection ( 210 X 29? 1 ¥ 7 23 91890 ----------- Install -------- Order --------- (Please read the note on the back first? Matters then (Fill in this page) 521189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 91890 A7 V. Description of Invention (24) A specific request can be a "back" or "non-post" request. Generally speaking, when the request is When the source node transmits (for example, by the source node Interface), a post request is considered to be completed by the source node. Therefore, a post request is politically completed at the source knowledge point. As a result, the source node can issue other requests and continue other operations, while the packet or post request packet proceeds to The target node and the target node request after completion. The source node does not directly detect when the subsequent request is actually completed by the target node. In an exemplary embodiment, the coordinated request packet contains the last bit in the command field as a virtual channel identifier. A post-coordination request is completed in the coordination structure by sending a TgtDone response to the source node before completing the request before the target interface (for example, 'uncoordinated connection'). A non-post request, as opposed to a post request, is completed at the target interface. Requests that were not completed at the source interface before. In this way, the source of the request directly perceives (through completion of the request) that the request has been completed at the target. In general, the different non-post-request packets do not have logical / contractual conflicts with each other, because up to When the end point is reached (that is, the execution goal), there is no order in between. Therefore, Non-post-request packets can be included in a virtual channel. In the exemplary embodiment, post- and non-post-request packets belong to separate virtual channels to provide compatibility with certain input / output (or peripheral) bus protocols. For example, peripheral parts The connection interface (PCI) confluence interface provides writing after the interface. For operations that originate from PCI, the following sequence rules are required by PCI: (i) writing from the same source still maintains the order on the target interface, (ii) thereafter Followed by reading from the same source and writing after reading, the national standard (CNS) A4 specification ⑵Q χ Norwegian ^ ^ ~~~ — binding ---------. (Please read the precautions on the back before filling out this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521189 V. Description of the invention (25) Completed on the target interface before the materials are returned; (iii) Non-post-write can not exceed Write from the same source later; and (W) Post-write needs to allow past non-post requests. Requirement (1) is achieved by placing a request to order the virtual channel afterwards (and therefore it is still scheduled to a specific goal) and certain restrictions imposed by the main bridge (see Figure 28). Requirements (ii) and (iii) are logical conflicts between the post-request channel and the non-post-command channel on a non-coordinated structure. Additional details on logical conflicts over uncoordinated links are provided below. The current writing is restricted to the main bridge by implementing some two, and is transmitted from the uncoordinated connection to the coordinated connection. The requirements (η) and (iH) can be achieved (see Figure 28). The request (lv) can be achieved by providing individual post-order, non-post-order, and replying to the virtual channel. Later and non-post requests can result in the generation of probe request packets (to maintain coherence in the coordination structure) and response packets (to transfer data and provide confirmation of execution). Therefore, the probing packet and the reply packet are not included in the same virtual channel after the false positives and negatives (to avoid deadlock due to resource conflicts and logical conflicts). Furthermore, a probe packet can cause a probe response and a read response packet to be generated, and therefore the response packet is placed in a separate virtual channel. Reply packets can also generate additional reply packets (for example, __ and Talk_ can generate each other). Therefore, reply packets may conflict with other reply packets logically, if all reply packets are assigned to the same virtual channel. However, dispatching reply packets to several different virtual channels is undesirable because it increases resource requirements (for example, buffer storage) to handle additional virtual channels. It should be noted that the reply packet is the result of requesting ^ to Pakistan (later or non-later), directly or indirectly (such as through the investigation that produces the packet with ___ 乂 覆)

'Paper size applies to China National Standard (C'NS) A4 specification (210 X 91890 ----------- installed -------- order --------- (please (Please read the notes on the back before filling this page) ^ 21189 Printed A7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------------- V. Invention Pay (26) 'Therefore, in an exemplary embodiment, nodes 12 to i2D (and the following I / O nodes that are not shown) can be set to allocate sufficient resources for processing after the initial or non-post request packet is executed. Any response sent during the execution of the response = reply packet (including any reply data packet). Similarly, before generating a probe request packet, a node can be set to allocate sufficient resources to process each probe packet (if the reply packet will return to (The node). Because this pre-allocated resource 'can avoid logical conflicts and all response packets can be received by the processing node. Therefore, the' response packets can be merged into all the response virtual channels where the response packets (and corresponding data packets) are feasible. Probe the response packets Proceed in the probing virtual channel. Probing is used to maintain differences in memory locations The coherence between the cache buffer copy and the memory location itself. A coherent action corresponding to the first requested packet to be processed by the memory controller can be done before the subsequent request packet is processed. For example, if the memory controller The sequence is full of requests for the same cache area. The memory controller will not generate additional request packets until the first request is completed. Therefore, the probe request packets can be dispatched to separate virtual channels to ensure that they are separated from other virtual channels. The resource conflict of packets in the channel will not block the probe request packet. Table 42 also indicates the types of communication connections (such as coordinated or uncoordinated) that support various types of virtual channels. For example, both uncoordinated and coordinated connections support post-command, non-post- Command, and reply to the virtual channel. However, because the probe request packet is used to ensure that the coordination and non-coordination links do not support coherence, a non-connection will not be used as the probe virtual channel. ---- Install -------- Order i (Please read the precautions on the back before filling this page) # This paper size applies China National Standard (CNS) A4 (210 x 297 mm) 26 91890 521189 A7 Β7

Referring to Figure 10, a block diagram of an exemplary processing node 12A is shown. Other processing inscriptions > System implementation The point of view 12Bi 12D can be similar. Furthermore, the processing node 12a 5 々GAN Er sighs again. It is possible that other specific embodiments of the IT team to 12D are considered. In Figure 10, the extravagant perch is added. Π "This is in conjunction with the review series 18A, 18B, 蛊 β々 steep mochi 3 interface Ma Yong" 18C and memory controller 16A. In addition, Lang point 12A includes processing award > The processing core 52 and the cache processing logic 58 and optionally include the second processing 0 packet cache 54. The second interface logic 18A to 18C is connected to the packet management logic 58. The processor and processor ^ r '52 and% are connected to the fast buffer: 0 and 54. The fast buffer storage areas ⑼ and 54 are connected to the packet processing ^ The packet processing logic 58 is connected to the memory controller 16A. Generally speaking The packet processing logic 58 is configured to respond to the request packet received on the connection connected by the processing node 2 in response to a request from the fast buffer sub-regions 50 and 54 and / or the processor core η *% to generate a request packet, and In response to the execution of the service selected by the memory controller 16

Generate a probe request and reply packet, and route the packet so that node 12A is an intermediate node to another-interface logic 18 ... 8C for transmission to another node. The interface logic 18A, 18B, and 18C may include logic to receive packets and synchronize the packets to the internal clock used by the packet processing logic 58. The packet processing logic 58 may include hardware to support resource independence of the virtual channels supported by the computer system 10. For example, the packet processing logic 58 may provide an individual buffer memory for each virtual channel, as illustrated in the figure. Another embodiment may provide hardware to provide resource independence of the virtual channel in the interface logic 18A to 18C, or any appropriate location. This paper size is in accordance with Chinese National Standard (CNS) A4 specification (⑵〇χ 297 公 爱) ----- 27 f Please read the note on the back first? Please fill in this page for more details) 1 Ding --------- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 91890 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Areas 50 and 54 contain cache memory, which is configured to store data in cache areas. The cache areas 50 and 54 can be combined into individual processor cores 52 and 56. Alternatively, the cache areas 50 and 54 can be connected to the processor cores 52 and 56 by a rear cache area structure or a coaxial structure upon request. Furthermore, the cache areas 50 and 54 can be implemented by a cache area system. If needed, the fast buffer memory areas adjacent to processor cores 52, 56 can be combined into processor cores $ 2 and $ 6 (in the cache memory system). Processor cores 52 and 56 contain circuits To execute instructions based on a set of predefined instructions. For example, the x86 instruction group structure can be selected. Alternatively, Alpha, PowerPC, or any other instruction can be selected Order structure. In general, the processor core accesses the data and instructions of the cache. If a cache miss is detected, a read request will be generated and sent to the map of the missing cache block. The memory controller in the node. Referring to FIG. 11, a block diagram of an exemplary embodiment of the packet processing logic 58 is shown. Other specific embodiments are possible and considered. In the specific embodiment of FIG. Ji, the packet processing logic 58 includes a first set of command and data packet buffer memory 60, a second set of command and data packet buffer memory 62, a third set of command and data packet buffer memory 64, control logic 66, data buffer memory slot 68, and Reply counter slot 70. The command and data packet buffer memory 60 includes a back command buffer memory (PCB) 60A, a non-post command buffer memory (NPCB) 60B, a reply buffer memory (RB) 60c, and a probe buffer memory. (PB) 60D, post-command data buffer memory This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) " ----- 28 Si 890 ---------- ---- ------ Order --------- (Please read the precautions on the back before filling out this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Employee Cooperatives 521189 A7 B7 V. Invention Description (29) ( PCDB) 60E, non-post command data buffer memory (NPCDB) 60F, and reply data buffer memory (RDB) 60G. Similarly, the command and data packet buffer memory 62 includes a post command buffer memory (PCB) 62 A, Non-post-command buffer memory (NPCB) 62B, response buffer memory (RB) 62C, probe buffer memory (PB) 62D, post-command data buffer memory (PCDB) 62E, non-post-command data buffer memory (NPCDB) 62F, and response data buffer memory (RDB) 62G. Command and data packet buffer memory 64 includes post-command buffer memory (PCB) 64A, non-post-command buffer memory (NPCB) 64B, reply buffer memory (RB) 64C, probe buffer memory (PB) 64D, post-command Data buffer memory (PCDB) 64E, non-post-command data buffer memory (NPCDB) 64F, and reply data buffer memory (RDB) 64G. The command and data packet buffer memory 60 is connected to receive packets received by the interface logic 18A (e.g., on line 24B). Similarly, the command and data packet buffer memory 62 is connected to receive packets received by the interface logic 18B, and the command and data packet buffer memory 64 is connected to receive packets received by the interface logic 18C. Command and data packet buffers 60, 62, and 64 are connected to control logic 66. In addition, the reply data buffer memories 60G, 62G, and 64G are connected to the data buffer memory slot 68. The data buffer memory slot 68 and the response counter slot 70 are connected to the control logic 66, which further includes a node ID register 72, a command packet active register 74 A to 74C, and a data packet active register 76A to 76C. The control logic 66 is connected to the interfaces 1 8A to 18C via the receiving and transmitting interface, and is also connected to the memory control --I--111111AW ------- I order (Please read the notes on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210x 297 mm) 29 91890 521189 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 30 A7 V. Invention Description (3 〇) 16A and fast buffer storage area 50 (and optional fast external data buffer storage slot 68 is further connected to the record == Pirate 16A and fast buffer storage area 50 (and selective fast buffer Storage area 54) 〇 Each set of command and data packet buffer storage provides different buffer storage for each virtual channel. For example, in this embodiment, the post-command buffer storage 60A can be assigned to the post-command virtual channel, not the post-command. The command buffer memory 60B can be assigned to a non-post-command virtual channel, the reply buffer memory 60C can be assigned to a reply virtual channel, and the probe buffer memory can be assigned to a probe virtual channel. Α In this way, receiving packets on a virtual channel will not Will be Reception of packets in one virtual channel is hindered. Packets from each virtual channel can be stored in the command packet buffer memory corresponding to the virtual channel, and therefore will not actually conflict with packets received by another virtual channel (its storage In a different command packet buffer memory). Buffer memory M and 64 similarly named buffer memory can be assigned to the virtual channel as described above. Similarly, the data packet buffer memory is provided for each virtual channel carrying a data packet. In an exemplary embodiment, the probe virtual channel may not carry data packets. For example, the post-command data buffer memory may be assigned to the post-command virtual channel, and the non-post-command data buffer memory 60 may be assigned to non-post-command data. The virtual channel and the response data buffer storage 60G can be assigned to the response virtual channel. Buffer storages similarly named in the buffer memories 62 and 64 can be assigned to the virtual channels as described above. In this specific embodiment, the interface logic 丨 8A to 〖8C is configured to be divided into M's scales applicable to China, standard (CNS) A4 specifications⑵G x 29 91890 AW ^ -------- Order— (Please read the notes on the back before filling this page) # 521189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 31 A7 V. Description of the Invention (31) The packet provided on the control path and the shell material packet provided on the data path. The control path is connected to the command eight punch storage 60A to the coffee interface ^ Μ㈣ memory (for example, the interface logic 18Α is connected to the control and is out of date). The controller is connected to the data packet buffer storage (for example, ㈣ _ to 600, which is connected to the data channel by the interface logic 18A). :: = 66 is configured to receive the indication of the packet type via the receiving and transmitting interface-step by step is configured to allocate buffer storage The specific embodiment that the receiver item considers in the received packet, the received packet is not an interface logic: In the specific embodiment, the control logic 66 can receive a control (ctl) signal to distinguish the 7G time of the shell material and the control information. Bit time. Generally speaking, the control logic 66 may be configured to handle packets that are stolen from different buffer storages and are unrelated to packets held in other buffer storages. Therefore, actual collisions of packets traveling between different virtual channels will be avoided. In an exemplary embodiment, the control logic 66 checks the packets in the command packet buffers 60, 62, and 64 to determine whether the packet is assigned to the node 12 (the node ") or forwards it to another node. The node ID register a stores the node ID of "the node", and the logic 66 will perform a comparison on the node E to determine whether the packet is assigned to "the node, which needs to be noted" in this specific In the embodiment, the packet in the probe virtual channel is a broadcast packet, and is therefore designated to "this node" and "this node" will transmit the other node of the packet. Therefore, the control logic 66 may omit the comparison of the point ID's of the packet nodes received on the probe virtual channel. However, in addition to exploring the virtual channel, the packet in the virtual channel is a directed packet, where the end node field of the packet identifies whether the packet is specified to the node or point or will be forwarded to another node. Therefore, thanks to the Guan Family Standard (CNi ^ F (_21Q χ 29 91890

Aw ^ --------- (Please read the notes on the back before filling out this page) 5. Description of the invention (32 system logic "can perform node ID comparison on such packets. Control logic 66 may include one or Multiple routing tables. For each destination node, the workers p + /, not the same, that is, the interface logic 18A to 18c can be broadcast packets or designated to 1 other M κ et ^ state from turn to turn one by one. Packet. The control logic 66 can be packeted. When receiving the received packet received via the identified 1 I, sub ^^ interface, 18A1, it will be idle, and the packet will be stored in the packet buffer memory. In addition, if the packet and the company—Daochen ’s virtual envelope specifically specifies a data packet, then the control logic 66 forwards the packet and the sequence is as follows:】 Ding / ..., Ti Caiyue ’s data packet, control The logic does say that for the allocated packet buffer, the s-virtual packet buffer storage availability of the virtual packet. If the control logic 66 determines that the packet (and the data packet, if determined) will be forwarded and confirm the appropriate packet. Know the availability of flush storage, then control The logical receiver uses the receiving and transmitting interface to forward the packet to the identified interface logic 18A to 18c. The interface logic 18A to 18c then forwards the packet to the receiving node. In addition, the control logic 66 notices that the corresponding type of buffer memory has been released ( Because packets and data packets are forwarded if specifically specified). An information packet can then be transmitted via the appropriate interfaces 18A to i8c to notify the availability of node buffer storage at the receiving end. Then the right packet refers to "the" Node ", the control logic 66 then processes the packet according to the packet type. For example, if the packet is a write request directed to the memory controller 16A, the control logic "attempts to pass the write request packet to the memory controller 16A . For example, 'If the sequence is full, the memory controller 16A can use the sequence to execute the processing and can reject the write request packet. If the received packet is a probe request packet, it means I logic 66 Compatible with Fast Zones 50 and 54 (and any processor Shan scale applicable to Zhongguanjia Standard (CNS) A4 specifications (210 X 297 public love) 521189 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Co-operative Society 91890 A7 V. Description of Invention (33) Quick buffer storage areas in cores 52 and 56) to determine the status of the fast buffer misstore area blocks that are located by probing. The control logic 66 can then borrow Generate a probe response to the status of the cached block area of the report address response packet (or a read response packet with data, if the cached block has been modified), and then send a probe response packet if the receiving node has Indicate the availability of appropriate packet buffer memory. In addition to processing received packets, control logic 66 can generate packets in response to fill requests and sacrifice blocks from fast buffer storage areas 50 and 54, and the response is directly from the processor core Packets for requests from 52 and 56 (eg, non-cacheable requests, I / O requests, etc.). Furthermore, a reply packet can be generated in response to the memory controller providing the transmitted data or completing the execution. If the receiving node buffer memory is available, the control logic 66 may generate a probe request packet in response to the memory controller 16 A which selects the corresponding request for processing, and may broadcast the probe request packet. As mentioned above, a node allocates sufficient resources to process the received reply packet, and responds to the request packet transmitted by the node. In an exemplary embodiment, the control logic 66 may transmit the packet, which will cause the reply packet to be sent back to the node in two ways: when a request packet is generated for initial execution (for example, the response is processed by the fast buffer storage areas 50 and 54 or processed) Requests from the processor cores 52 and 56) 'and (η) when a probe request packet is generated for a request packet directed to the memory controller i 6A. More specifically, mode ⑻ may occur in a fixed-size write. In either way, control logic: allocate resources to provide receiving and processing reply packets. _ & —Specific embodiment, the control logic 66 can be buffered by the data. The paper size applies the Chinese National Standard (CNS) A4 specification mo X 297 public copy. ^ --------- (Please read the note on the back first Please fill in this page again for details) 521189 B7 V. Description of the invention (34) The memory slot 68 and the reply counter slot 70 minutes to reply. The data buffer is stored in the memory for receiving and processing. The buffer storage tank 68 may include a block of a fast buffer storage area, and the response count is a second storage lean counter. The second data buffer memory slot item contains a plurality of response data for execution. -A counter can be equipped with a knife to store any status corresponding to the reservation to be provided in the probe reply; data: counter calculations assigned to the reply and assigned (for example, until the expected one: the number of responses?) Enables: the number of received reply packets Data can be stored in the assigned punch. It should be noted that 'at most, two ",-red wrong storage seal" L: The controller came' if Memc_ reply packet 'also arrived before the reply packet was sent, and this sturdy body control fast, and An exploration of two data packets of a copy of the fast buffer area by 〃Beco, will be discarded by 禊 杳 明 朴 七七 右 镬 received from the body controller. 疋 Yin according to the type of implementation ... once received Each prospective response and Abeco 'control logic 66 can send data to the memory controller 16A or the fast buffer area 5 ()-54. For example, if the response is generated in response to a response generated by the packet processing logic 58 The probe reply to the probe request will be sent to the memory controller 16A. Or, if the reply is generated by reading the lamp, the data can be transferred to the fast buffer storage areas 50 and 54. The buffer storage slot 68 can also be used to store data to be transmitted by the node 12 A. For example, for the write-sacrifice block data generated by the node 2a or the written data will be stored in the data buffer storage 丨 # 68. $ # 'for this Individual data will be provided for individual buffer storage. In addition, 1 paper size woven card coffee 297 (Public Love) 34 91890 521189 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 5. The invention description (35) is not provided for Different implementations of the buffer memory, while the line type of individual buffer memory. Generally speaking, as used herein, a buffer memory is a piece of buffer memory used to store one or more sub-returns. The buffer memory may contain One or more registers, latches, registers, or other timing storage devices. Alternatively, the buffer storage may include a set of random access memory (RAM) cells for the women's volleyball team. The buffer storage is divided into A plurality of storage locations, each storage location is configured with an information item of a corresponding type of buffer storage. The storage location can be allocated and unassigned in any suitable way. For example, 'buffer storage can be operated to transfer a FIFO buffer storage (FIFO), where older items are deleted, the location of the stored item is shifted down. Alternatively, end and end counters can be used to indicate buffer storage The oldest and newest item location, and the item can remain in a specific storage location in the buffer memory until deleted. The name "control logic" as used herein refers to any combination of combinatorial logic and / or executed on input Operate and generate a state machine that rotates in response to completion of the operation. In an exemplary embodiment, the packets are received by the interface logic i 8A to 18 C in a series of bit times. The interface logic 18A to 18c indicates whether the command or data bit time is transmitted, and the control logic 66 causes the appropriate buffer memory to store the bit time. The control logic 66 may use a command packet active (CPA) register 74 and a data packet active (DPA) register 76 to identify which virtual channel a receiving packet is assigned to. A CPA register 74 is provided for each interface logic 18A to 18C (for example, CPA 74A corresponds to interface 18A). Similarly, a fake DPA register 76 is provided for each interface logic ----------- «install -------- order --------- ^ ρ · (Please read the precautions on the back before filling out this page) This paper size applies the Chinese national standard (cns) a4 specification (210 x 297 mm) 35 91890 521189 Smart money employee consumption A7 V. Description of invention (36) 18A to 18C (For example, DpA76A corresponds to the interface i8A. Therefore, in an exemplary embodiment, in response to all the bit time, control the first logical 66 decoding command field (which determines and assigns the received packet to $ That time, the time is 1) The knife is sent to that virtual channel. Control logic 6 The buffer memory is located at the edge of the sword, and is aligned with the corresponding command packet. The buffer logic stores the interface logic 18A 5,,, and the corresponding sound.铒 to 18C) and set the state of cpA temporary storage, which corresponds to receiving jitter seven * field ^ 15 76 镬 The interface logic of receiving packets 18A to 18C, with & a command to assign the packet buffer memory location. From the same interface logic ;: After 18c, the bit time of the subsequent packet is stored in the instruction buffer memory. Straight: Each bit time of the received packet. Similarly, if "specific data packet", the control logic 66 allocates the data packet buffer storage location to the data packet buffer storage corresponding to the virtual channel identified by M ^ ... The lean packet bit time is stored in the instruction The buffer register indicates the position until each bit time of the packet is received. In another embodiment, the interface logic 18A to 18c may collect the bit time of the packet and then send the entire packet to the packet processing logic 58. Here Specific embodiment 'CPA register 74 and ship register% can be eliminated. In another specific embodiment', interface logic 18A can collect several bits to transmit to packet processing logic 58 at the same time, but the bit time The number will be less than one packet. In another embodiment, the buffer memories 60, 62, and 64 may be located in the individual interface logic 18A to 18C instead of the packet processing logic 58. The specific embodiment shown in FIG. 11 Provide individual buffer storage groups, each interface logic 18 people to 18C. In another specific embodiment, the buffer storage paper size puncture _ home standard (CNS) A4 specifications (0x297 public love)- -36 91890 ^ -------- ^ --------- ί Please read the notes on the back before filling in this page)

I 521189 A7 B7 V. Description of the invention (37) (Please read the note on the back before filling this page) The memory can be provided as one or more buffer memory slots divided between interface logic (for each virtual Channel type). In this specific embodiment, the buffer memory does not need to be assigned to interface logic that is not connected to another node (for example, the interface logic 18C of the example in Figure 1), so that the use efficiency of the buffer memory slot is maximized. Therefore, otherwise, the buffer memory allocated to the interface logic 18c will be allocated for use by the interface logic 18A to 18C. Referring to FIG. 12, there is shown a diagram illustrating a specific embodiment of the position of the data buffer memory slot in the data buffer memory slot 68. As shown in FIG. Other specific embodiments are possible and considered. In the specific embodiment of FIG. 12, the data buffer storage slot position 80 includes the source tag field 82, the source point field 8 4, the source early field 8 and the data field $ 6. When the control logic 66 allocates the data buffer storage The slot position 80 is used to store the execution response data packet. The control logic 66 can store the execution source node, source unit, and source tag in the source node field, the source unit field 88 ', and the source tag field 82, respectively. Yinlai, Dundi, Shuiyi point, source unit, and source tag uniquely identify an unfinished execution, and the source node source unit, and source tag are the intellectual property of the Ministry of Economic Affairs corresponding to the unfinished execution. The employee's consumer cooperative prints and carries out the response packets (with the corresponding data packets, and the pair of daggers) identified by the control logic 66, and the data packets can be stored in the assigned items. For example, if the combined thin packet specifies the received reply data packet, then the reply packet :: node, source unit, and source tag will correspond to the source node field: unit field 88, and source tag field 82. Bass, Suwon 敕. It is determined that the position of the data buffer memory slot of the reply data is 80.羑 Without knife, copy from the reply data buffer storage to the allocation of funds :: 枓 Then you can ___ One-pin needle buffer storage slot position This paper size applies Chinese National Standard (CNS) A4 specification (210 ----- — 37 91890 521189 A7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------- B7___ V. Description of the invention (38) 80 in the field of shell materials 86. In an exemplary embodiment, The data area% may contain a block of fast buffer storage area of data. 〃 Next, referring to FIG. 13, an icon specific example of the reply counter 90 in the reply counter slot 70 is shown. Other specific embodiments are Possibility and consideration. In the specific embodiment of FIG. 13, the reply counter 90 packs 3 the source tag field 92, the source node field 94, the source unit field 95, the reply count field%, and the receive status field. When the control logic 66 assigns a reply The counter 90 stores the response count of the execution, and the control logic 66 can store the executed source node, source unit, and source tag in the source node field 94, the source unit field 95, and the fish source tag, respectively. Domain 92. Source node domain 94, source unit domain 9 /, and source tag domain 92 are used in a similar manner to the corresponding fields 84, 88, and 82 of the data buffer memory slot position 80. The reply count field 96 may Initially, when the allocation to execution reaches the expected number of replies for that execution. When the response packets with source nodes, source units, and source tags stored in fields 94, 95, and 92 are received, the response count will decrease. When The response count reaches zero, then all responses have been received and execution will be delivered. Alternatively, the count will start at zero and the response packet may cause the response count to increase until the expected number of responses is received. The reception status field 98 can be used to indicate receipt. The state of the data. Carcinoma refers to the right to not access the cache area and the responsibility to maintain the consistency of the cache area, which is obtained when the node 12A receives the cache area. It is implemented in a demonstration. For example, the MOESI (Modify, Own, Exclusive, Share, and Invalid) status will be used and I—I ---- 11 —Aw ---- --- Order ---------- (Please read the notes on the back before filling this page)

Member of the Intellectual Property Office of the Ministry of Economic Affairs A7 V. Description of Invention (39) Receipt] i field 98 will be coded to one of the supported states. Alternatively, any other suitable coherent state group (eg, MESI state) can be used. Receiving Status The entry field 98 will start to a state corresponding to the condition that no other node has a copy of the fast buffer storage area block that is being transmitted. When a reply is received, the reception status field is updated. For example, if a probe response indicates that a copy of the fast buffer storage area is maintained by the probe node, or if the foul data has a response, the receiving field 98 will be updated accordingly. In a specific embodiment, the shared bits will be included in the probe response packet to indicate that a copy of the cache block is maintained by the probed node that provided the probe response. In addition, receiving a read reply packet from the exploration section. Point # can instruct the node to have a dirty copy of the 2-speed buffer storage block. The read reply packet may also include a common drought bit to indicate whether a copy of the cache block is maintained by the node being probed. 1. It should be noted that the implementation of the data buffer memory slot 68 and the reply counter. The use of knife allocation resources is only an example, and the allocation of resources to process the reply for incomplete execution can be implemented in other ways. For example, an incomplete = 仃 form can be maintained. The form may contain source nodes, source units, source tags, data, receiving status, and number of replies similar to or equivalent to the above, allowing the control logic 66 to determine whether all replies have been received. Referring to Fig. 14, a flow chart showing part of the packet processing logic for receiving packets is shown. Other specific embodiments are possible and the steps shown in the figure are easy to understand, in a particular order: ^ Any appropriate order can be used. In addition, steps can be performed in parallel using packet processing logic 58 ^^. For each interface, the logic is as close as this paper. 297 Public Love 91890 ----------- Shang -------- Order --------- (Please read the precautions on the back before filling this page) 39 521189 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ~ 1 —............ B7 V. Description of Invention (40) ^ '~-18C, the steps illustrated in Figure 14 can be performed in parallel and independently, because the bit time can be received by each interface logic at the same time. The specific embodiment illustrated in FIG. 14 receives packets to the packet processing logic 58 in a series of bit times. Other embodiments may accumulate the bit time of the packets at interface logics 18A to 18C and provide completion packet-to-packet processing logic 58. In this case, the packet processing logic 58 will eliminate the step of managing packet reception in bit time. In the specific embodiment illustrated in FIG. 14, when receiving bit time, the packet processing logic 58 receives a signal from the interface logic, indicating whether the received bit time is part of a data packet or a command packet ^. If the bit time is the bit time of the data packet (determined block ι〇〇), the bit time will be stored in the data buffer memory in the allocation buffer memory location, and the allocation buffer memory location is corresponding to the interface logic ( Step ι〇2) indicated by the active packet register. If the data packet bit time is the last bit time of the data packet, the control logic 66 can invalidate the corresponding data packet active register. On the other hand, if the bit time is the command packet bit time, the packet processing logic 58 determines whether the command packet is being received (for example, if the packet active register is valid, block 104 is determined). If the command packet is in progress', the bit time will be stored in the command packet buffer memory indicated by the command packet active register (step 106). If the command packet bit time is the last bit time of the packet, the control logic 66 will invalidate the corresponding command packet active register. If the command packet is not in progress, the packet processing logic will decode the command field of the recently received enemy packet to identify the ^ -------- ^ --------- (please assign the packet) (Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 size x 297 meals 40- 91890 521189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Invention Description ) Simulated channel (step ⑽). The buffer buffer memory location corresponding to the identified virtual packet will be allocated, and the η packet buffer memory location of the commanded packet bit will be allocated. = Child's order of distribution In addition, the packet processing logic 58 judges a subsequent data packet (determining ... specifically specifying the packet, then the packet processing logic 58 assigns a data buffer memory by a corresponding identification virtual data buffer storage location, and Second: The remaining registers are buffered with the assigned data (step 112). The buffer store 1§ refers to Figure 15 and shows a section for processing subsequent request packets or subsequent request packets. = (For example, the non-flow H and the flow chart of the operation of packet processing logic 58. Other specific embodiments are possible and the steps shown in the figure are easy to understand. I, 15th The specific order is called sun and moon, and any appropriate order can be used. In addition, 'step ..., any

The combination logic in packet processing logic 58 of 1 is executed in parallel. For each interface logic 18A to 18C: / or each command packet buffer memory, the execution in Figure 15 is performed in parallel and independently, because the request packets from different interfaces and / or different virtual channels are actually independent. Alternatively, a group of 10A E requested packets (or one request packet per interface logic! 8A to 18C) can be selected and processed according to appropriate fairness formulas. Generally speaking, the packets selected for processing by a virtual channel follow the order of the packets in the virtual channel (for example, packets from the same source to the same destination are selected in order), but if required, the packets can be selected out of order for processing , If the order rule allows selection out of order. As illustrated in FIG. 15, the packet processing logic 58 determines that the requested packet [the paper size applies the Chinese National Standard (CNS) A4 specification⑵◦ χ 297 公 爱 y 91890 Αν ^ -------- ^ ---- ----- ^ __ w. (Please read the notes on the back before filling out this page) 41 521189 消 A7 B7 V. Description of invention (42) Whether the target is "the node," (decision block 126). For example, The packet 58 can be compared. * Find the packet recorded in the destination node (DestNQde) and the logical node out and the second node stored in the node ID register 72. The point IDs match. No target will be "this node". If this is the target, the package may forward the packet to the appropriate destination node (if specified) (step 128 /, ❹n processing logic 58 can maintain the identification of the boundary °) to forward the packet to Envelope of the transmission interface of the specific destination node. The packet processing logic 58 then seeks the packet to the destination node through the identified interface logic 2. If the logic 58 also determines the user month (and the data buffer storage 'if you want to specify the data packet d' The packet routing table with the receiving node designated by Zhao can =. Example embodiment 'If the request packet specifically specifies a data packet, the logic M ;: The request packet is slowly forwarded until the logic 58 receives the specifically specified data packet. If the request packet targets " the node as the target' then The packet processing logic π can provide a request packet (and the corresponding data packet, if applicable) to the memory controller 16A (step 130). It should be noted that once the request packet is processed (that is, "forwarded or accepted by this node"), The request packet will be removed by the command cache and any corresponding data will be removed by the command data cache. It should be noted that the probe request can be processed in a similar way. However, because the probe request does not have a corresponding data packet, the data packet The "check" will be omitted. Furthermore, because the search request can be a broadcast packet, the search request can be in the inner scale Zhang Yiyi Guan Jiaxian (CNS) A4 specification 42 91890 | 521189 B7 V. Description of the invention (43) After processing (for example, by sending a probe node. Probe nodes, regardless of, diagnosis ~ ', ", fast buffer storage area) and transfer to the buffer storage area, Health: On-site: Other nodes can reply to packets quickly during exploration and transport exploration. It should be noted that if the packet is not received, it is different and the physical package specifies a corresponding packet that has not been received. ❹ Can process the request Packet, even if the data is sealed, Lang Dian can wait for the data packet to arrive, in order to simplify the transfer of or allow the i-packet that specifically specifies the data packet that has been completely received to be forwarded on the same connection, and the other packet # 去 & Pull A right field. When the month packet is processed, the data packet = not received, then when the data packet is finally received

Processed in the manner described above with respect to FIG. 14. f " T Referring to FIG. 16, a flowchart is shown to explain the processing of the response # for the second packet processing logic 58 operation. Other specific embodiments are considered for ... Although the steps shown in Figure 16 are easy to understand and are described in a particular order, any suitable order may be used. In addition, the steps may be performed in parallel using combinational logic in the packet processing logic 58. For each interface logic 18Ai 18C and / or each reply packet to buffer storage theft, the steps illustrated in Figure 16 can be performed in parallel and independently, because the request packets from different interfaces and / or different virtual channels are actually independent. Staff Consumption As shown in Figure 16, the packet processing logic 58 determines the end node of the reply packet in substantially the same manner as above, and the node is " (decision block 144). If the destination node is another node, the packet processing logic will forward the reply packet (and the corresponding data packet, if applicable). If it is located on the line where the reply packet is forwarded, the idle buffer location of the reply virtual channel in the receiving node can Obtained (step 146). This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) 91890 521189

V. Description of the Invention (44 Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 91890 If the end point of the reply packet is "the node", the packet processing logic is reduced by V. Override the δ decimator and update the received status (if the reply is A probe reply indicates that the received status will be changed from the implicit status) (歩 二 148) In addition, the right reply packet specifically specifies the data packet, and the data envelope ^ will be moved from the buffer storage of the response reply data to the one allocated to the reply = red Slow storage (step 150). After reducing the counter more widely, the packet processing logic can test the counter to determine whether all reply packets have been received and processed (decision block 152). If it is determined that all reply packets have been received and Processing, the packet processing logic 58 may notify the memory controller 16A or the fast buffer storage areas 50 and 54 that it can complete execution, and provide the relevant data from the data buffer storage and the reception status from the response counter (if applicable ( Step 154)). It should be noted that once the reply packet is processed (that is, 'forwarded or accepted by " the node', the reply is The packet will be removed from the reply buffer and any reply data will be removed from the reply buffer. In some specific embodiments, if the selected reply packet specifies the corresponding data packet, then The reply packet will be processed even if the shell packet has not been received (ie, the data packet has not been stored in the data buffer storage), or the reply packet processing can wait for the arrival of the data packet to simplify the transfer of the data or allow specific designation of a fully received packet The other packet of the data packet is forwarded on the same connection. If the data packet has not been received when the reply packet is processed, then when the data packet is finally received, the data packet can be processed in the manner described in Figure 14. Figure 17 shows a flowchart The description is used to start a paper standard applicable to the Chinese National Standard (CNS) A4 specifications (Gχ 297 public meals) -------- 44. Packing -------- Order ------ --- WAWi (Please read the notes on the back before filling out this page) 189 189

Fifth, the invention description (45), part of the packet on the communication line connected to the node demonstrates the operation of the packet processing logic 8. Other specific embodiments are possible and considered. Although the steps shown in paragraph 1 are easy to understand, they are described in a specific order, but any order may be used. In addition, the steps can be performed in parallel using the combinational logic in the packet processing logic U. The packet processing logic may initiate packets on the connection in response to fill requests / sacrifice blocks from the cache areas 50 and 54 and / or operations performed by the processor cores 52 and%. In addition, a probe packet may be initiated in response to selecting a memory controller 16A in a memory operation location. The reply packet can be initiated after the probing process, and it is answered that the execution of the node "generated or targeted by" the node "is completed. As illustrated in Figure 17, the packet processing logic 58 determines whether the packet to be initiated may cause data to be returned to the node (decision block 16). For example, a read execution initiated by a node causes data to be returned to the node, while a write execution initiated by a node does not cause data to be returned to the node. Changet〇Dirty implementation may cause data to return to the node (if another node has an affected fast buffer storage area in a dirty state). Similarly, the probe packet may cause the data to be returned to the node. If the cache buffer area affected by another node is dirty, and the probe response points to the point. If execution may result in data being returned to the node, the packet processing logic 58 will allocate a data buffer memory from the data buffer memory slot 68 (step 162). In addition, the 'packet processing logic 5 8 determines whether the probe response will return to the node in response to the packet (step 1 6 6). If the packet is a probe, or if the packet is initiating an execution, causing the probe response to "the node" (for example, a read execution), then the probe response _j ^ 回 _ will be generated. If the answer to the inquiry will return "this ----------- install -------- order --------- (Please read the precautions on the back before filling this page) Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size applies to the Chinese National Standard (CNS) A4 (210 x 297 mm) 45 91890 189 2 5 A7

V. Description of the invention (46) Match the reply counter and set the initial count, or any other suitable node packet processing logic 58. Assign a received counter to receive the reply, and start the reply counter to the expected number of responses: , The number of nodes in the coordination structure) (step 168). (The packet processing logic 58 further determines that the county does not * a # / 疋 疋 疋 疋 No other replies will be returned to this node (for example, km / ft > ^ brother, such as SrcDone, TgtDone) in response to the initial packet burst) . If such other responses are returned, the packet processing logic will start counting (step 165). Subsequently, the packet processing logic 58 transmits the packet (step 170) 〇 Since the resource is allocated in advance to process the reply packet (including the data) before starting an execution, the reply packet can be processed upon receipt. Therefore, even though some reply packets may have logical / protocol conflicts with other reply packets, the reply packets can be merged into the reply virtual channel because the actual conflict is eliminated by processing each reply packet when it is received at its end node. Next, referring to FIG. 18, a block diagram is shown to explain a specific embodiment of the inf0 packet 180 containing the buffer memory release field. Other specific embodiments are possible and considered. The exemplary embodiment illustrated in Fig. 18 ' buffer storage release field includes each buffer storage type. The RespData field corresponds to the response data buffer storage, and the RespOnse field corresponds to the response buffer storage. Similarly, the postCmdData field corresponds to the post-command data buffer, and the PostCmd field corresponds to the post-command buffer. ] S [onpostData field corresponds to non-post-command data buffer memory, and NonPostCmd field corresponds to non-post-command buffer memory. Probe field ^ to probe buffer memory. 11 11 ^ -------- Order --------- (Please read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is applicable to China Standard (CNS) A4 specification (210 x 297 mm) 46 91890 521189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (47) Each buffer storage release area contains two bits, allowing release, Or liberate, each type has a maximum of three buffer memory locations, and a single info packet 180 is transmitted from the transmitter to the receiver for a specific communication connection. If there are more than three buffer memory locations of a particular type, additional info packets will be used to release additional buffer memory locations if needed. The packet processing logic 58 may include various types of buffer memory and each interface logic 188 to μ. The buffer memory count indicates the total number of types of buffer memory provided by the receiver at the other end of the connection connected at each interface. These counters can start when the power is turned on, by transmitting inf0 packets from the receiver to the transmitter, and the buffer memory release field is set to the number of buffer memory positions that the receiver can obtain. If the receiver has more than three buffer memory locations for a particular type, several inf0 packets will be transmitted. The packet processing logic 58 can transmit the packet to a specific virtual channel, as long as the corresponding type of buffer memory (and data buffer memory, if the packet specifically specifies a data packet) is available at the receiver to which the packet will be transmitted. In addition, for the packets processed by the packet processing logic 58 such that each interface 18A to 18C released at the node 12A, the packet processing logic 58 records the number of buffer memory positions of each type. Periodically, the packet processing logic 58 transmits the inf0 packet 180 via each interface logic 18A to 18C, indicating the number of buffer memory locations of the transmitter on the individual communication connection that has been released by the packet processing logic 58. -Non-coordinated structure Referring to FIG. 19, a block diagram of a specific embodiment of the I / O subsystem 200 is shown. Other odorant embodiments are possible and considered. In Figure 丨 9, there is a 'paper scale turning home care standard (CNS) A4 secret Gx crack -------- order --------- (Please read the precautions on the back before filling (This page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives 521189 A7 B7 V. Description of the Invention (48) system embodiment, the I / O secondary system 200 includes a main bridge 202 and multiple I / O nodes 204A, 204B, and 204C. The main bridge 202 is connected to the processing node 12D via a coordinated connection including lines 241 to 24J, and is further connected to the I / O node 204A via a non-coordinated connection including lines 24K to 24L. The I / O nodes 204A to 204C are interconnected via additional non-coordinated connections in a link chain connection structure (lines 24N to 240). It should be noted that although the main bridge 202 shown is separated from the processing node 12, the main bridge 202 may be incorporated into the processing node if necessary. Generally speaking, the main bridge 202 transfers packets moving between the I / O subsystem and the processing nodes. For example, an uncoordinated packet transmitted by I / O node 204B and targeted at processing node 12A passes through I / O node 204A to main bridge 202. The main bridge 202 transfers uncoordinated packets to corresponding coordinated packets. Generally speaking, the I / O nodes 204A to 204C can be executed in the I / O subsystem 200. Execution will eventually target another I / O node 204A to 204C, one on another non-coordinated I / O node, or memory 14. For simplicity, execution can be performed on the main bridge 202 and I / O nodes 204A to 204C, regardless of the actual goal. For example, the main bridge 202 can be started and executed in the I / O secondary system 200, representing requests from processing nodes 12A to 12D, and can be processed from I / O nodes 204A to 204C, with the goal of coordinating in the computer system Implementation of a structure or another major bridge. The packets in the I / O sub-system 200 travel in the I / O stream, which are cluster traffic that can be independently processed by a non-coordinated structure. In an exemplary specific embodiment, m is not in a non-coordinated structure, and all packets can be entered ----------- loading ... (Please read the precautions on the back before filling this page) Order — This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 48 91890 521189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 V. Description of the invention (49) to the main bridge 202 or from the main bridge 2 〇2 march. Therefore, the packets transmitted by 1/0 nodes 204 A to 204C can flow through the connection chain (ie, "upstream") to the main bridge 202. It should be noted that the request packets issued by 1/0 nodes 2Q4A to 204C contain the source node UnitIE ^ Similarly, the reply packet issued by 1/0 nodes 204A to 204C contains the UmtID of the node that generated the reply. Therefore, UnitID can be used to identify the 1 / () stream of the upstream packet. The packet transmitted by the main bridge 202 can be The flow direction receives 1/0 nodes 204a to 204C (ie, `` downstream ''). It should be noted that, in an exemplary embodiment, the downstream response includes the UnhID of the node to which the response will be sent, and the downstream request has a zero value for UnitID, which is a code reserved for the main bridge 202. Therefore, individual I / O streams may not be identified in downstream request traffic, and it is assumed that all downstream traffic (requests and replies) are on the same 1/0 stream. All devices in the structure are programmed to treat their main bridge directions as upstream ". By connecting I / O nodes with the main bridge in the connection chain, and allowing the I / O nodes to communicate with the main bridge only (at the level of execution), a logical view of the I / O subsystem 200 is provided, in which the I / O nodes present Connect directly to the main bridge and not to other nodes. The I / O secondary system 200 can be connected to the main bridge at both ends of the connection chain to provide solidity in the event of a connection failure, or to allow sharing of the 1/0 secondary system between processing node groups. The bridge at the first end of the connecting chain can be designated as the primary bridge and the bridge at the other end can be designated as the secondary bridge. In an exemplary embodiment, all I / O nodes in the secondary system belong to the primary bridge. After the failure of the debt test contact, the H / O nodes on each side of the failure will rewrite the program so that 11 -------- Order · -------- (Please read the precautions on the back before filling in this page)

91890 2

V. Description of the invention (50) It is the main bridge on the side of individual failures. Therefore, two 1 / 0th order systems are formed and communication with the processing nodes in the processing order system can be maintained. In another embodiment, I / O nodes can be allocated between two main bridges of the 1 / 0th system, even if no connection fails. Such structures can help balance communications traffic. If the packet reaches the end of the connection chain (for example, I / O node 204C in the example in Figure 19) and I / O nodes 204A to 204C have not yet received the packet, an error will be generated by the I / O node at the end of the link. Generally speaking, the I / O secondary system 200 will connect 24K to 24P to perform an uncoordinated connection. In an exemplary embodiment, the data packet definition of the uncoordinated connection is similar to the data packet definition of the coordinated connection shown and described in FIG. 6. Similarly, the inf0 packet definition for uncoordinated connections is similar to the coordinated inf0 packet definition shown in Figures 3 and 18 (the pr0be field will be retained). The definitions of request and reply packets for uncoordinated connections are illustrated in Figures 21 and 22 and will be described below. In an exemplary embodiment, the above-mentioned definition of the virtual channel for coordinated connections is also applicable to uncoordinated connections. The definition of virtual channels and their individual applications are presented in Figure 9. Note that probe requests may not be used for uncoordinated connections, and therefore, probe virtual channels for uncoordinated connections can be canceled. Referring to FIG. 20, a table 210 is displayed, which illustrates a packet used according to an exemplary embodiment of the uncoordinated connection in the computer system 10. Other specific embodiments are possible and considered, including any other appropriate packet groups and command field codes. Form 210 contains a command code (CMD) block that describes the command code 'virtual channel (Vchan) block assigned to the parent command, defines the virtual channel assigned to each uncoordinated packet, and the Command column contains a mnemonic (please (Please read the notes on the back before filling in this page) Packing -------- Order ----- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 specifications (210 x 297 mm) 50 91890 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 521189 A7 ~~ ----- 21 ---- 丨 -_ 5. Description of the invention (51) The symbol indicates the order, and the packet type (packet Type) block, indicating which packets 30, 212, and 214 (and data packet 36, specifically specified) are used for the corresponding command. As illustrated in Table 210, the uncoordinated packet contains NOp,

Wr (Sized), Read (SiZed), RdResponse, TgtDone, Broadcast, and Sync packets. Among them, in an exemplary embodiment, they are similar to the corresponding coordination packets described in FIG. It should be noted, however, that no probes are issued on uncoordinated connections: probe packets or probe reply packets. As mentioned above for the coordination connection, the post-write request can be identified by setting a post bit of the Wr (Sized) request packet. However, in a non-coordinated structure, a set of last bits not only serves as a virtual channel identifier, but also indicates that the write request will not receive a response at the structure. That is, unlike the coordination structure, the TgtDone response packet will not be written into the request after the non-coordination structure is released in response. Uncoordinated packets also include Flush and Fence request packets, which are described in more detail below. Referring next to Fig. 21, a block diagram of a specific embodiment of a request packet 212 that can be used for uncoordinated contact is shown. The request packet 212 contains a command field (CMD [5: 〇]) similar to the coordination request packet. Furthermore, the alternative source tag field (SrcTag [4: 〇]) can be included in bit ㈣2, which is similar to the coordination request packet. Address (Addr [15: 8], Add ^ 23 Μ,

Addr [31:24], Addl * [39:32]) are included in bit ㈣ 4 i 7 (and for agricultural low political address bit is selectively at bit time 3). The requested packet 2U further includes the unit ID (UnitlD [4 〇]) at bit time 1 (instead of the source node ID that coordinates the corresponding packet ____ 'Early EDs identification This paper standard applies the Zhongguan Standard (CNS) A4 specification ⑵Q χ (297 public meals) ------------ 91890 (Please read the notes on the back before filling this page) Order — 0 51 消 521189 V. Description of the invention (52) The logical source of the packet. I / O nodes can have multiple unit IDs, for example, if a node contains multiple logically separate devices or functions. Therefore, the ι / 〇 node ζ generates and accepts packets with different unit EDs. In a specific embodiment, the unit mark may include five bits. Therefore, if the unit ㈣ is assigned to the main bridge and 31 of the units are used to report errors, a maximum of thirty units can be present at the ι / 〇 node connected to a link chain 1 / 0th system. In addition, # 求 包包 212 contains the sequence ID (SeqED [3: 〇]) field at bit time 〇 and bSeqID field can be used to classify and order a group of two or more traveling in the same virtual channel with the same unit Cost of requesting packets. For example, 'if the SeqID field is zero' relative to other packets, one packet will be out of order. However, if the SeqID field has a non-zero value compared to other packets, the packets will be ordered in the same channel with the matching value in the ^ field and the same UnitID. Further, the 'request packet 212 contains a pass-through write (PassPw) bit π at bit time bPassPW bit indicates whether the request packet 212 allows the post-write request to be transmitted by the same unit ID. H Demonstration & Clear 'The packet will not be allowed to write beyond the request packet after the previous transmission. If the bit is set, the packet will allow the packet to be written beyond the previous one. For the read request packet, the command field may include a state indicating whether the read response exceeds the write request status ~ 7L The state of the cancer passpw bit is the reply packet corresponding to the read request packet. As described in 2, the non-coordination request packet contains ^ 11 and Fence requests. , _Μ W φ Used by the source node to ensure that one or more previous papers are suitable-91890

Μ -------- ^ ---------. (Please read the notes on the back before filling out this page) 52 189 2 5

V. Description of the invention (53) After printing the cloth by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, it has been written in the main account, such as ^ • The request in the stream, one with one expected function, the Flush request went bad. All 虚拟 and rabbits in the post-command virtual channel and the post-command virtual channel are sought before Gan Yiyue (for example, by the PassPW bit described below). Therefore, issuing a Fiush request disk to receive a corresponding TgtDone response packet is allowed to "" to determine whether the previous request has flooded into the end point of the coordination structure.

Fence requested to provide a barrier between writes after applying all UnitIDs in the 1/0 system. Fenee _ Qiu can only be released in the upstream direction and travel in the post-command virtual channel. In order to perform its intended function, Fence requests to push all requests of the command channel before and after it. For example, if the passpw bit is cleared, the Fence packet will not exceed any packet in the back channel, regardless of the UnitID of the packet. Other packets with PassPW bit clearing will not exceed Fence packets regardless of their UnitID. Referring next to Fig. 22, a block diagram of a specific embodiment of a reply packet 214 that can be used for non-coordinated contact is shown. The reply packet 214 includes a (CMD [5: 0]) command field, a unit ID (UnitID [4: 0]) field, a source tag (SrcTag [4.0]) field, and a passpw bit similar to the request packet 212. However, it should be understood that other fields and bits can be included on request. Next, referring to FIG. 23, a block diagram showing a specific embodiment of the 1/0 node 204A is shown. The other I / O nodes 204B to 204C can be configured in a similar manner. Other specific embodiments are possible and considered. In the specific embodiment of FIG. 23, I / O node 204 A includes interface logic 18M and 18N, the first group of packet buffer storage 220, the second group of packet buffer storage 222, and -1 1111 ------ --Order —----- (Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 53 91890 Employees ’Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed 521189 A7 B7 V. Description of the invention (54) Node logic 224. The interface logic 18M is connected to the lines 24K and 24L, the packet buffer memory 220, and the node logic 224. The interface logic 18N is connected to the lines 24M and 24N, the packet buffer memory 222, and the node logic 224. The node logic 224 is further connected to the packet buffer memories 220 and 222. The interface logic 18M and 18N are configured to receive packets by the lines 24L and 24M (individually) and transmit the packets on the lines 24K and 24N (individually). The interface logic for coordinating connections is similar. Interface logic 18M and 18N can separate the received packets to the control channel and the data channel. The control path is connected to the command packet buffer memory and the data path is connected to the data packet buffer memory. Alternatively, the interface logic 18M and 18N may not separate the received packets to the control and data channels, or instead, the node logic 224 may receive the CTL signal corresponding to each bit time and perform separation according to this. Similar to the coordination interface, the packet buffer memories 220 and 222 each contain a buffer memory for each virtual channel in the uncoordinated connection. That is, for the command packet, the buffer memories 220 and 222 include a post-command buffer memory (PCB), a non-post-command buffer memory (NPCB), and a reply buffer memory (RB), corresponding to three executions in non-coordination. Connected virtual channel. In addition, for each virtual channel (eg, post-command data buffer memory (PCDB), non-post-command data buffer memory (NPCDB), and reply data buffer memory (RDB)), the packet buffer memories 220 and 222 include Data packet buffer memory. Node logic 224 can process the packets received in buffer memory 220 and 222, and can initiate packets in response to the week performed by I / O node 204A < please read the precautions on the back before filling this page) ------ Order ------ This paper size is applicable to China National Standard (CNS) A4 (210 x 297 mm) 54 91890 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 521189 A7 B7 V. DESCRIPTION OF THE INVENTION (55) Side function. Similar to the control logic 66 shown in Fig. 11, the node logic 224 can execute the command packet active registers 226A and 226B (corresponding to the packet buffer memory 220 and 222, respectively) and the data packet active register 228A and 228B (corresponding to the packet Buffer storage 220 and 222). In addition, because communication for uncoordinated connections corresponds to unit IDs rather than node IDs, the node logic 224 may include one or more unit ID registers 230A to 230N to store the unit EDs assigned to the I / O node 204A. Depending on the number of unit IDs implemented in the I / O nodes, the number of unit ED registers 230A to 230N may vary from node to node. Because packets in different virtual channels are stored in different buffer memories in I / O node 204A, packets in different virtual channels do not actually conflict with each other. Therefore, in general, deadlock-free operation can be achieved. In addition, the node logic 224 can pre-allocate resources to process reply packets and reply data (such as the above-mentioned coordinated connection), so that reply packets can be combined into a single virtual channel. The node logic 224 may further include logic corresponding to different I / O logic or peripheral functions performed by the I / O node 204A. For example, the I / O node 204A may include storage peripherals such as a disk drive, a CD-ROM, a digital video disc drive, and the like. The I / O node 204A may include communication peripherals such as IEEE 1394, Ethernet, universal serial bus (USB), peripheral component connection interface (PCI) bus, modem, and so on. Any appropriate I / O function may be included in I / O node 204A. Referring to FIG. 24, a flowchart of part of the exemplary node logic 224 operation for receiving packets is shown. Other specific embodiments are possible and considered. Although the funeral shown in Figure 24 is understandable, it is said in a specific order (please read the precautions on the back before filling this page) -------- Order --------- This The paper size applies the Chinese National Standard (CNS) A4 specification (210 x 297 mm) 55 91890 521189 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 5. The description of the invention (56), but any appropriate order can be used. In addition, the steps may be performed in parallel using the combination logic in the node logic 224. For each interface logic 18Nί to 18N, the steps illustrated in Figure 24 can be performed in parallel and independently, because the bit time can be received by each interface logic at the same time. In the specific embodiment illustrated in FIG. 24, the packet is received to the buffer memories 2220 and 222 in a series of bit times. Other specific embodiments may accumulate the bit time of the packet in the interface logic 8M to 8N and provide the completed packet to the buffer memories 220 and 222. In this case, the step of managing the packet reception in bit time will be eliminated. In Figure 24, steps 100 to η2 may be the same as or similar to the corresponding steps 100 to 112 described in Figure 14 above. However, the node logic 224 may implement some additional ordering rules, as explained in steps 114 and 116 of Fig. 24. Certain command packets can be set to "push" the requesting node after it has been transmitted by the same source node. In other words, the requested packet is pushed to the destination node before other packets reach its destination after being pushed. In a specific embodiment, for example, Flush Request packets (which are defined with PassPW bit clearing), and other packets with their passpw bit clearing, can be defined as request packets after pushing, as described above. Furthermore, request packet definitions with a non-zero value in their Seqm field To push before requesting a packet, it is streamed on the same I / O and has a matching value in its individual SeqlD field. Therefore, if a received packet has the Passpw bit cleared, or a non-zero value in the SeqlD field (decision area Block 114), the node logic ㈣ can look for the previous request I packet in the subsequent command buffer memory and the command virtual channel. For example, 'node logic 224 can look for the same unit m = 2. Please apply the Chinese standard (CNS) for this paper size A4 specifications ⑵ Gx 297 public love) -------- Order --------- (Please read the precautions on the back before filling this page), 56 91890 521189 A7

91890 A7 V. Description of the invention (58) The address in the request packet is judged and 'if the downstream request packet is _ ^ broadcast (= 2 (steps then) the node accepts and forwards the packet dropout, regardless of other requirements, additional packets can be implemented before Step; = That point logic 224 please proceed with processing. For example, in decision block 124, the node logic 224 determines whether the request 刼 —θ ^ is set to push a packet that has not yet been processed and then requests the packet. Such as I * β u sends the previously requested packet (as shown on the right ^-the packet is requested and set to the push bit)), _ = a non-zero value in the field of ^ or ^ _, the source label of the requested packet to be recorded The source tag of the packet (the disk unit corresponds to the push request ^ 〇70 70 ID) order buffer storage, looking for a ^ ^ month to find the packet. If found-a storage with source label and unit ID: looking for the packet, then The processing of the request packet will be put on hold until the previously stored request packet has been processed. In addition, the node logic 224 is configured to forward the request packet in the same direction (upstream or downstream) rather than according to the packet routing table 袼 (step ⑷). If The packet flows upstream, then the packet will never be point H, accepted, and will instead be transshipped 'until it reaches the main bridge. It should be noted that once the packet G is processed (for example, by the node " (Transmit or receive), the packet will be removed from the corresponding buffer memory location and, if applicable, the relevant data packet will be removed from the data buffer memory location. ^ It should be further noted that if the selected request packet specifically specifies the shoulder bag material Packet, different embodiments can process the request packet even if the data packet has not been received. Or, processing will be delayed until the data packet arrives, so simplifying the transfer of the data packet or allowing another packet, which specifies _ 1 paper size Applicable to Zhongguanjia ^^^) Α4 x 297) -------- 58 (Please read the precautions on the back before filling in this page) Install -------- Order ---- # Economic Ministry Printed by the Intellectual Property Bureau's Consumer Co-operative Society 91890 B7 V. Description of the Invention (59) The data packet that has arrived completely will be forwarded on the same communication connection.; At the time of full reception, the data is processed in the same way as the image. When receiving, the gastrointestinal packet can be ordered as described above with reference to FIG. 26, and a flowchart showing the node logic for processing the packet is shown. The operation of the specific embodiment. The other two specific examples are possible and considered. Although the steps shown in FIG. 26 are easy to understand, they are described in a specific order, but any appropriate order can be used. In addition, the steps can use node logic 224 The combination of logic is executed in parallel. For each interface logic 18M ^ 18N and / or each reply packet buffer storage, the steps illustrated in Figure 26 can be performed in parallel and independently, because different interfaces and / or different virtual channels The packet is virtually independent. Right packet state_downstream (step 249), the node logic 224 determines whether to receive the packet by checking the unit IDs in the reply packet UnitID field and the unit ① register 2 to 230N (step 144, The corresponding step 144 of the M map is similar). As mentioned above, in the reply packet downstream, UmtID is the initial request packet that caused the reply release. However, if the packet flows downstream, the packet will not be accepted and will be forwarded until it reaches the main bridge. The reply packet in the upstream is the target node of the request (that is, the node that issues the reply). Similar to the flowchart in Figure 25, node logic 224 can perform additional checks before processing the reply packet. For example, in the decision block i4G, the node logic 224 determines whether the reply packet is set to push a previous i-LiL that has not yet been processed—the right receives the reply packet and is set to push the previously requested paper size_ 中 关 * 标准 （CNS) A4 Specification ⑵Q x 59 91890 A7 _ B7 V. Description of the invention (60) = (eg: Passpw bit) 'Then when the reply packet is received,' the source label of the request packet will be pushed. Node logic 224 may request a packet corresponding to the source tag (and unit 1D) of the reply packet. Please: device. If the storage with the source tag and unit 1d is found ::::, the processing of the reply packet will be suspended until the end node of the previous request packet to reverse the packet is another-node ', then the node logic 224 = reply virtual channel in the receiver A reply packet with a buffer storage location and availability (with potential, the packet will be forwarded (step Γ50) Γ in one two = applicable) to reply two is-: Allow reply packets to be the same Direction node flow), when the packet has flowed. Person ::: The end node of the packet is " The node 'then saves the corresponding data packet, if any, it will be broken up from the response reply to the reply buffer mi assigned to the reply packet. Controller (step 252). The node logic 224 then completes the processing of the response packet, "" buffering the memory (step 254). It should be noted that--(that is, transferred or received by "the node"), 〇, the location of the flushed memory is moved In addition, if applicable, remove the buffer storage position with the application material. 'Φ μ It should be noted that if the selected reply packet specifically specifies a subject packet, different specific embodiments can process the reply packet ==. If you do, the processing will delay the direct packet = this transfer or another packet is allowed, which has a fixed-a full f scale applies the Chinese National Standard (cns) A4 specification ⑵ ◦ 297 public issue) ου 91890 ----- ------ · & -------- tr --------- (Please read the notes on the back before filling this page) ------- 521189 A7

A7 A7 Printed by the Intellectual Property Office of the Ministry of Economic Affairs 91910 V. Description of the invention (62) The bridge can be judged that the previous packet has moved forward. The packet to be released will not interfere with the sequence. Coordination structure so that the main bridge can subsequently be determined to be required by non-coordination knots. &# m 偁 来 之 Packet Which Order

Secret P checks the command code in each packet.

SeqED, PassPW and other special operations, which can be achieved with major bridges; which == requires major bridges What order is released to the coordination structure. The different waiting requirements are listed in Table 270. Form 27G contains Requestj, which lists the first order—request, Request2, and second order: the outbound repairs to the main bridge to allow the second request to continue. ^ As indicated elsewhere in Form 27G, the packet of ㈣ is coordinated. In addition, in an exemplary embodiment, it is not listed in Form 27. Γ ^ Waiting for request. Going one step further, the table only applies: the main bridge 202 first determines whether the order exists between the two requested packets. For example, a sequence requirement may exist if the two request packets have non-zero numerical sequence IDs, or if the first request packet is written after one and the second request has the PassPW bit cleared. In the first item of the table 270, a pair of sequential memory write requests are transmitted by the main bridge by delaying the transmission of the second memory write request until a T-packet corresponding to the first memory write request is received at The coordination structure is completed by the main bridge. In addition, the main bridge blocks a SrcDone packet corresponding to the second memory write request until a TgtD () ne packet corresponding to the first memory write request is received. This paper is based on the Chinese National Standard (CNS) A4 Specifications (210 X 297 Public Love-11 —I— -------- ^ --------- ^ 9 (Please read the notes on the back before filling this page) A7 B7

V. Description of the invention (ό3) After the 'uncoordinated connection' (if the memory does ^ 1, the hidden write is a non-post request), corresponding to the second memory write, please wait for a night. GtD〇Ile packet will be delayed Until the corresponding to the first 5 mnemonic write request gray> Trv + T ΔD Done packet is terminated by coordination. Figure 28. The other forms of the mouth form can be explained in a similar way to the first item given above. 2. A main bridge 202 is provided to implement the waiting requirements listed in the table in FIG. 28 and a post-order virtual channel is set in the coordination structure to ensure that it can meet the sequence requirements of the post-writer request in the coordination structure. The sequence requirements of the post-write request in the non-coordination structure can be met by using the Passpw bit. As described above, as described above for the 9th ®, the following four requirements apply to the PCI bus in the sub-system after the write: (i) The writing from the same source still maintains the order at the target interface; (11) The writing from the same source is followed by the writing to read the data and returns to the target interface. (ill) non-post-write will not overtake subsequent writes from the same source; and (iv) post-write needs to allow past non-post operations. For write requests after pointing to the same coordination target node, the request can be achieved by placing a write request packet after ordering the virtual channel, and applying the wait request of table 270 item 272 to the write request after pointing to a different coordination target node. . Requirement (ii) can be fulfilled by imposing a waiting request under Table 270, item 274. Requirement (iii) may also be fulfilled by imposing a wait request for item 272. Finally, the request (iv) can be achieved by commanding the virtual channel after use. For each request (i) to (iv), it is assumed that the PassPW bit in the second packet is cleared. No, if ^ set ^ sets the passPW bit, the second packet ------------------ (Please read the precautions on the back before filling this page) Order- -------- The paper printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs applies the Chinese national standard (CNS) A4 specification (210 X 297 meals) 63 91890 V. Description of invention (64) Article-packet. The other items in Form 27 () can be used to provide a sequence of other types of requirements in the coordination structure from non-coordinated connections. Once the above disclosure is fully understood, many changes and modifications will be apparent to those skilled in the art. The following patents are intended to be interpreted as including all such changes and modifications. Although the invention is susceptible to various modifications and alternative forms, specific specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. Or "said" the invention encompasses all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the scope of the appended claims. [Description of component symbols] 10 Computer system 12A, 12B, 12C, 12D 14A, 14B, 14C, 14D 16A, 16B, 16C, 16D 18A to 18L Interface logic 22 Bus 24A to 24L Line 30, 32 38 > 42 12 Processing Secondary system node memory memory controller bridge packet foundation bidirectional connection 214 packet 34-36 > 212 21〇 table 40A, 40B virtual channel fast buffer storage area processor core 58 packet processing logic 64 data packet buffer storage

60A > 62A '64A rear command buffer memory 521189 A7 B7

V. Description of the invention (65) 60B, 62B, 64B 62C 62D 62E 62F 62G

60C 60D 60E 60F 60G 66 70 > 90 74A to 74C

64C 64D 64E 64F 64G Control logic reply register 226A, 226B 228A, 228B Non-post-command buffer memory Reply buffer memory Probe the buffer memory after command data buffer memory Non-post-command data buffer memory Reply data buffer memory 68 Data buffer memory slot 72 Node ID register slot Command packet active register Data packet active register 76A to 76D, 80 Data buffer memory slot positions 82, 84, 86, 88, 92, 94, 95, 96 , 98 Source tag field 180 packets 200 I / O sub-systems 202 Major bridges 204A, 204B, 204C I / O nodes 220, 222 Packet buffer storage 224 Node logic 230A to 230N ID registers -------- --- 4 (Please read the notes on the back before filling out this page) · n ϋ ϋ ϋ I nan ϋ #_ Printed on the paper by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 210 X 297 mm) 65 91890

Claims (1)

A method for routing packets between a plurality of nodes in a computer system, the method includes: a member of the Intellectual Property Bureau of the Ministry of Economic Affairs, X Consumer Cooperatives, prints clothes and receives a first packet among a plurality of nodes, and the first point includes a plurality of nodes A packet buffer storage, wherein each packet buffer stores, 'knifes to a specific virtual channel among a plurality of virtual channels' and the first packet is received on the first virtual channel; and the first packet is stored in the first packet Buffer memory, the first 2-packet buffer memory is dedicated to the packets received by the first virtual channel. For example, the method of claim 1 in the patent scope, wherein the first packet is a post-request packet, the first packet buffer storage is a post-command packet buffer storage device, and the first virtual channel is a post-command virtual channel. If the method of applying for the second item of the patent scope further comprises: receiving a second packet at the first node; determining a second virtual channel receiving the second packet; and storing the second packet in the second virtual channel according to the determination of the second virtual channel. The second packet buffer memory, wherein if the second virtual channel is not a post-command virtual channel, the second packet buffer memory is different from the post-command packet buffer memory. 4. The method according to item 3 of the patent application scope, further comprising: determining an end point of the second packet; and if the end point is a second node different from the first node, the second node includes a second plurality of packet buffer memories, Each of the second plurality of packet buffer storages will be allocated to a specific virtual channel of the plurality of virtual communication channels, then ------------ install -------- Order --------- 2 Please read the precautions on the back before filling in this page> This paper size applies to China National Standard (CNS) A4 (21〇X 297 mm) 66 91890 ^ 1189 2. The scope of patent application 6 determines the profitability of one of the buffer registers allocated to the second virtual channel; and the packet points. According to the availability of the judgment, 'Method of transmitting the second packet to the second section of the second patent ^ Patent Encirclement 2', where the request is then made for the person to write the packet. The method in the scope of the patent No. 5 further packs. Receive the data packet at the first node: and store the data packet in the first plurality of packet buffers ^-'The packet buffer storage is assigned to the virtual communication after ordering 7 · Method of item 6 in the scope of patent application 'Where the first—the plurality of packet buffer storages includes a command packet buffer storage and a data packet storage', where the post command packet buffer storage is one of the command packet storages ... and wherein the data packet is contained in the data packet ^ One of buffer memory. 8. The method according to the scope of application for patent item $ i, wherein the plurality of virtual channels include a post-command virtual channel, a non-post-command virtual channel, and a reply virtual channel. 9. The method according to the scope of application for patent item No. 8, wherein the plurality of virtual channels include a probe virtual channel. 10. The method of item 3 of the scope of patent application, further comprising: determining whether the second packet is set as a push-request packet, and if so, the paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ) ♦ -------- tr ---------% ί Please read the precautions on the back of the book before filling out this page) Intellectual Property Bureau, Ministry of Economic Affairs, Consumer Cooperatives, Printed Clothing 91890 Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperative 521189 ΐ ΐ C8 --------- D8 _____ VI. The scope of the patent application is placed in the buffer memory of the rear order after storing from the same source that produced the second packet Requesting a packet, and requesting a packet to a second node after transmitting the placed storage before processing the second packet. 11. A computer system comprising: a first node configured to transmit a packet on a plurality of virtual channels; and a first node coupled to receive a packet from the first node on a plurality of virtual channels, wherein the first node The two nodes include a plurality of packet buffer storages, each of which is allocated to a specific virtual channel, and wherein the second node is configured to store each received packet on a specific virtual channel allocated to receive individual packets One of the packet buffer storages. 12. The computer system of item u in the scope of patent application, wherein the first node is configured to request a packet on the post-command virtual channel after transmission, and the second node is configured to store the first packet in the post-command packet buffer storage 13 If the computer system of claim 12 is applied, the first node is configured to transmit a second packet to the second node on a second virtual channel different from the post-command virtual channel, and the second node is configured to store The second packet is in a packet buffer memory different from the post-command packet buffer memory. 14. · The computer system according to item 13 of the scope of patent application, further comprising a third node connected to receive packets from the second node in a plurality of virtual «1 -------- tr ------ (Please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 68 91890 Intellectual Property Bureau of the Ministry of Economic Affairs X Consumer Cooperation, Printing 69 On the channel, each of the third node packet includes the second plurality of packets and a plurality of packet buffer memories, and the channel, and wherein the second? The second plural number of the buffer memory allocated to the specific virtual rough channel: two is configured to be based on the applicability assigned to the second virtual key, and the value of one of the buffer memory buffers can be sent to the second Closing station 1 15. If the third node is the 12th in the scope of patent application. The package contains the data packet which is written into the Xia computer system, and then the packet is requested. 16. The data packet corresponding to the number ^ of the patent application scope. Each packet buffer storage unit is a data buffer storage unit allocated to the post-command virtual channel, and the second node is configured to store the data packet in the post-command data according to the reception by the node. Buffer storage. Hengru declared the computer system and system of item 13 of the patent scope, wherein the second packet is configured to request a packet after pushing, and wherein the second node is configured to find a request for a packet after storage generated by the same source that generated the second packet After that, the packet buffer storage is commanded, and before processing the second node, the packet is requested to the third node after transmission and storage. 18. The computer system according to item u of the application, wherein the plurality of virtual channels include a post-command virtual channel and a non-post-command virtual channel. 19. The computer system of claim 18, wherein the plurality of virtual channels further include a reply virtual channel. 20. The computer system of claim 19, wherein the plurality of virtual channels further include a probe virtual channel. 21 · A method for routing packets between multiple nodes in a computer system 91890 ------------ ^ i 丨 丨 丨 丨 丨 丨 Orders! __1 丨-(Please read the notes on the back before filling this page) 521189 VI. The scope of patent application method includes: producing, and requesting the _th node in a plurality of nodes; and transporting a plurality of packets including a post request packet, the first through a plurality of virtual channels, the plurality of packets Each of them will be transmitted via a specific virtual channel, where the post-request packet is transmitted to the second node for the post-request packet dedicated to the post-command virtual channel, and where the post-request packet and other packets transmitted on other virtual channels They are transmitted independently. 22. For the method of claim 21, wherein the second node includes a plurality of packet buffer storages, the packet buffer storage includes a post-command packet buffer storage, and each packet buffer storage is allocated to a plurality of virtual buffer storages. Passing the specific virtual channel of itt, and its toweling the second packet to the second node is based on the availability of the packet buffer memory according to the post-command. 23. The method of claim 22, comprising: storing the post-request packet in the post-command packet buffer storage at the second node according to the post-request packet being received. 24. If the method of claim 21 is applied, the first node includes a plurality of packet buffer storages allocated between a plurality of virtual channels, and the method includes: generating a second packet at the first node, the The second packet is set to generate a reply packet by the target node. · Allocate one of the packet buffer storages to receive the reply packet. The allocated packet buffer storage is allocated to the plurality of virtual channels. 21G χ 297 male ^ ------------ # 装 -------- Order --------- (Please read the precautions on the back before filling this page) Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 91890 521189 A8B8C8D8 6. One of the patent application scopes responds to the virtual channel; and sends the second packet to the target node. (Please read the precautions on the back before filling this page) 25 The method of claim 21, wherein the first node includes a plurality of command buffer storages and a plurality of data buffer storages allocated between the plurality of virtual channels, and the method includes: in the first section Receiving a packet via a first virtual channel different from the post-command virtual channel; determining whether the received packet specifically specifies a corresponding data packet; and if so, allocating one of the data buffer storages allocated to the first virtual channel to store The corresponding data packet; and the corresponding data packet is stored in the allocated data buffer storage according to the reception by the first node. 26. If the method of the scope of patent application No. 25 includes: determining the end point of the received packet, the end point The node includes a plurality of command buffer storages and a plurality of data buffer storages allocated between the plurality of virtual channels; one of the command buffer storages allocated to the first virtual channel by the consumer consumption cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the printed judgment The availability of one of the data buffer storages; and according to the determined availability, the received packet and the corresponding data packet are transmitted to the destination node on the first virtual channel. 27. A computer system including: a first node , Configured to transmit complexes via multiple virtual channels Packets of the first node is configured to apply commands to the present paper China National Standard Scale (CNS) A4 size (210 X 297 mm) via a plurality of virtual channels after 71 91890 A8 B8 C8 D8 2. The scope of the patent application makes the virtual channel generate and request a packet after transmission. The first node is configured to print clothing 521189 of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the other packets are transmitted independently through other virtual channels. Packet; and a second node connects to request a packet after receiving. 28_ The computer system of claim 27, wherein the second node includes a plurality of packet buffer storages allocated between the plurality of virtual channels, and wherein the first node is configured to be assigned to the post-command virtual channel according to the allocation Among the plurality of packet buffer memories in the second node, 2 can obtain a packet buffer memory, and transmit the subsequent request packet to the second node. 29. If applying for the computer system of item 28, wherein the second node is configured to store the request packet after receiving the packet in an available buffer buffer. 30. If the computer system according to item 27 of the patent application scope, wherein the first node includes a plurality of packet buffer storages allocated between a plurality of virtual channels, and wherein the first node is configured to generate a second packet, the The second packet is set to generate a reply packet by the target node, and the first node is configured to allocate one of the packet buffer storages to receive the reply packet before transmitting the second packet to the target node, and the allocated packet will be allocated to a plurality of packets. One of the virtual channels responds to the virtual channel. 31. The computer system according to item 27 of the scope of patent application, wherein the first node includes a plurality of buffer storages and a plurality of data-level buffer storages allocated between a plurality of virtual channels, and the first node is set as ： It is judged that the paper size on the virtual channel which is different from the post-command virtual channel applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 91890 ------------ install- ------ Order ------- {Please read the notes on the back before filling out this page} 521189 A8 B8 C8 D8 VI. Whether the packets received in the scope of patent application specifically specify the corresponding data packets; To one of the data buffer storages of the first virtual channel to store a corresponding data packet; and according to the reception, storing the corresponding data packet in the allocated data buffer storage. 32. The computer system of claim 21, wherein the first node is configured to: determine an end node of the received packet, the end node including a plurality of command buffer memories and a plurality of numbers allocated between the plurality of virtual channels; Data buffer storage; determining the availability of one of the command buffer storage and one of the data buffer storage at the destination node, the command buffer storage and the data buffer storage are allocated to the first virtual channel; And according to the determined availability, the received packet and the corresponding data packet are transmitted to the destination node on the first virtual channel. ----------- f -------- Order! !! _ ·· (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 73 91890