TW502171B - Data transmitting system - Google Patents

Abstract

I/O bus 20 which is a bus structure that combines channel type/bus type consists of I/O common bus that is connected to I/O device 21-23 and of channel interface signal line that is independently installed by each of I/O device. Each of the channel interface signal line comprises clock pulse SCLK. The data transmitting between each of I/O device and bus arbitrator 15 and the clock pulse SCLK is carried out simultaneously. In the I/O common bus, commands, addresses, and data transmit CAD bus with 8 bit width based on a time distribution and comprises, in the CAD bus, signal line used as distinguishing command from data. Because there is installed with a distinguishing signal for the command/data, I/O device can independently require data transmitting so as to achieve flexible access control.

Description

502171 V. Description of the invention (1) [Technical category to which the invention belongs] The present invention relates to a data transmission system using an improved bus structure. [Known Technology] There are generally known two types of bus structures for I / O devices used in electronic devices such as portable information terminals, such as (υ bus type and (2i channel type). The bus type is a plural I / O device, and the structure is connected by a common bus. In addition to the address bus and the data bus, the clock signal line is also shared among the plural I / O devices. Therefore, the number of signal wiring can be reduced, but because the signals are shared between the devices, in order to improve the instability of the generated signal waveform, wiring countermeasures must be taken, which is disadvantageous to the increase of frequency and power consumption. In terms of the channel type, each I / O device is independently configured in the address bus, data bus, clock signal line, etc. Each I / O device can perform flexible access control and is compared with the bus type Below, the noise countermeasures are relatively simple, and it is easy to improve the performance. However, on the contrary, there is a problem of increasing the number of signal wirings. For portable information terminals, etc. In small electronic devices, because the actual assembly area of the components is limited, the number of signal wirings must be minimized. However, when using the above-mentioned bus-type wiring structure, all the equipment must be frequently used. The reason for supplying the clock pulse is that the power consumption may increase. Therefore, even when a channel-type wiring structure is used, 'in order to reduce the number of signal line wiring, 502171 V. Description of the invention (2) Therefore, a new bus is required. Structure. In order to reduce the number of signal wirings of the bus, it is a well-known fact that the address and data are on the same bus, and the time is allocated. However, it is known that the output order of the address and data and the output timing It is determined in advance, so it must always be accessed at this timing. Therefore, when a sequence deviation occurs due to noise, a problem that can cause erroneous actions can occur. In addition, the address phase and data phase requirements must be continuous, so Access separates the bit phase and data phase of an I / O device. It is difficult to control access to other I / O devices, or to accept access requests from other I / O devices. [Invention Summary] The present invention seeks to solve the problem in view of this situation. A data transfer system suitable for a small electronic device such as a portable data terminal that requires a small size and low power consumption is realized by realizing a new bus structure, and the data transfer system of the present invention is a data transfer system of the present invention. The data transmission system for transmitting data between I / O devices is characterized in that each of the aforementioned I / O devices is provided with a demand device that requires ownership of the bus; the aforementioned bus arbiter is provided to allow the aforementioned bus ownership Grounding device; wherein the aforementioned bus arbiter and the aforementioned I / O device have: a device in which instructions, addresses and data are output in the same bus; when using the aforementioned bus to transmit data, a clock pulse is transmitted to the other party Device; a trusted device after receiving a clock pulse from the other party and then receiving data from the other party; the aforementioned instructions, addresses, and data are in » 4- 502171 V. Description of the invention (3) Same—When the bus is output, it will be different from the output of the bus that is outputting instructions or signal signals. For this data transmission device, output instructions and bits on the same bus are used. The structure of the address and the data is transmitted by the data transfer between the bus arbiter and the plural I / O devices. The instructions on the bus used by pzf and the address and data are transmitted by time allocation. In this case, in the case of the bus, The output is a command or 'material is specified by a special signal output by the transmission place. Therefore, even if each command and data can not be transmitted at the timing determined by the conventional, data transmission can be performed normally, Therefore, the sequence deviation of noise can improve the tolerance. Moreover, the address phase and data phase do not need to be performed continuously, so the division is used to access a certain I / O. Data phase between the set address phase and data phase and other I / O devices can also be performed. Also, the signal to be distinguished as a command or data is output by the I / O device. 5 The I / O The content output from the device to the bus can be clearly marked as a notice to the bus arbiter as a command or a data I / O device can issue instructions on its own to transmit data. In particular, in this data transmission system, the receiving end and the slave transmitting end The transmitted clock pulses are synchronized to receive the channel-type structure of the data. Because it is used in a combination of the bus-type architecture in which commands, addresses, and data are output on the same bus, data is transmitted from the I / O device It is because of the mechanism that needs to be judged because 5 is formed by reading data from the I / O device, or it is formed by the instruction of the I / O device itself. 71 dedicated letter V. invention is described in No. (4), the I / O end notification address arbitration device architecture, the access control can be achieved more elastic properties. [Brief description of the drawings] Fig. 1 is a block diagram showing a system architecture of an information processing device using a data transmission system according to an embodiment of the present invention. Fig. 2 shows the ~ terminal specifications of the same implementation type in the bus arbiter and 1/0 device. Fig. 3 illustrates a pattern of a 3-clock pulse command and a 4-clock pulse command used in the same embodiment. Section 4_ shows the structure of the instructions used in the same implementation type. Figure 5 shows the types of data transfer that can be specified because of the instructions used in the same implementation. Fig. 6 shows a specific circuit architecture diagram of a transmission circuit portion used in the same embodiment. Fig. 7 shows a timing flow chart when the CPU writes data to the I / O device for the same embodiment. Fig. 8 is a flowchart showing the timing of the retry sequence in the same embodiment. Fig. 9 shows the timing flow chart of the display operation when the CPU reads data from the I / O device in the same embodiment. Fig. 10 shows a timing flow chart during the data transmission operation according to the read request from the I / O device in the same implementation mode. Fig. 11 shows a timing flow chart of the data transmission operation according to the write request from the I / O device in the same implementation mode. V. Description of the invention (5) Brother 1 2 时序 The sequence diagram showing the stopping of operations during data transmission in a consistent application mode. Fig. 13 shows a timing chart of the switching operation of the I / O device in the same embodiment. Fig. 14 is a timing chart showing other examples of the switching operation of the 1 / () device in the same embodiment. [Embodiment example] In Fig. 1, a system architecture of an information processing device using a data transmission system according to an embodiment of the present invention is shown. This information processing is used as a portable information terminal, etc. As shown in the figure, it includes a CPU 11, a RAM 12, a ROM 13, a gate array 14, and a plurality of I / O devices 21 to 23. The I / O devices 21 to 23 are various peripheral devices such as a magnetic disk drive (FDD), a hard disk drive (HDD), an audio device, a digital camera, and a communication controller. Gate Array 14 is a two-way connection between the memory bus 10 on the host side and the I / O bus 20 on the I / O devices 21 ~ 23. The I / O bus 20 is connected according to the access request from the CPU 11 for I / O. The access control of the O devices 21 to 23 or the memory access control is performed in response to the memory access requirements from the I / O devices 21 to 23. The gate array 14 is assembled as a peripheral device, such as a display driving circuit that drives a liquid crystal display device (not shown). In addition, the gate array 14 includes a bus arbitrator circuit 15 for controlling I / O devices 21 to 23 to control bus switching. -7-502171 V. Description of the invention (6) The host-side memory bus 1 0 'as shown in the figure' includes a 32-bit wide data bus, a 26-bit wide address bus, and control signals. The control signals include a chip selection signal CS, a read signal Read, and three write signals Write. The Write signal indicates that 1-byte write, 2-byte write, and 4-byte write. The CPU 11 accesses the RAM 12 and the ROM 13 by using the memory bus 10 to issue a memory address. For the I / O devices 2 1 to 23, the CPU 1 1 also uses the bus memory 10 to issue a memory address and access it. That is, from the perspective of the CPU 11, all the I / O devices 21 to 23 become a hardware architecture developed on a memory map, and each I / O device is used as a memory map I / O. The I / O bus 20 to which the I / O devices 21 to 23 are connected is the bus structure used for the aforementioned channel / bus type, which is a common I / O bus connected to the I / O devices 21 to 23 Rows, and each I / O device are made up of channel signal lines that are set independently. The data transfer width of the memory bus 丨 〇 is 32 bits, and the data transfer width of the corresponding I / O common bus is 8 bits. That is, the common I / O bus includes an 8-bit-wide CAD bus that transmits instructions and addresses and data by time allocation, and each; [/ 0 data transmission between devices is via CAD to implement. Therefore, when data is transferred between the CPU 11 and each I / O device, a 26-bit wide address and 32-bit wide parallel data are each divided into 8-bit units, and then serialized. (Send to i / C) Device side for sequence: "J / parallel conversion processing" or 8-bit data sheet 502171 from I / O device side 5. Description of invention (7) bit 'Address or data for sequence transfer The aggregate is 32 bits wide and forwarded to the memory bus 10 to perform the sequence / parallel transform process. In the bus arbitrator circuit 15, three channels of channels 1 to 3 are prepared. Each channel is connected to the corresponding I / O device through the channel interface signal line. The bus arbiter circuit 15 and the terminal specifications of each I / O device are as shown in Figure 2. That is, the I / O common bus is 13 and 8 CAD signal lines CAD [7: 〇], 1 It consists of two instruction / address status signal lines CA, two acknowledgement signal lines ACK [1: 0], one OFF signal line OFF, and one reset signal line RESETB. The command / address status signal line CA serves as a signal to distinguish the command or data currently output on the CAD. During the output period of the instruction or address, the status signal CA is set to the active status "H" by its output terminal (master terminal). The status signal CA is set to the inactive state during the data output period. Acknowledge signal line ACK [1: 0] is a response signal indicating the receiving status of the command, address, or data receiver, and ACK = ”01 " is a signal indicating that the command, address, or data cycle has ended normally ( Acknowledge), and ACK "10" is a cyclic retransmission request for instructions, addresses, or data. This acknowledges that the signal line ACK [l: 〇] is output in several cycles, and is based on each address. The phase and the data phase are fixed. The OFF signal line 0FFB and the reset signal line RESETB are signals output from each bus arbiter circuit 15 to the I / O device side, and indicate the disconnection and reset of the I / O device. 502171 Ί V. Explanation of the invention (δ) And for each channel interface signal line, a source synchronous clock pulse is set? Signal SCLK, insert signal INTB, bus usage right request signal BREQ, bus usage right permission signal BGNT, one each. Source The pole synchronous clock pulse signal SCLK is a synchronous clock pulse used for transferring instructions, addresses, or data. It is used for data (command, address, and data) samples on the CAD bus. Source synchronous clock pulse The signal StLK is output from the master control. The data reception of the slave device at the receiving end starts according to the source synchronous clock pulse signal SCLK from the master, and receives the instruction in synchronization with the source synchronous clock pulse signal SCLK. Address, or information. The bus use right request signal BREQ is a signal requesting 10 common bus use rights for the bus arbiter circuit 15, and is sent from the 1/0 device to the bus arbiter circuit 15. The bus Bus arbiter circuit! 5 In order to mediate the usage right request signal BREQ 'from each of the I / O devices 2 1 to 23 to correspond to the bus usage right; [/ 〇The bus sends the bus usage right permission signal BGNT. Bus The right-of-use demand signal BREQ and the bus-use-right permission signal BGNT are each a negative logic signal. Therefore, the 15 terminals of the bus arbiter circuit are 13 + (3x4) = 25 'and each I / O device terminal is 13 + 4 = 17 terminals. Between the bus arbiter circuit 15 and the I / O devices 21 ~ 23, the data exchange is often generated by the two relationships between the master control slave device and the output end of the transmission data. Indeed After the bus power is controlled, the clock pulse SCLK for transfer is controlled to perform data transfer. [/ 0 device has each bus-1 〇- 502171 V. Description of the invention (9) Demand (BREQ) circuit, only the bus arbiter circuit is obtained 15 permitted I / O devices can output data. ≪ Instructions and Addresses > Next, referring to Figures 3 or 5, the instructions and addresses transferred in 8-bit wide CAD [7: 0] will be explained. For the bus system of this embodiment type, a three-clock pulse command such as 3 (a) 圏 and a four-clock pulse command such as 3 (b) _ are prepared. 3 The clock pulse command is composed of an 8-bit instruction and its subsequent address (A) [15: 8], A [7: 0] divided into two transfers. These three clock pulse commands are usually used, and the memory address space represented by the three clock pulse commands becomes the access target. The 4 clock pulse command is a command used when the memory address space is expanded. It is an 8-bit command and its subsequent divided into 3 transfer addresses (A [23:16], Α [ 15: 8], Α [7: 0]). To use the 3-clock pulse command or to use the 4-clock pulse command, it is specified by the extension bit defined in the 8-bit instruction. Figure 4 shows the 8-bit instruction structure. The four digits of CAD [6] to CAD [3] are command sections (CM [3] ~ CM [0]) that indicate the type of data transfer. An example of the relationship between the combination of CM [3] to CM [0] and the instruction content is shown in Figure 5. When continuous data transfer of more than 2 bytes is performed, the read / write address of each byte of the instruction receiver is usually increased by +1 automatically. However, in this embodiment, it is also prepared. When the address is not increased, a continuous data transfer command of more than 2 bytes is executed. Once, CM [3] ~ CM [0] can also refer to »11- 502171 V. Description of the invention (10) instructs to suspend the transfer of data during execution. CAD [2] indicates the access type of read / write, caD [2] = " 0 "indicates read access, and CAD [2] = " 1 " indicates write access. CAD [1] alignment The presence or absence of address expansion, which indicates that the current instruction and address are 3-clock pulse commands, or the 4-bit pulse command indicates the address expansion bit. CAD [l] = " 〇 "means 3-clock pulse command, CAD [1] = ”r is f clock pulse command. CAD [0] is used to refer to the content of the first bit of the address that is not wrapped around the instruction. 'As A [1 6] when 3 clock pulse command, or The 4-clock pulse command is used as A [24]. Therefore, in fact, 8-bit instruction formation also includes address information. ≪ Circuit Architecture > Second, referring to Figure 6, for the bus system The specific circuit architecture of the used data transfer circuit section will be explained. Since the bus interface of the 1/0 device 21 to 23 is the same, the I / O device 21 is used as a representative in FIG. 6. In the interface signal line, the insertion signal is omitted. In addition to the bus mediation in the bus arbiter circuit 15 In addition, it includes the function of data transfer between control and I / O devices. That is, the bus arbiter circuit 15 is provided with a FIFO buffer 151, an instruction / address / data synthesis circuit (as shown in the figure) CAD synthesis circuit) 152, transfer control circuit 153, and DMA circuit 154. The FIFO buffer 1 51 is an interface buffer with the memory bus 1 0. In order to realize the aforementioned parallel / sequence conversion, serial / parallel conversion -12- 502171 V. Description of the invention (11) Change 'execute control signal, address, data receipt and accumulation from memory bus 10, and execute instruction, address, data receipt from CAD bus For example, when the CPU 11 performs write access to the I / O device, the address, data, and write signal are held in the FIFO buffer 1 5 1. The CAD synthesis circuit 152 is held in the FIFO buffer. The storage data stored in the device 151 is boarded on a CAD bus to be converted into the contents of 8-bit sequence data, and the CAD synthesis circuit 152 and the FIFO buffer 151 are used to form the aforementioned parallel / sequence conversion interface. CPU 1 1 32-bit implementation of I / O devices When writing and accessing data, the CAD synthesizing circuit 152 generates the aforementioned 3-clock pulse or 4-clock pulse command (CA) according to the write signal and address, and divides the 32-bit wide data into 8 bits each. Bits are converted into 3-byte sequence data from D0 to D3. Transmission control circuit 1 53 performs actual data transmission control with each I / O device. For this transmission control circuit 1 53, as shown in the figure A bus ground (BGNT) circuit 201, a clock pulse generating circuit 202, a CAD transfer circuit 203, an instruction interpretation circuit 204, and an error detector 205 are provided. The bus ground (BGNT) circuit 201 has a busbar use right demand signal BREQ1 to 3 and a bus connection between each I / O device 2 1 to 23 and the bus ground (BGNT) circuit 201 in a one-to-one connection. The usage rights are used as the permission signals BGNT 1 ~ 3, and these usage right demand signals BREQ1 ~ 3 and the bus usage right permission signals BGNT 1 ~ 3 are used to perform the mediation of the usage rights of the I / O common bus. For the I / O common bus -13-502171 V. Description of the invention () The mediation of the right to use the common bus. For the bus liberation timing of the 1 / () common bus, 'the cycle in which the command / address phase and data phase are liberated has been fixed.' If there are other bus usage rights request signals BREQ, then the bus is executed at this timing Right switch. The clock pulse generating circuit 202 is used for generating the aforementioned source synchronous clock pulse signal SCLK during data output. This source synchronous clock pulse signal SCLK can also be used as the operation clock pulse of the CAD transfer circuit 203. The frequency of the source synchronous clock pulse signal SCLK can be set to be variable according to the transfer processing speed of the counterpart I / O device. In addition, the clock pulse generating circuit 202 has a switching circuit therein, and when receiving a signal, the source synchronization clock pulse signal SCLK received from the I / O device is given to the CAD transmission circuit 202 or the error detector 205 as data. Load clock pulse. The CAD transmission circuit 203 is used for data transfer between the CAD bus and the I / O device. It has the aforementioned sending / receiving interface of the command / address status signal CA. When a command and an address are output on the CAD bus, the CAD transfer circuit 203 sets the status signal CA to the " H " level. The instruction interpretation circuit 204 interprets the instruction issued from the I / O device, and sets a parameter for executing the DMA transfer to the DMA circuit 154 in accordance with the result. This allows the memory read / write request from the I / O device to be processed by DMA transfer. The error detector 205 receives the acknowledgement signal ACK returned by the I / O device at a fixed timing, and judges the reception status of the I / O device according to the result. When the RETRY demand returns, the CAD transmission circuit 203 instructs RETRY. -14-502171 V. Description of the Invention (i3) Each I / O device is provided with a bus request (BREQ) circuit 301, a clock pulse generation circuit 302, a CAD transmission circuit 303, an instruction interpretation circuit 304, and an error detection circuit, as shown in the figure. A tester 305, a FIFO buffer 306, a data read control circuit 307, a recorder group 308, and a DMA controller (DMAC) 309. The bus demand (BREQ) circuit 301 requests the bus arbiter circuit 15 for the bus grounding (BGNT) circuit 201 to use the bus right request signal BREQ. The bus grounder (BGNT) circuit 201 requires the bus right to use it. The permission signal BGNT allows data to be output by the CAD transfer circuit 303. The clock pulse generation circuit 302, the CAD transmission circuit 303, the instruction interpretation circuit 304, and the error detector 305 are each connected to the clock pulse generation circuit 202, the CAD transmission circuit 203, the instruction interpretation circuit 204, and the error detection circuit of the bus arbiter circuit 15. The tester 205 has the same function. However, there is no special need for the clock pulse generating circuit 302, such as the clock pulse frequency variable function of the bus arbiter circuit 15. The data read / write control circuit 307 executes read / write of the recorder group 308 in response to an access request from the bus arbiter circuit 15. The read / write data is transmitted to and received from the CAD transfer circuit 303 through the FIFO buffer 306. The FIFO buffer 306 is used to display the idle status in the recorder. If it is full, the error detector 205 returns a RETRY signal. If there is no problem, a positive response is returned. If no data is received, there is no response. DMA controller (DMAO309 uses I / O device as the bus master * -15- 502171 V. Description of invention (14) to act, when setting the start address and the number of transferred bits, the corresponding instruction and address Then, it is output by the CAD transfer circuit 303. Next, 'the specific operation of the bus system will be explained. ≪ When the CPU writes data to the I / O device > First, refer to Figures 7 and 8' from the CPU A description will be given of the case where 32-bit data is written into the I / O device 21. When this 1 is combined, the CPU 11 writes the "4-bit write signal" with the "address (25-bit)" and " Data (32-bit) ”is output to the memory bus 10. The data is input and stored in the FIFO buffer 151 of the bus · arbiter circuit 15. In the instruction / address / data synthesis circuit (CAD In the synthesis circuit) 1 52, the data is taken out from the FIFO buffer 1 51 and converted into instructions / addresses (CA) / and data D0-D3 like the bus system equipped with this embodiment. Here, CA becomes Instruction + address, instruction is, 4-bit transfer + write + 4 clock pulse command + A [24] address is, A [23:16], A [15:18], A [7: 0] The data is D0 + D1 + D2.D3 (8 bits x 4 = 32 bits). These data are written into the I / O device 21 through the CAD bus. The data transfer control operation at this time is as follows. (1) The bus arbiter 15 ensures that the bus right becomes the master (Bus Owner). (2) The bus arbiter 15 transfers SCLK 1 to the I / O device 21 of the access object to match the transfer of the I / O device 21 The frequency of the speed is output. -16- 502171 V. Description of the invention (i5) (3) At the starting point of SCLK 1 '! / 〇 The device 21 recognizes the content selected by itself and prepares for the reception of the data. (4) Confluence The bank arbiter 15 synchronizes with the rising point of SCLK, and outputs the CAK [7: 0] bus in the order of instruction, address, and data. In the command / address phase of the output instruction and address, the bus The arbiter 15 sets the aforementioned instruction / address status signal CA to " H ". (5) I / O is set 2 and synchronized with the falling point of SCLK 1, to read CAD [7: 0]. Then ' Interpret the instruction and the start address to prepare for the write operation. (6) The I / O device 21 uses 4 clock pulses as one cycle, and signals ACK [1: 0] at the T3 timing of the third clock pulse. Output status (in the case of a 3-clock pulse command, the ACK [1: 0] output status is output at T2 timing.) (7) The data of the number of transfer bits specified after that is output by the bus arbiter 15. 8) The I / O device 21 receives the transmitted data and writes it into the designated memory area. (9) In the data phase, the I / O device 21 outputs a state to the ACK [1: 0] terminal at its initial T1 timing. When there is a request for Retry, the transfer end, that is, the bus arbiter 15 determines that the transfer of the cycle (4 or 3 clock pulses) has failed, and retransmits it (Figure 8). (10) The data transfer ends at the same time as the clock pulse stops. In the data phase, the timing of the ACK is D 0 (T 1). Whether the data can be received is based on the idle state of the FIFO. You can immediately understand 502171. 5. Description of the invention (16) 'So it can be determined by the timing of D0. Submit. However, in the case of a command, it is necessary to explain what kind of command it is, so it cannot be sent out at the first clock pulse. < When the CPU reads data from the I / O device > Secondly, referring to FIG. 9, when the CPU 11 reads 8-byte data from the I / O device 21, it will be described. ** In this case 'CPU 1 1 generates the fetch signal and address on the memory bus 10. When the FIFO buffer 15 of the bus arbiter circuit 15 receives a read signal, it waits for a wait signal WaU until the I / O is ready. Next, the bus arbiter circuit 15 transfers a read command and an address to the I / O device 21, and the I / O device starts reading the data. The data transfer control operation at this time is as follows. (1) The bus arbiter 15 outputs SCLK 1 to the I / O device 21 to be accessed in accordance with the transfer speed frequency of the I / O device 21. (2) At the rising point of SCLK 1, the I / O device 21 recognizes the content selected by itself and selects the reception of the data. (3) The bus arbiter 15 is synchronized with the rising point of SCLK 1, and outputs the order of command, address, and data to the CAD [7: 0] bus. In the command / address phase of the output command and address, the bus arbiter 15 sets the aforementioned command / address status signal CA.

(4) I / O device 21 is synchronized with the falling point of SCLK 1 and reads CAD

[7: 〇]. Next, the instruction and the start address are interpreted in preparation for a write operation. (5) The bus arbiter 15 becomes -18- 502171 due to the data transfer so far. 5. Description of the invention (17) Standby output from 1 / ◦ device 21. (6) After this, the I / 〇 device 2 1 outputs BREQ 1 to the bus arbiter 15 and requests the bus right. (7) The bus arbiter 15 judges the priority order of the bus request, and gives the bus right to the BGNT 1 issued by the I / O device 21. (8) After the I / O device 21 ensures the bus power, SCLK 1 is output at a frequency that matches the transfer speed of the I / O device 21. (9) The I / O device 21 is synchronized with the rising point of SCLK, and outputs the data of the number of bytes specified by the CAD bus in byte units. (10) At the end of the specified number of transfers, the I / O device 21 makes BREQ 1 inactive, and the bus arbiter 15 receives this content to make B G N T 1 inactive. < DMA transfer according to read request from I / O > Next, referring to Fig. 10, the operation will be described in the case where DMA transfer is performed according to the read request from I / O device 21. (1) The I / O device 21 issues a BREQ 1 to request the bus flow right. (2) The bus arbiter 15 issues BGNT 1 to give the uo device 21 the bus right. (3) I / O device 21 outputs SCLK 1 in accordance with the transfer speed and frequency of the I / O device, and then synchronizes with SCLK 1 and outputs the read command and the start address on the CAD bus in sequence. In the instruction / address phase of the output instruction and address, the I / O device 21 sets the aforementioned instruction / address status signal CA to " H ". -19- 502171 V. Description of the invention (18) (4 ) Because the signal CA is " H ", the bus arbiter 15 is synchronized with the falling point of SCLK 1, and reads CAD [7: 0] as the instruction / address from the I / O device 21. Then, ' Interpret the instruction and the start address to prepare for DMA transfer. (5) 1/0 device 21 becomes the standby output from the bus arbiter 15 due to the data transfer so far, making BREQ 1 inactive ~ (6) Later, the bus arbiter 15 obtains the bus right and outputs SCLK 1 to the I / O device 21. Then, the data of the transmission byte designated by the CAD bus is sequentially output in byte units. ≪ DMA transfer according to write request from I / O > Next, referring to FIG. 11, the operation will be described in the case of performing DMA transfer based on the write request from I / O device 21. (1) 1 The / 0 device 21 issues a BREQ 1 to request the bus right. (2) The bus arbiter 15 issues a BGNT 1 to give the I / O device 21 a bus right. (3) The 1/0 device 21 outputs SCLK 1 in accordance with the transfer speed frequency of the I / O device, and then synchronizes with SCLK 1 to sequentially output the write instruction and the start address on the CAD bus. In the output instruction In the command / address phase of the address, the I / O device 21 sets the aforementioned command / address status signal CA to ΠΗ ". (4) Because the signal CA is " Η ", the bus arbiter 15 is synchronized with the falling point of SCLK 1, and CAD [7: 0] is read as the instruction / address. Then, the instruction and the start address are explained to prepare for DMA transfer. -20- 502171 V. Description of the invention (19) During this preparation period, the bus use right is temporarily liberated by I / O device 21 1. (5) I / O device 21 issues BREQ 1 to request the bus right. (6) The bus arbiter 15 is ready when the DMA transfer is ready At this time, BGNT 1 is sent to give I / 〇 device 21 a bus right. (7) I / O device 21 outputs SCLK 1 to match the transfer speed frequency of the I / O device. (8) I / O device 21 is synchronized with the falling point of SCLK 1, and the data of the transmission byte specified by the CAD bus is output in the order of byte unit. ≪ Stopping on the way> Next, referring to FIG. 12, it illustrates that when the CPU 11 writes data to the I / O device 21, it will explain the stopping operation during data transfer. (1) The bus arbiter 15 performs I / O The device 21 outputs SCLK 1 in accordance with the transfer speed frequency of the I / O device. (2) The bus arbiter 15 is synchronized with the rising point of SCLK 1, and outputs the order of the instructions, addresses, and data written in 8 bytes to the CAD [7: 0] bus. On the command / address phase of the output instruction and address, the bus arbiter 15 sets the aforementioned command / address status signal CA to "H " 〇 (3) The bus arbiter 15 for some reason When the transfer is interrupted halfway, reset the command / address status signal CA to "H", issue a new command, or issue a stop command to the I / O device. In this way, the data transfer in progress can be stopped halfway. -21- 502171 V. Description of the invention (2Q) < Switching of data transfer i > Next, referring to FIG. 13, in the process of transferring data to the I / O device 21, 'switch the bus cycle to I The / O device 22 will explain the data reading operation. Here, it is assumed that the 1/0 device 22 accepts the read command in advance, and before the read data from the 〖/ 〇 device 22 is transferred, When writing access to I / O device 21 is started first. (1) Bus arbiter 15 outputs SCLK 1 to I / O device 21 in accordance with the transfer speed and frequency of the I / O device 21. (2) The bus arbiter 15 is synchronized with the rising point of SCLK 1. For CAD [7: 0] the bus will refer to , Address, data to be sequentially output.

(3) In the data transfer to the I / O device 21, when the BREQ 2 from the I / O device 22 becomes active, the bus arbiter 15 cooperates with a predetermined bus open timing (in this case, the D3 end point) to output BGNT 2 ′ grants the right to use the bus to the I / O device 22. At the same time, the output of SCLK 1 is stopped, and the transfer of write data to the I / O device 21 is stopped. (4) The I / O device 22 outputs SCLK 2 in accordance with the transfer speed frequency of the I / O device 22. (5) The I / O device 22 is synchronized with the rising point of SCLK 2 and outputs the specified transmission byte data to the CAD in sequential order starting from the byte unit. (6) The bus arbiter circuit 15 uses the predetermined bus open timing to set the BGNT 2 to non-active to liberate the bus, and then obtains the bus use right again. Then, SCLK 1 is output, and the remaining data for the I / O device 21 is started again. Repeat the above to end the transfer. -22- V. Description of the invention (21) < Switching of data transfer 2 > Next, referring to FIG. 14, in the process of transferring data from the I / O device 21, the bus cycle is switched to I / O The data reading operation timing of the device 22 will be described. Here, it is assumed that the I / O device 22 accepts the read command in advance, and before the read data from the I / O device 22 is transferred, read access to the I / O device 21 is started. The occasion. ‘(1) After the I / O device 21 obtains the bus power, it outputs SCLK 1 in accordance with the transfer speed frequency of the I / O device 21. (2) The I / O device 21 synchronizes with the rising point of SCLK 1, and outputs the byte data of the transmission designated by CAD in the order of byte units. (3) In the data transfer from the I / O device 21, when the BREQ 2 from the I / O device 22 becomes active, the bus arbiter 15 cooperates with a predetermined bus opening sequence (the end point of D7 at this time) to enable BGNT 1 is inactive, making BGNT 2 active. (4) After the I / O device 22 obtains the bus power, it outputs SCLK 2 in accordance with the transfer speed frequency of the I / O device 22. (5) The I / O device 22 synchronizes with the rising point of SCLK 2 and sequentially outputs the byte data for the transfer specified by CAD in byte units. (6) In the data transfer from the I / O device 22, when the BREQ 1 from the I / O device 21 becomes inactive, the bus arbiter 15 cooperates with a predetermined bus opening sequence (in this case, the D3 end point) Make BGNT 2 inactive and BGNT 1 active. (7) I / O device 21 outputs 3 (:) 11 ^ 1 to start the transfer of the remaining data. Borrow »23- 502171 V. Description of the invention (22) The above actions are repeated to end the transfer. As described above 'for this The invention relates to a bus system. A. A channel / bus general bus structure is used, and a signal CA that distinguishes instructions / addresses and data is added. Therefore, A-1) For example, according to 1 in FIG. 10 The DMA transfer of the read request of / 〇 stated that 'not only the request (command) from the bus arbiter 5' corresponds to the independent request (DMA request) from the I / O. A-2) Furthermore, in the description of the stop of the write transfer in Fig. 12, even during the data transfer, the bus arbiter is used due to some reason on the 5th end, and the CA signal is set to active. It can make the I / O terminal recognize the situation where the data is not transferred, stop the latest order with the newly set command, or stop it halfway by the stop command. A-3) For example, in the description of the I / O write operation in FIG. 7, since the phase of the instruction / address can be identified, the sequence can be re-established when it occurs for some reason during the sequence. B. For example, in the RETRY operation description in FIG. 8, since the return ACK timing is fixed, B-1) does not need to send a clock pulse for locking the ACK, and can reduce pi η 〇 2-2) ACK The generated timing uses the clock pulse of the transmitting end, so the judgment of the response content (acknowledge, retry, and error) of the ACK can be designed synchronously to simplify the circuit ° B-3) Especially due to the ACK response timing setting of the data phase At the front end, the receiving end of the ACK can get the answer of the data transfer at an early time, so -24-502171 5 'invention description (23) can simplify the circuit to make it easy to respond. C. For example, in the description of the I / O read switching in FIG. 14 'the phase of the instruction / address fixes the bus open timing at the 3rd or 4th cycle, and the data phase fixes the bus open timing at the 3rd or 4th cycle. 2 cycle or 4 cycle, C-1) The communication signal can be deleted without notifying the timing of the open bus. C-2) Due to the fixation, the switching timing from I / O 21 to I / O 22 can be judged before the actual switching is more than 1 clock pulse, so the switching loss can be minimized. D. In addition, the instruction can have an address expansion bit, so it is usually accessed in a short cycle to achieve high-speed operation. When a large memory capacity is to be used, the expansion bit can be used to expand the memory area. Ε. Usually, when the number of data to be transferred is specified, the address on the I / O side is +1. Because the address is the same and the number of additional data transfers can be changed, the same address of the FIFO can also be read continuously. Write information. Therefore, according to the bus system of the present invention, the number of signal lines can be reduced, and the same flexible access control as the channel type can be realized. Symbol Description

6… control signal 10… memory bus 1 1-CPU 12… RAM -25- 502171 V. Description of the invention (24)

13… ROM 14… Gate Array 15… Bus Arbiter Circuit 20… I / O Bus 2L · " I / O Device 1 22 ... I / O Device 2 23: 1/0 Device 3 26 ... Address Bus 32… data bus

151, 306 ... FIFO 152 ... CAD synthesis circuit 153 ... Transfer control circuit 154 "· DMA circuit 201 ... BGNT circuit 2 0 2 ... Clock pulse generation circuit 203 ... CAD transmission circuit 204 ... Instruction interpretation circuit 205, 305 ... Error detection Tester 307 ... Data reading and writing control circuit 308 ... Recorder group

309… DMAC -26-

Claims (1)

502171 6. Scope of patent application1. A data transmission system is a data transmission system for transmitting data between the bus arbiter 5 and a plurality of I / O devices, which is characterized in that the aforementioned I / O devices are provided with A device for requesting the ownership of the bus is provided. For the aforementioned bus arbiter, a grounding device is provided to allow the ownership of the aforementioned bus. The aforementioned bus arbiter and each of the I / O devices have: instructions, addresses and data in A device for transmitting A on the same bus; a device that transmits a clock pulse to the other party when using the aforementioned bus to transmit data; a receiving device that receives the clock pulse from the other party and then receives the data transmitted by the other party; the aforementioned instructions and bits When the address and data are output on the same bus, the device that outputs the command or data signal output on this bus will be distinguished. 2. If the data transmission system of item 1 of the patent application scope, the bus arbiter and each of the aforementioned I / O devices are further equipped with the same bus to receive instructions, addresses, and data from the other party. The timing of the notification of the receiving state of the receiving end to the notification device of the other party. 3. The data transmission system of item 1 in the scope of patent application, in which the bus opening sequence used in the aforementioned instruction, address and data transmission is fixed, and the aforementioned bus arbiter is used to open the timing control in a fixed bus. Allocation of bus ownership. 4. If the data transmission system of the first item of the patent application scope, wherein the foregoing instructions include the address extension bit indicating whether there is an extension of the subsequent address bit length, the aforementioned arbiter and the aforementioned I / O devices The length of the address bit following the instruction is determined according to the address extension bit. -27- 502171 6. Application scope 5. If the data transmission system of item 丨 of the scope of application for patent, the aforementioned arbiter and each of the aforementioned I / O devices have the first data to increase the address while performing continuous data transmission The transmission mode and the second data transmission mode in which continuous data transmission is performed without incrementing the address, are further provided with a designated device that uses any one of the aforementioned first and second data transmission modes in accordance with the aforementioned instruction. 6. As claimed-please apply for the data transmission system of any one of items 1 to 5 of the patent, where the aforementioned arbiter's address transmitted from the CPU, the data is divided, and it is converted into a device mounted on the bus sequence data. 7 · A data transmission system is provided with a bus that transmits instructions, addresses, and data in time distribution, a plurality of I / O devices connected to the bus, and a connection to the bus, and 1 / () Data transmission between devices The data transmission system of the data transmission control device performed by the aforementioned bus is characterized in that a phase difference signal line is defined on the aforementioned bus, which is used to indicate that Any one of the foregoing instruction and the foregoing data, wherein the foregoing data transmission control device and each of the I / O devices have: receiving a clock pulse signal transmitted by the other party through a clock pulse signal line disposed therebetween, and receiving the clock pulse signal from the clock pulse signal The transmitting end is a command, address, or data receiving start device transmitted through the bus; when the command, address, or data is output on the bus in synchronization with the clock pulse signal, the bus is The output device is a command or data, and the device notifies the other party by using the phase difference signal line. 8. If the data transmission system of the 7th scope of the patent application, for the first 502171 VI, the bus of the scope of the patent application, defines the response signal line at the receiving end to notify the other party of the status of the instruction or data, the aforementioned response signal The driving phase of the command is that the command phase output by the command on the bus and the data phase output by the data on the bus are required to be fixed. 9 · If the data transmission system of item 7 of the patent application scope, wherein the aforementioned data transmission control device 'is a bus mediation device that has ownership of the mediation bus in response to the request for the bus right from the aforementioned I / O device, The liberation timing of the bus, the command phase output by the command on the bus, and the data phase output by the data on the bus are required to be fixed. The bus mediation device corresponds to the new bus right. It is required to release each of the command phase and the data phase in execution at a fixed timing. -29-