TW499636B - PC card controller with advanced power management reset capabilities - Google Patents

Abstract

A power management PC expansion, card controller that includes power on reset circuitry to reset power management enable registers during a reset period, thereby ensuring that the PME registers correctly identify the power management capabilities of the controller. Once the PME registers are reset, an instruction may be provided to change the state of the registers from a default reset state to a state that supports advanced power management capabilities, for example wake-up functions. Additionally, the controller includes blocking circuitry to block conventional reset signals from resetting the power management and proprietary registers if the PME register is instructed to change states, thereby preserving the data contained in the power management and proprietary registers against future reset events. The controller of the present invention supports advanced power management specifications without requiring additional pinout arrangement or reassignment of pin functionality, so that the controller of the present invention can be implemented in current computer system without a the need for retooling or re-layout of system board circuitry and wiring diagrams.

Description

Printed by the Employees' Cooperative of the Bureau of Intellectual Property, Bureau 1 of the Ministry of Economic Affairs A7 V. Description of the Invention () Delivery of the Invention: This invention is related to each person's computer card controller with advanced power management and register reset capabilities. More specifically, the present invention relates to a personal computer card controller that achieves an advanced power management mode by supporting a register reset capability. The purpose of the present invention is to support a higher power management capability of a plurality of expansion cards with a Cardbus controller. Background of the Invention: Prior to the setting of power management specifications, traditionally portable notebook PC devices can support the following power states: ⑴ power on state, (2) power off P4 state, (3) low power (sleep) state (To turn off the internal clock signal < 10,000-style) and (4) Pause state (to turn off most of the system's power). However, this approach has its limitations. For example, a device that does not have an internal clock (such as an internal pLL generating clock) can take an extra time to return to an open complaint before it can be used < In addition, because the operating system usually does not know the status data of each device, it may mistakenly treat the device as broken when it does not respond in timeout. Figure 1 shows the traditional registers 12, 14 and 16 of a conventional personal computer card plug-in bus controller 10, among which the traditional registers include a PCI configuration register 12 ′ which provides a controller! 〇 and an interface between the PCI bus; card plug-in bus control register 14, which generates internal instructions and commands' for personal card plug-in bus control; and a special register 16 (for the controller Designed by the manufacturer, these controllers contain general 1/0 temporary storage page 3 --I --- II --- install -------- order ------ I-- ( (Please read the notes on the back before filling out this page) 499636 A7

V. Description of the invention ()

Employees of the Intellectual Property Office of the Ministry of Economic Affairs, Consumer Cooperatives (printers, special pinout registers, etc.). In the conventional controller 1Q, the presence of a PCI reset signal is used to reset the registers 12, 14 and 16. In the traditional card plug-in controllers, the various card plug-in buses cannot enter the power saving mode at all, because these controllers do not meet the specifications of power management. In order to solve the above problems, Microsoft has made a series of agreements, called ACPI (Advanced Configuration and Power Interface Specification). Similarly, the p c I committee has developed specifications for P CI power management to address these issues. In order to comply with the above specifications, the PCMCIA committee (also based on the pci power management specification) formulated computer card power management specifications. At this time, most of the PCI devices (including computer card controllers) in laptops were also modified. To meet advanced power management specifications. According to the PCI power management specifications, PCI buses and buses have di, di D2, D3, HOT, and D3 —COLD states. 'The inherited PCI devices generally automatically support the DO (power on) and D3-COLD (power off) states, and D1, D2, and D3-HOT states are power saving states with various degrees under these specifications. Generally speaking, the D 1 state consumes less energy than the DO state, and the D 2 state consumes less power than the D 1 state. There is a new power supply in the p c I power management specification, which is generally called AUXVCC, which is added in the D3-COLD state. AUXVCC is a new power provision that can be maintained in a fixed logic while the main power supply (referred to as PCI VCC) is off. Therefore, AUXVCC was added to maintain the logic at a predetermined minimum value, but at this time, other parts of the system are still closed. In order to maintain the existence of certain information in some registers, when the system is switched from D3 to COLD, the paper size applies to China National Standard (CNS) A4 (210 X 297 mm).

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499636 A7 V. Description of the invention (When the DO state is reached, AUXVCC will supply power to these registers to wake them up and confirm their identity. In order to recall the system from the D3-CLD state to the DO state, a certain These power management and inheritance registers must maintain the existence of their internal data to allow the operating system to know the data, so when the wake-up command is issued, the operating system can know which device the wake-up signal was sent to when the controller received it. When requesting to wake up from D3-COLD state to D〇 state, the AUXVCC signal enables the appropriate power management register to maintain the existence of the request and process the request, so the operating system will receive the request from looking for the request The appropriate signal from the device. In the traditional card plug-in bus controller, the 'power management and inheritance register block system. When the device sending the request signal enters another state from the D3-COLD state, the power management and inheritance The register block system will be reset_, where the device status is changed by checking the power status register. However, when the system is finished When the full power is off and the power is on, the card plug-in bus device will have difficulty in judging the correctness of the information contained in the power state register. The card plug-in bus socket power register is a typical card plug-in bus controller. Example: Because there are many types of computer plug-in cards, the controller may mistakenly supply a 5 volt power supply to a card with a 3 volt power supply when the socket power is incorrectly used. When BI0S has not detected this error, the The card will be damaged. Therefore, when the system is powered from a complete power off state, it is necessary to properly reset the power management and inheritance registers. It is most important to reset the system when power is applied. The simple method is to apply the Chinese National Standard (CNS) A4 specification (21 × 297 mm) on page 5 of this paper. (Please read the precautions on the back before filling out this page}! Ι!, Ι; 7 ·! λ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy 499636 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (An extra pin is provided on the controller And use this pin to perform a general reset of each appropriate register. However, this method needs to change the designated connection of a certain pin. Assuming that the card plug-in bus controller is installed in a large amount, this method It is not applicable because the line routing method and the position of the parts need to be changed 'to accommodate this additional pin. In addition, the card plug-in bus controller technology is a mature technology, and the pin design of each manufacturer The methods are different, and most of the pins have been multiplexed to perform various functions, so there is little room for changing the arrangement of the pins. Therefore, a power supply for the PCI and card plug-in buses is provided when power is applied. A card card bus controller that temporarily stores the reset capability of the appliance is necessary, where the controller does not need to require any changes in the pin assignments on the connection or on the line traces. Purpose and summary of the invention: Therefore, the general purpose of the present invention is to provide a card plug-in control stomach that can support advanced power management specifications without the need for additional pins or re-designated pin functions. The controller can be used in the current computer system without re-arranging the system board circuit and wiring diagram. It is an object of the present invention to provide a card insertion controller including an f-source reset circuit, to reset the power management startup (PME) register during the reset period, thereby ensuring that the register can be obtained correctly. Power management capabilities. Another object of the present invention is to provide _ a kind of Carbenau standard including a blocking circuit · Chinese national standard (21〇χ 297 public inspection 7 ------------------- -^ --------. (Please read the precautions on the back before filling out this page) 499636 A7 V. Description of the invention () Plug-in bus controller 'to block the traditional reset signal instead of heavy The power management register is reset after the initialization. In a broader sense, the present invention provides a computer card controller that includes at least a power management enable (PME) register. When the PME register is used, the-trigger signal changes state; _ power on reset circuit is used to receive the trigger signal and generate a first reset signal to be added to the PME register for the first time The pME register is reset at time. In the exemplary embodiment, the present invention also provides a card plug-in bus controller, which includes a power management start (PME) register, PCI and card plug-in bus power management temporary storage. Device, a trigger signal will change state when the power is first applied to the .PME; and a power-on reset circuit is used to connect The trigger signal generates a first reset signal to reset the pME register. In a preferred embodiment, the present invention includes a blocking circuit for receiving the PCI and card card bus temporary storage. A conventional reset signal from the controller is used to receive a signal indicating the status of the PME register. The blocking circuit generates a second signal to reset the PCI and card bus registers. If the control signal is not If activated, the blocking circuit will generate a second reset signal according to the traditional reset signal to reset the PCI and card card bus registers. If the control signal is activated, then regardless of the traditional reset signal , The blocking circuit will block the second reset signal to avoid the possibility of resetting the PCI and card plug-in bus registers. The invention also provides a reset of a computer card controller. The paper size is applicable to the country of China Standard (CNS) A4 Specification (210 X 297 mm) ------------ Installation --- (Please read the precautions on the back before filling this page) Order ------- -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs or 49963 6 A7 B7 V. Description of the Invention (Multi-register method, the method includes at least the following steps: selection-trigger signal 'where the trigger signal will change when the power is first applied to the power management startup (PME) register Power level; generating a reset signal based on the trigger signal; and using the reset signal to reset the PME register. In some preferred embodiments, the method further includes the following steps: generating a second reset Signal and resetting the power management register with the second reset signal. The method may further include the following steps: generating a control signal indicating a reset state of the pME register; and causing the first control signal and A conventional reset signal performs an AND operation to generate a current-time signal. At the same time, the method may further include the following steps: instructing the reset stone register to change state; changing the state of the control signal; and blocking the possibility that the power management register is reset again. Those who are familiar with this technology can understand the following details. The detailed description is based on the preferred embodiments and methods of use as examples. However, the scope of this cigarette is really defined by the scope of the attached application. Other purposes, features, and advantages of the invention printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics and Economics will be detailed in the following detailed preferred embodiments and the attached patent application. Schematic auxiliary description, where the phase number in each formula represents the same part, where: Brief description of the diagram: The same as shown in Figure 1 is a traditional computer card controller. Light six ^ # 器 的 方 图 0 第Figure 2 is a system-level block of the relevant part of the controller of the present invention. (Please read the precautions on the back before filling this page) Page 8 This paper size is applicable to China National Standard (CNS) A4 (21〇X 297 mm)

Description of the invention (Figure, in which the controller can support the two-stage power management push and contain the power-on reset circuit, and the reset is performed by the register ... ^ Some temporary pictures when turned on are Figure 2 The clock example of the reset signal of the power-on reset reset signal is shown in Figure 4. Figure 4 shows the example flow chart of the invention to generate a rain% source-on reset signal in the present invention. Another example of the circuit used in the controller of Fig. 2 is to use Ai Tunyuan to open the circuit. Κ No. 1 contrast description: 12 traditional PCI configuration register 14 card plug-in control register 16 proprietary register 20 card plug-in bus control 20 »Card plug-in bus controller 22 Card plug-in power management register 30 Power-on reset circuit 30 丨 Power-on reset circuit 32 AUXVCC power supply 38 and logic gate 44 Logic 46 Flip-flop 50 Power management startup register 52 Inverter 56 operating system input invention detailed description: Fig. 2 shows an example block diagram of the card connector bus controller 20 of the present invention, which can support advanced power management specifications (such as ACPI specifications) and has a power on Reset management capabilities. Generally speaking, it can support power management. The private paper size on page 9 applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ----- ^ __ w ^ ------ —Order --------- Line · (Please read the notes on the back before filling out this page} Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employees' Cooperatives of the Ministry of Economic Affairs ’Intellectual Property Bureau () The controller specifications include traditional pCI configuration register 12, card plug-in bus control register 14, PCI and card plug-in power management register 22, and pME startup (_ble) register 50. As mentioned above As mentioned, the register 22 can know the state of advanced power management protocols, such as D0, D1, D2, and D3. The register 22 can also include an inherited register, which can be a certain register. Produced by specific manufacturers, such as the OZ6833 card plug-in controller produced by 〇2MiCro International Co., Ltd., etc. The pME startup register 50 provides a wake-up function in the level-level power management operation mode. The operating system from the operating system ( OS) Enter 56 which provides an instruction to activate these registers, so Make the PCI and card plug-in bus power management registers 22 support the wake-up function (different from the power modes D0, D1, D2, D3-h0t, and D3-c0ld described above). 'Once reset or When the power is turned on (that is, when the AUXVCC is switched from the high level to the high level), the POR circuit 30 uses AUXVCC as a trigger signal to generate a reset signal R1 (34). R1 resets the pme boot register 50 to its reset level. Initial or default state. The default state of register 50 will generate a signal 24 (low level) indicating that the power management event (PME) is not activated (that is, the wake-up function is not supported). In addition, when the power is turned on, the PCI reset signal will be set to an active high level to reset the registers 12 and 14. Due to the presence of the inverters 52, and, and the logic gate 38, the register 22 is reset by R2, and R2 is the PCI reset signal 18. The instruction to support the PME is provided to the pme by the operating system via the OS input 56 Activate the register 50. If the deduction is sent to the register 50 ', then the signal 24 will transition from the non-starting (low level) state to the starting (high level) state. Therefore, the register 22 can no longer be the first 10 pages ------------ install -------- order ------ II-(Please read the precautions on the back before filling this page), invention description ()

The active level of the PcI reset signal 18 is reset early, so these registers are protected in one action. Therefore, the Taizheng ntw system is both physical and logical. The present invention provides a register 30 and the ability to re-enable I during the power-on or start-up period to ensure that the data in these registers is correct and undoubted. Inventory 22 is reset during normal operations to protect the data in these registers. It is better to use an existing signal to reset the register so that the controller does not need additional pins. To achieve this, the present invention adds a power-on reset (POR) circuit 30, which can generate-reset the signal R1 (34) to register the pME register according to a signal during the power-on period. 50 reset. In the preferred embodiment, the POR circuit generates a reset signal 34 (according to the ACPI specification) according to the AUXvcc signal. The existence of this signal is advantageous because it does not change state at the end of a set-up period. Generally speaking, resetting when the power is turned on is defined as the controller going from no power to being supplied for the first time. The time of power supply, where the power supply includes pci vcc (not shown) and AUXVCC 32, without any power supply may be because the computer system (with the controller 20 of the present invention plugged in) is not plugged into the power supply or the battery is insufficient. The reason. As mentioned above, the data contained in these registers are unreliable when power is first applied. Therefore, we hope that the registers will be stored when the controller 20 is adjusted to comply with the Advanced Power Management Specification (ACPI). This time (for example, turning off to the D0 state) is reset, and then it will not be reset (such as D3-cold to D0 state) until the power is turned on again. Of course, those skilled in the art can understand that other signals can also achieve the reset operation of the register 22, and the use of AUXVCC as the reset trigger is just one example. Page 11 This paper is in accordance with the Chinese National Standard (CNSiA4 specification (21〇 X 297 変)) Read the notes on Φ to write this page

Order BII Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by 499636 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by A7 B7 V. Description of the invention () The power management register 22 here contains the PCI power management pre-store register ( power management preserve registers) and / or card plug-in power management registers and / or inheritance registers. In conventional technology, these registers have various power management states (such as D0, Dl, D2, D3_hot, and D3 — cold power management states) and supply voltage (such as 5V, 3.3V, 3V, etc.). Power requirements of the computer card being controlled. In addition, the following examples are described for a card plug-in controller, but it should be noted that the controller of the present invention can be applied to any kind of computer expansion card technology, including traditional PCMIA and Smartcard. FIG. 3 shows a clock diagram of the POR circuit 30. During the period immediately after the power was turned on, the AUXVCC 32 signal transitioned from a low level to a high level (as shown in the figure). When the voltage of the signal 32 rises, the POR circuit 30 generates a reset signal 34 (R1), which will be explained below. During the period when the voltage of the auxvcc signal rises, the relevant part of the signal includes Vs and Vth. Because the reset signal R1 must be issued before AUXVCC becomes an active signal, the reset signal must be issued before the threshold voltage Vih of AUXVCC (that is, before A U X V C C is considered high on time). v s represents the start time of the reset signal, which is usually triggered by a sufficiently large voltage on the AUXVCC signal. The time between Vs and Vth is represented by tPOR, and the power-on reset signal is generated within this period. In this example, the active state of R1 is the low level state. This is because the reset signal generally required by the PME register is the low level signal as the active signal. If the PME register requires a high-level active signal, the POR circuit must include an inverter. The POR circuit 30 may include an RC circuit for applying the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to the paper swing voltage on page 12. 第., ---------- ------- ^ ----- II ---. (Please read the notes on the back before filling out this page) 499636 A7 B7 V. Description of the invention (Triggered when generated, as shown in Figure 2. However, those skilled in the art can understand that other circuits can also generate signals such as in Figure 2. Such circuits should be considered as the equivalent scope of the present invention. Please refer to Figure 2. R1 in the figure is based on the above The method is used to reset the P ME startup register 50, in which the PME is disabled by default, and will generate a non-activated (low level) signal 2 4., And the input of the logic gate 3 8 is PCI reset signal 18 and PME signal 24. After a period of time, if the operating system command controller supports the wake-up function, a signal will be sent to the p ME boot register 50 through the OS signal input 56 to start pmE startup register, at this time PME startup register 50 will change the state of the startup signal 24 from low level (not start) to high level After this period of time, the output of "and" logic gate 38 has been maintained at a low level, so the PCI reset signal cannot be reset to the register 22 (because of the status of R2 and PCI reset signal Irrelevant 'is always low level), so as to ensure that the registers 22 and 50 cannot be reset by the reset signal of pc I added later. Once the controller determines that it has high power management capabilities, If the registers 22 and 50 are reset when the power is turned on, the register 22 can control the advanced power management state, that is, it can control the D0, D1, D2, D3 hot, and D3-coId states. Although the internal reset signal is explained Nothing about the present invention 'but Figure 2 still shows the internal reset signal generation method required for a specific power management state (required by the ACpi specification). For example, if the controller is required to enter the D3-hot state' then The register 22 will control the Cardbus controller to enter this state. If the state changes (such as from page 13, this paper standard applies the Chinese National Standard (CNS) A4 specification (210 X 297 feet) Please read first CAUTIONS face of

I Page I I I Order Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 499636 A7

V. Description of the Invention () Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, D3_hot is changed to the DO state) ', then the register 22 will generate a wake-up signal 42 to logic 44. When the logic 44 receives the wake-up signal, it will then generate-ACPI reset signal & 28. The Acpi reset signal is an internal reset signal that resets the PCI & state register 12 and the card plug-in bus control register when D3-h0t is required to change to the D state. 4 Home. If the PME signal 24 remains inactive, then the ACPI reset signal 28 will also reset the PCI and card plug-in bus power management registers and inheritance registers 22. FIG. 4 shows an example of a card plug-in bus controller 20 and another pOR circuit 30f. In this example, the pOR circuit 30 includes a flip-flop circuit 46 '. The flip-flop circuit 46 generates an R1 signal 34 according to the AUXVCC 32 and the PCI reset signal 18. In this example, the PCI reset signal is used to trigger the flip-flop 46, and the operation of the rest of the circuit is the same as that of the circuit in Fig. 2-. As the status of the PCI reset signal can (will) be changed under normal operation, and the status of AUXVCC will only change when the power is turned on, so the flip-flop is set to enable the reset signal after the reset signal is changed twice. It is important that the output R1 remains unchanged (of course, the power is turned on again) to avoid the PME startup register being continuously reset. When the power starts, a PCI reset signal is issued to reset the power management register '22. After a period of time, the PCI reset signal stops resetting. At this time, R1 must not be activated until AUXVCC is activated again (that is, until the power is removed from the controller and power is applied again). On the other hand, the AUXVCC signal can also be used as a trigger signal, and other clock circuits (not shown) can be added to it so that R1 can be abandoned to actuate into a reset signal after a specific time. China National Standard (CNS) A4 specification (210 X 297 mm) --- installation ------- 丨 order i I ------ line (Please read the precautions on the back before filling this page) Economy The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Education printed A7 _ ^ _ 一 ― _B7_ --_-- V. Invention Description () number. FIG. 5 is a flowchart of a preferred power-on reset operation of the card plug-in bus controller 20 or 20 in the present invention. The power-on reset 102 is started at the beginning of this action flow, as described above. A signal that changes the diamond shape during the power-on period is selected as 104. Since this application is related to the method of resetting under a power-off condition, most (if not all) of the relevant signals of the card plug-in bus controller can meet this condition. Therefore, it is necessary to select a signal that does not change state at the end of the power-on period. In the preferred embodiment, this signal is an AUXVCC signal, but other signals that meet this requirement may be selected. The selected address book (such as AUXVCC signal) in step 丨 〇4 is designated as the trigger signal ι〇6. When the AUXVCC signal is used as a trigger signal, a P0R (power on reset) signal is then generated. The POR signal resets the PME · start register u〇, and the PME internal status signal (or flag signal) is then generated 114. At the same time, the power management and inheritance registers are reset for the POR signal. The status of the PME fixed signal will not change unless it is changed by a certain instruction, such as the instruction sent by the operating system. The controller can know whether the operating system has changed the status of the PME default status signal 1 16. If the pME signal status does not change, the controller will allow the power management and inheritance registers to be reset in the future. Therefore, the controller of the present invention can achieve the purpose of the invention because the power management registers (and inherited registers) of the PCI and card plug-in buses are powered on and managed. The power reset management is provided by —The pin assignment of the existing card plug-in bus controller was achieved, so the system parts are not on page 15. This paper size applies to China National Standard (CNS) A4 (21G > c 297 mm) '----- ------- I --- i — 1 — m ^ --- I -----. (Please read the notes on the back before filling this page) 499636

Need to add pins and / or re-layout. Familiar with this technology, understand that the present invention can make many changes. For example, in the description of Figure 2 and Figure 4, the reset signal R1 is assumed to be a low-level signal and the signal is active. You only need to invert the R1 signal. It can become a signal with a high level state as the active state (the mode can be implemented when needed). In general, the exemplary states of the signals described in the present invention can be changed according to certain specifications. Those who are familiar with this technology can also understand that the card plug-in bus controller is only shown in the diagram with its relevant parts. Of course, the card plug-in bus controller can also include other traditional parts (such as 1 > (: 1 interface circuit), To exchange commands and data along a PCI bus between the controller and a host computer system. In addition, computer card processing logic can be added to the system. This logic can include card card bus processing control logic and / or traditional Computer card processing control logic and / or other computer expansion card technology β Furthermore, those skilled in the art can also understand the need to add appropriate buffering and / or when implementing in the specific integrated circuit with the concepts described in this case Bias function to meet the specifications of power consumption. .--------- 1——I— ^ Awi (Please read the precautions on the back before filling this page) The above and other changes belong to the present invention. Within the spirit scope, the scope of the present invention is defined by the scope of patent application attached later. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs

Claims (1)

A8 B8 C8 ______ D8 VI. --- 1 · A kind of personal computer card controller, the controller contains at least: power management start (PME) register; trigger signal, the first time power is added to the power management startup temporary The memory changes state; and a power-on reset circuit for receiving the trigger signal and generating a first reset signal when the power is attached to the PME register to reset the PME register. 2 · The controller according to item 1 of the scope of patent application, wherein the controller further includes a power management register, and the power-on circuit can generate a first time when the power is first added to the power management register. 2 reset signal to reset the power management register. 3. The controller as described in item 2 of the scope of patent application, wherein the ρ μ E register is reset to a predetermined state and a control signal indicating the predetermined state is generated; and the PME register is used for Receive a command to change from a predetermined state to a different state, and generate a control signal indicating the different state. 4. The controller as described in item 3 of the scope of patent application, wherein the default state includes at least a state that does not support the wake-up function and the different states include at least one state that supports the wake-up function. 5. The controller described in item 4 of the scope of patent application, which also includes blocking _____ This paper AJt applies Chinese National Standard (CNS) A4g (2i〇〆297), (Please read the precautions on the back first (Fill in this page again.) Order printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 499636 Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs printed A8 B8 C8 D8 ~, patent application circuit, used to receive a tradition of this power management register The reset signal and the control signal, and the second reset signal is generated. When the control signal indicates that a different state occurs, the blocking circuit prevents the power management register from being reset by the traditional reset signal. . 6. The controller according to item 5 of the scope of patent application, wherein the power management register includes at least a PCI and card plug-in bus power management saving register and inheriting register, and the traditional reset signal includes at least one PCI Reset the signal. 7. The controller according to item 5 of the scope of patent application, wherein the blocking circuit includes at least a sum logic gate for receiving the traditional reset signal required by the power management register and receiving the control signal, The second reset signal is generated. … 8. The controller as described in item 3 of the scope of patent application, wherein the instruction is generated by an operating system and communicates with the PME register, wherein the default state is defined as the state when the power management function is not activated, and The command generated from the operating system changes the state of the PME register to enable the power management function. 9. The controller according to item 1 of the patent application scope, wherein the power-on reset circuit is configured to generate the reset signal before the trigger signal reaches a predetermined threshold power value. _________ Page 18_ The national standard of this paper is CNS) A4 size (210X297 mm) (Please read the precautions on the back before this page) ............... ..... see > V ------ I equipment, 1T 499636 A8 B8 C8 D8 Six patent application scopes I 0 · As described in the patent application scope item 9, the controller, The trigger signal rarely includes an AUXVCC signal, and the circuit includes at least an rc circuit. The RC circuit is selected to generate the first reset signal. II · The controller as described in item 1 of the patent application scope, wherein the power-on reset circuit includes at least a flip-flop circuit, the trigger signal is a traditional reset circuit, and the flip-flop is used to receive the trigger The signal and the -0 source are added to the register for the first time and generate a signal to change the state when the first reset signal is generated. 12. The controller according to item 丨 丨 in the scope of patent application, wherein the trigger signal includes at least a PCI reset signal, and the PCI reset signal changes state when the power supply is first applied to the register, and After that, the state is changed according to an external reset command, and once the PCI reset signal changes state twice, the positive and negative circuits are used to permanently disable the first reset signal until the power is first applied to the This signal changes only when the system is running. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 1 3 · The controller described in item 1 of the scope of patent application, wherein the power-on reset circuit is used to generate the first reset signal, and only when the power is first applied to the The PME register is reset during the register. 14. · A method for resetting one or more registers of a personal computer card controller. The method includes at least the following steps: Selecting a trigger signal, wherein the trigger signal is first applied to the power supply. 499636 A8 B8 C8 D8 6. The scope of the patent application will change the power level when the power management startup (PME) register is generated; a reset signal is generated according to the trigger signal; and the PME register is reset using the reset signal . 15. The method according to item 14 of the scope of patent application, further comprising the following steps: generating a second reset signal; and resetting the power management register with the second reset signal. 16. The method as described in item 15 of the scope of patent application, further comprising the following steps: generating a control signal indicating the reset status of the PME register; and * making the first control signal and a conventional reset signal The set signal performs an AND operation to generate the second reset signal. 17. The method according to item 16 of the scope of patent application, further comprising the following steps: instructing the reset PME register to change state; changing the state of the control signal; and blocking the power management register from being reset again Placement possible. 1 8 · The method described in item 14 of the scope of patent application, which further includes the following steps: __ 笛 20 百 _ This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read it first) Note on the back, please fill in this page again.) Order · Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 499636 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 D8 Voltage; according to the predetermined threshold: the voltage generates the reset signal. 19 · The method as described in item 4 of the patent application scope, which further includes the following steps: selecting a traditional reset signal; rotating the traditional reset signal and the trigger signal to a flip-flop; and generating the The signal is reset until the trigger of the flip-flop changes state from a starting state twice. 20. —A card plug-in bus_air controller, which includes at least a power management enable (PME) register, a PCI and card plug-in bus power management register, and a first-time addition to the PME, PCI, and card Plug-in. Bus register. Trigger signal and power-on reset circuit that change state. The power-on reset circuit is used to receive the trigger signal and to generate a first reset signal to reset the PME register. . 21. The controller according to item 20 of the scope of patent application, wherein the pME register receives the reset signal and generates a power management signal, wherein if the power management signal is activated, the power pipe buried register is Can enter advanced power management state, and if the power management signal is not activated, the power management register cannot enter advanced power management status. 22 · The controller described in item 21 of the scope of patent application, which also includes resistance. Page 21 (Please read the precautions on the back before filling this page) 8 888 ABCD 499636 6. Scope of patent application The circuit is interrupted. The blocking circuit is used to receive the power management signal and a traditional reset signal, and generate a second reset signal for the PCI and card file bus registers. 23. The controller according to item 22 of the scope of patent application, wherein the blocking circuit includes at least a sum logic gate for receiving the traditional reset signal, the power management signal, and the reset signal. 2 4. The controller as described in item 23 of the scope of patent application, wherein the logic gate can make the second reset signal become the second reset signal when the power management signal is not activated and the traditional reset signal is active. initiative. 25. The controller as described in item 23 of the scope of patent application, wherein the and logic gate can make the second reset signal inactive when the power management signal is activated. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 26. The controller as described in the scope of patent application No. 22, wherein the blocking circuit can be activated when the power management signal is not activated and the traditional reset signal is activated The second reset signal further disables the first reset signal when the power management signal is activated and the traditional reset signal is enabled or disabled. 27. The controller as described in claim 22, wherein the conventional reset signal includes at least one PCI reset signal. _ Page 22 _ __ ^ --- This paper size applies to China National Standard (CNS) A4 (210X297 mm) 499636 8888 ABC0 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. Scope of patent application 28. If applying for a patent The controller according to item 20 of the scope, wherein the trigger signal is an AUXVCC signal, and the AUXVCC signal is defined in Advanced Power Source Management Specification (ACPI). 29. The controller according to item 20 of the patent application scope, wherein the power-on reset circuit is configured to generate the reset signal before the trigger signal reaches a predetermined threshold power value. 30. The controller according to item 29 of the scope of patent application, wherein the trigger signal includes at least an AUXVCC signal, and the circuit includes at least an -Rc circuit, and the RC circuit is selected to generate the first reset signal. 3 1 · The controller as described in item 20 of the patent application scope, wherein the power-on reset circuit includes at least a flip-flop circuit, the trigger signal is a traditional reset signal, and the flip-flop is used for receiving The trigger signal and the signal for changing the state when the power is first applied to the register are used to generate the first reset signal. 32. The controller according to item 3 of the scope of patent application, wherein the trigger signal includes at least a PCI reset signal, and the PCI reset signal changes state when the power supply is first applied to the register, and After that, the state is changed according to an external reset command, and once the PCI reset signal is changed twice, the flip-flop makes the first reset signal never start until the signal is first applied to the power supply. The system stops while changing state. _ _— page 23 This paper size is applicable to the Chinese National Standard (CNS) A4 (2ΐ〇χ 297 public envy) one by one 'one-(Please read the precautions on the back before filling this page} 499636 A8 B8 C8 D8 VI. Patent application scope 3 3 · The controller as described in item 20 of the patent application scope, wherein the power-on reset circuit is used to generate the first reset signal, and only when the power supply is used for the first time. Reset the PME register when added to the register. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _page 24 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm)