TW497201B - Method for preventing latch-up of CMOS by extra doping in shallow trench isolation structure - Google Patents

Abstract

A method for preventing latch-up of CMOS by extra doping in a shallow trench isolation structure uses a doping in the well region to reduce the parasitic serial resistance, thereby effectively inhibiting the occurrence of latch-up in a CMOS circuit and improving the isolation border of the field region and the well region in the CMOS circuit. The method comprises: (i) using a photomask lithography technique and an etching technique to define an active region on a substrate; (ii) growing an oxidation layer; (iii) using the photoresist layer to form a mask layer on the p-well region, and implanting a first dopant in the n-well region of the un-masked layer; (iv) after removing the mask layer, using another photoresist layer to form a mask layer on the n-well region, and implanting a second dopant in the p-well region of the un-masked layer; and (v) filling up the shallow trench, and using a photomask lithography technique and an implantation technique to form a well region and adjusting the threshold voltage thereof, and separately forming a MOS transistor on the p-well region and the n-well region.

Description

V. Description of the invention (1) Preventable ί :::: Specifically related to a type of semiconductor element: -Species: Additional implanted impurities in the trench barrier structure to avoid gate oxygen; accumulated ϊKin :, micron process … Improving the importance of the circuit is important! At the same time, smaller insulation rules must be used because the size of the grains is reduced. The insulation specifications of the closed ϊ Γ, Ν: ίρ + will lead to the double cm in the ⑽s technology because there are two parasites in the switch transistor, but a parasitic bipolar transistor is not completely independent.隼 炻 ★! The base of the crystal and the other parasitic bipolar transistor will be another two "*. In other words, the base of each bipolar transistor is looped, and the collector of the triode transistor is driven to form a positive feedback. The thunderclap female circuit is the so-called pnpn diode element. The lowest power required when the current flow in the CMOS is 2 _ tnPnPn diodes in operation; closed =: the function of the road will be temporarily or permanently lost, that is to say, the above-mentioned blocking% Like '☆ Knowledge & Technology, many parties have come out. Among them, shallow trench isolation (STI) is a CMOS isolation technology in a 10-time micro-fabrication process. " With reference to Figure 1, the traditional shallow trench isolation process system includes the following steps: ⑴ As shown in Figure la, a layer of nitrogen is deposited on the Shixi substrate 10 :: Wide, sub-lithographic lithography Technology (ph〇t〇Hth〇graphy) and etching technology etc ing), define the active area, and form the trench 100

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V. Description of the invention (2) As shown in the figure, a thermal oxidation layer 11 0 ′ is formed on the inner side of the shallow trench as a lining layer using thermal oxidation technology; (iii) Please refer to FIG. 丨 c, followed by # 来Backfill the shallow trench 11 with oxide 120; (iv) Please refer to FIG. 1d, and then use the photolithography technology and implant technology to form the PMOS area 11 and the ρ well area in the η well area, respectively. And the critical voltage °; (ν) Please refer to the ie diagram to perform an additional field implant (fieid implant) 1 30 to prevent latch-up. Then, the conventional MOS transistor manufacturing process is used to facilitate the establishment of a transistor on the 1) well, and a pMOS transistor on the n well. The two are isolated by a field oxide layer and a channel barrier. Then, a “⑽ element” composed of NM〇s & pM0s is formed. Although the above process can complete the production of the circuit, and can prevent the latch-up phenomenon 'but', because the field implantation will spread laterally, so “to: = well The isolation margin of the area cannot be reduced, and the accumulation degree of the ⑽s circuit cannot be reduced. The upper resistance path is small, and the design rule of the collector makes it possible to provide a type of gold oxide. According to the closed loop path, bi-carriers are generated. In view of this, the double-carriers, which are born in the electric path, are used in semi-transistors to reduce the

It seems that a large current can flow between the VDD power line and the VSS ground line to flow through the circuit. The current gain of the shunt crystal increases with the design specification. Therefore, to shrink; it is necessary to reduce the parasitic series resistance from p well 30 (or n well 40) to pnp (or npn, rw), as shown in Figure 2, through which the current of the transistor flows into the substrate through the ground wire. In order to overcome the above-mentioned problems, the purpose of the present invention is to implant additional impurities in the isolation structure of the Yiqugou to avoid mutual interference; a method of making a lock uses implanting a hybrid series resistor in the well area. Therefore, the method of the present invention may have ;

Page 6 Description of the invention (3) Suppressing the occurrence of latch-up in CMOS circuits In addition, the method of the present invention can also improve the isolation margin of CD circuit and well area. In order to further explain the steps, architecture, and advantages of the present invention, the two buckles will be described with reference to the accompanying drawings. Among them: Figures 1a to 1b show the use of the conventional CMOS circuit system. Section view of a trench. Wang Yi Figure 2 is a top view of the conventional CMOS circuit. Figures 3a and 3g are diagrams illustrating the use of the invention in

2 A cross-sectional view of a manufacturing method in which a structure is additionally implanted with impurities to avoid latch-up of a complementary metal-oxide semiconductor transistor. Explanation of reference numerals Silicon substrates 10, 50, NM0S regions 12, 52 in the PM0S regions n, 51 in the n-well region, silicon nitride 20, 60, p-well region 30, n-well region 0, trench 1 〇, 200, lining layers 110, 21 (), oxides 120, 220, field implantation 130. Description of Examples

Please refer to FIG. 3a and FIG. 3b. The manufacturing method of the present invention includes the following steps. (1) First, as shown in FIG. 3a, a nitride is deposited on the substrate 5 0 = material 60, and a photomask is used. Lithography and etching technology define the active area and form a trench 20 0; (ii) Next, referring to Figure 3b, use the thermal oxidation method to grow an oxide layer with a thickness of about 350 Angstroms as the inner lining layer ( Lying 〇xide) 210; (iii) Then, as shown in FIG. 3c, a photolithography technique is used to form a pM〇s region 51 in the η well region by photoresist.

497201

A mask layer 70 is formed above; (iv) Please refer to FIG. 3d, and then use the implantation technique 'implant in the key region 52 in the predetermined p-well area not masked by the mask layer 70'; (v) As shown in FIG. 3e, after removing the mask layer 70, the mask lithography technology is used again to form another mask layer 72 on the NMOS region 52 in the p-well region that is scheduled to be formed; vi) Please refer to FIG. 3f. Using implantation technology, arsenic (or phosphorus) is implanted into the PMOS region 51 in the η-well region that is not formed by the mask layer; (vi 丨) As shown in FIG. 3g, The shallow trench is then filled with oxide 220. After that, the photolithography technique and the implantation technique are used to form a well area and adjust its critical voltage. Then, a MOS transistor is formed thereon. The method is the same as the conventional method, and the details of step (iii) and (iv) and steps (v) and (vi) described above will not be repeated here. In other words, arsenic (or phosphorus) can be implanted in the PMOS region 52 first, and then boron can be implanted in the NOMS region 51. 'In addition, in the above-mentioned step of implanting boron or arsenic, the implantation energy of the impurities is about 10 to 10 OKeV, the doping concentration is about 5E12 to 1E14 / cm2, and the implantation is forward. By using the method of the present invention described above, impurities implanted in the field region are dispersed and scattered, so the parasitic resistance can be effectively reduced. At the same time, since the implanted impurities & do not spread out, this also makes the isolation margin trapped in the well area or field area can be further reduced, so the degree of circuit integration can be improved.

Claims (1)

497201 VI. Application Patent Scope 1. A method for making additional implantation of impurities in a shallow trench isolation structure to avoid latch-up of complementary metal-oxide-semiconductor transistors, including the following steps: (i) First, using photolithography technology and Etching technology defines the active area on the substrate; (ii) Next, grow an oxide layer; (iii) Then, a photoresist layer is used to form a mask layer in the first well area, and then the mask layer is not masked by the mask layer. A first impurity is implanted in the second type well area; (iv) after removing the mask layer, another photoresist layer is used to form a mask layer in the second type well area, and the first type is not masked by the mask layer; A second impurity is implanted in the well area; and (v) the shallow deep trench is then filled. 2. The manufacturing method according to item 1 of the scope of patent application, wherein in the above step (i i), the oxide layer is grown by a thermal oxidation method. 3. The manufacturing method of item 1 in the scope of patent application, wherein the first type is p-type and the second type is n-type. 4. The manufacturing method according to item 1 of the scope of patent application, wherein the first type is an η type and the second type is a ρ type. 5. For the manufacturing method according to item 1 of the scope of patent application, wherein in the above step (ν), the shallow trench is filled with oxide. 6. The manufacturing method of item 1 in the scope of patent application, wherein in the steps (iii) and (i ν), the implantation energy of the first impurity and the second impurity is about 10 ~ 100 KeV, and the doping concentration thereof About 5E12 ~ 1E14 / cm2. 7. The manufacturing method according to item 3 of the scope of patent application, wherein the first impurity is a boron ion. Page 9 497201 6. Scope of patent application 8. For the method for making item 3 of the scope of patent application, the second impurity is arsenic ion or phosphorus ion. 9. The manufacturing method according to item 4 of the scope of patent application, wherein the first impurity is arsenic ion or phosphorus ion. 10. The manufacturing method according to item 4 of the scope of patent application, wherein the second impurity is boron ion. ί I Page 10