494553 7574twf.d〇c/006 A7 B7 五、發明說明（(） 本备明是有關於一種堆疊型晶片封裝結構及其製 程，且特別是有關於一種可以大幅降低封裝厚度之堆疊型 晶片封裝結構及其所對應之製程。 近年來，隨著電子技術的日新月異，高科技電子產 品也相繼問世，因而更人性化、功能性更佳之電子產品不 斷推陳佈新，然而各種產品無不朝向輕、薄、短、小的趨 勢設計，以提供更便利舒適的使用。因此，就半導體封裝 的領域而言，許多封裝的形式均是利用多晶片封裝的槪念 來設計其封裝架構，以縮減整體電路體積的大小，並提高 電性效能。 經濟部智慧財產局員工消費合作社印製 請參照第1圖，其繪示習知堆疊型封裝結構之剖面 示意圖。一封裝體100具有一第一晶片120、第二晶片130、 一基板140、多個導線160a、160b、多個焊球170、一封 裝材料150。其中，第一晶片120及第二晶片130分別具 有一主動表面122、132及對應之一晶片背面124、134， 而在弟一晶片120及第二晶片130之主動表面122、132 的表層分別具有多個焊墊126、136，位於主動表面122、 132週邊的位置，其中第一晶片120以其晶片背面124黏 合於第二晶片130之主動表面132的中間區域，並且第一 晶片120之水平截面積必須小於第二晶片130之水平截面 積。基板140具有一第一表面142及對應之一第二表面 ’在第一表面142上具有一晶片座146及多個打線接 點148a、148b，而在第二表面144具有多個焊球接點149， 其中打線接點148a、148b環繞於晶片座146的週邊區域， 3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494553 7574twf.doc/006 A7 B7 五 經濟部智慧財產局員工消費合作社印製 發明說明（>) 並且第二晶片130以其晶片背面134貼附於晶片座146上 另外，第一晶片120可以透過導線i60a使第〜晶片 ° 之焊墊126與基板140之打線接點148a電性連擒· j2Q _ 9 rfn 二晶片130可以透過導線160b使第二晶片130之恒叙％ 千愛13 與基板140之打線接點148b電性連接。封裝材料ι5〇 覆第一晶片120、第二晶片130及導線160a、16〇b，而& 球170焊合於第二表面144之焊球接點149上。 $ 在上述的構裝中，由於第一晶片120及第二晶片13〇 係堆疊於基板140之晶片座146上，此種封裝結構的厚ρ 甚厚，且封裝體100的散熱效率及電性品質並不佳。 因此本發明的目的之一就是在提供一種堆疊型晶# 封裝結構及其製程，可以降低封裝體之厚度。 本發明的目的之二就是在提供一種堆疊型晶片封裝 結構及其製程，可以提高晶片之散熱效率。 本發明的目的之三就是在提供一種堆疊型晶片封裝 結構及其製程，可以提高晶片之電性品質。 爲達成本發明之上述和其他目的，提出一種堆疊型 晶片封裝結構，其至少包括：一基板，具有一基板表面， 且該基板還具有一開洞、多個第一打線接點、多個第二打 線接點，第一打線接點及第二打線接點係位於基板表面 上，而開洞係貫穿基板。一第一晶片’具有一第一主動表 面及對應之一第一晶片背面，而第一晶片還具有多個第一 焊墊，位於第一主動表面上。一第二晶片，具有一第二主 -第二晶片背面’而第二晶片還具有多個 閱 背494553 7574twf.d〇c / 006 A7 B7 V. Description of the Invention (() This note relates to a stacked chip packaging structure and its manufacturing process, and in particular to a stacked chip packaging structure that can significantly reduce package thickness. And its corresponding process. In recent years, with the rapid development of electronic technology, high-tech electronic products have also come out one after another. As a result, more humane and more functional electronic products have been introduced. Thin, short, and small trend design to provide more convenient and comfortable use. Therefore, in the field of semiconductor packaging, many packaging forms are designed using multi-chip packaging concepts to reduce the overall circuit The size of the volume and improve the electrical performance. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to Figure 1, which shows a schematic cross-sectional view of a conventional stacked package structure. A package 100 has a first chip 120, The second wafer 130, a substrate 140, a plurality of wires 160a, 160b, a plurality of solder balls 170, and a packaging material 150. Among them, the first wafer 12 0 and the second wafer 130 have an active surface 122, 132 and a corresponding one of the wafer back surfaces 124, 134, respectively, and a surface of the active surface 122, 132 of the first wafer 120 and the second wafer 130 has a plurality of bonding pads 126, respectively. And 136 are located around the active surfaces 122 and 132, where the first wafer 120 is adhered to the middle area of the active surface 132 of the second wafer 130 by its back surface 124, and the horizontal cross-sectional area of the first wafer 120 must be smaller than the second The horizontal cross-sectional area of the wafer 130. The substrate 140 has a first surface 142 and a corresponding second surface. The wafer 140 has a wafer holder 146 and a plurality of wire bonding contacts 148a and 148b on the first surface 142, and a second surface 144. There are multiple solder ball contacts 149, of which wire bonding contacts 148a, 148b surround the peripheral area of the wafer holder 146, 3 paper sizes are applicable to China National Standard (CNS) A4 (210 X 297 mm) 494553 7574twf.doc / 006 A7 B7 Printed the invention description by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and the second wafer 130 is attached to the wafer holder 146 with its wafer back 134. In addition, the first wafer 120 can pass through the wire i 60a electrically connects the bonding pad 126 of the first wafer to the wiring contact 148a of the substrate 140. j2Q _ 9 rfn The second wafer 130 can make the second wafer 130 constant through the wire 160b. The wire contacts 148b are electrically connected. The packaging material ι50 covers the first chip 120, the second chip 130, and the wires 160a and 160b, and the & ball 170 is bonded to the solder ball contact 149 on the second surface 144. In the above configuration, since the first wafer 120 and the second wafer 130 are stacked on the wafer holder 146 of the substrate 140, the thickness of this packaging structure is very thick, and the heat dissipation efficiency and electrical properties of the package 100 The quality is not good. Therefore, one of the objectives of the present invention is to provide a stacked crystal package structure and its manufacturing process, which can reduce the thickness of the package body. Another object of the present invention is to provide a stacked chip package structure and a manufacturing process thereof, which can improve the heat dissipation efficiency of the chip. A third object of the present invention is to provide a stacked chip packaging structure and a manufacturing process thereof, which can improve the electrical quality of the chip. In order to achieve the above and other objectives of the present invention, a stacked wafer package structure is proposed, which includes at least: a substrate having a substrate surface, and the substrate also has an opening, a plurality of first wiring contacts, a plurality of first The two wire contacts, the first wire contact and the second wire contact are located on the surface of the substrate, and the openings penetrate the substrate. A first wafer 'has a first active surface and a corresponding back surface of the first wafer, and the first wafer also has a plurality of first pads on the first active surface. A second wafer has a second main-second wafer back 'and the second wafer also has a plurality of read backs.
訂 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494553 7574twf . doc/ 006 A7 B7 五、發明說明（>) 第二焊墊，位於第二主動表面上，第二晶片位於開洞中， 且第一晶片以其第一晶片背面貼附於第二晶片之第二主動 表面上。多個第一導線，第一導線之一端與第一焊墊電性 連接，而第一導線之另一端與第一打線接點電性連接。多 個第二導線，第二導線之一端與第二焊墊電性連接，而第 二導線之另一端與第二打線接點電性連接。以及一封裝材 料，該封裝材料包覆第一晶片、第二晶片、第一導線、第 二導線及基板表面。依照本發明的一較佳實施例，其中堆 疊型晶片封裝結構，還包括多個焊球，且基板還具有一基 板背面，基板背面與基板表面係位於基板相對應之兩面’ 而基板還具有多個焊球接點，位於基板背面上，且焊球分 別位於焊球接點上。另外，第二晶片可以是突出於基板背 面所形成之平面，或者第二晶片背面與基板背面亦可以是 共平面。此外，第一晶片係以其第一晶片背面貼附於第二 晶片之第二主動表面的中間區域。 爲達成本發明之上述和其他目的，提出一種堆疊型 晶片封裝結構，其至少包括：一基板’具有一基板表面’ 且基板還具有一開洞、多個打線接點，打線接點係位於基 板表面上，而開洞係貫穿該基板。一第一晶片，具有一第 一主動表面及對應之一第一晶片背面，而第一晶片還具有 多個第一焊墊，位於第一主動表面上。一第二晶片’具有 一第二主動表面及對應之一第二晶片背面，而第二晶片還 具有多個第二焊墊，位於第二主動表面上，第二晶片位於 開洞中，且第一晶片以其第一晶片背面貼附於第二晶片之 5 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) -----------裝--- (請先閲讀背面之注意事'寫本頁) . 線」 經濟部智慧財產局員工消費合作社印製 494553 7574twf.d〇c/006 A7 _ B7 五、發明說明（+) 第二晶片背面上。多個導線，導線之一端與該些第一焊墊 電性連接，而導線之另一端與打線接點電性連接。以及一 封裝材料，封裝材料包覆第一晶片、第二晶片、導線及基 板表面。依照本發明的一較佳實施例，其中堆疊型晶片封 裝結構，還包括多個凸塊，凸塊分別位於第二焊墊上。而 堆疊型晶片封裝結構，還包括多個焊球，且基板還具有一 基板背面’基板背面與基板表面係位於基板相對應之兩 面，而基板還具有多個焊球接點，位於基板背面上，焊球 分別位於焊球接點上。此外，第二晶片可以是突出於基板 背面所形成之平面，或者第二晶片之第二主動表面與基板 背面亦可以爲共平面的形式。另外，第一晶片係以其第一 晶片背面貼附於第二晶片之第二晶片背面的中間區域。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式’作 詳細說明如下： 圖式之簡單說明： 第1圖繪示習知堆疊型封裝結構之剖面示意®1 ° 第2圖至第4圖繪示依照本發明第一較隹實施例之 一種堆疊型晶片封裝結構製程之剖面示意圖。 第5圖繪示依照本發明第二較佳實施例之一種堆疊 型晶片封裝結構之剖面示意圖。 第6圖繪示依照本發明第三較佳實施例之種堆疊 型晶片封裝結構之剖面示意圖。 第7圖繪示依照本發明第四較佳實施例之一種堆疊 6 ________〆------ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項寫本頁) 裝 . 經濟部智慧財產局員工消費合作社印製 494553 7574twf.d〇c/006 A7 __B7_ 五、發明說明（f ) 型晶片封裝結構之剖面示意圖。 第8圖繪示依照本發明第五較佳實施例之一種堆疊 型晶片封裝結構之剖面示意圖。 第9圖繪示依照本發明第六較佳實施例之一種堆疊 型晶片封裝結構之剖面示意圖。 圖式之標示說明： 100、200、300、400、500、600、700 :封裝體 210 :載座 212 :載座表面 214 ·•開口 216 :鍍金區 218 :基板置方區 610、710 :晶片 120、220、320 :第一晶片 222、712 :第一主動表面 224、324 :第一晶片背面 226、326、716 :第一焊墊 122、132 :主動表面 經濟部智慧財產局員工消費合作社印製 ------------裝--- (請先閱讀背面之注意事項 寫本頁) 124、134 :晶片背面 126、136 :焊墊 130、230、330、430、530 :第二晶片 232、332、532、714 :第二主動表面 234、334、434 :第二晶片背面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494553 7574twf.doc/006 A7 _B7_ 五、發明說明（士） 236、336、718 :第二焊墊 140、250、350、650 :基板 252 :基板表面 (請先閱讀背面之注意事填寫本頁) 254、354、454、554 :基板背面 256 :開洞 258 :第一打線接點 260 :第二打線接點 142 :第一表面 144 :第二表面 146 :晶片座 148a、148b、358、758 :打線接點 149、 262、362 :焊球接點 394、794 ··凸塊 240、242 :耐熱性膠帶 160a、160b、372、670、770 :導線 272 :第一導線 270 :第二導線 170、292、392 :焊球 經濟部智慧財產局員工消費合作社印製 150、 290、390 :封裝材料 280 :模具 282 :凹穴 實施例 請參照第2圖至第4圖，其繪示依照本發明第一較 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 494553 7574twf-doc/006 A7 B7 五、發明說明（η) 一 佳實施例之一種堆疊型晶片封裝結構製程之剖面示意圖。 首先提供一載座210，載座210具有一載座表面212 ’而 在載座表面212上具有一開口 214、一鍍金區216、一基 板置放區218,其中鍍金區216係環繞於開口 214的邊緣， 而基板置放區218係位於鍍金區216的外側邊緣。然後還 要提供一第一晶片220、一第二晶片230,第一晶片具有 一第一主動表面222及對應之一第一晶片背面224 ’而第 一晶片220還具有多個第一焊墊226 ’位於第一主動表面 222上的邊緣區域；而第二晶片230，具有一第二主動表 面232及對應之一第二晶片背面234，而第二晶片230還 具有多個第二焊墊236，位於第二主動表面232上的邊緣 區域。還要提供一基板250，基板250具有一基板表面252 及對應之一基板背面254,且基板還具有一開洞256、多 個第一打線接點258、多個第二打線接點260及多個焊球 接點262，其中第一打線接點258及第二打線接點260係 位於開洞256週邊區域之基板表面252上，而開洞256貫 穿基板250。 接下來，敘述堆疊型晶片封裝結構之製作程序’首 先透過耐熱性膠帶240，將第二晶片230以其第二晶片背 面234貼附於載座210之開口 214內；並且透過耐熱性膠 帶242，將基板250以其基板背面254貼附於載座210之 基板置放區218。然後進行一打線製程，製作多個第二導 線270，使得第二晶片230之第二焊墊236與基板250之 第二打線接點260電性連接。接下來，再透過黏合的製程’ 9 (請先閱讀背面之注意事填寫本頁) 裝 訂·· 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494553 7574twf . doc/ΟΟι Α7 Β7 五、發明說明（左） 將第一晶片220以其第一晶片背面224貼附於第二晶片23〇 之第二主動表面232的中間區域。然後再進行一打線製程， 製作多個第一導線272，使得第一晶片220之第一焊塾226 與基板250之第一打線接點258電性連接。 請參照第3圖，然後進行一封膠之製程，利用一模 具280壓在基板250的邊緣上，而模具280具有〜凹穴 282,可以容納第一晶片22〇、第二晶片23〇、第一導線272 及第二導線270，並且將模具280壓住基板250的邊緣。 接下來，便將一封裝材料290灌入於凹穴282中，使得封 裝材料290包覆第一晶片220、第二晶片230、第〜導線 272、第二導線270。然後再進行冷卻、脫模、剝離載座之 步驟，由於封裝材料290與載座210之鍍金區216接觸， 而金與封裝材料290間的接合性甚差，因此封裝材料290 與載座210間是容易相互拔離的。 請參照第4圖，最後再進行一植球的步驟，透過迴 焊的製程，可以將多個焊球292與基板250之焊球接點262 焊合，便完成一封裝體200的製作。如此之封裝體200， 第二晶片230是突出於基板背面254所形成之平面。 在上述的結構中，由於封裝體200的厚度會趨近於 第〜晶片220與第二晶片230堆疊後的加總厚度，如此封 裝體200的厚度可以變得甚薄。另外，當封裝體200焊合 於一印刷電路基板（未繪示）上時，第二晶片230可以其第 二晶片背面234直接與印刷電路基板導熱性連接，故可以 大幅增加第二晶片230之散熱效率。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --裝--- (請先閱讀背面之注意事寫本頁) . 線」 經濟部智慧財產局員工消費合作社印製 494553 7574twf.doc/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（i) 然ifc本發明的應用，並非侷限於上述的方式，亦可 以如第5圖所示，其繪示依照本發明第二較佳實施例之一 種堆疊型晶片封裝結構之剖面示意圖。其中，第二晶片330 亦可以是類似覆晶的形式，其製作方式乃是先藉由耐熱貼 帶（未繪示），將第二晶片330以其第二主動表面332貼附 於載座（未繪示）的開口（未繪示）內。然後藉由耐熱貼帶（未 繪示），將基板350以其基板背面354貼附於載座之基板 置放區（未繪示）。另外，再進行一貼附的製程，將第一晶 片320以其第一晶片背面324貼附於第二晶片330之第二 晶片背面334上。接下來，進行一打線製成，透過一導線 372，使得第一晶片320之第一焊墊326與基板350之打 線接點358電性連接。然後再進行一封裝製程，一封裝材 料390包覆第一晶片320、第二晶片330及導線372。接 下來，進行一製作凸塊之製程，可以製作多個凸塊394於 第二晶片330之第二焊墊336上。最後再進行一植球的步 驟，透過迴焊（reflow)的製程，可以將多個焊球392與基 板350之焊球接點362焊合，便完成一封裝體300的製作。 如此之封裝體300，第二晶片330是突出於基板背面354 所形成之平面。 在上述的結構中，由於第二晶片330係透過多個凸 塊394與印刷電路基板（未繪示）進行電性連接，如此第二 晶片330與印刷電路基板間的電性路徑會縮短，故可以降 低訊號衰減與延遲的發生機率，而提高電性品質。 在上述的第一較佳實施例與第二較佳實施例中’其 (請先閱讀背面之注意事項科填寫本頁) :裝 . -丨線』 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494553 經濟部智慧財產局員工消費合作社印製 7574twf.doc/006 A7 B7 五、發明說明（~) 第二晶片均是突出於基板背面所形成之平面，然而本發明 的應用並非侷限於上述的方式，亦可以是如第6圖、第7 圖所示，其中第6圖繪示依照本發明第三較佳實施例之一 種堆疊型晶片封裝結構之剖面示意圖，而第7圖繪示依照 本發明第四較佳實施例之一種堆疊型晶片封裝結構之剖面 示意圖。請先參見第6圖，第二晶片430之第二晶片背面 434與基板背面454亦可以是共平面的形式，因而當封裝 體400在與印刷電路基板（未繪示）焊合前，亦可以先製作 至少一導熱性墊片（未繪示）於印刷電路板上對應於第二晶 片的區域；當封裝體400在與印刷電路基板焊合後，第二 晶片430會與導熱性墊片碰觸，如此第二晶片430的熱便 可以藉由導熱性墊片而加速傳導出去。而在製作上，其大 致與第一較佳實施例雷同，只是載座（未繪示）在對應於晶 片放置的區域並不具有開口，亦即晶片放置區與基板置放 區係爲同平面的配置，如此封裝體400在製作完成之後， 第二晶片背面434與基板背面454會形成共平面的形式。 請參見第7圖，第二晶片530之第二主動表面532 與基板背面554亦可以是共平面的形式。而在製作上，其 大致與第一較佳實施例雷同，只是載座（未繪示）在對應於 晶片放置的區域並不具有開口 ’亦即晶片放置區與基板置 放區係爲同平面的配置，如此封裝體5〇〇在製作完成之後， 桌一主動表面532與基板背面554會形成共平面的形式。 在上述的實施例中，封裝體係具有多個晶片，然而 本發明並非侷限於上述的方式，亦即封裝體亦可僅具有單 --------------裝--- (睛先閱讀背面之注意事項寫本頁) · i線. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 494553 7574twf.doc/〇〇6 A7 B7 五 經濟部智慧財產局員工消費合作社印製 發明說明（（ρ 一晶片，如第8圖、第9圖所示，其中第8圖繪示依照本 發明第五較佳實施例之一種堆疊型晶片封裝結構之剖面示 意圖，而第9圖繪示依照本發明第六較佳實施例之一種堆 疊型晶片封裝結構之剖面示意圖。請先參照第8圖’封裝 體600僅具有一晶片610，而透過多個導線670分別與基 板650電性連接，並且晶片610可以直接與印刷電路基板 (未繪示）導熱性連接，以加速晶片610的散熱。 請參照第9圖，封裝體700僅具有一晶片710 ’而 晶片710具有一第一主動表面712及一第二主動表面714， 在晶片710還具有多個第一焊墊716及多個第二焊墊718 ’ 其中第一焊墊716位於第一主動表面712上對應於晶片710 邊緣的區域，而第二焊墊718位於第二主動表面714上。 另外，透過多個導線770，第一焊墊716可以與基板750 之打線接點758電性連接，並且在晶片710之第二焊墊718 上還可以製作多個凸塊，透過凸塊794可以使晶片710直 接與印刷電路基板（未繪示）電性連接。 綜上所述，本發明至少具有下列優點： 1·本發明之堆疊型晶片封裝結構及其製程，由於封 裝體的厚度會趨近於第一晶片與第二晶片堆疊後的加總厚 度，如此形式之封裝體厚度可以變得甚薄。 2.本發明之堆疊型晶片封裝結構及其製程，當封裝 體焊合於一印刷電路基板上時，第二晶片可藉由其第二晶 片背面直接與印刷電路基板導熱性連接，故可以大幅增加 第二晶片之散熱效率。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公釐） 494553 7574twf.d〇c/006 A7 _B7 五、發明說明（丨1) 3.本發明之堆疊型晶片封裝結構及其製程，由於第 二晶片係透過多個凸塊與印刷電路基板進行電性連接，如 此第二晶片與印刷電路基板間的電性路徑會縮短，故可以 降低訊號衰減與延遲的發生機率，而提高電性品質。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。The size of the paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 494553 7574twf.doc / 006 A7 B7 V. Description of the invention (>) The second pad is located on the second active surface. The wafer is located in the opening, and the first wafer is attached to the second active surface of the second wafer with the back of the first wafer. A plurality of first wires, one end of the first wire is electrically connected to the first bonding pad, and the other end of the first wire is electrically connected to the first wire-bonding contact. A plurality of second wires, one end of the second wire is electrically connected to the second solder pad, and the other end of the second wire is electrically connected to the second wire bonding point. And a packaging material covering the first chip, the second chip, the first lead, the second lead and the surface of the substrate. According to a preferred embodiment of the present invention, the stacked chip package structure further includes a plurality of solder balls, and the substrate also has a substrate back, and the substrate back and the substrate surface are located on two sides corresponding to the substrate. Each solder ball contact is located on the back of the substrate, and the solder balls are respectively located on the solder ball contacts. In addition, the second wafer may be a plane formed by protruding from the back surface of the substrate, or the back surface of the second wafer and the back surface of the substrate may be coplanar. In addition, the first wafer is attached to the middle region of the second active surface of the second wafer with the back of the first wafer. In order to achieve the above and other objects of the present invention, a stacked chip package structure is proposed, which includes at least: a substrate 'having a substrate surface', and the substrate also having an opening, a plurality of wire bonding contacts, and the wire bonding contacts are located on the substrate On the surface, the openings penetrate the substrate. A first wafer has a first active surface and a corresponding back surface of the first wafer, and the first wafer also has a plurality of first pads on the first active surface. A second wafer 'has a second active surface and a corresponding back surface of a second wafer, and the second wafer also has a plurality of second pads on the second active surface, the second wafer is located in the opening, and One wafer is attached to the second wafer with the back of the first wafer. The size of this paper is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm). (Please read the note on the back first, write this page). LINE "Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494553 7574twf.d〇c / 006 A7 _ B7 V. Description of the invention (+) On the back of the second chip. For a plurality of wires, one end of the wire is electrically connected to the first solder pads, and the other end of the wire is electrically connected to the wire contact. And a packaging material covering the surface of the first chip, the second chip, the wires and the substrate. According to a preferred embodiment of the present invention, the stacked wafer package structure further includes a plurality of bumps, and the bumps are respectively located on the second bonding pads. The stacked chip package structure also includes a plurality of solder balls, and the substrate also has a substrate back. The substrate back and the substrate surface are located on two sides corresponding to the substrate, and the substrate also has a plurality of solder ball contacts on the substrate back. The solder balls are located on the solder ball contacts. In addition, the second wafer may be a plane formed protruding from the back surface of the substrate, or the second active surface of the second wafer and the back surface of the substrate may be in the form of a coplanar surface. In addition, the first wafer is attached to the middle region of the second wafer with the back of the first wafer on the back of the second wafer. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings' as follows: Brief description of the drawings: Figure 1 Schematic cross-section diagrams of a conventional stacked package structure 1 ° Figures 2 to 4 illustrate schematic cross-section diagrams of a stacked wafer package structure manufacturing process according to the first comparative embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of a stacked chip package structure according to a second preferred embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a stacked chip package structure according to a third preferred embodiment of the present invention. Figure 7 shows a stack 6 according to the fourth preferred embodiment of the present invention. ________ 〆 This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read first Note on the reverse side of this page) Packaging. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 494553 7574twf.d0c / 006 A7 __B7_ V. Schematic cross-section diagram of the (f) type chip package structure. FIG. 8 is a schematic cross-sectional view of a stacked chip package structure according to a fifth preferred embodiment of the present invention. FIG. 9 is a schematic cross-sectional view of a stacked chip package structure according to a sixth preferred embodiment of the present invention. Description of the drawings: 100, 200, 300, 400, 500, 600, 700: package body 210: carrier 212: carrier surface 214 · opening 216: gold plated area 218: substrate square area 610, 710: wafer 120, 220, 320: the first wafer 222, 712: the first active surface 224, 324: the back of the first wafer 226, 326, 716: the first pad 122, 132: the active surface of the Intellectual Property Bureau of the Ministry of Economy System ------------ Install --- (Please read the precautions on the back to write this page) 124, 134: The back of the chip 126, 136: Pads 130, 230, 330, 430, 530 : The second wafer 232, 332, 532, 714: The second active surface 234, 334, 434: The back of the second wafer The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494553 7574twf.doc / 006 A7 _B7_ V. Description of the Invention (Shi) 236, 336, 718: Second pad 140, 250, 350, 650: Substrate 252: Surface of the substrate (please read the notes on the back first and fill in this page) 254, 354, 454 554: Back of substrate 256: Hole 258: First wire contact 260: Second wire contact 142: First surface 144: Second surface 146: Wafer Seats 148a, 148b, 358, 758: Wire contacts 149, 262, 362: Solder ball contacts 394, 794 ... Bumps 240, 242: Heat-resistant tapes 160a, 160b, 372, 670, 770: Leads 272: No. One wire 270: Second wire 170, 292, 392: Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 150, 290, 390: Packaging material 280: Mold 282: Cavities For examples, please refer to Figures 2 to 4 Figure showing the application of the Chinese National Standard (CNS) A4 specification (210 X 297 mm) according to the first paper size of the present invention. Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 494553 7574twf-doc / 006 A7 B7 V. Description of the Invention (η) A cross-sectional view of a manufacturing process of a stacked chip package structure according to a preferred embodiment. First, a carrier 210 is provided. The carrier 210 has a carrier surface 212 ′ and an opening 214, a gold-plated area 216, and a substrate placement area 218 on the carrier surface 212. The gold-plated area 216 surrounds the opening 214. The substrate placement area 218 is located on the outer edge of the gold-plated area 216. A first wafer 220 and a second wafer 230 are then provided. The first wafer has a first active surface 222 and a corresponding one of the first wafer back surfaces 224 ′. The first wafer 220 also has a plurality of first pads 226. 'The edge region is located on the first active surface 222; and the second wafer 230 has a second active surface 232 and a corresponding second wafer back surface 234, and the second wafer 230 also has a plurality of second pads 236, An edge region on the second active surface 232. A substrate 250 is also provided. The substrate 250 has a substrate surface 252 and a corresponding substrate back surface 254, and the substrate also has an opening 256, a plurality of first wiring contacts 258, a plurality of second wiring contacts 260, and more. Of the solder ball contacts 262, the first wire contact 258 and the second wire contact 260 are located on the substrate surface 252 around the opening 256, and the opening 256 runs through the substrate 250. Next, the manufacturing process of the stacked chip package structure is described. First, the second wafer 230 is attached to the opening 214 of the carrier 210 with the second wafer backside 234 through the heat-resistant tape 240, and the heat-resistant tape 242 is passed through. The substrate 250 is attached to the substrate placement area 218 of the carrier 210 with the substrate back surface 254. Then, a wire bonding process is performed to make a plurality of second wires 270, so that the second bonding pads 236 of the second chip 230 and the second wire bonding contacts 260 of the substrate 250 are electrically connected. Next, through the gluing process' 9 (Please read the notes on the back to fill in this page) Binding ·· This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 494553 7574twf. Doc / ΟΟι A7 B7 V. Description of the invention (left) The first wafer 220 is attached to the middle area of the second active surface 232 of the second wafer 23 with the first wafer back surface 224 thereof. Then, a wire bonding process is performed to make a plurality of first wires 272, so that the first solder pad 226 of the first chip 220 and the first wire bonding contact 258 of the substrate 250 are electrically connected. Please refer to FIG. 3, and then perform a glue process, using a mold 280 to press on the edge of the substrate 250, and the mold 280 has a ~ cavity 282, which can accommodate the first wafer 22o, the second wafer 23o, the first A wire 272 and a second wire 270 press the mold 280 against the edge of the substrate 250. Next, a potting material 290 is poured into the cavity 282, so that the potting material 290 covers the first chip 220, the second chip 230, the first to second conductive wires 272, and the second conductive wire 270. Then, the steps of cooling, demolding and peeling the carrier are performed. Since the encapsulating material 290 is in contact with the gold-plated area 216 of the carrier 210, and the adhesion between the gold and the encapsulating material 290 is poor, the encapsulating material 290 and the carrier 210 are poor It is easy to detach from each other. Please refer to FIG. 4, and finally perform a ball implantation step. Through the process of re-soldering, a plurality of solder balls 292 and the solder ball contacts 262 of the substrate 250 can be welded to complete the production of a package 200. In such a package 200, the second chip 230 is a plane formed by protruding from the substrate back surface 254. In the above-mentioned structure, since the thickness of the package body 200 approaches the combined thickness of the first to second wafers 220 and 230 after being stacked, the thickness of the package body 200 can be made so thin. In addition, when the package 200 is soldered to a printed circuit board (not shown), the second chip 230 can be directly thermally connected to the printed circuit board by the second wafer back surface 234, so the second chip 230 can be greatly increased. Thermal efficiency. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) --- --- (Please read the notes on the back and write this page). 494553 7574twf.doc / 006 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (i) Of course, the application of the present invention is not limited to the above-mentioned method, but it can also be shown in Figure 5, which shows A schematic cross-sectional view of a stacked chip package structure according to a second preferred embodiment of the present invention. The second chip 330 may also be a flip-chip-like form. The manufacturing method is to first attach the second chip 330 to the carrier with its second active surface 332 through a heat-resistant tape (not shown) ( (Not shown) inside the opening (not shown). Then, the substrate 350 is attached to the substrate placement area (not shown) of the carrier with the substrate back surface 354 through a heat-resistant adhesive tape (not shown). In addition, an attaching process is performed to attach the first wafer 320 with the first wafer back surface 324 to the second wafer back surface 334 of the second wafer 330. Next, a wire is made. Through a wire 372, the first pad 326 of the first chip 320 is electrically connected to the wire contact 358 of the substrate 350. Then, a packaging process is performed, and a packaging material 390 covers the first wafer 320, the second wafer 330, and the wires 372. Next, a bump manufacturing process is performed, and a plurality of bumps 394 can be manufactured on the second pads 336 of the second wafer 330. Finally, a ball implantation step is performed. Through a reflow process, a plurality of solder balls 392 and the solder ball contacts 362 of the base plate 350 can be welded to complete the production of a package 300. In such a package 300, the second wafer 330 is a plane formed by protruding from the substrate back surface 354. In the above structure, since the second chip 330 is electrically connected to the printed circuit board (not shown) through the plurality of bumps 394, the electrical path between the second chip 330 and the printed circuit board is shortened, so Can reduce the probability of signal attenuation and delay, and improve electrical quality. In the first preferred embodiment and the second preferred embodiment described above, (these (please read the Caution Section on the back to fill out this page first): installed.-丨 "This paper size applies to China National Standard (CNS) A4 Specifications (210 X 297 mm) 494553 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7574twf.doc / 006 A7 B7 V. INTRODUCTION TO THE INVENTION (~) The second wafer is a plane formed protruding from the back of the substrate, but the present invention The application is not limited to the above manner, and may also be as shown in FIG. 6 and FIG. 7, where FIG. 6 is a schematic cross-sectional view of a stacked chip package structure according to a third preferred embodiment of the present invention, and FIG. 7 is a schematic cross-sectional view of a stacked chip package structure according to a fourth preferred embodiment of the present invention. Please refer to FIG. 6 first. The second wafer back surface 434 and the substrate back surface 454 of the second wafer 430 may also be in a coplanar form. Therefore, before the package 400 is welded to a printed circuit board (not shown), it may be used. First, at least one thermally conductive pad (not shown) is made on an area of the printed circuit board corresponding to the second chip; when the package 400 is welded to the printed circuit board, the second chip 430 will collide with the thermally conductive pad. In this way, the heat of the second wafer 430 can be conducted out through the heat conductive pad. In manufacturing, it is substantially the same as the first preferred embodiment, except that the carrier (not shown) does not have an opening in the area corresponding to the wafer placement, that is, the wafer placement area and the substrate placement area are in the same plane. In this way, after the package 400 is manufactured, the second wafer back surface 434 and the substrate back surface 454 will form a coplanar form. Referring to FIG. 7, the second active surface 532 and the substrate back surface 554 of the second wafer 530 may also be in the form of coplanarity. In terms of production, it is substantially the same as the first preferred embodiment, except that the carrier (not shown) does not have an opening in the area corresponding to the wafer placement. That is, the wafer placement area and the substrate placement area are in the same plane. After the fabrication of the package 500, the active surface 532 of the table 1 and the back surface 554 of the substrate will form a coplanar form. In the above embodiment, the packaging system has a plurality of wafers, but the present invention is not limited to the above-mentioned manner, that is, the package body may only have a single -------------- package-- -(Please read the notes on the back first to write this page) · i-line. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 494553 7574twf.doc / 〇〇6 A7 B7 Property Bureau employee consumer cooperative printed invention description ((ρ a chip, as shown in Figure 8 and Figure 9, where Figure 8 shows a cross-section of a stacked chip package structure according to the fifth preferred embodiment of the present invention) FIG. 9 is a schematic cross-sectional view of a stacked chip package structure according to a sixth preferred embodiment of the present invention. Please refer to FIG. 8 first. The package 600 has only one chip 610 and passes through a plurality of wires 670. They are electrically connected to the substrate 650 respectively, and the chip 610 can be directly thermally connected to a printed circuit board (not shown) to accelerate the heat dissipation of the chip 610. Please refer to FIG. 9, the package 700 has only one chip 710 'and the chip 710 has a first active surface 712 and The second active surface 714 further includes a plurality of first pads 716 and a plurality of second pads 718 ′ on the wafer 710. The first pads 716 are located on the first active surface 712 at a region corresponding to the edge of the wafer 710. The two solder pads 718 are located on the second active surface 714. In addition, the first solder pads 716 can be electrically connected to the bonding contacts 758 of the substrate 750 through a plurality of wires 770, and are also provided on the second solder pads 718 of the chip 710. Multiple bumps can be made, and the wafer 710 can be electrically connected directly to the printed circuit board (not shown) through the bump 794. In summary, the present invention has at least the following advantages: 1. The stacked chip package of the present invention Because of the structure and manufacturing process, the thickness of the package body will approach the combined thickness of the first chip and the second chip after being stacked, so that the thickness of the package body in this form can become very thin. 2. The stacked chip package structure of the present invention And its manufacturing process, when the package is welded on a printed circuit board, the second chip can be directly thermally connected to the printed circuit board through the back of the second chip, so the heat dissipation efficiency of the second chip can be greatly increased. This paper size applies the Chinese National Standard (CNS) A4 specification (21〇X 297 mm) 494553 7574twf.d〇c / 006 A7 _B7 V. Description of the invention (丨 1) 3. The stacked chip package structure of the present invention and its structure In the manufacturing process, since the second chip is electrically connected to the printed circuit board through a plurality of bumps, the electrical path between the second chip and the printed circuit board will be shortened, so the probability of signal attenuation and delay can be reduced, and the increase Electrical quality. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.
(請先閱讀背面之注意事S --裝--- 寫本頁} 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）(Please read the note S on the back first-install --- write this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)