TW488064B - Nonvolatile semiconductor device and manufacturing method, nonvolatile semiconductor memory device and manufacturing method, and semiconductor memory device mixed with nonvolatile and volatile semiconductor memory devices and manufacturing method - Google Patents

Nonvolatile semiconductor device and manufacturing method, nonvolatile semiconductor memory device and manufacturing method, and semiconductor memory device mixed with nonvolatile and volatile semiconductor memory devices and manufacturing method Download PDF

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TW488064B
TW488064B TW089103918A TW89103918A TW488064B TW 488064 B TW488064 B TW 488064B TW 089103918 A TW089103918 A TW 089103918A TW 89103918 A TW89103918 A TW 89103918A TW 488064 B TW488064 B TW 488064B
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Taiwan
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insulating film
gate electrode
semiconductor memory
memory device
charge accumulation
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TW089103918A
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Chinese (zh)
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Kuniyoshi Yoshikawa
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present invention provides a nonvolatile semiconductor device and its manufacturing method, nonvolatile semiconductor memory device and its manufacturing method, and semiconductor memory device mixed and loaded with nonvolatile semiconductor memory device and volatile semiconductor memory device and its manufacturing method. There is disclosed a new structure with regard to a nonvolatile semiconductor memory which can store therein an information corresponding to a plurality of bits. The nonvolatile semiconductor memory according to the present invention has a charge trapping layer 4 for accumulating electrons in an end of a gate electrode. In the nonvolatile semiconductor memory according to the present invention, the electrons are stored in this charge trapping layer 4 to thereby store the information corresponding to the plurality of bits.

Description

4^8064 Α7 Β7 五、發明說明（i ) 本發明係有關非揮發性半導體 裝置及其製造方法， 非揮發性半導體記憶裝置及其製造方法，以及將非揮發性 半導體記憶裝置和揮發性半導體記憶裝置的半導體記憶裝 置混合載入於同一晶片上之半導體記億裝置及其製造方法 者。 以往之E E P R〇Μ等之不揮發性記憶體中，經由於 1個格實現2個臨限値，於1個格，記億1位元分之資訊 。對此因爲記億體高密度化，於1個格具有4個以上之臨 限値，提案將2位元分以上之資訊，記憶於1個格之技術 (M.Bauer et al·，ISSCC95，ρ·132 )。惟，爲實現此技術 時，需要臨限値電壓之正確控制，臨限値電壓之小變化分 化正確檢知，更且更較以往之電荷保持的可靠性。因此， 此技術中，實際上不一定可得以往同等性能者。又，此技 術係有製造產率低的問題。爲此，新提案將電荷物理性蓄 積於不同複數位置，記憶複數位元分資訊的格構造。（B. Etan et al.，IEDM96，P169 ，圖6 )。又，於此做爲類似之 格構造，以前由本發明人於閘極電極之側壁，提案有設置 電荷蓄積層的構造（美國專利號碼4881 108號）。 但是，此等格構造之製造工程係非常複雜，且通道範圍之 控制性亦有不充分之問題。 另一方面，對於將由近來之系統嵌入晶片之要求的可 電氣性消除之非揮發性記憶體和可高速寫入讀取的揮發性 記憶體，實現於同一晶片上之需求亦提高。尤其，對於混 合載入E E P R〇Μ或快閃記億體等之浮閘構造的非揮發 本紙張尺度適用中國國家標準<CNS)A4規格<210 x 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- §· -4 - 488064 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（2) 性記憶體和可高速動作之動態R A Μ的V L S I的要求亦 急遽增加。然而，近年之動態R A Μ之記憶格係呈溝渠構 造或堆疊構造之非常複雜的3次元構造。爲此，欲混合載 入浮閘型非揮發性記憶體和動態R A Μ時，自該記憶格構 造之不同，製造步驟則複雜化，光罩工程數亦會增加。因 此，該混載晶片之製造成本會成爲很大。 使用浮閘型之非揮發性記憶體實現動態R A Μ之記憶 格時，經由格構造之共通化，製造步驟係被單純化，可減 一 低製造成本。但是，該共通化之記憶格中，難以實現動態 RAM特徵之高速寫入。 本發明係有鑑於上述情事，提供以簡單之格構造可記 憶複數位元分之資訊的非揮發性記憶體的構造爲目的者。 本發明之其他目的係以簡單之製造步驟製造記憶複數 位元分之資訊的非揮發性記憶裝置的非揮發性記憶裝置之 製造方法者。 本發明之另一目的係提供以簡單之步驟，混合載入可 電氣性消除之非揮發性記憶體和可高速寫入讀取的揮發性 記億體的半導體記億裝置之構造者。 本發明之另一目的係提供以簡單之步驟，混合載入可 電氣性消除之非揮發性記憶體和可高速寫入讀取的揮發性 記憶體的半導體記億裝置之製造方法者。 爲達成上述之目的，本發明之第1特徵係具備於半導 體基板之主面上，介由閘極絕緣膜，加以配置之第1之閘 極電極，和配置於該第1之閘極電極之側面上的電荷蓄積 本S張尺度適用中0®家^ (CNS)A4規格（210 X 297公釐） c —V----- —------------訂---------線 (請先閱讀背面之注意事項再填寫本頁) ；0644 ^ 8064 Α7 Β7 V. Description of the Invention (i) The present invention relates to non-volatile semiconductor devices and methods of manufacturing the same, non-volatile semiconductor memory devices and methods of manufacturing the same, and non-volatile semiconductor memory devices and volatile semiconductor memories. The semiconductor memory device of the device is a semiconductor memory device and its manufacturing method mixedly loaded on the same wafer. In the conventional non-volatile memory such as E E P ROM, two thresholds are realized through one grid, and one hundred bits of information is recorded in one grid. For this reason, due to the high density of the billion body, there are more than four thresholds in one grid. The proposal proposes to memorize information of more than two bits in one grid (M. Bauer et al., ISSCC95, ρ · 132). However, in order to realize this technology, it is necessary to properly control the threshold voltage, the small change in threshold voltage can be correctly detected, and the reliability of charge retention is more than that in the past. Therefore, in this technology, it is not always possible to obtain the equivalent performance in the past. In addition, this technique has a problem of low manufacturing yield. To this end, the new proposal physically stores charges in different complex positions and memorizes the lattice structure of the complex bit information. (B. Etan et al., IEDM96, P169, Figure 6). Here, as a similar grid structure, a structure in which a charge storage layer is provided on the side wall of the gate electrode by the present inventors has been proposed (U.S. Patent No. 4,881,108). However, the manufacturing engineering of such a lattice structure is very complicated, and the controllability of the channel range is also insufficient. On the other hand, there is an increasing demand for the non-volatile memory that can be electrically eliminated and the volatile memory that can be read and written at a high speed, which are required to be embedded in a chip by a recent system, on the same chip. In particular, the Chinese national standard < CNS) A4 specification < 210 x 297 mm is applicable to the non-volatile paper size of the floating gate structure mixed with EEPR0M or flash memory, etc. (Please read the note on the back first Please fill in this page for matters) Packing -------- Order --------- § · -4-488064 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Invention Description (2) The requirements for VLSI of memory and dynamic RAM with high-speed operation are also increasing rapidly. However, in recent years, the memory of the dynamic RAM is a very complicated 3-dimensional structure with a trench structure or a stacked structure. For this reason, when a floating gate type non-volatile memory and a dynamic RAM are to be mixedly loaded, since the memory cell structure is different, the manufacturing steps are complicated, and the number of photomask processes is also increased. Therefore, the manufacturing cost of the mixed wafer may become large. When a floating gate type non-volatile memory is used to realize a dynamic RAM memory cell, through the commonization of the lattice structure, the manufacturing steps are simplified, which can reduce the manufacturing cost. However, in this common memory cell, it is difficult to achieve high-speed writing of dynamic RAM characteristics. The present invention has been made in view of the foregoing circumstances, and has as its object to provide a structure of a non-volatile memory with a simple grid structure capable of memorizing information of a plurality of bits. Another object of the present invention is a method for manufacturing a non-volatile memory device that manufactures a non-volatile memory device that memorizes multiple bits of information in a simple manufacturing process. Another object of the present invention is to provide a constructor of a semiconductor memory device capable of mixing a nonvolatile memory that can be electrically erased and a volatile memory that can be written and read at a high speed in a simple process. Another object of the present invention is to provide a method for manufacturing a semiconductor memory device incorporating a nonvolatile memory that is electrically erasable and a volatile memory that can be read and written at high speed in a simple procedure. In order to achieve the above object, a first feature of the present invention includes a first gate electrode disposed on a main surface of a semiconductor substrate, a gate insulating film disposed thereon, and a first gate electrode disposed on the first gate electrode. The charge accumulation on the side of this S-sheet scale is applicable to the 0® house ^ (CNS) A4 size (210 X 297 mm) c —V ----- —------------ order- -------- line (please read the notes on the back before filling this page); 064

A7 B7 五、發明說明（3) 層，和於前述第1之閘極電極之側面上，介由前述電荷蓄 積層，加以配置之第2之閘極電極，和將前述第1之閘極 電極和前述第2之閘極電極電氣性連接之導電層的非揮發 性記憶體。 本發明之第2特徵係至少具備配置於半導體基板之主 面上，由第1、第2及第3之絕緣膜所成之閘極絕緣膜， 和配置於前述第2之絕緣膜之端部的電荷蓄積層，和配置 於前述閘極絕緣膜上之閘極電極的非揮發性記億體。 本發明之第3特徵係混合載置非揮發性半導體記憶體 和揮發性半導體記憶體之半導體記憶裝置中，非揮發性半 導體記憶體係至少具備配置於半導體基板之主面上的第1 之下部絕緣膜，和配置於第1之下部絕緣膜之中央之上部 的第1之中間絕緣膜，和配置於第1之下部絕緣膜之端部 之上部的第1之電荷蓄積層，和配置於第1之中間絕緣膜 及第1之電荷蓄積層之上部的第1之上部絕緣膜，和配置 於第1之上部絕緣膜之上部的第1之閘極電極，揮發性半 導體記憶體係具備配置於半導體基板之主面上，與第1之 中間絕緣膜同一材料所成之第2之下部絕緣膜，和於半導 體基板之主面上，且配置於第2之下部絕緣膜之兩端的極 薄絕緣膜’和配置於極薄絕緣膜之上部，與第1之電荷蓄 積層同一材料所成之第2之電荷蓄積層，和配置於第2之 下部絕緣膜及第2之電荷蓄積層之上部，與第1之上部絕 緣膜同一材料所成之第2之上部絕緣膜，和配置於第2之 上部絕緣膜上部的第2之閘極電極。 本紙張尺度適用中國國家標準（CNS〉A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) --------訂---------線* 經濟部智慧財產局員工消費合作社印製A7 B7 5. Description of the invention (3) layer, and a second gate electrode arranged on the side of the first gate electrode through the aforementioned charge accumulation layer, and a first gate electrode A non-volatile memory with a conductive layer electrically connected to the second gate electrode. A second feature of the present invention includes at least a gate insulating film formed of the first, second, and third insulating films disposed on the main surface of the semiconductor substrate, and an end portion of the second insulating film disposed. A charge storage layer and a non-volatile memory of a gate electrode disposed on the gate insulating film. A third feature of the present invention is that in a semiconductor memory device in which a nonvolatile semiconductor memory and a volatile semiconductor memory are mixed, the nonvolatile semiconductor memory system includes at least a first lower portion insulation disposed on a main surface of the semiconductor substrate. Film, and the first intermediate insulating film disposed above the center of the first lower insulating film, and the first charge storage layer disposed above the end of the first lower insulating film, and disposed on the first The intermediate insulating film and the first upper insulating film on the first charge storage layer, and the first gate electrode disposed on the upper portion of the first insulating film, and the volatile semiconductor memory system includes a semiconductor substrate On the main surface, a second lower insulating film made of the same material as the first intermediate insulating film, and an extremely thin insulating film on the main surface of the semiconductor substrate and disposed at both ends of the second lower insulating film ' And a second charge storage layer formed of the same material as the first charge storage layer and disposed on the upper portion of the ultra-thin insulating film, and a second charge storage layer disposed on the second lower insulation film and the second charge storage layer, A second upper insulating film made of the same material as the first upper insulating film, and a second gate electrode disposed above the second upper insulating film. This paper size applies to Chinese national standards (CNS> A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) -------- Order --------- Line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs

488064 A7 B7 五、發明說明（4) 本發明之第4特徵係混合載置非揮發性半導體記憶體 和揮發性半導體記憶體之半導體記憶裝置中，非揮發性半 導體記憶體係至少具備配置於半導體基板之主面上的第1 之下部絕緣膜，和配置於第1之下部絕緣膜之中央之上部 的第1之中間絕緣膜，和配置於第1之下部絕緣膜之端部 之上部的第1之電荷蓄積層，和配置於第1之中間絕緣膜 及第1之電荷蓄積層之上部的第1之上部絕緣膜，和配置 於第.1之上部絕緣膜之上部的第1之閘極電極，揮發性半 導體記憶體係具備配置於半導體基板之主面上的極薄絕緣 膜，和配置於極薄絕緣膜上，與第1之電荷蓄積層同一材 料所成之第2之電荷蓄積層，和配置於第2之電荷蓄積層 上之第2之上部絕緣膜，和配置於第2之上部絕緣膜上的 第2之閘極電極。 本發明之第5特徵係具備至少配置於半導體基板之主 面上之凸部或凹部，和配置於包含凸部或凹部之半導體基 板之主面上，由第1、第2及第3之絕緣膜所成閘極絕緣 膜，和配置於第2之絕緣膜之端部的電荷蓄積層，和配置 於閘極絕緣膜上之閘極電極的非揮發性半導體記憶裝置。 本發明之第6特徵係具備至少配置於半導體基板之主 面上之凸部或凹部，和配置於包含凸部或凹部之半導體基 板之主面上，由第1及第2之絕緣膜所成閘極絕緣膜，和 配置於第1及第2之絕緣膜之間的電荷蓄積層，和配置於 閘極絕緣膜上之閘極電極的非揮發性半導體記億裝置。 本發明之第7特徵係至少具備於半導體基板之主面上 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -J - (請先閱讀背面之注意事項再填寫本頁) --------訂---------線* 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（5 ) ，介由閘極絕緣膜，加以配置之閘極電極，和配置於閘極 電極之端部的凹部，和於凹部介由絕緣膜加以配置之電荷 蓄積層，電荷蓄積層係配置於通道範圍及汲極源極範圍之 兩方上部之非揮發性半導體記憶裝置。 本發明之物件及特徵具體說明描述於圖面或申請專利 範圍之中，而此優點非歸因於1個技術或部分之技術發明 者。 【圖面之簡單說明】 圖1係顯示有關本發明之第1之實施形態之非揮發性 半導體記憶體之記億格構造的截面圖。 圖2A乃至圖2 C係說明有關本發明之第1之實施形 態之非揮發性半導體記憶體之動作的截面圖。 圖3 A乃至圖3 E係顯示有關本發明之第1之實施形 態之非揮發性半導體記億體之製造工程的截面圖。 圖4係顯示有關本發明之第2之實施形態之非揮發性 半導體記憶體之記憶格構造的截面圖。 圖5 A乃至圖5 B係說明有關本發明之第2之實施形 態之非揮發性半導體記億體之操作的截面圖。 圖6 A乃至圖6 G係顯示有關本發明之第2之實施形 態之非揮發性半導體記憶體之製造工程的截面圖。 圖7係顯示有關本發明之第4之實施形態之非揮發性 半導體記憶體之記憶格構造的截面圖。 圖8 A乃至圖8 B係說明有關本發明之第4之實施形 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I I— I I l· I ----裝--------訂---------線· (請先閱讀背面之注意事項再填寫本頁) -8 - 488064 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 態之非揮發性半導體記憶體之動作的截面圖。 圖9係顯示構成有關本發明之第5之實施形態之非揮 發性半導體記憶體之周邊電路的Μ〇S電晶體之構造截面 圖。 圖1 0Α乃至圖1 0G係顯示圖9之MOS電晶體之 製造工程的截面圖。 圖1 1 Α係顯示搭載於有關本發明之第6之實施形態 之半導體記憶裝置之非揮發性半導體記憶體之記憶格構造 的截面圖。 圖1 1 B係顯示搭載於有關本發明之第6之實施形態 之半導體記憶裝置之揮發性半導體記億體之記憶格構造的 截面圖。 圖1 2A乃至圖1 2 B係說明有關本發明之第6之實 施形態之非揮發性半導體記憶體之動作的截面圖。 圖1 3A乃至圖1 3 I係顯示有關本發明之第6之實 施形態之非揮發性半導體記憶體之記憶格之製造工程的截 面圖。 圖1 4A乃至圖1 4 I係顯示有關本發明之第6之實 施形態之揮發性半導體記憶體之記憶格之製造工程的截面 圖。 圖1 5 A係顯示搭載於有關本發明之第7之實施形態 之半導體記億裝置之非揮發性半導體記憶體之記憶格構造 的截面圖。 圖1 5 B係顯示搭載於有關本發明之第7之實施形態 -J 一 (請先閱讀背面之注意事項再填寫本頁) ,ΦΜ.---- 訂---------線* 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -9- 488064 A7 B7 ___ 五、發明說明（7 ) 之半導體記憶裝置之揮發性半導體記憶體之記憶格構造的 截面圖。 (請先閱讀背面之注意事項再填寫本頁) 圖1 6 A乃至圖籲譯有關本發明之第7之實 施形態之非揮發性半導體記億記憶格之製造工程的截 面圖。 圖1 7 A乃至圖示有關本發明之第7之實 施形態之揮發性半導體記記億格之製造工程的截面 圖。 圖1 8係顯示有關本發明之第8之實施形態之非揮發 性半導體記憶體之記億格構造的截面圖。 圖1 9 A乃至圖1 9 B係說明有關本發明之弟8之貫 施形態之非揮發性半導、體記憶體之動作的截面圖。 圖2 0 A乃至係顯示有關本發明之第8之實 施形態之揮發性半導體te擎體之記憶格之製造工程的截面 圖。 圖2 1係顯示有關本發明之第9之實施形態之非揮發 性半導體記憶體之記憶格構造的截面圖。 經濟部智慧財產局員工消費合作社印製 圖2 2 A乃至圖2 2 F係顯示有關本發明之第9之實 施形態之非揮發性半導體記憶體之記憶格之製造工程的截 面圖。 圖2 3係顯示有關本發明之第1 〇之實施形態之非揮 發性半導體記憶體之記憶格構造的截面圖。 圖2 4A乃至圖2 4B係說明有關本發明之第1 0之 實施形態之非揮發性半導體記憶體之動作的截面圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 10- 488064 Α7 Β7 五、發明說明（8) 圖2 5A乃至圖2 5 Ί係:、說明有關本發明之第1 〇之 實施形態之非揮發性半導體記'^:舉之動作的截面圖。 's/ (請先閱讀背面之注意事項再填寫本頁) 圖2 6係顯示有關本發明之第1 1之實施形態之非揮 發性半導體記憶體之記憶格構造的截面圖。 圖2 7A乃至圖2 7 F係顯示有關本發明之第1 1之 實施形態之非揮發性半導體記憶體之記億格之製造工程的 截面圖。 圖2 8係顯示有關本發明之第1 2之實施形態之非揮 發性半導體記憶體之記憶格構造的截面圖。 圖2 9 A乃至圖2 9 I係顯示有關本發明之第1 2之 實施形態之非揮發性半導體記憶體之記憶格之製造工程的 截面圖。 圖3 0係顯示有關本發明之第1 3之實施形態之非揮 發性半導體記憶體之記憶格構造的截面圖。 圖3 ί A乃至圖3 1 B係以η型Μ〇S電晶體加以構 成，說明有關本發明之第1 3之實施形態之非揮發性半導 體記憶體之動作的截面圖。 經濟部智慧財產局員工消費合作社印製 圖3 2Α乃至圖3 2Β係以Ρ型MOS電晶體加以構 成，說明有關本發明之第1 3之實施形態之非揮發性半導 體記憶體之動作的截面圖。 圖3 3係顯示具有與有關本發明之第1 3之實施形態 之非揮發性半導體記憶體之記憶格同一之閘極構造的 M〇S電晶體之構造的截面圖。 圖3 4係顯示有關本發明之第1 4之實施形態之非揮 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -11 - 488064 經濟部智慧財產局員工消費合作社印製 A7 __— __B7___ 五、發明說明（9 ) 發性半導體記憶體之記憶格構造的截面圖。 圖3 5係顯示具有與有關本發明之第1 4之實施形態 之非揮發性半導體記憶體之記憶格同一之閘極構造的 M〇 S電晶體之構造的截面圖。 本發明之各種具體化係描述於參考附圖。於圖面中相 同相似之元件以相同相似之符號加以表示。對於相同相似 之元件之描述則簡化或加以省略。 以下參照圖面，說明本發明之實施形態。於以下之圖 面記載中，於同一或類似部分，附上同一或類似之符號。 惟’圖面係模式性的，厚度和平面尺寸之關係，各層之厚 度之比率等與現實者不同，需加以注意。因此，具體之厚 度或尺寸係參酌以上之說明加以判斷者。又，於圖面相互 間，當然包含相互之尺寸之關係或比率不同之部分。 (第1之實施形態） 圖1係顯示有關本發明之第1之實施形態之非揮發性 半導體記憶體之記憶格構造的截面圖。此記憶格係以η型 Μ〇S電晶體加以構成。有關本發明之第1之實施形態之 非揮發性半導體記憶體之記憶格構造中，於Ρ型半導體基 板1之表面，介由閘極絕緣膜2，設置第1閘極電極3， 於第1閘極電極3之兩側面，設置電荷蓄積層4 ( 4 a ， 4b)。此電荷蓄積層4係具有堆積構造，第1層以第1 氧化膜5 ，第2層以氮化膜6，第3層以第2氧化膜7加 以構成。更且，於電荷蓄積層4之上部設置第2閘極電極 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） ‘ ： ----裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) -12- 488064 經濟部智慧財產局員工消費合作社印製 A7 ___B7____ 五、發明說明（10) 8。於電荷蓄積層4之側面，設置側壁間隔9 ，於此側壁 間隔9之下部之P型半導體基板1中，設置接觸於通道範 圍之低不純物濃度之η —型擴散層1 〇，和位置於此n -型 擴散層1 〇之外側的高不純物濃度之η +型擴散層1 1。於 各第1閘極電極3，電荷蓄積層4，第2閘極電極8及η + 型擴散層1 1之表面，設置導電層1 2。第1閘極電極3 和第2閘極電極8係介由此導電層1 2加以電氣連接。 有關本發明之第1之實施形態之非揮發性半導體記憶 體之記憶格係具有將源極範圍及汲極範圍以低不純物濃度 之η —型擴散層1 0和高不純物濃度之η+型擴散層1 1構 成之L D D構造。然後，於第1閘極電極3之兩側面，形 成電荷蓄積層4，將保持於此2個之電荷蓄積層4之氮化 膜6的電子之有無所產生之臨限値電壓的變化分，對應於 記憶資訊的、、0 0 ， 、、0 1 " ， 、、：L 0 " ， vv 1 1 "。 更且，於電荷蓄積層4之上部，形成第2閘極電極8，將 此第2閘極電極8電氣連接於第1閘極電極3地，提高通 道範圍之控制性，使臨限値電壓變化分之檢測容易化。 接著，對於有關本發明之第1之實施形態的非揮發性 記憶體之動作，使用圖2 A乃至圖2 C加以說明。圖2 A 係說明寫入動作之非揮發性記憶體之截面圖。圖2 B係說 明讀取動作之非揮發性記憶體之截面圖。圖2 C係說明消 除動作之非揮發性記憶體之截面圖。如圖2 A所示’於記 億格之寫入時，於閘極G施加高電壓（〜1 〇 V )，同時 於接近蓄積電子之電荷倉積層4 b的汲極D ’施加高電壓 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I i--------裝·----I--訂--------- (請先閱讀背面之注意事項再填寫本頁) -13- 經濟部智慧財產局員工消費合作社印製 488064 A7 _____ B7 五、發明說明（11) (〜8 V )，將不接近之源極S加以接地。如此地，施加 電壓時，產生通道熱電子，此熱電子被電荷蓄積層4 b之 氮化膜6加以捕獲。於電荷蓄積層4 b捕獲電子時，格電 晶體之臨限値感測放大器則變化。記憶格之讀出係檢測臨 限値電壓之變化分加以進行。具體而言，如圖2 B所示， 於閘極G加上電壓5 V，同時於汲極D施加電壓3 V，將 電流量之差經由感測放大器加以檢測。又，記憶格之消除 係如圖2 C所示’於閘極G施加負電壓（〜一 6 V )，於 接近於消除之電荷蓄積層4 b的汲極D施加正電壓（ 〜9V)，放出被電荷蓄積層4b所捕獲之電子地加以進 行。然而，如周知所述，Μ〇S電晶體之源極S和汲極D 係呈對稱，一般而言，可置換源極S和汲極D。因此，.於 上述說明中，可置學源極S和汲極D。’ 接著，將有關本發明之第1之實施形態的非揮發性半 導體記憶體之記憶格之製造方法，使用圖3 Α乃至圖3 Ε 加以說明。首先，如圖3所示，於p型半導體基板1 ，於 整面經由L P CVD法，堆積滲雜η型或p型不純物之 3 0 0 n m之多結晶矽膜後，經由周知之曝光技術及蝕刻 技術加以圖案化，形成第1閘極電極3。 接著，如圖3 b所示，除去形成源極範圍及汲極範圍 之範圍的P型半導體基板1之表面之閘極絕緣膜2後，將 P型半導體基板1於9 0 0 °C〜1 2 0 0 °C之氧化氣氛熱 氧化，形成1 0 n m之第1氧化膜5。然後，於第1氧化 膜5上經由LP CVD法堆積1 〇 nm〜1 0 0 nm之氮 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --- I I I I I ---1 --------I----I I (請先閲讀背面之注意事項再填寫本頁) -14- 488064 經濟部智慧財產局員工消費合作社印製 A7 __B7__ 五、發明說明（l2) 化膜6 ，經由之後9 0 0 °C之氫燃燒氧化或C V D法，於 氮化膜6表面形成5 nm程度之第2氧化膜7。 接著，如圖3 C所示，於第2氧化膜7上，例如經由 L P CVD法，堆積2 5〜2 5 0 nm程度之多結晶砂後 ，進行經由R I E法之向異性蝕刻，將此多結晶矽膜、第 1氧化膜5、氮化膜6及第2氧化膜7僅除去此等之膜厚 分，於上部將具有第2閘極電極8之電荷蓄積層4形成於 第1閘極電極側面。 接著，如圖3 D所示，形成低不純物濃度之n -型擴散 層1 0。η —型擴散層1 0係經由離子植入技術，將第1閘 極電極3及電荷蓄積層4做爲光罩，植入Ν型不純物，經 由之後之熱處理，活化植入之不純物而形成者。 接著，如圖3 Ε所示，於電荷蓄積層4之側壁，形成 側壁間隔9之後，形成高不純物濃度之η +型擴散層1 1。 η +型擴散層1 1係經由離子植入技術，將第1閘極電極3 、電荷蓄積層4及側壁間隔9做爲光罩，植入η型不純物 ，經由之後之熱處理活化植入之不純物而加以形成。 接著，於Ρ型半導體基板1之整面，經由CVD法或 濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將Ρ 型半導體基板1於不活性氣氛中經由熱處理，於各第1閘 極電極3、電荷蓄積層4、第2閘極電極8及η+型擴散層 1 1之表面，形成以高融點金屬矽化物所構成之導電層 1 2。此時，交連第1閘極電極3及第2閘極電極8上之 高融點金屬矽化物層地，需設定第1氧化膜5、氮化膜6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） —«.—f^--------訂--------- (請先閲讀背面之注意事項再填寫本頁) -15- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7_ 五、發明說明（13) 、第2氧化膜7，尤其需設定氮化膜6之膜厚。形成導電 層1 2後，除去殘留於上述以外之範圍的未反應高融點金 屬時，可完成圖1所示之記憶格構造。 然而，雖未圖示，圖1之記憶格構造完成後，順序經 由層間絕緣膜形成工程，連接孔形成工程，配線形成工程 ，鈍化膜形成工程等之通常之CMO S製造工程，完成最 終之非揮發性記憶格。 根據本發明之第1之實施形態時，於電荷蓄積層4之 上部，亦設置第2閘極電極8之故，提升臨限値之控制性 。然而，本發明之第1之實施形態中，雖對於令記憶格以 η型Μ〇S電晶體構成之時加以說明，於p型M〇S電晶 體所構成之時，亦可得同樣之效果。又，記憶格係具有 L D D構造，但亦可爲單汲極構造、雙汲極構造。 (第2之實施形態） 接著，說明有關本發明之第2之實施形態。圖4係顯 示有關本發明之第2之實施形態之非揮發性半導體記憶體 之記憶格構造的截面圖。此記憶格係以η型Μ 0 S電晶體 加以構成。有關本發明之第2之實施形態的非揮發性記億 體之記憶格構造中，於Ρ型半導體基板1之表面，介由第 1閘極絕緣膜1 3，設置第2閘極絕緣膜1 4。然後，於 第2閘極絕緣膜14之兩端，形成電荷蓄積層4a ，4b 。於第2閘極絕緣膜1 4及電荷蓄積層4 a、4 b上，介 由第3閘極絕緣膜1 5，設置閘極電極3。於閘極電極3 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 丨4^---_—------**·裝--------訂 --------- SI (請先閱讀背面之注意事項再填寫本頁) -16- 經濟部智慧財產局員工消費合作社印製 488064 A7 ___ B7_ 五、發明說明（14) 之側面，介由氧化膜1 6，設置側壁間隔9，於此側壁間 隔9之下部之P型半導體基板1 ，設置接觸通道範圍之低 不純濃度之型擴散層1 〇，和位於此型擴散層1 〇 之外側之高不純物濃度之η +型擴散層1 1。於各閘極電極 3及η+型擴散層1 1之表面，設置導電層1 2。 有關於本發明之第2之實施形態之非揮發性半導體記 憶體之記憶格係具有將源極範圍及汲極範圍以低不純濃度 之η _型擴散層1 0，和高不純物濃度之η +型擴散層1 1 加以構成之L D D構造。然後，閘極絕緣膜則由第1閘極 絕緣膜1 3不得下層）、第2閘極絕緣膜1 4 (中間層） 及第3閘極絕緣膜1 5所成3層堆積膜所構成，第2閘極 絕緣膜14之兩端部中，形成電荷蓄積層4a及4b。於 此2個之電荷蓄積層4 a及4 b蓄積電子。該蓄積狀態係 可有（1)電荷蓄積層4a、4b之任一者皆未蓄積電子 之狀態，（2 )僅電荷蓄積層4 a蓄積電子之狀態，（3 )僅電荷蓄積層4b蓄積電子之狀態’ （4)電荷蓄積層 4 a ，4 b皆蓄積電子之狀態之4個狀態。經由保持於此 2個之電荷蓄積層4a ，4b之電子之有無’將所產生之 臨限値之變化分，對應於記億資訊之〃 ， "〇1" ，、、1 〇 〃 ， '、1 1 〃 。又，於此記憶格構造之中，電荷 蓄積層4 a ，4 b係位於通道範圍端部之上方之故’通道 範圍中央部之臨限値電壓係僅以通道範圍之不純物濃度加 以決定，不依附於電荷蓄積層4 a ’ 4 b之電子之蓄積狀 態。因此，可防止電荷蓄積層4 a ，4 b之電子之過度不 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂----- 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） -17- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（l5) 足的過度消除，由此不會產生由於過度消除起因的泄放不 良，程式不良，讀取不良等。又，源極範圍和汲極範圍間 之泄放電流係可僅以閘極電壓加以抑制，實現高可靠性之 非揮發性半導體記憶體。電荷蓄積層4 a及4 b係以 C V D法之電荷蓄積能力高的矽氮化膜加以構成即可。經 由於矽氮化膜之離散性之電荷捕獲準位蓄積電子，可得難 以於下部絕緣膜之膜質影響之電荷保持特性。又，以矽膜 ，多結晶矽膜加以構成之時，可便宜地加以製造。更且， 將第1閘極絕緣膜1 3、第3閘極絕緣膜1 5以具有矽氧 化膜（S i〇2膜）之2倍程度之介電率的矽氮化膜（ S i 3N4膜）加以構成時，可將矽氧化膜換算膜厚爲4〜 1 1 n m程度之非常薄的閘極絕緣膜安定實現。例如’矽 氧化膜換算膜厚爲5 nm之矽氮化膜之實質膜厚爲1 0 nm程度之故，直接進行隧道植入亦不會激働。因此’電 子之植入抽出時之電壓係被低電壓化，不單是記億格之微 細化，亦可達周邊高電壓動作元件之微細化。 有關本發明之第2之實施形態之非揮發性半導體記憶 體之記憶格中，於源極範圍及汲極範圔之耐壓提升之目的 上，設置η—型擴散層10，以構成LDD構造，以單汲極 構造，雙汲極構造構成源極範圍及汲極範圍亦可。第2閘 極絕緣膜1 4係雖可防止電荷蓄積層4 a - 4 b間之泄放 ，例如可以矽氧化膜構成。又，於第2閘極絕緣膜1 4使 用具有高介電率之金屬氧化膜時，可提升通道範圍中央之 電流傳達特性。做爲金屬氧化物例如可有T i 0 2、 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I Jr--I----- --------^--------- (請先閱讀背面之注意事項再填寫本頁) -18- 488064 經濟部智慧財產局員工消費合作社印製 A7 B7 ___ 五、發明說明（16)488064 A7 B7 V. Explanation of the invention (4) The fourth feature of the present invention is a semiconductor memory device in which a nonvolatile semiconductor memory and a volatile semiconductor memory are mixedly disposed. The nonvolatile semiconductor memory system includes at least a semiconductor substrate. The first lower insulating film on the main surface, the first intermediate insulating film arranged on the upper part of the center of the first lower insulating film, and the first first insulating film arranged on the upper part of the end of the first lower insulating film. A charge storage layer, a first upper insulating film disposed on the first intermediate insulating film and a first charge storage layer, and a first gate electrode disposed on the upper portion of the first insulating film. The volatile semiconductor memory system includes an extremely thin insulating film disposed on the main surface of the semiconductor substrate, and a second charge accumulation layer formed on the extremely thin insulation film and formed of the same material as the first charge accumulation layer, and A second upper insulating film disposed on the second charge storage layer, and a second gate electrode disposed on the second upper insulating film. A fifth feature of the present invention includes a convex portion or a concave portion disposed at least on the main surface of the semiconductor substrate, and a main surface of the semiconductor substrate including the convex portion or the concave portion, and is insulated by the first, second, and third portions. A non-volatile semiconductor memory device including a gate insulating film formed of the film, a charge storage layer disposed at an end portion of the second insulating film, and a gate electrode disposed on the gate insulating film. A sixth feature of the present invention includes a convex portion or a concave portion disposed at least on the main surface of the semiconductor substrate, and a main surface of the semiconductor substrate including the convex portion or the concave portion, and is formed of the first and second insulating films. A non-volatile semiconductor memory device including a gate insulating film, a charge accumulation layer disposed between the first and second insulating films, and a gate electrode disposed on the gate insulating film. The seventh feature of the present invention is at least provided on the main surface of the semiconductor substrate. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -J-(Please read the precautions on the back before filling this page ) -------- Order --------- Line * Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7 V. Description of the Invention (5 ), A gate electrode disposed through a gate insulating film, a recessed portion disposed at an end of the gate electrode, and a charge storage layer disposed in the recessed portion through an insulating film, and the charge storage layer is disposed in a channel range And the non-volatile semiconductor memory device on both sides of the drain source region. The specific description of the objects and features of the present invention are described in the drawings or patent applications, and this advantage is not attributed to a technology or part of the technical inventor. [Brief Description of Drawings] FIG. 1 is a cross-sectional view showing a petabyte structure of a nonvolatile semiconductor memory according to a first embodiment of the present invention. 2A to 2C are cross-sectional views illustrating the operation of the nonvolatile semiconductor memory according to the first embodiment of the present invention. 3A to 3E are cross-sectional views showing a manufacturing process of a nonvolatile semiconductor memory device according to the first embodiment of the present invention. Fig. 4 is a sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a second embodiment of the present invention. 5A and 5B are cross-sectional views illustrating the operation of the non-volatile semiconductor memory device according to the second embodiment of the present invention. 6A to 6G are cross-sectional views showing a manufacturing process of a nonvolatile semiconductor memory according to a second embodiment of the present invention. Fig. 7 is a sectional view showing a memory cell structure of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention. Figures 8A and 8B are illustrations of the fourth embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) II—II l · I ---- installation-- ------ Order --------- Line · (Please read the notes on the back before filling this page) -8-488064 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A cross-sectional view illustrating the operation of the (6) state nonvolatile semiconductor memory. Fig. 9 is a sectional view showing the structure of a MOS transistor constituting a peripheral circuit of a non-volatile semiconductor memory according to a fifth embodiment of the present invention. 10A to 10G are cross-sectional views showing the manufacturing process of the MOS transistor of FIG. Fig. 1A is a sectional view showing a memory cell structure of a nonvolatile semiconductor memory mounted on a semiconductor memory device according to a sixth embodiment of the present invention. Fig. 11B is a cross-sectional view showing a memory cell structure of a volatile semiconductor memory device mounted on a semiconductor memory device according to a sixth embodiment of the present invention. 12A to 12B are cross-sectional views illustrating the operation of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention. 13A to 13I are sectional views showing a manufacturing process of a memory cell of a nonvolatile semiconductor memory according to a sixth embodiment of the present invention. 14A to 14I are cross-sectional views showing a manufacturing process of a memory cell of a volatile semiconductor memory according to a sixth embodiment of the present invention. Fig. 15A is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory mounted on a semiconductor memory device according to a seventh embodiment of the present invention. Figure 1 5 B shows the seventh embodiment of the present invention-J I (Please read the precautions on the back before filling this page), ΦM .---- Order --------- Line * This paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) -9- 488064 A7 B7 ___ V. Description of Invention (7) The memory cell structure of the volatile semiconductor memory of the semiconductor memory device Sectional view. (Please read the precautions on the back before filling out this page) Figure 16A and even the figure shows a cross-sectional view of the manufacturing process of the non-volatile semiconductor memory cell of the seventh embodiment of the present invention. Fig. 17A is a cross-sectional view showing a manufacturing process of a volatile semiconductor in a scale of one hundredth according to the seventh embodiment of the present invention. Fig. 18 is a cross-sectional view showing a petabyte structure of a nonvolatile semiconductor memory according to an eighth embodiment of the present invention. Fig. 19A and Fig. 19B are cross-sectional views illustrating the operation of the nonvolatile semiconductor and body memory related to the embodiment of the eighth embodiment of the present invention. Fig. 20A is a cross-sectional view showing the manufacturing process of the memory cell of the volatile semiconductor te engine according to the eighth embodiment of the present invention. Fig. 21 is a sectional view showing a memory cell structure of a nonvolatile semiconductor memory device according to a ninth embodiment of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Figure 2 A and Figure 2 F are cross-sectional views showing the manufacturing process of the memory cell of the non-volatile semiconductor memory according to the ninth embodiment of the present invention. Fig. 23 is a cross-sectional view showing a memory cell structure of a non-volatile semiconductor memory according to a tenth embodiment of the present invention. Figs. 24A to 24B are cross-sectional views illustrating the operation of the non-volatile semiconductor memory according to the tenth embodiment of the present invention. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 10-488064 A7 B7 V. Description of the invention (8) Figure 2 5A and even Figure 2 Non-volatile semiconductors in the embodiment: ^: Cross-sectional view of the lift operation. 's / (Please read the precautions on the back before filling this page) Figure 2 6 is a cross-sectional view showing the memory cell structure of the non-volatile semiconductor memory according to the 11th embodiment of the present invention. Fig. 2A and Fig. 2F are cross-sectional views showing the manufacturing process of the non-volatile semiconductor memory according to the eleventh embodiment of the present invention. Fig. 28 is a sectional view showing a memory cell structure of a non-volatile semiconductor memory according to a twelfth embodiment of the present invention. Figs. 29A to 29I are cross-sectional views showing a manufacturing process of a memory cell of a nonvolatile semiconductor memory according to a twelfth embodiment of the present invention. Fig. 30 is a sectional view showing a memory cell structure of a non-volatile semiconductor memory according to a thirteenth embodiment of the present invention. Fig. 3 and Fig. 3A and Fig. 3B are cross-sectional views illustrating the operation of the non-volatile semiconductor memory according to the thirteenth embodiment of the present invention, which are composed of n-type MOS transistors. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Figure 3 2A and Figure 3 2B are constructed by P-type MOS transistors, and are cross-sectional views illustrating the operation of the non-volatile semiconductor memory according to the 13th embodiment of the present invention . Fig. 33 is a cross-sectional view showing the structure of a MOS transistor having a gate structure identical to a memory cell of a nonvolatile semiconductor memory according to a thirteenth embodiment of the present invention. Figure 3 4 shows the non-printing paper dimensions related to the 14th implementation form of the present invention. Applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). -11-488064 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. System A7 __— __B7___ V. Description of the Invention (9) A cross-sectional view of the memory cell structure of a semiconductor semiconductor memory. Fig. 35 is a cross-sectional view showing the structure of a MOS transistor having the same gate structure as the memory cell of the non-volatile semiconductor memory according to the fourteenth embodiment of the present invention. Various embodiments of the invention are described with reference to the drawings. Identical components are indicated by the same symbols in the drawings. Descriptions of the same or similar elements are simplified or omitted. Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or similar symbols are attached to the same or similar parts. However, the drawing surface is model, the relationship between the thickness and the plane size, and the thickness ratio of each layer are different from the real ones, so it should be paid attention to. Therefore, the specific thickness or size is judged by referring to the above description. In addition, of course, the drawings include portions having different dimensional relationships or ratios. (First Embodiment) Fig. 1 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a first embodiment of the present invention. This memory cell is composed of n-type MOS transistor. In the memory cell structure of the non-volatile semiconductor memory according to the first embodiment of the present invention, a first gate electrode 3 is provided on the surface of the P-type semiconductor substrate 1 through a gate insulating film 2 and On both sides of the gate electrode 3, a charge storage layer 4 (4a, 4b) is provided. This charge accumulation layer 4 has a stacked structure. The first layer is formed by a first oxide film 5, the second layer is formed by a nitride film 6, and the third layer is formed by a second oxide film 7. In addition, a second gate electrode is provided on the upper part of the charge accumulation layer 4. The paper size is applicable to the Chinese National Standard < CNS) A4 specification (210 X 297 mm) ': ---- install ------- -Order --------- (Please read the precautions on the back before filling out this page) -12- 488064 Printed by A7 ___B7____ Cooperative of Employees and Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (10) 8. On the side of the charge accumulation layer 4, a sidewall spacer 9 is provided. In the P-type semiconductor substrate 1 below the sidewall spacer 9, a η-type diffusion layer 1 0 having a low impurity concentration in contact with the channel region is provided, and the position is here η + -type diffusion layer 11 having a high impurity concentration on the outer side of n--type diffusion layer 1 0. A conductive layer 12 is provided on the surface of each of the first gate electrode 3, the charge storage layer 4, the second gate electrode 8, and the η + -type diffusion layer 11. The first gate electrode 3 and the second gate electrode 8 are electrically connected via the conductive layer 12. The memory cell of the nonvolatile semiconductor memory according to the first embodiment of the present invention has a η-type diffusion layer 10 with a low impurity concentration and a η + type diffusion with a high impurity concentration. Layer 11 structure of LDD. Then, a charge storage layer 4 is formed on both sides of the first gate electrode 3, and the threshold voltage generated by the presence or absence of electrons in the nitride film 6 of the two charge storage layers 4 is changed. Corresponding to the memory information, 0, 0, 1, 0 1 ", ,,: L 0 ", vv 1 1 ". Furthermore, a second gate electrode 8 is formed on the upper part of the charge accumulation layer 4, and this second gate electrode 8 is electrically connected to the first gate electrode 3 to improve the controllability of the channel range and make the threshold voltage Detection of change is facilitated. Next, the operation of the non-volatile memory according to the first embodiment of the present invention will be described with reference to Figs. 2A to 2C. FIG. 2A is a cross-sectional view of a nonvolatile memory illustrating a write operation. Figure 2B is a cross-sectional view of the non-volatile memory illustrating the read operation. Fig. 2C is a cross-sectional view of the nonvolatile memory illustrating the erasing operation. As shown in FIG. 2A, when writing in a billion grid, a high voltage (~ 10V) is applied to the gate G, and a high voltage is applied to the drain D of the charge storage layer 4b near the stored electrons. Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I i -------- installation · ---- I--order --------- (please first Read the notes on the back and fill out this page) -13- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 _____ B7 V. Description of the invention (11) (~ 8 V), ground the inaccessible source S. In this way, when a voltage is applied, channel hot electrons are generated, and the hot electrons are captured by the nitride film 6 of the charge accumulation layer 4b. When the charge accumulation layer 4b captures electrons, the threshold value of the grid crystal sense amplifier changes. The reading of the memory cell is performed by detecting the threshold and voltage changes. Specifically, as shown in FIG. 2B, a voltage of 5 V is applied to the gate G, and a voltage of 3 V is applied to the drain D, and the difference in the amount of current is detected through the sense amplifier. In addition, as shown in FIG. 2C, the memory cell is erased by applying a negative voltage (~ 6 V) to the gate G, and applying a positive voltage (~ 9 V) to the drain D of the charge accumulation layer 4b close to the erase, The electrons captured by the charge accumulating layer 4b are emitted. However, as well known, the source S and the drain D of the MOS transistor are symmetrical. Generally speaking, the source S and the drain D can be replaced. Therefore, in the above description, the source S and the drain D can be set. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory according to the first embodiment of the present invention will be described with reference to Figs. 3A to 3E. First, as shown in FIG. 3, a polycrystalline silicon film doped with n-type or p-type impurities at 300 nm is deposited on the p-type semiconductor substrate 1 by LP CVD over the entire surface, and then the well-known exposure technology and It is patterned by an etching technique to form a first gate electrode 3. Next, as shown in FIG. 3 b, the gate insulating film 2 on the surface of the P-type semiconductor substrate 1 forming the range of the source range and the drain range is removed, and then the P-type semiconductor substrate 1 is heated at 90 ° C. to 1 °. Thermal oxidation in an oxidizing atmosphere at 200 ° C forms a first oxide film 5 at 10 nm. Then, a 10 nm to 100 nm nitrogen layer was deposited on the first oxide film 5 by the LP CVD method. The paper size is in accordance with China National Standard (CNS) A4 (210 X 297 mm) --- IIIII --- 1 -------- I ---- II (Please read the notes on the back before filling this page) -14- 488064 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 __B7__ V. Description of the Invention (l2 ) The chemical film 6 is formed with a second oxide film 7 of about 5 nm on the surface of the nitride film 6 by a hydrogen combustion oxidation or CVD method at 900 ° C. Next, as shown in FIG. 3C, on the second oxide film 7, for example, polycrystalline sand having a thickness of about 25 to 250 nm is deposited by the LP CVD method, and then anisotropic etching is performed by the RIE method. The crystalline silicon film, the first oxide film 5, the nitride film 6, and the second oxide film 7 are removed only by these film thicknesses, and a charge storage layer 4 having a second gate electrode 8 is formed on the first gate on the upper portion. Electrode side. Next, as shown in Fig. 3D, an n-type diffusion layer 10 having a low impurity concentration is formed. The η-type diffusion layer 10 is formed by implanting the first gate electrode 3 and the charge accumulation layer 4 as photomasks by ion implantation technology, implanting N-type impurities, and activating the implanted impurities by subsequent heat treatment. . Next, as shown in FIG. 3E, after forming sidewall spacers 9 on the sidewalls of the charge accumulation layer 4, an η + -type diffusion layer 11 having a high impurity concentration is formed. The η + type diffusion layer 1 1 is implanted with η-type impurities by using the first gate electrode 3, the charge accumulation layer 4 and the side wall spacer 9 as a photomask through ion implantation technology, and the implanted impurities are activated by subsequent heat treatment. And formed. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method or a sputtering method, and then the P-type semiconductor substrate 1 is heat-treated in an inert atmosphere. On the surfaces of the first gate electrode 3, the charge storage layer 4, the second gate electrode 8, and the η + -type diffusion layer 11, a conductive layer 12 composed of a high melting point metal silicide is formed. At this time, to cross-link the high melting point metal silicide layer on the first gate electrode 3 and the second gate electrode 8, the first oxide film 5 and the nitride film 6 need to be set. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — «.— f ^ -------- Order --------- (Please read the precautions on the back before filling this page) -15- Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 488064 A7 B7_ V. Description of the invention (13), the second oxide film 7, especially the film thickness of the nitride film 6 needs to be set. When the conductive layer 12 is formed and the unreacted high-melting-point metal remaining in a range other than the above is removed, the memory cell structure shown in FIG. 1 can be completed. However, although not shown, after the memory cell structure in FIG. 1 is completed, the usual CMO S manufacturing processes such as the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process are completed in order. Volatile memory cells. According to the first embodiment of the present invention, the second gate electrode 8 is also provided on the upper portion of the charge accumulation layer 4 to improve the controllability of the threshold value. However, in the first embodiment of the present invention, although the case where the memory cell is composed of an n-type MOS transistor is described, the same effect can be obtained when the p-type MOS transistor is formed. . In addition, the memory cell system has an L D D structure, but it may also have a single-drain structure or a double-drain structure. (Second Embodiment) Next, a second embodiment of the present invention will be described. Fig. 4 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a second embodiment of the present invention. This memory cell is composed of an n-type M 0 S transistor. In the non-volatile memory cell structure of the second embodiment of the present invention, a second gate insulating film 1 is provided on the surface of the P-type semiconductor substrate 1 through a first gate insulating film 1 3 4. Charge accumulation layers 4a, 4b are formed on both ends of the second gate insulating film 14. A gate electrode 3 is provided on the second gate insulating film 14 and the charge accumulation layers 4 a and 4 b via a third gate insulating film 15. For the gate electrode 3 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 丨 4 ^ ---_-------- ** · installation -------- Order --------- SI (Please read the notes on the back before filling out this page) -16- Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 ___ B7_ V. Side of Invention Note (14) A sidewall spacer 9 is provided through the oxide film 16, and a P-type semiconductor substrate 1 below the sidewall spacer 9 is provided with a low-impurity-concentration type diffusion layer 10 in the contact channel range, and a diffusion layer 1 located in the type. Η + -type diffusion layer 11 having a high impurity concentration on the outer side. A conductive layer 12 is provided on the surface of each gate electrode 3 and the n + -type diffusion layer 11. The memory cell of the non-volatile semiconductor memory according to the second embodiment of the present invention has a η-type diffusion layer 10 with a source range and a drain range at a low impurity concentration, and η + with a high impurity concentration. The LDD structure is composed of a type diffusion layer 1 1. Then, the gate insulating film is composed of a three-layer stacked film formed by the first gate insulating film 13 (the lower layer cannot be lower), the second gate insulating film 14 (the middle layer), and the third gate insulating film 15. The charge storage layers 4 a and 4 b are formed on both ends of the second gate insulating film 14. Electrons are accumulated in the two charge accumulation layers 4 a and 4 b. This accumulation state may be (1) a state where no electrons are accumulated in any of the charge accumulation layers 4a, 4b, (2) a state where electrons are accumulated only in the charge accumulation layer 4a, and (3) only electrons are accumulated in the charge accumulation layer 4b State '(4) The charge accumulation layers 4 a and 4 b are all four states in which electrons are accumulated. Through the presence or absence of electrons held in the two charge accumulation layers 4a and 4b, the change in the threshold value generated is divided into two, corresponding to the number of records in the billion information, " 〇1 ", ,, 1 〇〃, ' , 1 1 〃. Moreover, in this memory lattice structure, the charge accumulation layers 4 a and 4 b are located above the end of the channel range. The threshold of the center of the channel range, and the voltage is determined only by the impurity concentration of the channel range. The state of accumulation of electrons attached to the charge accumulation layers 4 a '4 b. Therefore, it is possible to prevent the excessive electrons of the charge accumulation layers 4 a and 4 b (please read the precautions on the back before filling this page). -------- Order ----- This paper size applies to China National Standard < CNS) A4 Specification (210 X 297 mm) -17- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7 V. Description of Invention (l5) Excessive elimination of sufficient Eliminate the cause of poor bleed, bad program, poor reading, etc. In addition, the bleeder current between the source range and the drain range can be suppressed by the gate voltage only, realizing a highly reliable non-volatile semiconductor memory. The charge accumulation layers 4 a and 4 b may be constituted by a silicon nitride film having a high charge accumulation ability by the C V D method. Due to the discrete charge-trapping potential of the silicon nitride film to accumulate electrons, it is difficult to obtain the charge retention characteristics affected by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be manufactured inexpensively. Furthermore, the first gate insulating film 1 3 and the third gate insulating film 15 are formed of a silicon nitride film (S i 3N4) having a dielectric rate approximately twice that of a silicon oxide film (S i02 film). Film), a very thin gate insulating film with a thickness of about 4 to 11 nm in terms of silicon oxide film can be stably realized. For example, since the silicon nitride film with a thickness of 5 nm as the silicon oxide film has a substantial film thickness of about 10 nm, direct tunnel implantation will not provoke it. Therefore, the voltage at the time of implantation and extraction of the 'electron' is reduced to not only the miniaturization of billions of grids, but also the miniaturization of peripheral high-voltage operating elements. In the memory cell of the non-volatile semiconductor memory according to the second embodiment of the present invention, an η-type diffusion layer 10 is provided for the purpose of increasing the withstand voltage of the source range and the drain range to form an LDD structure. It is also possible to use a single-drain structure and a double-drain structure to form the source range and the drain range. The second gate insulating film 14 can prevent leakage between the charge storage layers 4 a-4 b, and can be made of, for example, a silicon oxide film. When a metal oxide film having a high dielectric constant is used as the second gate insulating film 14, the current transmission characteristic in the center of the channel range can be improved. As a metal oxide, for example, there may be T i 0 2. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) I Jr--I ----- -------- ^ --------- (Please read the notes on the back before filling out this page) -18- 488064 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 ___ V. Description of Invention (16)

Ta2〇5、Al2〇5、PZT、SBT。 接著，對於有關本發明之第2之實施形態的非揮發性 ΐ己憶體之動作，使用圖5 A及圖5 B加以說明。圖5会係 說明寫入動作之非揮發性記憶體之截面圖。圖5 B係說明 消除動作之非揮發性記億體之截面圖。如圖5 A所示，於 記憶格之寫入時，於閘極G施加7〜8 V程度，於汲極D 施加5 V之程度，將源極S加以接地。如此地，施加電壓 時，以通道熱電子，將電子植入汲極範圍側之電荷蓄積層 4 b。於源極範圍側之電荷蓄積層4 a植入電子時，將施 加於各汲極D、源極S之電壓與上述之情形加以置換即可 ，另一方面，記億格之消除係如圖5 B所示，於閘極G施 加負電壓（--5V)，利用FN型隧道電流，自電荷蓄 積層4 a、4 b引出電子地加以進行。又，閘極電極3於 複數之記億格共有之時，自此等之記憶格可伺時引出電子 。此時，源極S、汲極D係呈與p型半導體基板1同電位 即可。又，將與P型半導體基板1之電位不同之正電壓， 施加於汲極D，將源極S呈浮電位之時，可僅由汲極D側 之電荷蓄積層4 a引出電子。僅由源極S側之電荷蓄積層 4 b引出電子之時，於源極S施加正電壓，令汲極D呈浮 電位即可。 記憶格之寫入係與記憶格之消除同樣地，可利用F N 電流加以進行。於閘極G和p型半導體基板1間施加 1 1 0V程度，於FN電流，將電子植入電荷蓄積層4 a ，4 b。此時，閘極G共通之複數記憶格中，可同時植入 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 14------ — — 裝--------訂--------- ΜΨ <請先閱讀背面之注意事項再填寫本頁) -19- 488064 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（i7) 電子。 又，雖未加以圖示，記憶格之讀取係檢測流於源極s 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ， 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 流傳達特性（通道電感）者。對於於源極S、汲極D之何 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態，得4個不 同之電流傳達特性，由此以1個格，可記憶2位元分之資 訊。 接著，將有關本發明之第2之實施形態的非揮發性半 導體記憶體之記憶格之製造方法，使用圖6 A乃至圖6 G 加以說明。首先，如圖6 A所示，於p型半導體基板1 ， 於整面，堆積電荷蓄積能力小之矽氮化膜，形成1 0 n m 之第1閘極電極1 3。電荷蓄積能力小之矽氮化膜之堆積 係例如以J V D法加以進行。對於J V D法而言，例如記 載於參考文獻「T.P.Ma，IEEE Transactions on Electron Devices, Volume 45 Number 3，March 1 998 p680」。形成 第1閘極絕緣膜1 3後，經由C V D法堆積矽氧化膜，形 成5〜1 0 n m程度之第2閘極絕緣膜1 4。接著，經由 J V D法，堆積電荷蓄積能力小之矽氮化膜，形成1 0 n m程度之第3閘極絕緣膜1 5。 接著，如圖6 B所示，於p型半導體基板1整面經由 L P CVD法，堆積滲雜η型或p型不純物之5 0〜 2 5 0 n m之多結晶矽膜後，經由曝光技術及蝕刻技術加 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -------------r AW ^--------^--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 488064 A7 B7___ 五、發明說明（18) 以圖案化，形成閘極電極3。接著，將閘極電極3做爲光 罩，將形成源極範圍及汲極範圍之範圍的P型半導體基板 1之表面的第1閘極絕緣膜1 3、第2閘極絕緣膜1 4及 第3閘極絕緣膜1 5，自我整合地加以乾蝕刻。 接著，如圖6 C所示，形成爲電荷蓄積層形成之空間 1 7。此空間1 7係使用較第1閘極絕緣膜1 3及第3閘 極絕緣膜1 5，第2閘極絕緣膜1 4之蝕刻速度爲大的蝕 刻液，將第2閘極絕緣膜1 4之端部選擇性地以濕蝕刻加 以形成。於本發明之第2之實施形態中，將第1閘極絕緣 膜1 3及第3閘極絕緣膜1 5以矽氮化膜加以構成，將第 2閘極絕緣膜1 4以矽氧化膜加以構成之故，做爲蝕刻液 使用例如氟酸即可。又爲電荷蓄積層形成之空間1 7係替 換使用蝕刻液之濕蝕刻法，以使用包含H F氣體之電漿乾 蝕刻法加以形成亦可。 接著，如圖6 D所示，於ρ型半導體基板1整面，經 由L P CVD法，將電荷蓄積能力高之矽氮化膜1 8，完 全埋入爲電荷蓄積層形成之空間1 7地加以堆積。然後， 如圖6 Ε所厚，對ρ型半導體基板1整面，進行R I Ε之 向異性蝕刻，形成以電荷蓄積能力高之矽氮化膜所構成之 電荷蓄積層4 a及4b。 接著，如圖6 F所示，於ρ型半導體基板1整面，形 成氧化膜1 6之後，形成低不純物濃度之型擴散層1 0 。η -型擴散層1 〇係經由離子植入技術，將閘極電極3做 爲光罩，植入Ν型不純物，經由之後之熱處理，活化植入 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------蠢------裝--------訂--------- (請先閲讀背面之注意事項再填寫本頁) -21， 經濟部智慧財產局員工消費合作社印製 488064 A7 _ B7 五、發明說明（19) 之不純物而形成者。 接著，如圖6 G所示，於1閘極電極3之側壁，形成 側壁間隔9之後，形成高不純物濃度之η +型擴散層1 1。 η +型擴散層1 1係經由離子植入技術，將閘極電極3及側 壁間隔9做爲光罩，植入η型不純物，經由之後之熱處理 活化植入之不純物而加以形成。 接著，於Ρ型半導體基板1之整面，經由CVD法或 濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將ρ 型半導體基板1於不活性氣氛中經由熱處理，於各閘極電 極3、及η+型擴散層1 1之表面，形成以高融點金屬矽化 物所構成之導電層1 2。形成導電層1 2後，除去殘留於 上述以外之範圍的未反應高融點金屬時，可完成圖4所示 之記憶格構造。 然而，雖未圖示，圖1之記憶格構造完成後，順序經 由層間絕緣膜形成工程，連接孔形成工程，配線形成工程 ，鈍化膜形成工程等之通常之CMO S製造工程，完成最 終之非揮發性記憶格。 根據本發明之第2之實施形態時，可將電荷蓄積層 4 a及4 b自我整合形成於閘極電極3之兩端下方。因此 ，可達格電晶體之閘極長方向之微細化。由此’可提供大 容量、高密度之非揮發性半導體記憶體。又每位元之格面 積較以往減少幾近一半，可實現大幅減剃之非揮發性半導 體記憶體。 又，電荷蓄積層4 a及4 b之通道長方向之寬度係經 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝 i------訂-------- · -22- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（20) 由第1閘極絕緣膜1 3及第3閘極絕緣膜1 5和第2閘極 絕緣膜1 4之蝕刻速度差，以及蝕刻時間之調節可容易控 制。由此，可對稱配置電荷蓄積層4 a及4 b。然後，電 荷蓄積層4 a和4 b係經由第2閘極絕緣膜1 4電氣性地 完全分離之故，電荷蓄積層1 4 a及1 4 b間之相互作用 不會產生。更且，電荷蓄積層4 a及4 b係自源極範圍、 閘極電極3及通道範圍，經由第1之絕緣膜1 3 ，第3之 絕緣膜1 5及氧化膜1 6完全加以絕緣之故，可提供電荷 保持性優異之非揮發性半導體記憶體。電荷蓄積層4 a及 4 b係自閘極電極3之端部延伸存在於通道範圍方向加以 形成，經由電荷蓄積層4 a及4 b中之通道範圍側部分之 電荷蓄積狀態，幾乎決定記憶格之電流傳達特性。因此， 將此部分之閘極長方向之長度縮小到極限之時，可提供更 爲微細之非揮發性半導體記憶體。 更且，格構造係可容易實現通常之CM〇S工程之故 ，使用既有之製造生產線，可以低成本製造非揮發性半導 體記憶體。 (第3之實施形態） 接著，說明有關本發明之第3之實施形態。本發明之 第3之實施形態係於圖4所示之第2之實施形態中，將第 1閘極絕緣膜1 3置換爲矽氧化膜，將第2閘極絕緣膜 1 4置換爲矽氮化膜，將第3閘極絕緣膜1 5置換爲矽氧 化膜者。以下，將有關本發明之第3之實施形態之非揮發 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I if-----------裝*------- 訂--------— (請先閱讀背面之注意事項再填寫本頁) -23 - 488064 A7 B7 五、發明說明（21 ) 性半導體記憶體之記憶格之製造方法，參照圖6 A乃至圖 6 C加以說明。 有關於本發明之第3之實施形態之非揮發性半導體記 憶體之記憶格係首先熱氧化P型半導體基板1，形成以 1 0 n m程度之矽氧化膜所構成之第1閘極絕緣膜1 3。 形成第1閘極絕緣膜1 3之後，堆積J D V法之電荷蓄積 能力低之矽氮化膜，形成5〜1 0 n m程度之第2閘極絕 緣膜1 4。接著，經由CVD法堆積矽氧化膜，形成1 〇 n m程度之第3閘極絕緣膜1 5 (參照圖6 A )。 接著，於P型半導體基板1整面，經由L P CVD法 ，堆積滲雜η犁或p型不純物之5 0 nm〜2 5 0之多結 晶矽膜後，經由曝光技術及蝕刻技術加以圖案化，形成閘 極電極3。接著，將閘極電極3做爲光罩，將形成源極範 圍及汲極範圍之範圍的p型半導體基板1之表面的第1閘 極絕緣膜1 3、第2閘極絕緣膜1 4及第3閘極絕緣膜 1 5，自我整合地加以乾蝕刻（參照圖6 B )。 接著，熱氧化P型半導體基板1 ，於P型半導體基板 1整面形成薄矽氧化膜。之後，形成爲電荷蓄積層形成之 空間1 7。此爲電荷蓄積層形成之空間1 7係使用較第1 閘極絕緣膜1 3及第3閘極絕緣膜1 5，第2閘極絕緣膜 1 4之蝕刻速度爲大的蝕刻液，將第2閘極絕緣膜1 4之 端部選擇性地以濕蝕刻加以形成。於本發明之第3之實施 形態中，將第1閘極絕緣膜1 3及第3閘極絕緣膜1 5以 矽氮化膜加以構成，將第2閘極絕緣膜1 4以矽氮化膜加 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) •裝 Ίδ]· I 丽 I 1 經濟部智慧財產局員工消費合作社印製 -24 - 經濟部智慧財產局員工消費合作社印製 488064 Α7 ________ Β7 五、發明說明（22) 以構成之故，做爲鈾刻液使用例如磷酸系即可。然而，第 2閘極絕緣膜1 4係幾乎不會經由熱氧化處理而氧化之故 ，於第2閘極絕緣膜之側面不形成氧化膜，因此提升蝕刻 之選擇性（參照圖6 c )。又，爲電荷蓄積層形成之空間 1 7係替換使用蝕刻液之濕蝕刻法，以使用含c F 4氣體之 氣體的電漿乾蝕刻法加以形成亦可。之後之工程係與第2 之實施形態相同。 (第4之實施形態） 接著，說明有關本發明之第4之實施形態。圖7係顯 示有關本發明之第4之實施形態之非揮發性半導體記憶體 之記憶格構造的截面圖。本發明之第4之實施形態係令記 憶格以P型Μ〇S電晶體加以構成之例者。如圖7所示， 有關本發明之第4之實施形態的非揮發性記憶體之記億格 構造中，於η型半導體基板1 9之表面，介由第1閘極絕 緣膜1 3，設置第2閜極絕緣膜1 4。然後，於第2閘極 絕緣膜14之兩端，形成電荷蓄積層4a ，4b。於第2 閘極絕緣膜1 4及電荷蓄積層4 a、4 b上，介由第3閘 極絕緣膜1 5，設置閘極電極3。於閘極電極3之側面， 介由氧化膜1 6 ，設置側壁間隔9，於此側壁間隔9之下 部之η型半導體基板1 9，設置接觸通道範圍之低不純濃 度之Ρ—型擴散層2 0，和位於此ρ —型擴散層2 0之外側 之高不純物濃度之Ρ+型擴散層2 1。於各閘極電極3及 Ρ+型擴散層2 1之表面，設置導電層12。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) !*llllllnll ·1111111 ^ < — — — — — — (請先閲讀背面之注意事項再填寫本頁) -25- 488064 A7 ___ B7 五、發明說明（23) (請先閱讀背面之注意事項再填寫本頁) 接著，對於有關本發明之第4之實施形態的非揮發性 記憶體之動作，使用圖8 A及圖8 B加以說明。圖8 A係 說明寫入動作之非揮發性記憶體之截面圖。圖8 B係說明 消除動作之非揮發性記憶體之截面圖。如圖8 A所示，於 記憶格之寫入時，於閘極G施加5 V程度，於汲極D施加 - 5 V之程度，將源極S呈浮電位。如此地，施加電壓時 ，於起因帶間隧道現象的電子，於汲極範圍附近之電場供 予能量，將電子植入汲極範圍側之電荷蓄積層4 b。於源 極範圍側之電荷蓄積層4 a植入電子時，將施加於各汲極 D、源極S之電壓與上述之情形加以置換即可，另一方面 ，記憶格之消除係如圖8 B所示，於閘極G施加負電壓（ 〜一5V)，利用FN型隧道電流，自電荷蓄積層4a、 4 b引出電子地加以進行。又，閘極G於複數之記憶格共 有之時，自此等之記憶格可同時引出電子。此時，源極S 及汲極D係呈與η型半導體基板19同電位或呈浮電位即 可〇 經濟部智慧財產局員工消费合作社印製 記憶格之寫入係可如本發明之第2之實施形態之時地 ，利用通道熱電子進行。此時’於閘極G施加一 2 · 5 V 程度，於汲極D施加- 5 V程度’接地源極S。如此地， 施加電壓，以通道熱電子，將電子植入汲極範圍側之電荷 蓄積層4 b。另一方面’於源極範圍側之電荷蓄積層4 a 植入電子之時，交換施加於各汲極D ’源極3的電壓。 又，雖未加以圖示，記億格之讀取係檢測流於源極S 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ’ -26- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（24) 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 流傳達特性（通道電感）者。對於於源極S、汲極D之何 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態，得4個不 同之電流傳達特性，由此以1個格’可記憶2位元分之資 訊。 (第5之實施形態） 接著，說明本發明之第5之實施形態。一般而言，於 半導體記憶體中，於記憶陣列之周邊配置周邊電路。例如 做爲該周邊電路，有解碼器’寫入/消除電路，讀取電路 ，類比電路，各種之I /〇電路’各種之電容電路等。本 發明之第5之實施形態中，顯示將構成此等周邊電路之 M〇S電晶體，使用第2〜第4之實施形態之記憶格電晶 體之製造工程，同時加以製造之例者。如圖9所示’根據 本發明之第5之實施形態時’除記憶格電晶體（記憶格 丁 r )以外，可實現閘極絕緣膜之不同7種之Μ〇S電晶 體（T r 1〜T r 7 )。然而’圖9之記憶格電晶體係如 圖4所示之記億格電晶體。又，Μ〇S電晶體T r 1〜 T r 7係顯示所有η型Μ 0 S電晶體。記憶格電晶體之η — 型擴散層1 0及型擴散層1 1、導電層1 2係爲使圖面 易於看見加以省略。對於Μ 0 S電晶體T r 1〜T r 7亦 相同。 接著，將圖9所示MO S電晶體之製造方法使用圖 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 11-1 I L--1 —--1AW ^ · 11---lit· — —------ (請先閱讀背面之注意事項再填寫本頁) 488064 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（25) 1 〇 A乃至圖1 0 G加以說明。首先，如圖1 0 A所示， 於P型半導體基板1整面，經由J VD法，堆積電荷蓄積 能力小之矽氮化膜，形成1 0 n m之第1閘極電極1 3。 形成第1閘極絕緣膜1 3後，經由周知之曝光技術及乾蝕 刻技術，除去p型半導體基板1上之一部範圍之第1閘極 絕緣膜1 3。接著，如圖1 0 B所示，經由C V D法，堆 積矽氧化膜後，形成5〜1 0 n m程度之第2閘極絕緣膜 1 4。形成第2閘極絕緣膜1 4後，經由曝光技術及蝕刻 技術，除去一部分之範圍之第2閘極絕緣膜1 4。接著， 如圖1 0 C所示，經由J V D法，堆積電荷蓄積能力之小 矽氮化膜，形成1 0 n m程度之第3閘極絕緣膜1 5。形 成第3閘極絕緣膜1 5後，經由曝光技術及蝕刻技術，除 去一部分之範圍之第3閘極絕緣膜1 5。如此，實現第1 閘極絕緣膜1 3、第2閘極絕緣膜1 4及第3閘極絕緣膜 1 5之中至少一個構成的7類閘極絕緣膜。 接著，如圖1 0 D所示，於p型半導體基板1整面經 由L P CVD法，堆積滲雜η型或p型不純物之5 0〜 2 5 0 n m之多結晶矽膜後，經由曝光技術及蝕刻技術加 以圖案化，形成閘極電極3。接著，將閘極電極3做爲光 罩，經由乾蝕刻，除去形成記憶格電晶體、Μ 0 S電晶體 之各源極範圍及沒植範圍的範圍之Ρ型半導體基板1之表 面之第1閘極絕緣膜1 3、第2閘極絕緣膜1 4及第3閘 極絕緣膜1 5。 接著，如圖1 0 Ε所示，將形成Μ 0 S電晶體T r 1 (請先閱讀背面之注意事項再填寫本頁) 裝 ----訂---- 華 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） 488064 A7 B7 五、發明說明（2ό) 〜T R 7範圍以光阻劑2 2加以被覆，將形成記憶格電晶 體的範圍加以濕蝕刻。蝕刻液係利用較第1閘極絕緣膜 1 3及第3閘極絕緣膜1 5，第2閘極絕緣膜1 4之蝕刻 速度爲大者。經由此濕蝕刻，選擇性蝕刻形成記憶格電晶 體之範圍之第2閘極絕緣膜1 4之端部，形成爲電荷蓄積 層形成之空間1 7。於本發明之第5之實施形態中，將第 1閘極絕緣膜1 3及第3閘極絕緣膜1 5以矽氮化膜加以 構成，將第2閘極絕緣膜1 4以矽氧化膜加以構成之故， 做爲蝕刻液例如使用氟酸即可。然後，如圖1 0 F所示， 於Ρ型半導體基板1整面，經由L P CVD法，將電荷蓄 積能力高之矽氮化膜18完全埋入爲電荷蓄積層形成之空 間1 7地加以堆積。然後，如圖1 0 G所示，對ρ型半導 體基板1整面，進行R I Ε之向異性蝕刻，於形成記憶格 電晶體之範圍，形成以電荷蓄積能力高之矽氮化膜所構成 之電荷蓄積層4 a及4 b。之後之工程係與本發明之第2 之實施形態相同。 根據本發明之第5之實施形態時，可將具有膜厚不同 之閘極絕緣膜的7種Μ〇S電晶體T r 1〜丁 r 7 ，與記 憶格電晶體同時製造。由此，可提供對應高電壓動作之高 耐壓電晶體至極低電壓動作電晶體的多樣動作電壓的 Μ〇S電晶體。更且，可共同實現η型Μ〇s電晶體，P 型Μ〇S電晶體。又，記億格電晶體及Μ 0 S電晶體 T r 1〜T r 7之閘極電極3係由同一材料所構成，以同 一之曝光工程及乾蝕刻工程加以形成。因此，提供光罩之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝--------訂---------^9— 經濟部智慧財產局員工消費合作社印製 -29- 488064 經濟部智慧財產局員工消費合作社印製 A7 B7____ 五、發明說明（27) 位置配合偏移少的微細電晶體。 (第6之實施形態） 接著，對於本發明之第6之實施形態加以說明。此第 6之實施形態係顯示將電氣性可寫入消除之非揮發性記憶 體和可高速寫入讀取之揮發性記憶體實現於同一晶片上之 例。圖1 1 A係顯示有關本發明之第6之實施形態的搭載 於半導體記憶裝置的非揮發性記億體之記憶格構造的截面 圖。圖1 1 B係顯示搭載於有關本發明之第6之實施形態 之半導體記億裝置之揮發性半導體記憶體之記憶格構造的 截面圖。圖1 1 A之非揮發性記億體和圖1 1 B之揮發性 記憶體係混合載置於同一晶片者。 (A )非揮發性記億體 如圖1 1 A所示，有關此第6之實施形態之非揮發性 記憶體之記憶格係以η型Μ 0 S電晶體加以構成。然後， 此非揮發性記憶體之記憶格構造中，於Ρ型半導體基板1 之表面，介由閘極絕緣膜1 3，設置第2閘極電極1 4， 於第2閘極電極14之兩端，形成電荷蓄積層4 (4a ， 4 b )。第2閘極絕緣膜1 4及電荷蓄積層4之上側面係 介由氧化膜1 6，設置側壁間隔9 ，於此側壁間隔9之下 部之ρ型半導體基板1之主面中，設置接觸於通道範圍之 低不純物濃度之η —型擴散層1 0，和位置於此η —型擴散 層1 0之外側的高不純物濃度之η +型擴散層1 1。於各閘 極電極3，及η+型擴散層1 1之表面，設置導電層1 2。 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） I-----------n^w ^--------訂·---— I — I (請先閱讀背面之注意事項再填寫本頁) -30- 488064 A7 B7 五、發明說明（28)Ta205, Al205, PZT, SBT. Next, the operation of the non-volatile memory cell according to the second embodiment of the present invention will be described with reference to Figs. 5A and 5B. FIG. 5 is a cross-sectional view of a non-volatile memory illustrating a write operation. Fig. 5B is a cross-sectional view of a non-volatile memory device explaining the elimination action. As shown in FIG. 5A, when the memory cell is written, the source G is applied to the gate G by approximately 7 to 8 V, and the source D is applied to the source 5 by ground. In this way, when a voltage is applied, electrons are channeled to the hot-electron channel and implanted into the charge storage layer 4b on the side of the drain region. When implanting electrons in the charge accumulation layer 4 a on the source range side, the voltage applied to each of the drain electrodes D and S can be replaced with the above situation. As shown in 5B, a negative voltage (-5V) is applied to the gate G, and electrons are extracted from the charge accumulation layers 4a and 4b by using an FN tunneling current. In addition, when the gate electrode 3 is shared by a plurality of hundreds of millions of cells, electrons can be extracted from these memory cells. In this case, the source S and the drain D may be at the same potential as the p-type semiconductor substrate 1. When a positive voltage different from the potential of the P-type semiconductor substrate 1 is applied to the drain D and the source S is at a floating potential, electrons can be extracted only from the charge accumulation layer 4 a on the side of the drain D. When the electrons are extracted only from the charge storage layer 4 b on the source S side, a positive voltage is applied to the source S so that the drain D may have a floating potential. The writing of the memory cell is similar to the erasure of the memory cell, and can be performed by the F N current. An electron of about 110V is applied between the gate G and the p-type semiconductor substrate 1, and electrons are implanted into the charge storage layers 4a, 4b at the FN current. At this time, the common memory cell of the gate G can be simultaneously implanted in the paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 14 --------- ---- Order --------- ΜΨ < Please read the notes on the back before filling out this page) -19- 488064 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention ( i7) Electronics. Also, although not shown, the reading of the memory cell is performed by detecting the reading current flowing between the source s and the drain D. Through the accumulation states of the charge accumulation layers 4a and 4b, the current transfer characteristics (channel inductance) in the vicinity of the source range and the drain range are modulated. For biasing between the source S and the drain D, it is sufficient to select a person whose modulation of the current transmission characteristic is significant. Through the four accumulation states of the charge accumulation layers 4a and 4b, four different current transfer characteristics are obtained, so that one bit can memorize the information of 2 bits. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory device according to a second embodiment of the present invention will be described with reference to Figs. 6A to 6G. First, as shown in FIG. 6A, a silicon nitride film having a small charge accumulation ability is deposited on the entire p-type semiconductor substrate 1 to form a first gate electrode 13 of 10 nm. The deposition of a silicon nitride film having a small charge accumulation ability is performed by, for example, the J V D method. For the J V D method, for example, it is described in the reference "T.P.Ma, IEEE Transactions on Electron Devices, Volume 45 Number 3, March 1 998 p680". After the first gate insulating film 13 is formed, a silicon oxide film is deposited by the CVD method to form a second gate insulating film 14 of about 5 to 10 nm. Next, a silicon nitride film having a small charge storage capacity is deposited by the J V D method to form a third gate insulating film 15 having a size of about 10 nm. Next, as shown in FIG. 6B, a polycrystalline silicon film doped with η-type or p-type impurities of 50 to 250 nm is deposited on the entire surface of the p-type semiconductor substrate 1 by the LP CVD method. Etching technology plus paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------------- r AW ^ -------- ^ --- ------ (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7___ V. Description of the invention (18) The gate electrode 3 is patterned. Next, using the gate electrode 3 as a photomask, the first gate insulating film 1 3, the second gate insulating film 1 4 and the second gate insulating film 1 on the surface of the P-type semiconductor substrate 1 forming the source range and the drain range are formed. The third gate insulating film 15 is self-integrated and dry-etched. Next, as shown in Fig. 6C, a space 17 is formed as a charge accumulation layer. This space 17 uses an etching solution having a higher etching rate than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 and the second gate insulating film 1 The ends of 4 are selectively formed by wet etching. In the second embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are formed of a silicon nitride film, and the second gate insulating film 14 is a silicon oxide film. For the constitution, for example, fluoric acid may be used as the etchant. The space 17 formed by the charge accumulation layer may be formed by replacing the wet etching method using an etchant with a plasma dry etching method using H F gas. Next, as shown in FIG. 6D, a silicon nitride film 18 having a high charge accumulation ability is completely buried in the space formed by the charge accumulation layer 17 over the entire surface of the p-type semiconductor substrate 1 through the LP CVD method. accumulation. Then, as shown in FIG. 6E, the entire surface of the p-type semiconductor substrate 1 is anisotropically etched with R I E to form charge storage layers 4a and 4b composed of a silicon nitride film having a high charge storage capability. Next, as shown in FIG. 6F, an oxide film 16 is formed on the entire surface of the p-type semiconductor substrate 1, and then a type diffusion layer 10 having a low impurity concentration is formed. The η-type diffusion layer 10 uses gate electrode 3 as a photomask through ion implantation technology, implants N-type impurities, and activates the implantation after subsequent heat treatment. This paper applies the Chinese National Standard (CNS) A4 specification. (210 X 297 mm) ------ Stupid ------ Installed -------- Order --------- (Please read the precautions on the back before filling in this Page) -21, printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 _ B7 V. The invention was created by the impure substance of (19). Next, as shown in FIG. 6G, a sidewall gap 9 is formed on the side wall of 1 gate electrode 3, and then an η + -type diffusion layer 11 having a high impurity concentration is formed. The η + -type diffusion layer 11 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask by implanting η-type impurities through a subsequent heat treatment to activate the implanted impurities. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method or a sputtering method, and then the p-type semiconductor substrate 1 is heat-treated in an inactive atmosphere. On the surfaces of the gate electrodes 3 and the η + type diffusion layer 11, a conductive layer 12 made of a high melting point metal silicide is formed. When the conductive layer 12 is formed and the unreacted high-melting-point metal remaining in a range other than the above is removed, the memory cell structure shown in Fig. 4 can be completed. However, although not shown, after the memory cell structure in FIG. 1 is completed, the usual CMO S manufacturing processes such as the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process are completed in order. Volatile memory cells. According to the second embodiment of the present invention, the charge storage layers 4 a and 4 b can be formed by self-integration under both ends of the gate electrode 3. Therefore, the miniaturization of the gate electrode in the long direction can be achieved. This' can provide a large-capacity, high-density non-volatile semiconductor memory. In addition, the grid area per bit is reduced by almost half compared with the past, which can realize a substantial reduction in shaved non-volatile semiconductor memory. In addition, the widths of the channels in the length direction of the charge accumulation layers 4 a and 4 b are in accordance with the Chinese national standard (CNS) A4 specification (210 X 297 mm) according to this paper standard (please read the precautions on the back before filling this page)- Equipment i ------ Order -------- · -22- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7 V. Description of the invention (20) The first gate insulating film 1 3 The difference in etching speed between the third gate insulating film 15 and the second gate insulating film 14 and the adjustment of the etching time can be easily controlled. Thereby, the charge storage layers 4 a and 4 b can be arranged symmetrically. Then, since the charge accumulation layers 4 a and 4 b are electrically and completely separated through the second gate insulating film 14, the interaction between the charge accumulation layers 14 a and 14 b is not generated. Furthermore, the charge accumulation layers 4 a and 4 b are completely insulated from the source region, the gate electrode 3 and the channel region through the first insulating film 1 3, the third insulating film 15 and the oxide film 16. Therefore, a nonvolatile semiconductor memory having excellent charge retention can be provided. The charge accumulation layers 4 a and 4 b are formed by extending from the ends of the gate electrode 3 and existing in the channel range direction. The charge accumulation state of the channel range side portions in the charge accumulation layers 4 a and 4 b almost determines the memory cell. The current transfer characteristics. Therefore, when the length of the gate length in this portion is reduced to the limit, a finer nonvolatile semiconductor memory can be provided. What's more, the lattice structure can easily realize the usual CMOS project. Using the existing manufacturing production line, non-volatile semiconductor memory can be manufactured at low cost. (Third Embodiment) Next, a third embodiment of the present invention will be described. The third embodiment of the present invention is the second embodiment shown in FIG. 4 in which the first gate insulating film 13 is replaced with a silicon oxide film, and the second gate insulating film 14 is replaced with silicon nitrogen. Film, and the third gate insulating film 15 is replaced with a silicon oxide film. In the following, the dimensions of the non-volatile paper in accordance with the third embodiment of the present invention are applied to the Chinese National Standard (CNS) A4 (210 X 297 mm) I if ----------- install *- ------ Order ---------- (Please read the precautions on the back before filling out this page) -23-488064 A7 B7 V. Description of the invention (21) The manufacturing method will be described with reference to FIGS. 6A to 6C. The memory cell of the non-volatile semiconductor memory according to the third embodiment of the present invention is firstly thermally oxidizing the P-type semiconductor substrate 1 to form a first gate insulating film 1 composed of a silicon oxide film having a degree of 10 nm. 3. After the first gate insulating film 13 is formed, a silicon nitride film having a low charge storage capacity by the J DV method is deposited to form a second gate insulating film 14 having a size of 5 to 10 nm. Next, a silicon oxide film is deposited by a CVD method to form a third gate insulating film 15 having a size of about 10 nm (see FIG. 6A). Next, on the entire surface of the P-type semiconductor substrate 1, a polycrystalline silicon film doped with η plow or p-type impurities of 50 nm to 250 is deposited on the entire surface of the P-type semiconductor substrate 1 by patterning through exposure and etching techniques. Forming a gate electrode 3. Next, using the gate electrode 3 as a photomask, the first gate insulating film 1 3, the second gate insulating film 1 4 and the surface of the p-type semiconductor substrate 1 forming a range of a source range and a drain range are formed, and The third gate insulating film 15 is self-integrated and dry-etched (see FIG. 6B). Next, the P-type semiconductor substrate 1 is thermally oxidized, and a thin silicon oxide film is formed on the entire surface of the P-type semiconductor substrate 1. Thereafter, a space 17 is formed as a charge storage layer. The space 17 formed by the charge accumulation layer uses an etching solution having a higher etching rate than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14. The ends of the 2 gate insulating film 14 are selectively formed by wet etching. In the third embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are made of a silicon nitride film, and the second gate insulating film 14 is made of silicon nitride. The size of the film plus paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling out this page) • Decoration δ] · I Li I 1 Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumption Printed by Cooperatives-24-Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 Α7 ________ Β7 V. Description of the Invention (22) For the purpose of construction, phosphoric acid can be used as the engraving solution. However, since the second gate insulating film 14 is hardly oxidized by a thermal oxidation treatment, an oxide film is not formed on the side of the second gate insulating film, so the selectivity of etching is improved (see FIG. 6 c). The space 17 formed for the charge accumulation layer may be formed by a plasma dry etching method using a gas containing c F 4 gas instead of a wet etching method using an etchant. The subsequent process is the same as the second embodiment. (Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. Fig. 7 is a sectional view showing a memory cell structure of a nonvolatile semiconductor memory according to a fourth embodiment of the present invention. The fourth embodiment of the present invention is an example in which the memory cell is constituted by a P-type MOS transistor. As shown in FIG. 7, in the terabyte structure of the non-volatile memory according to the fourth embodiment of the present invention, a surface of the n-type semiconductor substrate 19 is provided with a first gate insulating film 13 interposed therebetween.第 2 閜 electrode insulating film 1 4. Then, on both ends of the second gate insulating film 14, charge storage layers 4a, 4b are formed. A gate electrode 3 is provided on the second gate insulating film 14 and the charge accumulation layers 4 a and 4 b via a third gate insulating film 15. On the side of the gate electrode 3, a sidewall spacer 9 is provided through an oxide film 16. A n-type semiconductor substrate 19 below the sidewall spacer 9 is provided with a P-type diffusion layer 2 having a low impurity concentration in a contact channel range. 0, and a P + -type diffusion layer 21 with a high impurity concentration on the outside of the p-type diffusion layer 2 0. A conductive layer 12 is provided on the surface of each gate electrode 3 and the P + -type diffusion layer 21. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)! * Llllllnll · 1111111 ^ < — — — — — — (Please read the notes on the back before filling out this page) -25- 488064 A7 ___ B7 V. Explanation of the invention (23) (Please read the notes on the back before filling this page) Then, for the operation of the non-volatile memory of the fourth embodiment of the present invention, use FIG. 8A and FIG. 8 B. FIG. 8A is a cross-sectional view of a nonvolatile memory illustrating a write operation. Fig. 8B is a cross-sectional view of the nonvolatile memory illustrating the erasing operation. As shown in FIG. 8A, when the memory cell is written, the source G is applied with a potential of 5 V and the drain D is applied with -5 V, so that the source S is at a floating potential. In this way, when a voltage is applied, the electrons that cause the phenomenon of the inter-band tunneling are supplied with energy in an electric field near the drain region, and the electrons are implanted into the charge accumulation layer 4 b on the drain region side. When the electrons are implanted in the charge accumulation layer 4 a on the source range side, the voltages applied to the respective drains D and S can be replaced with those described above. On the other hand, the memory cell is eliminated as shown in FIG. 8 As shown in B, a negative voltage (~ -5V) is applied to the gate G, and electrons are extracted from the charge accumulation layers 4a and 4b by using an FN-type tunneling current. In addition, when the gate G has a plurality of memory cells in common, electrons can be simultaneously extracted from these memory cells. At this time, the source S and the drain D may be at the same potential as the n-type semiconductor substrate 19 or at a floating potential. The writing system of the memory cell printed by the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs may be the same as the second one This embodiment is performed using channel hot electrons. At this time, the gate electrode G is applied with a degree of 2 · 5 V, and the drain electrode D is applied with a degree of -5 V to the ground source S. In this way, a voltage is applied to channel the hot electrons, and the electrons are implanted into the charge storage layer 4b on the side of the drain region. On the other hand, when the electrons are implanted in the charge storage layer 4a on the source side, the voltage applied to each drain D 'source 3 is exchanged. In addition, although not shown in the figure, the reading of 100 million grids is performed by detecting the reading current flowing between the source S and the drain D. Via charge accumulating layer 4 a '-26- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 public love) Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 488064 A7 B7 V. Description of invention (24) 4 The accumulation state of b uses the current transmission characteristics (channel inductance) in the vicinity of the modulation source range and drain range. For biasing between the source S and the drain D, it is sufficient to select a person whose modulation of the current transmission characteristic is significant. Through the four accumulation states of the charge accumulation layers 4a and 4b, four different current transfer characteristics are obtained, and thus 2 bits of information can be memorized with one division. (Fifth Embodiment) Next, a fifth embodiment of the present invention will be described. Generally speaking, in semiconductor memory, peripheral circuits are arranged around the memory array. For example, as the peripheral circuit, there are a decoder 'write / erase circuit, a read circuit, an analog circuit, various I / O circuits, and various capacitor circuits. The fifth embodiment of the present invention shows an example in which the MOS transistors that will constitute these peripheral circuits are manufactured at the same time by using the memory cell transistors of the second to fourth embodiments. As shown in FIG. 9 'in the case of the fifth embodiment of the present invention', in addition to the memory grid transistor (memory grid D r), 7 different types of MOS transistors (T r 1 ~ T r 7). However, the memory lattice transistor system of FIG. 9 is shown in FIG. The MOS transistors T r 1 to T r 7 show all n-type M 0 S transistors. The η-type diffusion layer 10, the type diffusion layer 11 and the conductive layer 12 of the memory lattice transistor are omitted to make the drawing easier to see. The same applies to the M 0 S transistors T r 1 to T r 7. Next, the manufacturing method of the MOS transistor shown in FIG. 9 using the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 public love) 11-1 I L--1 —-- 1AW ^ · 11 --- lit · — —------ (Please read the notes on the back before filling out this page) 488064 A7 B7 Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description (25) 1 〇A and even Figure 10 G illustrates. First, as shown in FIG. 10A, a silicon nitride film having a small charge storage capacity is deposited on the entire surface of the P-type semiconductor substrate 1 through the JVD method to form a first gate electrode 13 of 10 nm. After the first gate insulating film 13 is formed, the first gate insulating film 13 on a portion of the p-type semiconductor substrate 1 is removed by a well-known exposure technique and a dry etching technique. Next, as shown in FIG. 10B, a silicon oxide film is deposited by the CVD method to form a second gate insulating film 14 having a thickness of 5 to 10 nm. After the second gate insulating film 14 is formed, a part of the second gate insulating film 14 is removed through an exposure technique and an etching technique. Next, as shown in FIG. 10C, a silicon nitride film having a small charge accumulation ability is deposited by the JVD method to form a third gate insulating film 15 having a size of about 10 nm. After the third gate insulating film 15 is formed, a part of the third gate insulating film 15 is removed through an exposure technique and an etching technique. In this way, a type 7 gate insulating film composed of at least one of the first gate insulating film 1 3, the second gate insulating film 14 and the third gate insulating film 15 is realized. Next, as shown in FIG. 10D, a polycrystalline silicon film doped with η-type or p-type impurities of 50 to 250 nm is deposited on the entire surface of the p-type semiconductor substrate 1 by LP CVD, and then exposed to light. And an etching technique to pattern the gate electrode 3. Next, using the gate electrode 3 as a photomask, the first surface of the P-type semiconductor substrate 1 in the range of the source range and the non-implanted range of the memory cell transistor and the M 0S transistor is removed by dry etching. The gate insulating film 1 3, the second gate insulating film 14 and the third gate insulating film 15. Next, as shown in Figure 10E, an M 0 S transistor T r 1 will be formed (please read the precautions on the back before filling this page). Standard < CNS) A4 specification (210 X 297 mm) 488064 A7 B7 V. Description of invention (2) ~ TR 7 is covered with photoresist 22, and the area where the memory cell transistor is formed is wet etched. As the etching solution, the etching speed is higher than that of the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14. After this wet etching, the ends of the second gate insulating film 14 in the range of the memory cell crystal are selectively etched to form a space 17 formed by the charge accumulation layer. In the fifth embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are formed of a silicon nitride film, and the second gate insulating film 14 is a silicon oxide film. For the constitution, for example, fluoric acid may be used as the etching solution. Then, as shown in FIG. 10F, a silicon nitride film 18 having a high charge storage ability is completely buried in the space formed by the charge storage layer 17 and stacked on the entire surface of the P-type semiconductor substrate 1 through the LP CVD method. . Then, as shown in FIG. 10G, the entire surface of the p-type semiconductor substrate 1 is anisotropically etched with RI and EI, and a silicon nitride film having a high charge storage capacity is formed in a range where a memory cell transistor is formed. The charge storage layers 4 a and 4 b. The subsequent process is the same as the second embodiment of the present invention. According to the fifth embodiment of the present invention, seven types of MOS transistors T r 1 to D r 7 having gate insulating films having different film thicknesses can be manufactured simultaneously with the memory transistor. This makes it possible to provide MOS transistors with a wide range of operating voltages from high withstand voltage crystals operating to high voltages to extremely low voltage operating transistors. Moreover, n-type MOS transistor and P-type MOS transistor can be realized together. In addition, the gate electrode 3 of the billion grid transistor and the M 0 S transistor T r 1 to T r 7 are made of the same material and are formed by the same exposure process and dry etching process. Therefore, the size of the paper provided with the photomask is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page). ------- ^ 9— Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics -29- 488064 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economics A7 B7____ V. Description of the invention (27) Subtle shifting of position Transistor. (Sixth Embodiment) Next, a sixth embodiment of the present invention will be described. This sixth embodiment shows an example in which the nonvolatile memory that is electrically writeable and erasable and the volatile memory that can be read and written at high speed are implemented on the same chip. Fig. 11A is a cross-sectional view showing a memory cell structure of a nonvolatile memory device mounted on a semiconductor memory device according to a sixth embodiment of the present invention. Fig. 11B is a cross-sectional view showing a memory cell structure of a volatile semiconductor memory mounted on a semiconductor memory device according to a sixth embodiment of the present invention. The non-volatile memory of Fig. 1 A and the volatile memory system of Fig. 1 B are mixed and placed on the same chip. (A) Non-volatile memory memory As shown in FIG. 1A, the memory cell of the non-volatile memory of the sixth embodiment is constituted by an n-type M0S transistor. Then, in the memory cell structure of this non-volatile memory, a second gate electrode 14 is provided on the surface of the P-type semiconductor substrate 1 through a gate insulating film 13 and two of the second gate electrode 14 are provided. End, a charge accumulation layer 4 (4a, 4b) is formed. The upper side surfaces of the second gate insulating film 14 and the charge accumulation layer 4 are provided with sidewall spacers 9 through an oxide film 16. A main surface of the p-type semiconductor substrate 1 below the sidewall spacers 9 is provided to contact The η-type diffusion layer 10 with a low impurity concentration in the channel range and the η + -type diffusion layer 11 with a high impurity concentration located outside the η-type diffusion layer 10. A conductive layer 12 is provided on each of the gate electrodes 3 and the surfaces of the n + -type diffusion layer 11. This paper size applies to Chinese National Standards < CNS) A4 specifications (210 X 297 mm) I — I (Please read the notes on the back before filling this page) -30- 488064 A7 B7 V. Description of the invention (28)

有關本發明之第6之實施形態之非揮發性半導體記憶 體之記憶格係具有將源極範圍及汲極範圍以低不純物濃度 之η —型擴散層1 〇和高不純物濃度之n+型擴散層1 1構 成之L D D構造。然後，閘極絕緣膜以第1閘極絕緣膜 1 3 (下層）、第2閘極絕緣膜1 4 (中間層）及第3閘 極絕緣膜1 5 (上層）所成三層堆積膜加以構成，於第2 閘極絕緣膜1 4之兩端部形成電荷蓄積層4 ( 4 a、4七 )。於此2個之電荷蓄積層4 a及4 b蓄積電子，該蓄積 狀態係可有（1 )電荷蓄積層4 a、4 b之任一者皆末蓄 積電子之狀態，（2 )僅電荷蓄積層4 a蓄積電子之狀態 ，（3 )僅電荷蓄積層4 b蓄積電子之狀態，（4 )電荷 蓄積層4 a ，4 b皆蓄積電子之狀態之4個狀態。經由保 持於此2個之電荷蓄積層4 a ，4 b之電子之有無，將所 產生之臨限値之變化分，對應於記憶資訊之'' 0 0 〃 ， VN 0 1〃 ， '' 1 0 〃 ， '' 1 1 〃 。又，於此記憶格構造之中 ，電荷蓄積層4係位於通道範圍端部之上方之故，通道範 圍中央部之臨限値電壓係僅以通道範圍之不純物濃度加以 決定，不依附於電荷蓄積層4之電子之蓄積狀態。因此， 可防止電荷蓄積層4之電子之過度不足的過度消除，由此 不會產生由於過度消除起因的泄放不良，程式不良，讀取 不良等。又，源極範圍和汲極範圍間之泄放電流係可僅以 閘極電壓加以抑制，實現高可靠性之非揮發性半導體記憶 體。電荷蓄積層4係以C VD法之電荷蓄積能力高的矽氮 化膜加以構成即可。經由於矽氮化膜之離散性之電荷捕獲 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝·！!_ 訂 -------- 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 488064 A7 一 B7 五、發明說明（29) 準位蓄積電子，可得難以於下部絕緣膜之膜質影響之電荷 保持特性。又，以矽膜，多結晶矽膜加以構成之時’可便 宜地加以製造。更且，將第1閘極絕緣膜1 3、第3閘極 絕緣膜1 5以具有矽氧化膜（S i 〇2膜）之2倍程度之介 電率的矽氮化膜（S i 3N4膜）加以構成時，可將矽氧化 膜換算膜厚爲4〜11nm程度之非常薄的閘極絕緣膜安 定實現。例如，矽氧化膜換算膜厚爲5 nm之矽氮化膜之 實質膜厚爲1 〇 nm程度之故，直接進行隧道植入亦不會 激勵。因此，電子之植入抽出時之電壓係被低電壓化，不 單是記億格之微細化，亦可達周邊高電壓動作元件之微細 化。 有關本發明之第6之實施形態之非揮發性半導體記憶 體之記憶格中，於源極範圍及汲極範圍之耐壓提升之目的 上，設置η —型擴散層1 〇，以構成L D D構造，以單汲極 構造，雙汲極構造構成源極範圍及汲極範圍亦可。第2閘 極絕緣膜1 4係雖可防止電荷蓄積層4 a — 4 b間之泄放 -，例如可以矽氧化膜構成。又，於第2閘極絕緣膜1 4使 用具有高介電率之金屬氧化膜時，可提升通道範圍中央之 電流傳達特性。做爲金屬氧化物例如可有T i〇2、 Ta2〇5、Al2〇5、PZT、SBT。 接著，對於有關本發明之第6之實施形態的非揮發性 記憶體之動作，使用圖1 2 A及圖1 2 B加以說明。圖 1 2 A係說明寫入動作之非揮發性記憶體之截面圖。圖 1 2 B係說明消除動作之非揮發性記憶體之截面圖。如圖 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） I -----—J----裝--------訂--------- (請先閲讀背面之注意事項再填寫本頁) -32 - 經濟部智慧財產局員工消費合作社印製 488064 A7 ........ B7 五、發明說明（30)The memory cell of the non-volatile semiconductor memory according to the sixth embodiment of the present invention has an η-type diffusion layer 10 with a source range and a drain range at a low impurity concentration and an n + -type diffusion layer with a high impurity concentration. 1 1 constitutes the LDD structure. Then, the gate insulating film is a three-layer stacked film formed of a first gate insulating film 1 3 (lower layer), a second gate insulating film 1 4 (middle layer), and a third gate insulating film 15 (upper layer). It is configured that the charge accumulation layers 4 (4 a, 47) are formed on both ends of the second gate insulating film 14. The two charge accumulation layers 4 a and 4 b accumulate electrons, and the state of accumulation may be (1) either of the charge accumulation layers 4 a and 4 b does not accumulate electrons, and (2) only the charge accumulation The state in which layer 4 a accumulates electrons, (3) the state in which only the charge accumulation layer 4 b accumulates electrons, and (4) the state in which the charge accumulation layers 4 a and 4 b accumulate electrons. Through the existence of the electrons held in the two charge accumulation layers 4 a and 4 b, the change in the threshold value 値 generated is divided into '' 0 '' 之, VN 0 1 ， 1 0 〃, '' 1 1 〃. In addition, in this memory lattice structure, the charge accumulation layer 4 is located above the end of the channel range. The threshold voltage at the center of the channel range is determined only by the impurity concentration in the channel range, and does not depend on the charge accumulation. State of accumulation of electrons in layer 4. Therefore, it is possible to prevent excessive elimination of excessive electron shortages in the charge accumulation layer 4, thereby preventing occurrence of defective discharge, defective programming, poor reading, and the like due to excessive elimination. In addition, the bleeder current between the source range and the drain range can be suppressed by the gate voltage only, realizing a highly reliable non-volatile semiconductor memory. The charge storage layer 4 may be constituted by a silicon nitride film having a high charge storage capability by the C VD method. Charge capture due to the discreteness of the silicon nitride film This paper is sized for China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). ! _ Order -------- Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economics Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economics 488064 A7-B7 V. Description of the Invention (29) Accumulated electronics at the standard level, difficult The charge retention characteristics affected by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be easily manufactured. Furthermore, the first gate insulating film 1 3 and the third gate insulating film 15 are made of a silicon nitride film (S i 3N4) having a dielectric constant approximately twice that of a silicon oxide film (S i 〇2 film). Film), it is possible to stably realize a very thin gate insulating film with a silicon oxide film conversion film thickness of about 4 to 11 nm. For example, since the silicon nitride film with a thickness of 5 nm is a silicon nitride film with a substantial thickness of about 10 nm, direct tunnel implantation will not encourage it. Therefore, the voltage at the time of implantation and extraction of electrons is reduced, not only the miniaturization of billions of grids, but also the miniaturization of peripheral high-voltage operating elements. In the memory cell of the nonvolatile semiconductor memory according to the sixth embodiment of the present invention, an η-type diffusion layer 10 is provided for the purpose of improving the withstand voltage of the source range and the drain range to form an LDD structure. It is also possible to use a single-drain structure and a double-drain structure to form the source range and the drain range. The second gate insulating film 14 can prevent the charge accumulation layers 4 a-4 b from leaking out, and can be made of, for example, a silicon oxide film. When a metal oxide film having a high dielectric constant is used as the second gate insulating film 14, the current transmission characteristic in the center of the channel range can be improved. Examples of the metal oxide include Ti 102, Ta205, Al205, PZT, and SBT. Next, the operation of the nonvolatile memory according to the sixth embodiment of the present invention will be described with reference to FIGS. 12A and 12B. FIG. 12A is a cross-sectional view of a nonvolatile memory illustrating a write operation. Figure 12B is a cross-sectional view of the non-volatile memory illustrating the erasing action. As shown in the figure, the paper size applies the Chinese National Standard < CNS) A4 specification (210 X 297 mm) I ------- J ---- installation -------- order ------ --- (Please read the notes on the back before filling out this page) -32-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 ........ B7 V. Invention Description (30)

1 2 A所示，於記憶格之寫入時，於閘極G施加7〜8 V 程度’於汲極D施加5 V之程度，將源極S加以接地。如 此地’施加電壓時，以通道熱電子，將電子植入汲極範圍 側之電荷蓄積層4 b。於源極範圍側之電荷蓄積層4 b植 入電子時，將施加於各汲極D、源極S之電壓與上述之情 形加以置換即可，另一方面，記憶格之消除係如圖1 2 B 所示，於閘極G施加負電壓（--5V)，利用FN型隧 道電流，自電荷蓄積層4 a、4 b引出電子地加以進行。 又’閘極G於複數之記憶格共有之時，自此等之記憶格可 同時引出電子。此時，源極S、汲極D係呈與p型半導體 基板1同電位即可。又，將與p型半導體基板1之電位不 同之正電壓'施加於汲極電極，將源極電極呈浮電位之時 ，可僅由汲極電極側之電荷蓄積層4 a引出電子。僅由源 極電極側之電荷蓄積層4 b引出電子之時，於源極電極施 加正電壓，令汲極電極呈浮電位即可。 記憶格之寫入係與記憶格之消除同樣地，可利用F N 電流加以進行。於閘極G和p型半導體基板1間施加 10V程度，於FN電流，將電子植入電荷蓄積層4a ， 4 b。此時，閘極G共通之複數記億格中，可同時植入電 子。 又，雖未加以圖示，記憶格之讀取係檢測流於源極S 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ， 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 流傳達特性（通道電感）者。對於於源極s、汲極D之何 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） — .lilll—Ί — — ^------1 — t_!! (請先閱讀背面之注意事項再填寫本頁) -33- 經濟部智慧財產局員工消費合作社印製 488064 Α7 _ Β7 五、發明說明（31) 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態，得4個不 同之電流傳達特性，由此以1個格，可記憶2位元分之資 訊。 (B )揮發性記億體 如圖1 1 B所示，有關此第6之實施形態之揮發性記 億體之記億格係以η型Μ 0 S電晶體加以構成。此揮發性 記憶體之記憶格構造中，於Ρ型半導體基板1之主面，直 接配置圖1 1 Α之第2閘極絕緣膜1 4。然後，於第2閘 極電極1 4之兩端，與圖1 1 A之非揮發性記憶體同樣地 ，形成電荷蓄積層4 (4c，4d)。此電荷蓄積層4c 及4d介由隧道絕緣膜21 ，配置於P型半導體基板1之 主面上之部分與圖1 1 A之非揮發性記憶體不同。於第2 閘極絕緣膜1 4及電荷蓄積層4上係介由第3閘極絕緣膜 1 5 ，設置閘極電極3。於閘極電極3之側面，介由氧化 膜1 6設置側壁間隔9 ，於此側壁間隔9之下部之P型半 導體基板1之主面中，設置接觸於通道範圍之低不純物濃 度之η —型擴散層1 0，和位置於此η —型擴散層1 0之外 側的高不純物濃度之η +型擴散層1 1。於各閘極電極3， 及η+型擴散層1 1之表面，設置導電層1 2。 有關本發明之第6之實施形態之揮發性半導體記憶體 之記憶格係具有將源極範圍及汲極範圍以低不純物濃度之 η —型擴散層1 0和高不純物濃度之η+型擴散層1 1構成 之L D D構造。然後，閘極絕緣膜以第2閘極絕緣膜1 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) il---,II.---I — ------訂------ —— (請先閱讀背面之注意事項再填寫本頁) -34- 經濟部智慧財產局員工消費合作社印製 488064 A7 _____B7___ 五、發明說明（32) 、隧道絕緣膜2 3及第3閘極絕緣膜1 5所構成，於第2 閘極絕緣膜1 4之兩端部形成電荷蓄積層4。於此2個之 電荷蓄積層4 c及4 d蓄積電子，該蓄積狀態係可有（1 )電荷蓄積層4 c、4 d之任一者皆未蓄積電子之狀態， (2 )僅電荷蓄積層4 c蓄積電子之狀態，（3 )僅電荷 蓄積層4d蓄積電子之狀態，（4)電荷蓄積層4c， 4 d皆蓄積電子之狀態之4個狀態。經由保持於此2個之 電荷蓄積層4 c ，4 d之電子之有無，將所產生之臨限値 之變化分，對應於記憶資訊之'' 0 0 〃 ， A 0 1 〃 ，vv 10〃 ， ''11〃 。又，於此記億格構造之中，電荷蓄積 層4係位於通道範圍端部之上方之故，通道範圍中央部之 臨限値電壓係僅以通道範圍之不純物濃度加以決定，不依 附於電荷蓄積層4之電子之蓄積狀態。因此，可防止電荷 蓄積層4之電子之過度不足的過度消除，由此不會產生由 於過度消除起因的泄放不良，程式不良，讀取不良等。又 ，源極範圍和汲極範圍間之泄放電流係可僅以閘極電壓加 以抑制，實現高可靠性之非揮發性半導體記憶體。電荷蓄 積層4係以C V D法之電荷蓄積能力高的矽氮化膜加以構 成即可。經由於矽氮化膜之離散性之電荷捕獲準位蓄積電 子，可得難以於下部絕緣膜之膜質影響之電荷保持特性。 又，以矽膜，多結晶矽膜加以構成之時’可便宜地加以製 造。更且，將第3閘極絕緣膜1 5以具有矽氧化膜（ 5 i〇2膜）之2倍程度之介電率的矽氮化膜（S i 3N4 膜）加以構成時，可將矽氧化膜換算膜厚爲4〜1 1 nm I -------ml ^ ---I-----^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -35- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（33) 程度之非常薄的閘極絕緣膜安定實現。例如’矽氧化膜換 算膜厚爲5 nm之矽氮化膜之實質膜厚爲1 〇 nm程度之 故，直接進行隧道植入亦不會激勵。因此，電子之植入抽 出時之電壓係被低電壓化，不單是記憶格之微細化’亦可 達周邊高電壓動作元件之微細化。 有關本發明之第6之實施形態之非揮發性半導體記憶 體之記憶格中，於源極範圍及汲極範圍之耐壓提升之目的 上，設置η —型擴散層1 0，以構成LDD構造’以單汲極 構造，雙汲極構造構成源極範圍及汲極範圍亦可。第2閘 極絕緣膜1 4係雖可防止電荷蓄積層4 c 一 4 d間之泄放 ，例如可以矽氧化膜構成。又，於第2閘極絕緣膜1 4使 用具有高介電率之金屬氧化膜時，可提升通道範圍中央之 電流傳達特性。做爲金屬氧化物例如可有T i 0 2、 Ta2〇5、Al2〇5、PZT、SBT。As shown in FIG. 2A, at the time of writing in the memory cell, about 7 to 8 V is applied to the gate G 'to about 5 V to the drain D, and the source S is grounded. When a voltage is applied here, electrons are channeled to the hot-electrons and implanted into the charge storage layer 4b on the drain side. When electrons are implanted in the charge accumulation layer 4 b on the source range side, the voltages applied to the respective drains D and S can be replaced with those described above. On the other hand, the memory cell is eliminated as shown in Figure 1 As shown in 2B, a negative voltage (-5V) is applied to the gate G, and an electron is extracted from the charge accumulation layers 4a and 4b by using an FN-type tunneling current. When the gate G is shared by a plurality of memory cells, electrons can be simultaneously extracted from these memory cells. In this case, the source S and the drain D may be at the same potential as the p-type semiconductor substrate 1. When a positive voltage 'different from the potential of the p-type semiconductor substrate 1 is applied to the drain electrode and the source electrode is at a floating potential, electrons can be extracted only from the charge storage layer 4 a on the drain electrode side. When the electrons are extracted only by the charge storage layer 4b on the source electrode side, a positive voltage may be applied to the source electrode so that the drain electrode has a floating potential. The writing of the memory cell is similar to the erasure of the memory cell, and can be performed by the F N current. Approximately 10 V is applied between the gate G and the p-type semiconductor substrate 1, and electrons are implanted into the charge storage layers 4a, 4b at the FN current. At this time, electrons can be implanted at the same time in the hundreds of millions of grids common to the gate G. Also, although not shown, the reading of the memory cell is performed by detecting the reading current flowing between the source S and the drain D. Through the accumulation states of the charge accumulation layers 4a and 4b, the current transfer characteristics (channel inductance) in the vicinity of the source range and the drain range are modulated. For the paper size of the source s and the drain D, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applicable. — .Lilll — — — ^ ------ 1 — t_ !! ( Please read the precautions on the back before filling out this page) -33- Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 Α7 _ Β7 V. Description of the invention (31) If the bias is selected, the modulation of the current transmission characteristics is significantly changed Just performers. Through the four accumulation states of the charge accumulation layers 4a and 4b, four different current transfer characteristics are obtained, so that one bit can memorize the information of 2 bits. (B) Volatile memory system As shown in FIG. 1B, the volatile memory system of the sixth embodiment is composed of n-type M 0 S transistors. In the memory cell structure of this volatile memory, the second gate insulating film 14 of Fig. 1A is directly arranged on the main surface of the P-type semiconductor substrate 1. Then, a charge storage layer 4 (4c, 4d) is formed on both ends of the second gate electrode 14 in the same manner as in the nonvolatile memory of FIG. 1A. The charge storage layers 4c and 4d are disposed on the main surface of the P-type semiconductor substrate 1 through the tunnel insulating film 21, and are different from the nonvolatile memory in FIG. 1A. A gate electrode 3 is provided on the second gate insulating film 14 and the charge accumulation layer 4 via a third gate insulating film 1 5. On the side of the gate electrode 3, a sidewall spacer 9 is provided through an oxide film 16. On the main surface of the P-type semiconductor substrate 1 below the sidewall spacer 9, a η-type having a low impurity concentration in contact with the channel range is set. A diffusion layer 10 and a high impurity concentration η + -type diffusion layer 11 located outside the η--type diffusion layer 10. A conductive layer 12 is provided on the surface of each gate electrode 3 and the n + -type diffusion layer 11. The memory cell of the volatile semiconductor memory according to the sixth embodiment of the present invention has an η-type diffusion layer 10 with a source range and a drain range at a low impurity concentration and an η + type diffusion layer with a high impurity concentration. 1 1 constitutes the LDD structure. Then, the gate insulation film is based on the second gate insulation film 1 4 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 male *) il ---, II .--- I — ---- --Order ------ —— (Please read the notes on the back before filling out this page) -34- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 _____B7___ V. Description of the Invention (32), Tunnel Insulation The film 23 and the third gate insulating film 15 are formed, and a charge storage layer 4 is formed on both ends of the second gate insulating film 14. The two charge accumulation layers 4 c and 4 d accumulate electrons, and the accumulation state may be (1) the charge accumulation layers 4 c and 4 d have no electrons accumulated, (2) only the charge accumulation The state in which layer 4 c accumulates electrons, (3) only the state in which charge accumulation layer 4d accumulates electrons, and (4) the state in which charge accumulation layers 4c, 4d accumulate electrons. Through the presence or absence of electrons held in the two charge accumulation layers 4 c and 4 d, the change in the threshold value 値 generated corresponds to the memory information '' 0 0 〃, A 0 1 〃, vv 10〃 , ''11 〃. In addition, in this billion grid structure, the charge accumulation layer 4 is located above the end of the channel range, and the threshold value of the central part of the channel range is determined by the impurity concentration of the channel range, and does not depend on the charge. The state of accumulation of electrons in the accumulation layer 4. Therefore, it is possible to prevent excessive elimination of excessive electron shortages in the charge accumulation layer 4, thereby preventing occurrence of defective discharge, defective programming, poor reading, and the like due to excessive elimination. In addition, the bleeder current between the source range and the drain range can be suppressed by the gate voltage only, realizing a highly reliable non-volatile semiconductor memory. The charge storage layer 4 may be formed of a silicon nitride film having a high charge storage capability by the C V D method. By accumulating electrons due to the discrete charge trapping level of the silicon nitride film, it is possible to obtain a charge retention characteristic which is difficult to be affected by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be manufactured inexpensively. In addition, when the third gate insulating film 15 is formed of a silicon nitride film (S i 3N4 film) having a dielectric constant twice as high as that of a silicon oxide film (5 102 film), silicon can be formed. The thickness of the oxide film is 4 ~ 1 1 nm I ------- ml ^ --- I ----- ^ --------- (Please read the precautions on the back before filling (This page) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -35- Printed by the Intellectual Property Bureau Employees Consumer Cooperatives of the Ministry of Economic Affairs 488064 A7 B7 V. Description of Invention (33) Very thin The gate insulation film is stable. For example, when the silicon oxide film is converted to a silicon nitride film with a film thickness of 5 nm, the actual film thickness is about 10 nm. Therefore, direct tunnel implantation will not stimulate it. Therefore, the voltage at the time of implantation and extraction of electrons is lowered, not only the miniaturization of memory cells, but also the miniaturization of peripheral high-voltage operating elements. In the memory cell of the non-volatile semiconductor memory according to the sixth embodiment of the present invention, an η-type diffusion layer 10 is provided for the purpose of improving the withstand voltage of the source range and the drain range to form an LDD structure. 'With a single-drain structure, a double-drain structure may be used to form the source range and the drain range. The second gate insulating film 14 can prevent the charge accumulation layer 4 c from leaking between 4 c and 4 d. For example, it can be made of a silicon oxide film. When a metal oxide film having a high dielectric constant is used as the second gate insulating film 14, the current transmission characteristic in the center of the channel range can be improved. Examples of the metal oxide include T i 0 2, Ta205, Al205, PZT, and SBT.

接著，有關本發明之第6之實施形態的揮發性記憶體 中，於電荷蓄積層4 c及4 d之下部，配置隧道絕緣膜 2 3。隧道絕緣膜2 3係以具有可隧道之膜厚的薄膜之砂 氧化膜所構成，可達動態R A Μ所要求之1 0 0 n s以下 之高速寫入讀取。將隧道絕緣膜2 3以矽氧化膜構成之時 ，該膜厚呈3 nm以下即可。又，以3 nm以下之矽氮化 膜構成之時，可安定實現砂氧化膜換算膜厚爲1 · 5 nm 程度之非常薄的閘極絕緣膜。經由介由隧道絕緣膜2 3之 漏電流，蓄積於電荷蓄積層4之電子係漸漸減少之故’實 際上難達長期間之資料保持。但是，於通常之動態R A M ΙΉ---*--c---^ --------^---------^9 (請先閱讀背面之注意事項再填寫本頁> 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -36- 經濟部智慧財產局員工消费合作社印製 488064 A7 B7 _ 五、發明說明（34) 之更新期間內可充分再寫入，做爲動態R A Μ之動作則完 全無問題。此係經由C.H.-J.Wann，示於1 995IEDN digest P.867 〇 記憶格之讀取係檢測流於源極電極和汲極電極間之讀 取電流加以進行。經由電荷蓄積層4 c ，4 d之蓄積狀態 ，利用調變源極範圍、汲極範圍附近之電流傳達特性（通 道電感）者。對於於源極電極、汲極電極之何者進行偏壓 ，則選擇電流傳達特性之調變顯著表現者即可。經由電荷 蓄積層4 c及4 d之4個蓄積狀態，得4個不同之電流傳 達特性，由此以1個格，可記憶2位元分之資訊。 更且，有關本發明之第6之實施形態之揮發性記憶體 ，係不植入電荷於電荷蓄積層4 c及4 d時，可做爲通常 之Μ〇S電晶體動作。 (C )非揮發性及揮發性混合載置記憶體之製造方法 接著，將有關本發明之第6之非揮發性記億體及揮發 性記憶體之記億格之製造方法，使用圖1 3 Α乃至圖 13 I及圖14A乃至圖141加以說明。圖13A乃至 圖1 3 I係顯示有關本發明之第6之實施形態之非揮發性 半導體記憶體之記億格之製造工程的截面圖。圖1 4 A乃 至圖1 4 I係顯示有關本發明之第6之實施形態之揮發性 半導體記億體之記憶格之製造工程的截面圖。 首先，如圖1 3A及圖14 A所示，於P型半導體基 板1整面，堆積電荷蓄積能力小之矽氮化膜’形成1 0 n m程度之第1閘極絕緣膜1 3。形成第1閘極絕緣膜 — l·---ί 1----裝·！ —----訂·-------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -37- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（35) 1 3之後，將圖1 3 A之非揮發性記億體形成範圍’例如 以光阻劑被覆，僅將圖1 4 A之揮發性記億體形成範圍之 第1閘極絕緣膜1 3，例如經由使用加熱磷酸溶液的濕蝕 刻法加以除去。因此，第1閘極絕緣膜1 3係僅形成於圖 1 3 A之非揮發性記憶體形成範圍。電荷蓄積能力小之矽 氮化膜之堆積，例如以J V D法加以進行。 接著，如圖13B及14B所示，經由CVD法，將 矽氧化膜堆積於P型半導體基板1整面，形成5〜1 0 n m程度之第2閘極絕緣膜1 4。接著，經由J V D法電 荷蓄積能力小之矽氮化膜，形成1 0 ri m程度之第3閘極 絕緣膜1 5。結果，於圖1 3 B之非揮發性記憶體形成範 圍，形成第1、第2及第3閘極絕緣膜1 3、1 4、1 5 ，於圖1 4 B之揮發性記憶體形成範圍，形成第2及第3 閘極絕緣膜1 4、1 5。 接著，如圖1 3 C及1 4 C所示，於p型半導體基板 1整面，經由L P CVD法，堆積滲雜η型或p型不純物 之5 0 nm〜2 5 0之多結晶矽膜後，經由曝光技術及蝕 刻技術加以圖案化，形成閘極電極3。接著，將閘極電極 3做爲光罩，於圖1 3 C之非揮發性記億體形成範圍中， 將形成源極範圍及汲極範圍之範圍的P型半導體基板1之 表面的第1閘極絕緣膜1 3、第2閘極絕緣膜1 4及第3 閘極絕緣膜1 5，自我整合地加以乾蝕刻。另一方面，於 圖1 4 C之揮發性記憶體形成範圍中，第2閘極絕緣膜 1 4及第3閘極絕緣膜1 5，自我整合地加以乾蝕刻。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I l· *--Ί I I ^ · I---ί — 訂------I-- (請先閱讀背面之注意事項再填寫本頁) -38 - 488064 A7 B7 五、發明說明（36) 接著’如圖1 3D及圖1 4D所示，形成爲電荷蓄積 層形成之空間1 7。此空間1 7係使用較第1閘極絕緣膜 1 3及第3閘極絕緣膜1 5，第2閘極絕緣膜1 4之蝕刻 速度爲大的蝕刻液，將第2閘極絕緣膜1 4之端部選擇性 地以濕蝕刻加以形成。爲圖1 3 D之非揮發性記憶體形成 範圍之電荷蓄積層形成之空間1 7，及爲圖i 4D之揮發 性記憶體形成範圍之電荷蓄積層形成之空間1 7係同時形 成。於本發明之第6之實施形態中，將第1閘極絕緣膜 1 3及第3閘極絕緣膜1 5以矽氮化膜加以構成，將第2 閘極絕緣膜1 4以矽氮化膜加以構成之故，做爲蝕刻液使 用例如氟酸系即可。又，空間1 7係替換爲使用蝕刻液之 濕蝕刻法，以使用含H F氣體之氣體的電漿乾蝕刻法加以 形成亦可。 接著，如圖1 3 Ε及圖1 4Ε所示，將Ρ型半導體基 板1整面經由R Τ 0法加以氧化，形成可直接隧道之矽氧 化膜所成隧道絕緣膜2 3。 接著，如圖1 3 F及圖1 4F所示，於ρ型半導體基 板1整面，經由L P CVD法，將電荷蓄積能力高之矽氮 化膜1 8，完全埋入爲電荷蓄積層形成之空間1 7地加以 堆積。然後，如圖1 3 G及1 4G所示，對ρ型半導體基 板1整面，進行R I Ε之向異性蝕刻，同時形成以電荷蓄 積能力高之矽氮化膜所構成之電荷蓄積層4 (4a 、4b 、4 c 、4 d ) 〇 接著，如圖1 3H及1 4H所示，於p型半導體基板 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝-----訂·--- 骞丨 經濟部智慧財產局員工消費合作社印製 -39- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 ___ 五、發明說明（37) 1整面，形成氧化膜1 6之後，形成低不純物濃度之η —型 擴散層1 0。η —型擴散層1 〇係經由離子植入技術，將閘 極電極3做爲光罩，植入Ν型不純物，經由之後之熱處理 ，活化植入之不純物而形成者。 接著，如圖13I及圖14I所示，於閘極電極3之 側壁，形成側壁間隔9之後，形成高不純物濃度之η +型擴 散層1 1。η +型擴散層1 1係經由離子植入技術，將閘極 電極3及側壁間隔9做爲光罩，植入η型不純物，經由之 後之熱處理活化植入之不純物而加以形成。 然後，於Ρ型半導體基板1之整面，經由C V D法或 濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將Ρ 型半導體基板1於不活性氣氛中經由熱處理，於各閘極電 極3、及η+型擴散層1 1之表面，形成以高融點金屬矽化 物所構成之導電層1 2。形成導電層1 2後，除去殘留於 上述以外之範圍的未反應高融點金屬時，可完成圖1 1 A 所示之非揮發性記憶體及圖1 1 B所示之揮發性記憶體之 記憶格構造。 然而，雖未圖示，圖1 1 A及圖1 1 B之記憶格構造 完成後，順序經由層間絕緣膜形成工程’連接孔形成工程 ，配線形成工程，鈍化膜形成工程等之通常之C Μ〇S製 造工程，完成最終之非揮發性記億格。 根據本發明之第6之實施形態時，可將電荷蓄積層4 (4a、4b、4c、4d)自我整合形成於閘極電極3 之兩端下方。因此，可達圖11A及圖11B之記億格電 IT ^ ^----------------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格(210 X 297公釐） -40 - 488064 A7 B7____ 五、發明說明（38> <請先閱讀背面之注意事項再填寫本頁) 晶體之閘極長方向之微細化。由此，可提供大容量、高密 度之非揮發性半導體記億體。又每位元之格面積較以往減 少幾近一半，可實現大幅減小之非揮發性記憶體及揮發性 記億體。 經濟部智慧財產局員工消費合作社印製 又，電荷蓄積層4之通道長方向之寬度係經由Ρ型半 導體基板1、第1閘極絕緣膜1 3及第3閘極絕緣膜1 5 和第2閘極絕緣膜1 4之蝕刻速度差，以及蝕刻時間之調 節可容易控制。由此，可對稱配置電荷蓄積層4。然後， 電荷蓄積層4間係經由第2閘極絕緣膜1 4電氣性地完全 分離之故，電荷蓄積層4間之相互作用不會產生。更且， 電荷蓄積層4係自源極範圍、汲極範圍、閘極電極3及通 道範圍，經由第1之絕緣膜13、隧道絕緣膜23、第3 之絕緣膜1 5、及氧化膜1 6完全加以絕緣之故，可提供 電荷保持性優異之非揮發性記憶體及揮發性記億體。電荷 蓄積層4係自閘極電極3之端部延伸存在於通道範圍方向 加以形成，經由電荷蓄積層4中之通道範圍側部分之電荷 蓄積狀態，幾乎決定記憶格之電流傳達特性。因此’將此 部分之閘極長方向之長度縮小到極限之時，可提供更爲微 細之非揮發性記憶體及揮發性記憶體。 格構造係可容易實現通常之CM〇S工程之故’使用 既有之製造生產線，可以低成本製造非揮發性記億體及揮 發性記憶體。 更且，上述非揮發性記憶體和揮發性記憶體係該製造 工程之大部分爲共通化之故，可於低成本且短製造工期’ 本紙張尺度適用中困國家標準<CNS)A4規格（210 X 297公釐） -41 - 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 __ 五、發明說明（39) 製造混合載置非揮發性記憶體和揮發性記憶體之半導體裝 置。 然而，於本發明之第6之實施形態中，雖令第1閘極 絕緣膜1 3以矽氮化膜構成，第2閘極絕緣膜1 4以矽氧 化膜，第3閘極絕緣膜1 5以矽氮化膜加以構成，但以可 令第1閘極絕緣膜1 3爲矽氧化膜構成，第2閘極絕緣膜 1 4爲矽氮化膜，第3閘極絕緣膜1 5爲矽氧化膜加以構 成。此時，例如第1閘極絕緣膜1 3係以熱氧化P型半導 體基板1之1 0 nm程度之矽氧化膜加以構成。第2閘極 絕緣膜1 4係以經由J V D法堆積之5〜1 0 n m程度之 電荷蓄積能力的低矽氮化膜加以構成。第3閘極絕緣膜 1 5係以經由J V D法堆積之1 0 n m程度之矽氧化膜所 構成即可。又，爲電荷蓄積形成之空間1 7之形成，係將 第1閘極絕緣膜1 3及第3閘極絕緣膜1 5以矽氧化膜加 以構成，第2閘極絕緣膜1 4以矽氮化膜加以構成之故， 做爲蝕刻液例如使用磷酸系即可。 (第7之實施形態） 接著，對於本發明之第7之實施形態加以說明。此第 7之實施形態係與上述之第6之實施形態同樣’顯示將電 氣性可寫入消除之非揮發性記憶體和可高速寫入讀取之揮 發性記憶體實現於同一晶片上之例。圖1 5 A係顯示有關 本發明之第7之實施形態的搭載於半導體記憶裝置的非揮 發性記憶體之記憶格構造的截面圖。圖1 5 B係顯示搭載 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公:42- ' I * - 1 --I ^ i — — — — — — ^*— — — — — 1 — —^9 (請先閱讀背面之注意事項再填寫本頁) 488064 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（4〇) 於有關本發明之第6之實施形態之半導體記憶裝置之揮發 性半導體記憶體之記億格構造的截面圖。圖1 5 A之非揮 發性記億體和圖1 5 B之揮發性記億體係混合載置於同一 晶片者對於圖1 5 A所示非揮發性記憶體與上述第6之實 施形態相同之故，在此省略其說明。 如圖1 5 B所示，有關此第7之實施形態之揮發性記 憶體之記憶格係以η型Μ〇S電晶體加以構成。此揮發性 記億體之記憶格構造中，於ρ型半導體基板1之主面，介 由隧道絕緣膜2 3，配置電荷蓄積層4 e。於電荷蓄積層 4 e上，介由第4閘極絕緣膜2 4，設置閘極電極3。於 閘極電極3之側面，介由氧化膜1 6設置側壁間隔9，於 此側壁間隔9之下部之ρ型半導體基板1之主面中，設置 接觸於通道範圍之低不純物濃度之n—型擴散層1 0，和位 置於此型擴散層1 〇之外側的高不純物濃度之n+型擴 散層1 1。於各閘極電極3，及n+型擴散層1 1之表面， 設置導電層1 2。 有關本發明之第7之實施形態之揮發性半導體記憶體 之記憶格係具有將源極範圍及汲極範圍以低不純物濃度之 η —型擴散層1 0和高不純物濃度之n+型擴散層1 1構成 之L D D構造。然後，閘極絕緣膜以隧道絕緣膜2 3及第 4閘極絕緣膜2 4所成堆積構造加以構成，於隧道絕緣膜 2 3和第4閘極絕緣膜2 4間配置電荷蓄積層4 e。於此 電荷蓄積層4 e蓄積電子，經由保持於此電荷蓄積層4 e 之電子之有無，將所產生之臨限値之變化分’對應於記億 -1 ---^--Ί 丨丨 裝！!1 訂----— II-- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -43 - 經濟部智慧財產局員工消費合作社印製 488064 A7 B7_ 五、發明說明（41 ) 資訊之0 〃 ， 1 〃 。電荷蓄積層4 e係以C V D法之 電荷蓄積能力高的矽氮化膜加以構成即可。經由於矽氮化 膜之離散性之電荷捕獲準位蓄積電子，可得難以於下部絕 緣膜之膜質影響之電荷保持特性。又，以矽膜，多結晶矽 膜加以構成之時，可便宜地加以製造。更且，將第4閘極 絕緣膜2 4以具有矽氧化膜（S i〇2膜）之2倍程度之介 電率的矽氮化膜（S i 3N4膜）加以構成時，可將矽氧化 膜換算膜厚爲4〜11nm程度之非常薄的閘極絕緣膜安 定實現。例如，矽氧化膜換算膜厚爲5 n m之矽氮化膜之 實質膜厚爲1 0 nm程度之故，直接進行隧道植入亦不會 激勵。因此，電子之植入抽出時之電壓係被低電壓化，不 單是記憶格之微細化，亦可達周邊高電壓動作元件之微細 化。 有關本發明之第7之實施形態之揮發性半導體記億體 之記憶格中，於源極範圍及汲極範圍之耐壓提升之目的上 ，設置η—型擴散層10，以構成LDD構造，以單汲極構 造，雙汲極構造構成源極範圍及汲極範圍亦可。 接著，有關本發明之第7之實施形態的揮發性記億體 中，於電荷蓄積層4 e之下部，配置隧道絕緣膜2 3。隧 道絕緣膜2 3係以具有可隧道之膜厚的薄膜之矽氧化膜所 構成，可達動態RAM所要求之1 0 0 n s以下之高速寫 入讀取。將隧道絕緣膜2 3以矽氧化膜構成之時，該膜厚 呈3 nm以下即可。又，以3 nm以下之矽氮化膜構成之 時，可安定實現矽氧化膜換算膜厚爲1· 5 nm程度之非 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I Γ---.--一---^--------^--------- 争 (請先閱讀背面之注意事項再填寫本頁) -44- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7_ 五、發明說明（42) 常薄的隧道絕緣膜2 3。 更且，有關本發明之第7之實施形態之揮發性記憶體 ，係不植入電荷於電荷蓄積層4 e時，可做爲通常之 Μ 0 S電晶體動作。 接著，將有關本發明之第7之非揮發性記憶體及揮發 性記憶體之記憶格之製造方法，使用圖1 6 Α乃至圖 1 6 I及圖17A乃至圖1 7H加以說明。圖1 7A乃至 圖1 7 I係顯示有關本發明之第7之實施形態之非揮發性 半導體記憶體之記億格之製造工程的截面圖。圖1 7 A乃 至圖1 7 Η係顯示有關本發明之第7之實施形態之揮發性 半導體記憶體之記憶格之製造工程的截面圖。 接著，將有關本發明之第7之非揮發性記憶體及揮發 性記憶體之記憶格之製造方法，使用圖1 6 Α乃至圖 1 6 Η及圖1 7A乃至圖1 7H加以說明。圖1 6A乃至 圖1 6 Η係顯示有關本發明之第7之實施形態之非揮發性 半導體記憶體之記憶格之製造工程的截面圖。圖1 7 Α乃 至圖1 7 Η係顯示有關本發明之第7之實施形態之揮發性 半導體記憶體之記億格之製造工程的截面圖。Next, in the volatile memory according to the sixth embodiment of the present invention, a tunnel insulating film 2 3 is disposed below the charge storage layers 4 c and 4 d. The tunnel insulating film 23 is composed of a sand oxide film having a thin film capable of being tunneled, and can achieve high-speed writing and reading below 100 n s required by the dynamic RAM. When the tunnel insulating film 23 is formed of a silicon oxide film, the film thickness may be 3 nm or less. When a silicon nitride film with a thickness of 3 nm or less is used, it is possible to stably realize a very thin gate insulating film having a thickness of approximately 1.5 nm in terms of a sand oxide film. The leakage current through the tunnel insulating film 23 causes the electron system accumulated in the charge accumulation layer 4 to decrease gradually. It is difficult to maintain data for a long period of time. However, the usual dynamic RAM ΙΉ --- *-c --- ^ -------- ^ --------- ^ 9 (Please read the precautions on the back before filling in this Page > This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -36- Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 488064 A7 B7 _ V. During the update period of the invention description (34) It can be fully rewritten, and it has no problem as a dynamic RA Μ action. This is shown in CH-J. Wann, shown in 1 995IEDN digest P.867. The reading system of the memory cell detects the flow of the source electrode and drain. The reading current between the electrodes is performed. By using the accumulation state of the charge accumulation layers 4 c and 4 d, the current transmission characteristics (channel inductance) in the vicinity of the source range and the drain range are modulated. For the source electrode, Which of the drain electrodes is biased, it is sufficient to select a person whose modulation of the current transfer characteristic is significant. Through the four accumulation states of the charge accumulation layers 4 c and 4 d, four different current transfer characteristics can be obtained. One cell can store 2 bits of information. Furthermore, the volatile nature of the sixth embodiment of the present invention The memory can be used as a normal MOS transistor when no charge is implanted in the charge accumulation layer 4 c and 4 d. (C) Non-volatile and volatile mixed-mounted memory manufacturing method Next, The manufacturing method of the sixth non-volatile memory cell and the billion memory cell of the volatile memory of the present invention will be described with reference to Figs. 13A to 13I and Figs. 14A to 141. Figs. 13A to 1 3 I is a cross-sectional view showing the manufacturing process of a billion-gigabyte of nonvolatile semiconductor memory according to the sixth embodiment of the present invention. Figure 1 4 A to FIG. 1 4 I is a view showing the sixth implementation of the present invention A cross-sectional view of the manufacturing process of a volatile semiconductor memory cell with a shape of 100 million. First, as shown in FIGS. 'Form the first gate insulating film to a degree of 10 nm 1 3. Form the first gate insulating film — l · --- ί 1 ---- 装 ·! —---- Order · ----- --- (Please read the notes on the back before filling out this page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -3 7- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7 V. Description of the invention (35) 13 After the formation of the non-volatile membrance of Fig. 13 A 'for example, cover with photoresist, only The first gate insulating film 13 in the range of formation of volatile terabytes in FIG. 14A is removed, for example, by a wet etching method using a heated phosphoric acid solution. Therefore, the first gate insulating film 13 is formed only in the figure 1 3 A non-volatile memory formation range. The deposition of a silicon nitride film having a small charge storage capacity is performed by, for example, the J V D method. Next, as shown in Figs. 13B and 14B, a silicon oxide film is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method to form a second gate insulating film 14 having a thickness of 5 to 10 nm. Next, a third gate insulating film 15 having a thickness of about 10 nm is formed through a silicon nitride film having a small charge storage capacity by the J V D method. As a result, the first, second, and third gate insulating films 1 3, 1, 4, and 15 were formed in the non-volatile memory formation range of FIG. 13B, and the volatile memory formation range of FIG. 14B The second and third gate insulating films 14 and 15 are formed. Next, as shown in FIGS. 1 3 C and 1 4 C, a polycrystalline silicon film of 50 nm to 2 50 doped with n-type or p-type impurities is deposited on the entire surface of the p-type semiconductor substrate 1 by the LP CVD method. Then, it is patterned through an exposure technique and an etching technique to form the gate electrode 3. Next, using the gate electrode 3 as a photomask, the first surface of the P-type semiconductor substrate 1 on the surface of the P-type semiconductor substrate 1 in the range of the source range and the drain range will be formed in the non-volatile memory body forming range of FIG. The gate insulating film 1 3, the second gate insulating film 14 and the third gate insulating film 15 are self-integrated and dry-etched. On the other hand, in the volatile memory formation range of FIG. 14C, the second gate insulating film 14 and the third gate insulating film 15 are self-integrated and dry-etched. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I l · *-Ί II ^ · I --- ί — Order ------ I-- (Please read the back first Please pay attention to this page and fill in this page again) -38-488064 A7 B7 V. Description of the invention (36) Then 'as shown in Fig. 1 3D and Fig. 1 4D, a space 17 formed as a charge accumulation layer is formed. This space 17 uses an etching solution having a higher etching rate than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 and the second gate insulating film 1 The ends of 4 are selectively formed by wet etching. The space 17 formed by the charge accumulation layer in the non-volatile memory formation range of FIG. 13D and the space 17 formed by the charge accumulation layer in the volatile memory formation range of FIG. 4D are simultaneously formed. In the sixth embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are made of a silicon nitride film, and the second gate insulating film 14 is made of silicon nitride. For forming the film, for example, a fluoric acid system may be used as the etching solution. The space 17 may be replaced with a wet etching method using an etching solution, and may be formed by a plasma dry etching method using a gas containing H F gas. Next, as shown in Figs. 13E and 14E, the entire surface of the P-type semiconductor substrate 1 is oxidized by the RTO method to form a tunnel insulating film 23 made of a silicon oxide film capable of direct tunneling. Next, as shown in FIGS. 13F and 14F, a silicon nitride film 18 having a high charge storage capacity is completely buried as a charge storage layer by the LP CVD method over the entire surface of the p-type semiconductor substrate 1. Spaces are stacked in 17 places. Next, as shown in FIGS. 1G and 14G, the entire surface of the p-type semiconductor substrate 1 is anisotropically etched with RI E, and at the same time, a charge storage layer 4 made of a silicon nitride film having a high charge storage capability is formed ( 4a, 4b, 4c, 4d) 〇 Then, as shown in Figures 1H and 14H, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied to this paper size for p-type semiconductor substrates (please first (Please read the notes on the back and fill in this page again.) Packing ----- Order · --- 骞 丨 Printed by the Employees 'Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-39- Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 488064 A7 B7 ___ 5. Description of the invention (37) 1 After the oxide film 16 is formed on the entire surface, an η-type diffusion layer 10 having a low impurity concentration is formed. The η-type diffusion layer 10 is formed by implanting the gate electrode 3 as a photomask, implanting N-type impurities, and activating the implanted impurities by subsequent heat treatment. Next, as shown in Figs. 13I and 14I, after forming sidewall spacers 9 on the sidewalls of the gate electrode 3, an η + -type diffusion layer 11 having a high impurity concentration is formed. The η + -type diffusion layer 11 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask by implanting η-type impurities, and then activating the implanted impurities by subsequent heat treatment. Then, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method or a sputtering method, and then the P-type semiconductor substrate 1 is heat-treated in an inactive atmosphere. On the surfaces of the gate electrodes 3 and the η + type diffusion layer 11, a conductive layer 12 made of a high melting point metal silicide is formed. After the conductive layer 12 is formed, when the unreacted high-melting-point metal remaining in a range other than the above is removed, the nonvolatile memory shown in FIG. 1A and the volatile memory shown in FIG. 1B can be completed. Memory cell construction. However, although it is not shown, after the memory cell structure of FIGS. 1A and 1B is completed, the common C M is sequentially passed through the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process. 〇S manufacturing process, complete the final non-volatile memory billion. According to the sixth embodiment of the present invention, the charge storage layers 4 (4a, 4b, 4c, 4d) can be self-integrated and formed under both ends of the gate electrode 3. Therefore, it is possible to reach the ITEG IT of Figures 11A and 11B ^ ^ ----------------- (Please read the notes on the back before filling this page) Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -40-488064 A7 B7____ V. Description of the invention (38 > < Please read the precautions on the back before filling this page) Miniaturization. As a result, a large-capacity, high-density non-volatile semiconductor memory can be provided. In addition, the grid area per bit is reduced by almost half compared with the past, which can realize a significant reduction of non-volatile memory and volatile memory. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The width of the channel in the longitudinal direction of the charge accumulation layer 4 passes through the P-type semiconductor substrate 1, the first gate insulating film 1 3, and the third gate insulating film 15 and the second. The difference in the etching speed of the gate insulating film 14 and the adjustment of the etching time can be easily controlled. Thereby, the charge storage layers 4 can be arranged symmetrically. Then, since the charge accumulation layers 4 are electrically and completely separated via the second gate insulating film 14, no interaction between the charge accumulation layers 4 occurs. Furthermore, the charge accumulation layer 4 is from the source range, the drain range, the gate electrode 3, and the channel range, and passes through the first insulating film 13, the tunnel insulating film 23, the third insulating film 15, and the oxide film 1. 6 Because it is completely insulated, it can provide non-volatile memory and volatile memory with excellent charge retention. The charge accumulation layer 4 is formed by extending from the end of the gate electrode 3 in the direction of the channel range, and the charge accumulation state of the channel range side portion in the charge accumulation layer 4 almost determines the current transfer characteristics of the memory cell. Therefore, when the length of the gate length in this portion is reduced to the limit, finer nonvolatile memory and volatile memory can be provided. Lattice structure system can easily realize the common CMOS process. It is possible to manufacture non-volatile memory and volatile memory at low cost by using existing production lines. In addition, most of the manufacturing processes of the above non-volatile memory and volatile memory system are common, so it can be manufactured at low cost and short manufacturing period. This paper standard is applicable to the national standard &CN; A4 specification ( 210 X 297 mm) -41-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7 __ V. Description of the invention (39) Manufacture of semiconductor devices that mix non-volatile memory and volatile memory. However, in the sixth embodiment of the present invention, although the first gate insulating film 13 is made of a silicon nitride film, the second gate insulating film 14 is a silicon oxide film, and the third gate insulating film 1 5 is composed of a silicon nitride film, but the first gate insulating film 13 is a silicon oxide film, the second gate insulating film 14 is a silicon nitride film, and the third gate insulating film 15 is A silicon oxide film is formed. At this time, for example, the first gate insulating film 13 is formed by thermally oxidizing a silicon oxide film of about 10 nm of the P-type semiconductor substrate 1. The second gate insulating film 14 is composed of a low silicon nitride film having a charge accumulation capability of about 5 to 10 nm which is deposited by the J V D method. The third gate insulating film 15 may be formed of a silicon oxide film having a thickness of about 10 nm by the J V D method. In order to form the space 17 formed by charge accumulation, the first gate insulating film 13 and the third gate insulating film 15 are formed by a silicon oxide film, and the second gate insulating film 14 is formed by silicon nitrogen. For the formation of a chemical film, for example, a phosphoric acid system may be used as the etching solution. (Seventh Embodiment) Next, a seventh embodiment of the present invention will be described. This seventh embodiment is the same as the sixth embodiment described above. It shows an example where the nonvolatile memory that can be electrically written and erased and the volatile memory that can be written and read at high speed are implemented on the same chip. . Fig. 15A is a sectional view showing a memory cell structure of a non-volatile memory mounted on a semiconductor memory device according to a seventh embodiment of the present invention. Figure 1 5 B shows that the paper is equipped with the Chinese National Standard (CNS) A4 specification (210 X 297 male: 42- 'I *-1 --I ^ i — — — — — — — ^ * — — — — — 1 — — ^ 9 (Please read the notes on the back before filling out this page) 488064 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (40) In the sixth embodiment of the present invention A cross-sectional view of the terabyte structure of a volatile semiconductor memory of a semiconductor memory device. The nonvolatile terabytes of FIG. 15 A and the volatile terabytes of FIG. 15B are mixed on the same chip. Since the non-volatile memory shown in 5A is the same as the sixth embodiment, its description is omitted here. As shown in FIG. 1B, the memory cell system of the volatile memory in this seventh embodiment It is composed of n-type MOS transistor. In this volatile memory cell structure, a charge storage layer 4 e is disposed on the main surface of the p-type semiconductor substrate 1 through a tunnel insulating film 2 3. On the accumulation layer 4e, a gate electrode 3 is provided via a fourth gate insulating film 24. On the side of the electrode 3, a sidewall spacer 9 is provided through an oxide film 16. On the main surface of the p-type semiconductor substrate 1 below the sidewall spacer 9, an n-type diffusion layer with a low impurity concentration in contact with the channel region is provided. 10, and an n + -type diffusion layer 11 with a high impurity concentration located outside the type-diffusion layer 10, and a conductive layer 12 is provided on the surface of each gate electrode 3 and the n + -type diffusion layer 11 1. Related The memory cell of the volatile semiconductor memory according to the seventh embodiment of the present invention has an η-type diffusion layer 10 having a source range and a drain range with a low impurity concentration and an n + type diffusion layer with a high impurity concentration 1 1 LDD structure of the structure. Then, the gate insulating film has a stacked structure formed by the tunnel insulating film 23 and the fourth gate insulating film 24, and is disposed between the tunnel insulating film 23 and the fourth gate insulating film 24. The charge accumulation layer 4 e. The electrons are stored in the charge accumulation layer 4 e, and the change of the threshold value generated by the presence or absence of the electrons held in the charge accumulation layer 4 e corresponds to 亿 100-1 --- ^-Ί 丨 丨 Install!! 1 Order ----— II-- (Please read the Note: Please fill in this page again.) This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -43-Printed by the Intellectual Property Bureau Employee Consumer Cooperatives of the Ministry of Economic Affairs 488064 A7 B7_ V. Invention Description (41) Information 0 〃, 1 〃. The charge accumulation layer 4 e can be formed by a silicon nitride film having a high charge accumulation capability by the CVD method. The discrete charge trapping level of the silicon nitride film can accumulate electrons, which can be obtained. It is difficult to maintain the charge retention characteristics affected by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be manufactured inexpensively. In addition, when the fourth gate insulating film 24 is composed of a silicon nitride film (S i 3N4 film) having a dielectric rate approximately twice that of a silicon oxide film (S i02 film), silicon can be formed. An extremely thin gate insulating film with an oxide film conversion film thickness of about 4 to 11 nm is realized stably. For example, the thickness of a silicon nitride film with a thickness of 5 nm as a silicon oxide film is about 10 nm, so tunnel implantation is not an incentive. Therefore, the voltage at the time of implantation and extraction of electrons is reduced, not only the miniaturization of memory cells, but also the miniaturization of peripheral high-voltage operating elements. In the memory cell of the volatile semiconductor memory of the seventh embodiment of the present invention, an n-type diffusion layer 10 is provided for the purpose of improving the withstand voltage of the source range and the drain range to form an LDD structure. The single-drain structure and the double-drain structure may be used to form the source range and the drain range. Next, among the volatile memory cells according to the seventh embodiment of the present invention, a tunnel insulating film 23 is disposed below the charge storage layer 4e. The tunnel insulating film 23 is composed of a silicon oxide film with a thin film that can be tunneled, and can reach a high-speed write and read speed of less than 100 n s required by the dynamic RAM. When the tunnel insulating film 23 is formed of a silicon oxide film, the thickness of the film may be 3 nm or less. In addition, when it is composed of a silicon nitride film with a thickness of 3 nm or less, the thickness of the silicon oxide film converted to a thickness of about 1.5 nm can be achieved. The non-paper size applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) ) I Γ ---.-- 一 --- ^ -------- ^ --------- Contention (Please read the precautions on the back before filling this page) -44- Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau 488064 A7 B7_ V. Description of the invention (42) Often thin tunnel insulation film 2 3. Furthermore, the volatile memory according to the seventh embodiment of the present invention can operate as a normal M 0S transistor when no charge is implanted in the charge storage layer 4e. Next, a method for manufacturing a memory cell of a nonvolatile memory and a volatile memory according to the seventh aspect of the present invention will be described using FIG. 16A to FIG. 16I and FIG. 17A to FIG. 17H. FIG. 17A to FIG. 17I are cross-sectional views showing the manufacturing process of the non-volatile semiconductor memory according to the seventh embodiment of the present invention. Fig. 17A to Fig. 17 are sectional views showing a manufacturing process of a memory cell of a volatile semiconductor memory according to a seventh embodiment of the present invention. Next, the manufacturing method of the seventh non-volatile memory and the memory cell of the volatile memory of the present invention will be described with reference to FIGS. 16A to 16B and FIGS. 17A to 17H. 16A to 16 are cross-sectional views showing a manufacturing process of a memory cell of a nonvolatile semiconductor memory according to a seventh embodiment of the present invention. Fig. 17A and Fig. 17 are cross-sectional views showing the manufacturing process of a terabyte of a volatile semiconductor memory according to a seventh embodiment of the present invention.

首先，如圖1 6Α及圖1 7Α所示，於Ρ型半導體基 板1整面，堆積電荷蓄積能力小之矽氮化膜’形成1 〇 n m程度之第1蘭極絕緣膜1 3。電何蓄積能力小之砂氮 化膜之堆積，例如以J V D法加以進行。形成第1閘極絕 緣膜1 3之後，經由CVD法，堆積矽氧化膜’形成5〜 1 0 n m程度之第2閘極絕緣膜1 4。_著，經由J V D 11——一— --------訂---------^9. (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -45- 488064 經濟部智慧財產局員工消費合作社印製 A7 _ __B7 _ 五、發明說明（43) 法電荷蓄積能力小之矽氮化膜，形成1 〇 n m程度之第3 閘極絕緣膜1 5。 接著，如圖16B及17B所示’於p型半導體基板 1整面，經由L P CVD法’堆積滲雜η型或p型不純物 之5 0 n m〜2 5 0之多結晶矽膜後，於圖1 6 Β之非揮 發性記憶體形成範圍，經由曝光技術及蝕刻技術加以圖案 化，形成閘極電極3。接著，將閘極電極3做爲光罩’將 形成源極範圍及汲極範圍之範圍的p型半導體基板1之表 面的第1閘極絕緣膜1 3、第2閘極絕緣膜1 4及第3閘 極絕緣膜1 5，自我整合地加以乾蝕刻。另一方面，於圖 1 4 C之揮發性記億體形成範圍中，圖1 7 B之揮發性記 憶體形成範圍中，多結晶矽膜、第1閘極絕緣膜1 3、第 2閘極絕緣膜1 4及第3閘極絕緣膜1 5皆加以除去，露 出P型半導體基板1之表面。 接著，如圖1 6 C所示，於非揮發性記憶體形成範圍 ，形成爲電荷蓄積層形成之空間1 7。此空間1 7係使用 較第1閘極絕緣膜1 3及第3閘極絕緣膜1 5，第2閘極 絕緣膜1 4之蝕刻速度爲大的蝕刻液，將第2閘極絕緣膜 1 4之端部選擇性地以濕蝕刻加以形成。本發明之第7之 實施形態中，將第1閘極絕緣膜1 3及第3閘極絕緣膜 1 5以矽氮化膜加以構成，將第2閘極絕緣膜1 4以矽氮 化膜加以構成之故，做爲蝕刻液使用例如氟酸系即可。又 ，爲電荷蓄積層形成之空間1 7係替換爲使用蝕刻液之濕 蝕刻法，以使用含H F氣體之氣體的電漿乾蝕刻法加以形 本紙張尺度適用中國國家標準<CNS)A4規格（210 X 297公釐） !--!-----1·裝------- —訂--------- Φ (請先閲讀背面之注意事項再填寫本頁) -46- 經濟部智慧財產局員工消費合作社印製 488064 A7 ____B7 _ 五、發明說明（如） 成亦可。另一方面，如圖1 7 C所示，揮發性記憶體形成 範圍中，P型半導體基板1之表面則保持曝露。 接著，如圖1 6D及圖1 7D所示，將P型半導體基 板1整面經由R T 0法加以氧化，形成可直接隧道之矽氧 化膜所成隧道絕緣膜2 3。形成隧道絕緣膜2 3後，於P 型半導體基板1整面，經由L P CVD法，將電荷蓄積能 力高之矽氮化膜1 8。此時，完全埋入爲電荷蓄積層形成 之空間1 7地加以堆積。然後，如圖1 6 E所示，於非揮 發性記憶體形成範圍中，對P型半導體基板1整面，進行 R I E之向異性蝕刻，形成以電荷蓄積能力高之矽氮化膜 所構成之電荷蓄積層4 ( 4 a、4 b )。此時，圖1 7 E 之揮發性記憶體形成範圍係以光阻劑所被覆，矽氮化膜 1 8不會被蝕刻。 矽氮化膜1 8之蝕刻終了後，於p型半導體基板1整 面，堆積矽氧化膜，形成第4閘極絕緣膜2 4。在此，圖 1 6 E之非揮發性記憶體形成範圍之第4閘極絕緣膜2 4 則會加以除去。該除去係將圖1 7 E之揮發性記憶體形成 範圍以光阻劑被覆，蝕刻堆積於圖1 6 E之非揮發性記憶 體形成範圍的第4閘極絕緣膜2 4地加以進行。 接著，如圖17 F所示，於P型半導體基板1整面， 經由L PCVD法，堆積滲雜n型或p型不純物之5 0〜 2 5 0 n m程度之多結晶矽膜。然後經由曝光技術及蝕刻 技術，圖案化該多結晶矽膜，形成閘極電極3 a。接著， 將閘極電極3 a做爲蝕刻光罩，將形成源極範圍及汲極範 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----^--------* 裝---—---訂--------- (請先閱讀背面之注意事項再填寫本頁) -47- 經濟部智慧財產局員工消費合作社印製 488064 Α7 ______ Β7 五、發明說明（45) 圍之範圍的P型半導體基板1之表面的第1閘極絕緣膜 1 3、第2閘極絕緣膜1 4及第3閘極絕緣膜1 5，自我 整合地加以乾蝕刻。另一方面，非揮發性記憶體形成範圍 中，如圖1 6 F所示，除去所有多結晶矽膜亦可，配合閘 極電極3 a加以圖案化，形成新的閘極電極亦可。 接著’如圖1 6 Η及圖1 7 Η所示，於閘極電極3之 側壁，形成側壁間隔9之後，形成高不純物濃度之η +型擴 散層1 1。η +型擴散層1 1係經由離子植入技術，將閘極 電極3及側壁間隔9做爲光罩，植入η型不純物，經由之 後之熱處理活化植入之不純物而加以形成。 接著，於Ρ型半導體基板1之整面，經由CVD法或 濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將ρ 型半導體基板1於不活性氣氛中經由熱處理，於各閘極電 極3、及η +型擴散層1 1之表面，形成以高融點金屬矽化 物所構成之導電層1 2。形成導電層1 2後，除去殘留於 上述以外之範圍的未反應高融點金屬時，可完成圖1 5 A 所示之非揮發性記憶體及圖1 5 B所示之揮發性記億體之 記憶格構造。 然而，雖未圖示，圖1 5 A及圖1 5 B之記億格構造 完成後，順序經由層間絕緣膜形成工程，連接孔形成工程 ，配線形成工程，鈍化膜形成工程等之通常之C Μ〇S製 造工程，完成最終之非揮發性記億格。 於本發明之第7之實施形態中，雖令第1閘極絕緣膜 1 3以矽氮化膜構成，第2閘極絕緣膜1 4以矽氧化膜， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---I--- —. -48- 經濟部智慧財產局員工消費合作社印製 488064 Α7 ______ Β7 五、發明說明（46) 第3閘極絕緣膜1 5以矽氮化膜加以構成，但以可令第1 閘極絕緣膜1 3爲砂氧化膜構成，第2閘極絕緣膜1 4爲 矽氮化膜，第3閘極絕緣膜1 5爲矽氧化膜加以構成。此 時，例如第1閘極絕緣膜1 3係以熱氧化P型半導體基板 1之1 0 n m程度之矽氧化膜加以構成。第2閘極絕緣膜 1 4係以經由J VD法堆積之5〜1 0 nm程度之電荷蓄 積能力的低矽氮化膜加以構成。第3閘極絕緣膜1 5係以 經由J V D法堆積之1 〇 n m程度之矽氧化膜所構成即可 。又，爲電荷蓄積形成之空間1 7之形成，係將第1閘極 絕緣膜1 3及第3閘極絕緣膜1 5以矽氧化膜加以構成， 第2閘極絕緣膜1 4以矽氮化膜加以構成之故，做爲蝕刻 液例如使用磷酸系即可。 本發明之第6及第7之實施形態中，非揮發性記億體 及揮發性記億體之記憶格係皆爲對於η型Μ 0 S電晶體所 構成之例做了說明，當然爲相反之導電型之Ρ型M〇S電 晶體之記憶格亦可。於此時，於上述說明中，將適切、基 板或擴散層之導電型換讀爲相反者即可。 (第8之實施形態） 接著，對於本發明之第8之實施形態加以說明。於上 述第1乃至第7之實施形態中，有電荷蓄積層之構造係不 依附於電子植入效率的提升。於浮閘極構造之非揮發性半 導體記憶體中，於通道部分設置階差，嘗試提升電子植入 效率的提案（S. Ogiua，1998IEDM，ρ987 ，美國專利號碼 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） -49- —•J J---^---^--------訂 -------- (請先閱讀背面之注意事項再填寫本頁) 488064 Α7 Β7 五、發明說明（47) 第5780341號）。但是，於此提案之中，採用浮閘 構造之故，對於氧化膜中之缺陷或泄放側爲弱。又，對於 階差構造形成時所產生缺陷，有無法得充分之可靠性。本 發明之第8之實施形態係可以簡單之步驟，提升電子植入 效率。 圖1 8係顯示有關本發明之第8之實施形態的非揮發 性半導體記憶體之記憶格構造的截面圖。此第8之實施形 態係於記憶格之通道範圍設置階差或傾斜，達成於寫入時 之電子植入效率的提升者。如圖1 8所示，此記憶格係以 η型Μ〇S電晶體加以構成。然後，有關此第8之實施形 態的記憶格之構造中，於Ρ型半導體基板1之表面，介由 第1閘極絕緣膜1 3，設置第2閘極絕緣膜1 4。於第2 閘極絕緣膜14之兩端，形成電荷蓄積層4a ，4b。於 第2閘極絕緣膜1 4及電荷蓄積層4 a、4b上，介由第 3閘極絕緣膜1 5，設置閘極電極3。於閘極電極3之側 4 面，介由氧化膜1 6，設置側壁間隔9 ’於此側壁間隔9 之下部之P型半導體基板1，設置接觸通道範圍之低不純 濃度之η —型擴散層1 0，和位於此η _型擴散層1 0之外 側之高不純物濃度之η +型擴散層1 1。於各閘極電極3及 η +型擴散層1 1之表面，設置導電層1 2。 有關於本發明之第8之實施形態之非揮發性半導體記 億體之記憶格構造係於通道範圍2 5設置階差2 6。經由 此階差2 6，於Ρ型半導體基板1內之電子散亂方向’位 於電荷蓄積層4。因此，提升寫入時之電子之植入效率。 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 χ 297公爱） (請先閱讀背面之注意事項再填寫本頁)First, as shown in FIGS. 16A and 17A, a silicon nitride film 'having a small charge storage capacity is deposited on the entire surface of the P-type semiconductor substrate 1 to form a first blue insulating film 13 having a size of about 100 nm. The deposition of sand nitrided film with a small storage capacity is performed by, for example, the J V D method. After the first gate insulating film 13 is formed, a silicon oxide film 'is deposited by a CVD method to form a second gate insulating film 14 of about 5 to 10 nm. _ 着, via JVD 11—— 一 —— -------- Order --------- ^ 9. (Please read the notes on the back before filling this page) This paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) -45- 488064 Printed by A7 _ __B7 _ of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (43) Silicon nitride film with small charge storage capacity The third gate insulating film 15 having a size of about 10 nm. Next, as shown in FIGS. 16B and 17B, 'on the entire surface of the p-type semiconductor substrate 1 is deposited by doping η-type or p-type impurities with a polycrystalline silicon film ranging from 50 nm to 2 50 by the LP CVD method. The non-volatile memory formation range of 16B is patterned through exposure technology and etching technology to form the gate electrode 3. Next, using the gate electrode 3 as a photomask, the first gate insulating film 1 3, the second gate insulating film 1 4 and the second gate insulating film 1 on the surface of the p-type semiconductor substrate 1 in the range of the source range and the drain range are formed. The third gate insulating film 15 is self-integrated and dry-etched. On the other hand, in the volatile memory formation range of FIG. 14C and the volatile memory formation range of FIG. 17B, the polycrystalline silicon film, the first gate insulating film 1 3, and the second gate Both the insulating film 14 and the third gate insulating film 15 are removed, and the surface of the P-type semiconductor substrate 1 is exposed. Next, as shown in FIG. 16C, in the non-volatile memory formation range, a space 17 is formed as a charge accumulation layer. This space 17 uses an etching solution having a higher etching rate than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 and the second gate insulating film 1 The ends of 4 are selectively formed by wet etching. In a seventh embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are formed of a silicon nitride film, and the second gate insulating film 14 is a silicon nitride film. For the constitution, for example, a fluoric acid system may be used as the etching solution. In addition, the space 17 formed for the charge accumulation layer was replaced with a wet etching method using an etchant, and the plasma dry etching method using a gas containing HF gas was used to form the paper. The paper size is in accordance with the Chinese National Standard < CNS) A4 specification. (210 X 297 mm)!-! ----- 1 · Install ----------- Order --------- Φ (Please read the precautions on the back before filling this page ) -46- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 ____B7 _ 5. The invention description (if) can be completed. On the other hand, as shown in FIG. 17C, the surface of the P-type semiconductor substrate 1 remains exposed in the volatile memory formation range. Next, as shown in FIGS. 16D and 17D, the entire surface of the P-type semiconductor substrate 1 is oxidized by the R T 0 method to form a tunnel insulating film 23 made of a silicon oxide film capable of direct tunneling. After the tunnel insulating film 23 is formed, a silicon nitride film 18 having a high charge storage capacity is deposited on the entire surface of the P-type semiconductor substrate 1 by the L P CVD method. At this time, the space formed for the charge accumulation layer is completely buried and stacked. Then, as shown in FIG. 16E, in the non-volatile memory formation range, the entire surface of the P-type semiconductor substrate 1 is anisotropically etched by RIE to form a silicon nitride film having a high charge storage capability. The charge storage layer 4 (4 a, 4 b). At this time, the volatile memory formation range of FIG. 17E is covered with a photoresist, and the silicon nitride film 18 will not be etched. After the etching of the silicon nitride film 18 is completed, a silicon oxide film is deposited on the entire surface of the p-type semiconductor substrate 1 to form a fourth gate insulating film 24. Here, the fourth gate insulating film 2 4 in the non-volatile memory formation range of FIG. 16E will be removed. This removal is performed by covering the volatile memory formation area of FIG. 17E with a photoresist, and etching and depositing the fourth gate insulating film 24 on the nonvolatile memory formation area of FIG. 16E. Next, as shown in FIG. 17F, a polycrystalline silicon film having a size of 50 to 250 nm in which n-type or p-type impurities are doped is deposited on the entire surface of the P-type semiconductor substrate 1 through the L PCVD method. Then, the polycrystalline silicon film is patterned through an exposure technique and an etching technique to form a gate electrode 3a. Next, using the gate electrode 3 a as an etching mask, the source range and the drain template are formed. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ---- ^ ---- ---- * Pack ------- Order --------- (Please read the precautions on the back before filling out this page) -47- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 Α7 ______ Β7 V. Description of the invention (45) The first gate insulating film 1 on the surface of the P-type semiconductor substrate 1 within the range of the range 3, the second gate insulating film 1 4 and the third gate insulating film 1 5, self Integrated dry etching. On the other hand, in the non-volatile memory formation range, as shown in FIG. 16F, all polycrystalline silicon films may be removed, and the gate electrode 3a may be patterned to form a new gate electrode. Next, as shown in FIGS. 16 (a) and 17 (b), a sidewall interval 9 is formed on the side wall of the gate electrode 3, and then an η + -type diffusion layer 11 having a high impurity concentration is formed. The η + -type diffusion layer 11 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask by implanting η-type impurities, and then activating the implanted impurities by subsequent heat treatment. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method or a sputtering method, and then the p-type semiconductor substrate 1 is subjected to heat treatment in an inert atmosphere. A conductive layer 12 made of a high melting point metal silicide is formed on each of the gate electrodes 3 and the n + -type diffusion layer 11. After the conductive layer 12 is formed, when the unreacted high-melting-point metal remaining in a range other than the above is removed, the nonvolatile memory shown in FIG. 15A and the volatile memory shown in FIG. 15B can be completed. Memory cell construction. However, although it is not shown in the figure, after the billion grid structure of FIGS. 15A and 15B is completed, the normal C is sequentially passed through the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process. The MOS manufacturing process completes the final non-volatile 100 million grid. In the seventh embodiment of the present invention, although the first gate insulating film 13 is made of a silicon nitride film, and the second gate insulating film 14 is made of a silicon oxide film, the Chinese paper standard (CNS) ) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) -------- Order --- I --- —. -48- Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee consumer cooperative 488064 Α7 ______ Β7 V. Description of the invention (46) The third gate insulating film 15 is composed of a silicon nitride film, but the first gate insulating film 13 is made of a sand oxide film. The second gate insulating film 14 is a silicon nitride film, and the third gate insulating film 15 is a silicon oxide film. At this time, for example, the first gate insulating film 13 is formed by thermally oxidizing a silicon oxide film of about 10 nm to the P-type semiconductor substrate 1. The second gate insulating film 14 is composed of a low silicon nitride film having a charge storage capability of about 5 to 10 nm deposited by the J VD method. The third gate insulating film 15 may be composed of a silicon oxide film having a thickness of about 100 nm deposited by the J V D method. In order to form the space 17 formed by charge accumulation, the first gate insulating film 13 and the third gate insulating film 15 are formed by a silicon oxide film, and the second gate insulating film 14 is formed by silicon nitrogen. In order to form a chemical film, for example, a phosphoric acid system may be used as an etching solution. In the sixth and seventh embodiments of the present invention, the non-volatile memory cells and the memory cells of the volatile memory cells are described as examples of the η-type M 0 S transistor, and of course the opposite is true. A memory cell of a conductive P-type MOS transistor is also possible. At this time, in the above description, the conductive type of the appropriate cutting, substrate or diffusion layer may be read as the opposite. (Eighth Embodiment) Next, an eighth embodiment of the present invention will be described. In the first to seventh embodiments described above, the structure of the charge accumulation layer does not depend on the improvement of the efficiency of electron implantation. In the non-volatile semiconductor memory of the floating gate structure, a step is set in the channel part to try to improve the efficiency of electron implantation (S. Ogiua, 1998IEDM, ρ987, US Patent No. This paper applies the national standard of the paper size CNS) A4 specification (210 X 297 mm) -49- — • J J --- ^ --- ^ -------- Order -------- (Please read the note on the back first Please fill in this page for matters) 488064 Α7 Β7 V. Description of Invention (47) No. 5781341). However, in this proposal, a floating gate structure is adopted, which is weak against defects or bleed sides in the oxide film. In addition, it is impossible to obtain sufficient reliability for defects generated during the formation of the step structure. The eighth embodiment of the present invention can improve the efficiency of electron implantation by simple steps. Fig. 18 is a sectional view showing a memory cell structure of a nonvolatile semiconductor memory device according to an eighth embodiment of the present invention. The implementation form of this eighth is to set a step or tilt in the channel range of the memory cell to achieve the improvement of the electron implantation efficiency at the time of writing. As shown in Figure 18, this memory cell is composed of n-type MOS transistor. In the structure of the memory cell according to the eighth embodiment, a second gate insulating film 14 is provided on the surface of the P-type semiconductor substrate 1 through a first gate insulating film 13. Charge storage layers 4a, 4b are formed on both ends of the second gate insulating film 14. A gate electrode 3 is provided on the second gate insulating film 14 and the charge accumulation layers 4 a and 4 b through a third gate insulating film 15. On the side 4 of the gate electrode 3, a sidewall spacer 9 'is provided through the oxide film 16'. A P-type semiconductor substrate 1 below the sidewall spacer 9 is provided, and an η-type diffusion layer having a low impurity concentration in a contact channel range is provided. 10, and the η + -type diffusion layer 11 having a high impurity concentration on the outside of the η − -type diffusion layer 10. A conductive layer 12 is provided on the surface of each gate electrode 3 and the n + -type diffusion layer 11. The memory cell structure of the non-volatile semiconductor memory of the non-volatile semiconductor memory according to the eighth embodiment of the present invention is set at a channel range of 25 and a step of 26. Via this step difference 26, the direction of scattered electrons' in the P-type semiconductor substrate 1 is located on the charge accumulation layer 4. Therefore, the implantation efficiency of electrons during writing is improved. This paper size applies to China National Standard (CNS) A4 (21〇 χ 297 public love) (Please read the precautions on the back before filling this page)

·丨| I I I I I 訂·！ I I I 經濟部智慧財產局員工消費合作社印製 488064 A7 B7___ 五、發明說明（48) (請先閱讀背面之注意事項再填寫本頁) 有關於本發明之第8之實施形態之非揮發性半導體記 憶體之記億格係具有將源極範圍及汲極範圍以低不純濃度 之η -型擴散層1 〇，和高不純物濃度之η +型擴散層1 1 加以構成之L D D構造。然後，閘極絕緣膜則由第1閘極 絕緣膜1 3 (下層）、第2閘極絕緣膜1 4 (中間層）及 第3閘極絕緣膜1 5 (上層）所成3層堆積膜所構成，第 2閘極絕緣膜1 4之兩端部中，形成電荷蓄積層4 a及 4b。於此2個之電荷蓄積層4a及4b蓄積電子。該蓄 積狀態係可有（1 )電荷蓄積層4 a、4 b之任一者皆未 蓄積電子之狀態，（2)僅電荷蓄積層4 a蓄積電子之狀 態，（3 )僅電荷蓄積層4 b蓄積電子之狀態，（4 )電 荷蓄積層4 a ，4 b皆蓄積電子之狀態之4個狀態。經由 保持於此2個之電荷蓄積層4 a ，4 b之電子之有無，將 所產生之臨限値之變化分，對應於記憶資訊之> 0 0 " ’ 、、0 1 〃 ， 、、1 0 〃 ，、、1 1 〃 。又，於此記憶格構造之 經濟部智慧財產局員工消費合作社印製 中，電荷蓄積層4 a ，4 b係位於通道範圍端部之上方之 故，通道範圍中央部之臨限値電壓係僅以通道範圍之不純 物濃度加以決定，不依附於電荷蓄積層4 a ，4 b之電子 之蓄積狀態。因此，可防止電荷蓄積層4 a ，4 b之電子 之過度不足的過度消除，由此不會產生由於過度消除起因 的泄放不良，程式不良，讀取不良等。又，源極範圍和汲 極範圍間之泄放電流係可僅以閘極電壓加以抑制，實現高 可靠性之非揮發性半導體記憶體。電荷蓄積層4 a及4 b 係以C V D法之電荷蓄積能力高的矽氮化膜加以構成即可 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -51 - 488064 A7 B7 五、發明說明（49) 。經由於矽氮化膜之離散性之電荷捕獲準位蓄積電子，可 得難以於下部絕緣膜之膜質影響之電荷保持特性。又，以 矽膜，多結晶矽膜加以構成之時，可便宜地加以製造。更 且，將第1閘極絕緣膜1 3、第3閘極絕緣膜1 5以具有 矽氧化膜（S i 〇2膜）之2倍程度之介電率的矽氮化膜（ S i 3N4膜）加以構成時，可將矽氧化膜換算膜厚爲4〜 1 1 n m程度之非常薄的閘極絕緣膜安定實現。例如，矽 氧化膜換算膜厚爲5 nm之矽氮化膜之實質膜厚爲1 〇 nm程度之故，直接進行隧道植入亦不會激勵。因此，電 子之植入抽出時之電壓係被低電壓化，不單是記憶格之微 細化，亦可達周邊高電壓動作元件之微細化。 有關本發明之第8之實施形態之非揮發性半導體記憶 體之記億格中，於源極範圍及汲極範圍之耐壓提升之目的 上，設置n_型擴散層1 0，以構成LDD構造，以單汲極 構造，雙汲極構造構成源極範圍及汲極範圍亦可。第2閘 極絕緣膜1 4係雖可防止電荷蓄積層4 a — 4 b間之泄放 ，例如可以矽氧化膜構成。又，於第2閘極絕緣膜1 4使 用具有高介電率之金屬氧化膜時，可提升通道範圍中央之 電流傳達特性。做爲金屬氧化物例如可有T i〇2、 Ta2〇5、Al2〇5、PZT、SBT。 本發明之第8之實施形態中，於源極側、汲極側之兩 方，設置階差2 6 ，僅設於一方亦可。尤其，記憶1位元 分之資訊的記憶體中’有一方即充分。 接著，對於有關本發明之第8之實施形態的非揮發性 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閱讀背面之注意事項再填寫本頁) IT -ml — — — ^--I---I I · 經濟部智慧財產局員工消費合作社印製 -52- 488064 A7 _______________ B7 五、發明說明（5Q) 記憶體之動作，使用圖1 9 A及圖1 9 B加以說明。圖 1 9 A係說明寫入動作之非揮發性記憶體之截面圖。圖 1 9 B係說明消除動作之非揮發性記憶體之截面圖。如圖 1 9 A所示，於記憶格之寫入時，於閘極g施加6〜8 V 程度，於汲極D施加4 V〜5 V之程度，將源極s加以接 地。如此地，施加電壓時，以通道熱電子，將電子植入汲 極範圍側之電荷蓄積層4 b。於通道範圍2 5設置階差 26地，於電子散亂方向定位電荷蓄積層4b。爲此，對 於電荷蓄積層4 b之電子之植入效率的提升，可達植入速 度之高速化，施加電壓之減低化。於源極範圍側之電荷蓄 積層4 a植入電子時，將施加於各汲極D、源極S之電壓 與上述之情形加以置換即可，另一方面，記憶格之消除係 如圖1 9 B所示，於閘極G施加負電壓（--5 V )，利 用FN型隧道電流，自電荷蓄積層4a、4b引出電子地 加以進行。又，閘極電極3於複數之記憶格共有之時，自 此等之記憶格可同時引出電子。此時，源極S、汲極D係 呈與P型半導體基板1同電位即可。又，將與p型半導體 基板1之電位不同之正電壓，施加於汲極D，將源極S呈 浮電位之時，可僅由汲極D側之電荷蓄積層4 a引出電子 。僅由源極S側之電荷蓄積層4 b引出電子之時，於源極 S施加正電壓，令汲極D呈浮電位即可。 又，雖未加以圖示，記憶格之讀取係檢測流於源極S 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ， 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) —------訂·-------. 經濟部智慧財產局員工消費合作社印製 -53 - 488064 經濟部智慧財產局員工消費合作社印製 A7 ______Β7 _ 五、發明說明（51) 流傳達特性（通道電感）者。對於於源極S、汲極D之何 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態，得4個不 同之電流傳達特性，由此以1個格，可記憶2位元分之資 訊。 接著，將有關本發明之第8之實施形態的非揮發性半 導體記億體之記憶格之製造方法，使用圖2 0 A乃至圖 2 0 I加以說明。首先，如圖2 0 A所示，將被覆形成通 道範圍2 5之範圍的光阻劑圖案2 7，形成於p型半導體 基板1。然後，如圖2 0 B所示，例如經由R I E法，將 p型半導體基板1加以蝕刻，形成階差2 6。 接著，如圖2 0 C·所示，於p型半導體基板1 ，於整 面，堆積電荷蓄積能力小之矽氮化膜，形成1 0 n m之第 1閘極電極1 3。電荷蓄積能力小之矽氮化膜之堆積係例 如以J V D法加以進行。形成第1閘極絕緣膜1 3後，經 由CVD法堆積矽氧化膜，形成5〜1 0 nm程度之第2 閘極絕緣膜1 4。接著，經由J V D法，堆積電荷蓄積能 力小之矽氮化膜，形成1 0 n m程度之第3閘極絕緣膜 15。 接著，如圖2 0 D所示，於p型半導體基板1整面經 由L P CVD法，堆積滲雜η型或p型不純物之5 0〜 2 5 0 n m之多結晶矽膜後，經由曝光技術及蝕刻技術加 以圖案化，形成閘極電極3。接著，將閘極電極3做爲光 罩，將形成源極範圍及汲極範圍之範圍的P型半導體基板 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁} -l· 裝·！ —訂---- -54- 經濟部智慧財產局員工消費合作社印製 488064 A7 __B7___ 五、發明說明（52) 1之表面的第1閘極絕緣膜1 3 .、第2閘極絕緣膜1 4及 第3閘極絕緣膜1 5，自我整合地加以乾蝕刻。 接著，如圖2 0 E所示，形成爲電荷蓄積層形成之空 間1 7。此空間1 7係使用較第1閘極絕緣膜1 3及第3 閘極絕緣膜1 5，第2閘極絕緣膜1 4之鈾刻速度爲大的 蝕刻液，將第2閘極絕緣膜1 4之端部選擇性地以濕蝕刻 加以形成。於本發明之第2之實施形態中，將第1閘極絕 緣膜1 3及第3閘極絕緣膜1 5以矽氮化膜加以構成，將 第2閘極絕緣膜1 4以矽氧化膜加以構成之故，做爲蝕刻 液使用例如氟酸即可。又爲電荷蓄積層形成之空間1 7係 替換使用蝕刻液之濕蝕刻法，以使用包含H F氣體之電漿 乾蝕刻法加以形成亦可。 接著，如圖2 0 F所示，於ρ型半導體基板1整面， 經由L P C V D法，將電荷蓄積能力高之矽氮化膜1 8， 完全埋入爲電荷蓄積層形成之空間1 7地加以堆積。然後 ，如圖2 0 G所示，對ρ型半導體基板1整面，進行 R I Ε之向異性蝕刻，形成以電荷蓄積能力高之矽氮化膜 所構成之電荷蓄積層4 a及4 b。 接著，如圖2 0H所示，於ρ型半導體基板1整面， 形成氧化膜1 6之後，形成低不純物濃度之n -型擴散層 1 0。η —型擴散層1 〇係經由離子植入技術，將閘極電極 3做爲光罩，植入Ν型不純物，經由之後之熱處理，活化 植入之不純物而形成者。 接著，如圖2 0 I所示，於閘極電極3之側壁，形成 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閲讀背面之注意事項再填寫本頁) 裝 ----訂--------- -55- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7 五、發明說明（53) 側壁間隔9之後，形成高不純物濃度之η +型擴散層1 1。 n f型擴散層1 1係經由離子植入技術，將閘極電極3及側 壁間隔9做爲光罩，植入η型不純物，經由之後之熱處理 活化植入之不純物而加以形成。 接著，於Ρ型半導體基板1之整面，經由CVD法或 濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將Ρ 型半導體基板1於不活性氣氛中經由熱處理，於各閘極電 極3、及η+型擴散層1 1之表面，形成以高融點金屬矽化 物所構成之導電層1 2。形成導電層1 2後，除去殘留於 上述以外之範圍的未反應高融點金屬時，可完成圖1 8所 示之記憶格構造。 然而，雖未圖示，圖1 8之記億格構造完成後，順序 經由層間絕緣膜形成工程，連接孔形成工程，配線形成工 程，鈍化膜形成工程等之通常之CM〇S製造工程，完成 最終之非揮發性記憶格。 根據本發明之第8之實施形態時，可將電荷蓄積層 4 a及4 b自我整合形成於閘極電極3之兩端下方。因此 ，可達格電晶體之閘極長方向之微細化。由此，可提供大 容量、高密度之非揮發性半導體記億體。又每位元之格面 積較以往減少幾近一半，可實現大幅減剌之非揮發性半導 體記億體。 又，電荷蓄積層4 a及4 b之通道長方向之寬度係經 由第1閘極絕緣膜1 3及第3閘極絕緣膜1 5和第2閘極 絕緣膜1 4之蝕刻速度差，以及鈾刻時間之調節可容易控 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I HI L---I I I ^ — — — — — — — ^«1 —--in (請先閱讀背面之注意事項再填寫本頁) -56- 488064 A7 B7 五、發明說明（54) (請先閱讀背面之注意事項再填寫本頁) 制。由此，可對稱配置電荷蓄積層4a及4b。然後’電 荷蓄積層4 a和4 b係經由第2閘極絕緣膜1 4電氣性地 完全分離之故，電荷蓄積層1 4 a及1 4 b間之相互作用 不會產生。更且，電荷蓄積層4 a及4 b係自源極範圍、 閘極電極3及通道範圍，經由第1之絕緣膜1 3 ’第3之 絕緣膜1 5及氧化膜1 6完全加以絕緣之故，可提供電荷 保持性優異之非揮發性半導體記億體。電荷蓄積層4 a及 4 b係自閘極電極3之端部延伸存在於通道範圍方向加以 形成，經由電荷蓄積層4 a及4 b中之通道範圍側部分之 電荷蓄積狀態，幾乎決定記憶格之電流傳達特性。因此， 將此部分之閘極長方向之長度縮小到極限之時，可提供更 爲微細之非揮發性半導體記億體。 更且，格構造係可容易實現通常之CMO S工程之故 ，使用既有之製造生產線，可以低成本製造非揮發性半導 體記億體。 經濟部智慧財產局員工消費合作社印製 然後，本發明之第8之實施形態中，可提升寫入時之 電子植入效率。爲此，可達寫入速度之高速化，寫入時之 施加電壓之減低化。 (第9之實施形態） 接著，對於本發明之第9之實施形態加以說明。本發 明之第9之實施形態係於上述第8之實施形態中，無需圖 1 8之配置於電荷蓄積層4 a和電荷蓄積層4 b間之第2 閘極絕緣膜1 4，採用2個電荷蓄積層4 a及4 b —體化 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 488064 A7 B7___ 五、發明說明（55) (請先閱讀背面之注意事項再填寫本頁) 之構成。圖2 1係顯示有關本發明之第9之實施形態的非 揮發性記憶體之記億格構造的截面圖。如圖2 1所示，此 記憶格之構造係交換上述第8之實施形態之電荷蓄積層 4a、4b及第2閘極絕緣膜14，配置電荷蓄積層4f 者。 接著，將有關本發明之第9之實施形態的非揮發性半 導體記憶體之記憶格之製造方法，使用圖2 2 A乃至圖 2 2 F加以說明。首先，如圖2 2 A所示，將被覆形成通 道範圍2 5之範圍的光阻劑圖案2 7，形成於p型半導體 基板1。然後，如圖2 2 B所示，例如經由R I E法，將 P型半導體基板1加以鈾刻，形成階差2 6。 接著，如圖2 2 C所示，於p型半導體基板1整面， 堆積電荷蓄積能力小之矽氮化膜，形成1 0 n m之第1閘 極電極1 3。電荷蓄積能力小之矽氮化膜之堆積係例如以 J V D法加以進行。形成第1閘極絕緣膜1 3後，經由 C V D法堆積矽氧化膜，形成5〜1 0 n m程度之第2閘 極絕緣膜1 4。接著，經由J V D法，堆積電荷蓄積能力 小之矽氮化膜，形成1 0 n m程度之第3閘極絕緣膜1 5 經濟部智慧財產局員工消費合作社印製 〇 接著，如圖2 2 D所示，於P型半導體基板1整面經 由L P CVD法，堆積滲雜η型或p型不純物之5 0〜 2 5 0 n m之多結晶矽膜後，經由曝光技術及蝕刻技術加 以圖案化5形成閘極電極3。接著’將閘極電極3做爲光 罩，將形成源極範圍及汲極範圔之範圍的P型半導體基板 -58 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 488064 經濟部智慧財產局員工消費合作社印製 A7 ___B7_____ 五、發明說明（50) 1之表面的第1閘極絕緣膜1 3、矽氮化膜1 8及第3聞 極絕緣膜1 5，自我整合地加以乾蝕刻。在此，形成電荷 蓄積層4 f。 接著’如圖2 0 E所示，於ρ型半導體基板1整面， 形成氧化膜1 6之後，形成低不純物濃度之η —型擴散層 1 0。η -型擴散層1 〇係經由離子植入技術，將閘極電極 3做爲光罩，植入Ν型不純物，經由之後之熱處理，活化 植入之不純物而形成者。 接著，如圖2 0 F所示，於閘極電極3之側壁，形成 側壁間隔9之後，形成高不純物濃度之η +型擴散層1 1。 η +型擴散層1 1係經由離子植入技術，將閘極電極3及側 壁間隔9做爲光罩，植入η型不純物，經由之後之熱處理 活化植入之不純物而加以形成。 接著，於Ρ型半導體基板1之整面，經由CVD法或 濺射法，堆積·鎢、鈦、鈷等之高融點金屬膜，接著，將Ρ 型半導體基板1於不活性氣氛中經由熱處理，於各閘極電 極3、及η+型擴散層1 1之表面，形成以高融點金屬矽化 物所構成之導電層1 2。形成導電層1 2後，除去殘留於 上述以外之範圍的未反應高融點金屬時，可完成圖2 1所 示之記憶格構造。 然而，雖未圖示，圖2 1之記億格構造完成後，順序 經由層間絕緣膜形成工程，連接孔形成工程，配線形成工 程，鈍化膜形成工程等之通常之CM〇S製造工程’完成 最終之非揮發性記憶格。 (請先閱讀背面之注意事項再填寫本頁) 4 裝 -------訂----- I--- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -59 488064 Α7 Β7 五、發明說明（57) (第1 0之實施形態） (請先閱讀背面之注意事項再填寫本頁) 接著，對於本發明之第1 〇之實施形態加以說明。圖 2 3係顯示有關本發明之第1 〇之實施形態的非揮發性半 導體記憶體之記憶格構造的截面圖。上述第8及第9之實 施形態中，將通道範圍對於半導體基板呈凸狀態地，於通 道範圍兩端設置了階差，但於此第1 〇之實施形態中，將 通道範圍對於半導體基板呈凹狀態地，於通道範圍設置階 差者。然後，此第1 0之實施形態亦於記憶格之.通道範圍 設置階差或傾斜地，達成寫入時之電子植入效率的提升。 經濟部智慧財產局員工消費合作社印製 如圖2 3所示，此記憶格係以P型Μ〇S電晶體加以 構成。然後，有關此第1之實施形態的記憶格之構造中， 於η型半導體基板1 9之表面，介由第1閘極絕緣膜1 3 ，設置第2閘極絕緣膜1 4。於第2閘極絕緣膜1 4之兩 端，形成電荷蓄積層4 a ，4 b。於第2閘極絕緣膜1 4 及電荷蓄積層4a、4b上，介由第3閘極絕緣膜15， 設置閘極電極3。於閘極電極3之側面，介由氧化膜1 6 ，設置側壁間隔9 ，於此側壁間隔9之下部之η型半導體 基板1 9，設置接觸通道範圍之低不純濃度之Ρ ^型擴散層 2 0，和位於此Ρ —型擴散層2 0之外側之高不純物濃度之 Ρ +型擴散層2 1。於各閘極電極3及Ρ +型擴散層2 1之 表面，設置導電層12。 更且，有關於本發明之第1 0之實施形態之非揮發性 半導體記億體之記憶格構造係於通道範圍2 5設置階差 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -60 - 488064 A7 B7 五、發明說明（58) 2 6。經由此階差2 6 ，於P型半導體基板1內之電子散 (請先閱讀背面之注意事項再填寫本頁) 亂方向，位於電荷蓄積層4。因此，提升寫入時之電子之 植入效率。 有關於本發明之第1 0之實施形態之非揮發性半1 _ _ 記憶體之記憶格係具有將源極範圍及汲極範圍以低不純濃 度之P—型擴散層2 0，和高不純物濃度之P+型擴散層 2 1加以構成之L D D構造。然後，閘極絕緣膜則由第1 閘極絕緣膜1 3 (下層）、第2閘極絕緣膜1 4 (中間層 )及第3閘極絕緣膜1 5 (上層）所成3層堆積膜所構成 ，第2閘極絕緣膜1 4之兩端部中，形成電荷蓄積層4 a 及4 b。於此2個之電荷蓄積層4 a及4 b蓄積電子。該 蓄積狀態係可有（1 )霞荷蓄積層4 a、4 b之任一者皆 未蓄積電子之狀態，（2 )僅電荷蓄積層4 a蓄積電子之 狀態，（3 )僅電荷蓄積層4 b蓄積電子之狀態，（4 ) 電荷蓄積層4 a ，4 b皆蓄積電子之狀態之4個狀態。經 由保持於此2個之電荷蓄積層4 a ，4 b之電子之有無， 將所產生之臨限値之變化分，對應於記憶資訊之〇 〇 " 經濟部智慧財產局員工消費合作社印製 ，0 1 〃 ， ''10〃 ， 1 1 〃 。又，於此記憶格構造 之中，電荷蓄積層4 a ，4 b係位於通道範圍端部之上方 之故，通道範圍中央部之臨限値電壓係僅以通道範圍之不 純物濃度加以決定，不依附於電荷蓄積層4 a ，4 b之電 子之蓄積狀態。因此，可防止電荷蓄積層4a ，4b之電 子之過度不足的過度消除，由此不會產生由於過度消除起 因的泄放不良，程式不良，讀取不良等。又，源極範圍和 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） -61 - 經濟部智慧財產局員工消費合作社印製 488064 Α7 Β7 五、發明說明（59) 汲極範圍間之泄放電流係可僅以閘極電壓加以抑制’實現 高可靠性之非揮發性半導體記憶體。電荷蓄積層4 a及 4 b係以C V D法之電荷蓄積能力高的矽氮化膜加以構成 即可。經由於矽氮化膜之離散性之電荷捕獲準位蓄積電子 ，可得難以於下部絕緣膜之膜質影響之電荷保持特性。又 ，以矽膜，多結晶矽膜加以構成之時’可便宜地加以製造 。更且，將第1閘極絕緣膜1 3、第3閘極絕緣膜1 5以 具有矽氧化膜（S i 〇2膜）之2倍程度之介電率的矽氮化 膜（S i 3N4膜）加以構成時，可將矽氧化膜換算膜厚爲 4〜1 1 n m程度之非常薄的閘極絕緣膜安定實現。例如 ，矽氧化膜換算膜厚爲5 nm之矽氮化膜之實質膜厚爲 1 0 nm程度之故，直接進行隧道植入亦不會激勵。因此 ，電子之植入抽出時之電壓係被低電壓化，不單是記憶格 之微細化，亦可達周邊高電壓動作元件之微細化。 有關本發明之第1 0之實施形態之非揮發性半導體記 憶體之記憶格中，於源極範圍及汲極範圍之耐壓提升之目 的上，設置P _型擴散層1 0，以構成L D D構造，以單汲 極構造，雙汲極構造構成源極範圍及汲極範圍亦可。第2 閘極絕緣膜1 4係雖可防止電荷蓄積層4 a - 4 b間之泄 放，例如可以矽氧化膜構成。又，於第2閘極絕緣膜1 4 使用具有高介電率之金屬氧化膜時，可提升通道範圍中央 之電流傳達特性。做爲金屬氧化物例如可有T i 0 2、 Ta2〇5、Al2〇5、PZT、SBT。 本發明之第1 0之實施形態中，於源極側、汲極側之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -J· ----11--^---------. -02- 488064 A7 B7 五、發明說明（6Q) 兩方，設置階差2 6，僅設於一方亦可。尤其，記憶1位 元分之資訊的記憶體中，有一方即充分。 接著，對於有關本發明之第1 0之實施形態的非揮發 性記憶體之動作，使用圖2 4 A及圖2 4 B加以說明。圖 2 4 A係說明寫入動作之非揮發性記憶體之截面圖。圖 2 4 B係說明消除動作之非揮發性記憶體之截面圖。如圖 2 4 A所示，於記憶格之寫入時，於閘極G施加5 V程度 ，於汲極D施加—5 V之程度，將源極S呈浮電位。如此 地，施加電壓時，於帶間帶隧道現象之電子，以汲極附近 之電場供予能量，植入汲極範圍側之電荷蓄積層4 b。於 通道範圍2 5設置階差2 6地，於電子注入方向定位電荷 蓄積層4 b。爲此，對於電荷蓄積層4 b之電子之植入效 率的提升，可達植入速度之高速化，施加電壓之減低化。 於源極範圍側之電荷蓄積層4 a植入電子時，將施加於各 汲極D、源極S之電壓與上述之情形加以置換即可，另一 方面，記憶格之消除係如圖2 4 B所示，於閘極G施加負 電壓（〜—5V)，利用FN型隧道電流，自電荷蓄積層 4 a、4 b引出電子地加以進行。又，閘極電極3於複數 之記憶格共有之時，自此等之記憶格可同時引出電子。此 時，源極S、汲極D係呈與η型半導體基板1 9同電位即 可。又，將與Ρ型半導體基板1之電位不同之正電壓，施 加於汲極D，將源極S呈浮電位之時，可僅由汲極D側之 電荷蓄積層4 a引出電子。僅由源極S側之電荷蓄積層 4 b引出電子之時，於源極S施加正電壓，令汲極D呈浮 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁)· 丨 | I I I I I Order! III Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7___ V. Description of the Invention (48) (Please read the notes on the back before filling this page) Non-volatile semiconductor memory related to the eighth embodiment of the present invention The body of the grid is a LDD structure in which the source range and the drain range are composed of an η-type diffusion layer 10 with a low impurity concentration and an η + -type diffusion layer 1 1 with a high impurity concentration. The gate insulating film is a three-layer stacked film formed by the first gate insulating film 1 3 (lower layer), the second gate insulating film 1 4 (middle layer), and the third gate insulating film 1 5 (upper layer). As a result, the charge storage layers 4 a and 4 b are formed on both ends of the second gate insulating film 14. Electrons are accumulated in the two charge accumulation layers 4a and 4b. The accumulation state may be (1) a state in which neither of the charge accumulation layers 4 a, 4 b has accumulated electrons, (2) a state in which only the charge accumulation layer 4 a accumulates electrons, or (3) only a charge accumulation layer 4 The state where b accumulates electrons, (4) The charge accumulation layers 4 a and 4 b are all four states in which electrons are accumulated. Through the existence of the electrons held in these two charge accumulation layers 4 a and 4 b, the change in the threshold value 値 generated is divided into corresponding memory information > 0 0 " ',, 0 1 〃,,, , 1 0 〃,,, 1 1 〃. In addition, in the memory of the Intellectual Property Bureau of the Ministry of Economic Affairs ’employee consumer cooperatives, the charge accumulation layers 4 a and 4 b are located above the end of the channel range, and the threshold voltage at the center of the channel range is only It is determined by the impurity concentration in the channel range, and does not depend on the state of accumulation of electrons in the charge accumulation layers 4 a and 4 b. Therefore, it is possible to prevent excessive elimination of excessive electrons in the charge accumulation layers 4a, 4b, thereby preventing occurrence of defective discharge due to excessive elimination, defective programming, poor reading, and the like. In addition, the bleeder current between the source range and the drain range can be suppressed by the gate voltage only, realizing a highly reliable non-volatile semiconductor memory. The charge accumulating layers 4 a and 4 b are made of a silicon nitride film with high charge accumulating ability by the CVD method. This paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) -51-488064 A7 B7 V. Description of Invention (49). By accumulating electrons due to the discrete charge trapping level of the silicon nitride film, it is possible to obtain a charge retention characteristic which is difficult to be affected by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be manufactured inexpensively. Furthermore, the first gate insulating film 1 3 and the third gate insulating film 15 are formed of a silicon nitride film (S i 3N4) having a dielectric constant approximately twice that of a silicon oxide film (S i 〇2 film). Film), a very thin gate insulating film with a thickness of about 4 to 11 nm in terms of silicon oxide film can be stably realized. For example, since the silicon nitride film with a thickness of 5 nm is about 10 nm, the thickness of the silicon nitride film is about 10 nm, so the tunnel implantation will not stimulate it. Therefore, the voltage at the time of implantation and extraction of electrons is reduced, not only the miniaturization of memory cells, but also the miniaturization of peripheral high-voltage operating elements. In the hundreds of millions of non-volatile semiconductor memories related to the eighth embodiment of the present invention, an n_-type diffusion layer 10 is provided for the purpose of improving the withstand voltage of the source range and the drain range to form an LDD. The structure can be a single-drain structure or a double-drain structure to form a source range and a drain range. The second gate insulating film 14 can prevent the charge accumulation layers 4 a-4 b from leaking, and can be made of, for example, a silicon oxide film. When a metal oxide film having a high dielectric constant is used as the second gate insulating film 14, the current transmission characteristic in the center of the channel range can be improved. Examples of the metal oxide include Ti 102, Ta205, Al205, PZT, and SBT. In the eighth embodiment of the present invention, a step difference of 2 6 may be provided on both the source side and the drain side, and only one side may be provided. In particular, one of the memories that stores one-bit information is sufficient. Next, for the non-volatile paper size of the eighth embodiment of the present invention, the Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied < Please read the precautions on the back before filling this page) IT -ml — — — ^-I --- II · Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-52- 488064 A7 _______________ B7 V. Description of the invention (5Q) The operation of the memory, use Figure 1 9A and Figure 1 9 B. Figure 19 A is a cross-sectional view of a non-volatile memory illustrating a write operation. Figure 19B is a cross-sectional view of the non-volatile memory illustrating the erasing action. As shown in FIG. 19A, when writing in the memory cell, the gate electrode g is applied to a level of 6 to 8 V, and the drain electrode D is applied to a level of 4 V to 5 V to ground the source s. In this way, when a voltage is applied, electrons are channeled to the hot-electron channel, and the electrons are implanted into the charge accumulation layer 4b on the drain region side. A step 26 is set in the channel range 25, and the charge accumulation layer 4b is positioned in the electron scattering direction. For this reason, the improvement of the implantation efficiency of the electrons in the charge accumulation layer 4 b can be achieved by increasing the implantation speed and reducing the applied voltage. When the electrons are implanted in the charge accumulation layer 4 a on the source range side, the voltages applied to the respective drains D and S can be replaced with those described above. On the other hand, the memory cell is eliminated as shown in Figure 1 As shown in FIG. 9B, a negative voltage (-5 V) is applied to the gate G, and electrons are extracted from the charge storage layers 4a and 4b by using an FN-type tunneling current. When the gate electrode 3 is shared by a plurality of memory cells, electrons can be simultaneously extracted from these memory cells. In this case, the source S and the drain D may be at the same potential as the P-type semiconductor substrate 1. When a positive voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain D and the source S is at a floating potential, electrons can be extracted only from the charge storage layer 4a on the side of the drain D. When the electrons are extracted only from the charge storage layer 4b on the source S side, a positive voltage is applied to the source S so that the drain D may be at a floating potential. Also, although not shown, the reading of the memory cell is performed by detecting the reading current flowing between the source S and the drain D. Through the accumulation state of the charge accumulation layers 4 a and 4 b, the electric power in the vicinity of the source range and the drain range can be adjusted. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please read the back first) Please pay attention to this page before filling in this page) ———---- Order · -------. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs -53-488064 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ______ Β7 _ V. Description of the invention (51) Those who have flow transmission characteristics (channel inductance). For biasing between the source S and the drain D, it is sufficient to select a person whose modulation of the current transmission characteristic is significant. Through the four accumulation states of the charge accumulation layers 4a and 4b, four different current transfer characteristics are obtained, so that one bit can memorize the information of 2 bits. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory device according to the eighth embodiment of the present invention will be described with reference to FIGS. 20A to 20I. First, as shown in FIG. 20A, a photoresist pattern 27 covered with a channel range 25 is formed on the p-type semiconductor substrate 1. Then, as shown in FIG. 2B, the p-type semiconductor substrate 1 is etched by, for example, the R I E method to form a step difference 26. Next, as shown in FIG. 20C ·, a silicon nitride film having a small charge accumulation ability is deposited on the entire p-type semiconductor substrate 1 to form a first gate electrode 13 of 10 nm. The deposition of a silicon nitride film having a small charge storage capacity is performed by, for example, the J V D method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by a CVD method to form a second gate insulating film 14 of about 5 to 10 nm. Next, a silicon nitride film having a small charge storage capacity is deposited by the J V D method to form a third gate insulating film 15 having a size of about 10 nm. Next, as shown in FIG. 20D, a polycrystalline silicon film doped with n-type or p-type impurities of 50 to 250 nm is deposited on the entire surface of the p-type semiconductor substrate 1 by LP CVD, and then exposed to light through an exposure technique. And an etching technique to pattern the gate electrode 3. Next, using the gate electrode 3 as a photomask, a P-type semiconductor substrate forming a range of a source range and a drain range. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (please first Read the precautions on the back and fill out this page} -l · 装 ·！ —Order ---- -54- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 __B7___ V. Description of the Invention (52) 1 1 gate insulating film 1 3, second gate insulating film 14 and third gate insulating film 15 are self-integrated and dry-etched. Next, as shown in FIG. 20E, a charge accumulation layer is formed. Space 1 7. This space 1 7 uses an etching solution having a higher uranium etching speed than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14. The ends of the 2 gate insulating film 14 are selectively formed by wet etching. In the second embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are formed of silicon. Since the nitride film is formed, and the second gate insulating film 14 is formed of a silicon oxide film, for example, fluoric acid may be used as an etching solution. The space 17 formed by the charge accumulation layer may be replaced by a wet etching method using an etchant, and may be formed by a plasma dry etching method including an HF gas. Next, as shown in FIG. 2F, on the p-type semiconductor substrate 1 On the entire surface, a silicon nitride film 18 having a high charge storage capacity is completely buried in a space formed by the charge storage layer 17 by LPCVD, and is stacked. Then, as shown in FIG. 20G, a p-type semiconductor is deposited. Anisotropic etching of RI E is performed on the entire surface of the substrate 1 to form charge storage layers 4 a and 4 b composed of a silicon nitride film having a high charge storage ability. Next, as shown in FIG. 20H, on a p-type semiconductor substrate After the oxide film 16 is formed on the entire surface, an n-type diffusion layer 10 with a low impurity concentration is formed. The η-type diffusion layer 10 is implanted with the gate electrode 3 as a photomask through ion implantation technology. The N-type impurities are formed by the subsequent heat treatment to activate the implanted impurities. Next, as shown in FIG. 20I, on the side wall of the gate electrode 3, the paper size applicable to the Chinese National Standard (CNS) A4 specification ( 210 X 297 public love) (Please read the first Please fill in this page for further details.) Binding ---- Order --------- -55- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7 V. Description of the invention (53) After the sidewall spacer 9 Form η + -type diffusion layer 1 1 with high impurity concentration. Nf-type diffusion layer 1 1 uses gate implantation electrode 3 and sidewall spacer 9 as photomasks through ion implantation technology, and implants n-type impurity, after subsequent heat treatment The implanted impurities are activated and formed. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method or a sputtering method, and then the P-type semiconductor substrate is deposited. 1 Through heat treatment in an inactive atmosphere, a conductive layer 12 made of a high melting point metal silicide is formed on the surface of each gate electrode 3 and the η + type diffusion layer 11. When the conductive layer 12 is formed and the unreacted high-melting-point metal remaining in a range other than the above is removed, the memory cell structure shown in FIG. 18 can be completed. However, although it is not shown in the figure, after the completion of the Yiji structure in FIG. 18, the usual CMOS manufacturing process such as the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process are completed in order. The ultimate non-volatile memory cell. According to the eighth embodiment of the present invention, the charge storage layers 4 a and 4 b can be formed by self-integration under both ends of the gate electrode 3. Therefore, the miniaturization of the gate electrode in the long direction can be achieved. As a result, a large-capacity, high-density non-volatile semiconductor memory can be provided. In addition, the grid area of each bit is reduced by nearly half compared with the past, which can achieve a significant reduction in non-volatile semiconductor memory. Further, the widths in the longitudinal direction of the channels of the charge accumulation layers 4a and 4b are caused by the difference in etching speed between the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 and The adjustment of uranium engraving time can be easily controlled. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) I HI L --- III ^ — — — — — — — ^ «1 —-- in ( Please read the precautions on the back before filling out this page) -56- 488064 A7 B7 V. Description of the invention (54) (Please read the precautions on the back before filling out this page). Thereby, the charge storage layers 4a and 4b can be arranged symmetrically. Then, the charge storage layers 4 a and 4 b are electrically and completely separated through the second gate insulating film 14, so that the interaction between the charge storage layers 14 a and 14 b is not generated. Furthermore, the charge accumulation layers 4 a and 4 b are completely insulated from the source region, the gate electrode 3 and the channel region through the first insulating film 1 3 ′, the third insulating film 15 and the oxide film 16. Therefore, a nonvolatile semiconductor memory having excellent charge retention can be provided. The charge accumulation layers 4 a and 4 b are formed by extending from the ends of the gate electrode 3 and existing in the channel range direction. The charge accumulation state of the channel range side portions in the charge accumulation layers 4 a and 4 b almost determines the memory cell. The current transfer characteristics. Therefore, when the length of the gate length in this portion is reduced to the limit, a finer nonvolatile semiconductor memory can be provided. What's more, the lattice structure can easily realize the common CMO S project. Using the existing manufacturing production line, non-volatile semiconductors can be manufactured at low cost. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Then, in the eighth embodiment of the present invention, the efficiency of electron implantation at the time of writing can be improved. Therefore, the writing speed can be increased, and the applied voltage can be reduced during writing. (Ninth Embodiment) Next, a ninth embodiment of the present invention will be described. The ninth embodiment of the present invention is the eighth embodiment described above, and the second gate insulating film 14 disposed between the charge accumulation layer 4 a and the charge accumulation layer 4 b shown in FIG. 18 is not required, and two are used. Charge accumulating layers 4 a and 4 b — Dimensions This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 488064 A7 B7___ V. Description of the invention (55) (Please read the precautions on the back before filling This page). Fig. 21 is a cross-sectional view showing a petabyte structure of a nonvolatile memory according to a ninth embodiment of the present invention. As shown in FIG. 21, the structure of this memory cell is a structure in which the charge storage layers 4a, 4b and the second gate insulating film 14 of the eighth embodiment are exchanged, and the charge storage layer 4f is arranged. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory device according to a ninth embodiment of the present invention will be described with reference to Figs. 2A to 2F. First, as shown in FIG. 2A, a photoresist pattern 27 covering the channel range 25 is formed on the p-type semiconductor substrate 1. Then, as shown in FIG. 2B, for example, the P-type semiconductor substrate 1 is etched with uranium through the R I E method to form a step difference 26. Next, as shown in FIG. 2C, a silicon nitride film having a small charge accumulation ability is deposited on the entire surface of the p-type semiconductor substrate 1 to form a first gate electrode 13 of 10 nm. The deposition of the silicon nitride film having a small charge storage capacity is performed by, for example, the J V D method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by the CVD method to form a second gate insulating film 14 of about 5 to 10 nm. Next, through the JVD method, a silicon nitride film with a small charge accumulation capacity is deposited to form a third gate insulating film at a level of 10 nm. 15 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, as shown in Figure 2 2 D It is shown that a polycrystalline silicon film doped with η-type or p-type impurities of 50 to 2 50 nm is deposited on the entire surface of the P-type semiconductor substrate 1 by LP CVD, and then patterned 5 through exposure and etching techniques. Gate pole electrode 3. Next, using the gate electrode 3 as a photomask, a P-type semiconductor substrate with a source range and a drain range will be formed. -58-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 488064 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7_____ V. Description of the invention (50) The first gate insulating film 1 on the surface 1 3. The silicon nitride film 18 and the third odor insulating film 1 5. Self-integrated dry etching. Here, the charge accumulation layer 4f is formed. Next, as shown in FIG. 20E, after forming an oxide film 16 on the entire surface of the p-type semiconductor substrate 1, an η-type diffusion layer 10 having a low impurity concentration is formed. The η-type diffusion layer 10 is formed by implanting the gate electrode 3 as a photomask and implanting an N-type impurity through a subsequent heat treatment to activate the implanted impurity. Next, as shown in FIG. 20F, after forming sidewall spacers 9 on the sidewalls of the gate electrode 3, an n + -type diffusion layer 11 having a high impurity concentration is formed. The η + -type diffusion layer 11 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask by implanting η-type impurities through a subsequent heat treatment to activate the implanted impurities. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the P-type semiconductor substrate 1 by a CVD method or a sputtering method, and then the P-type semiconductor substrate 1 is heat-treated in an inert atmosphere. A conductive layer 12 made of a high melting point metal silicide is formed on each of the gate electrodes 3 and the surface of the η + type diffusion layer 11. When the conductive layer 12 is formed and the unreacted high melting point metal remaining in a range other than the above is removed, the memory cell structure shown in FIG. 21 can be completed. However, although it is not shown in figure 21, after the completion of the gige grid structure in FIG. 21, the usual CMOS manufacturing processes such as the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process are completed. The ultimate non-volatile memory cell. (Please read the precautions on the back before filling out this page) 4 Pack ------- Order ----- I --- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) -59 488064 Α7 Β7 V. Description of the invention (57) (the 10th embodiment) (Please read the precautions on the back before filling out this page) Next, the 10th embodiment of the invention will be described. Fig. 23 is a cross-sectional view showing a memory cell structure of a nonvolatile semiconductor memory device according to the tenth embodiment of the present invention. In the eighth and ninth embodiments, the channel range is convex to the semiconductor substrate, and a step is provided at both ends of the channel range. However, in the tenth embodiment, the channel range is presented to the semiconductor substrate. In a concave state, a step is set in the channel range. Then, this 10th implementation form is also set in the memory channel's channel range with a step or slope to achieve an improvement in the efficiency of electron implantation during writing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs As shown in Figure 23, this memory cell is composed of P-type MOS transistors. In the structure of the memory cell according to the first embodiment, a second gate insulating film 14 is provided on the surface of the n-type semiconductor substrate 19 through a first gate insulating film 1 3. Charge storage layers 4 a and 4 b are formed on both ends of the second gate insulating film 14. A gate electrode 3 is provided on the second gate insulating film 14 and the charge accumulation layers 4a and 4b via a third gate insulating film 15. On the side of the gate electrode 3, a sidewall spacer 9 is provided through an oxide film 16. A n-type semiconductor substrate 19 below the sidewall spacer 9 is provided with a P ^ -type diffusion layer 2 having a low impurity concentration in a contact channel range. 0, and a P + -type diffusion layer 21 having a high impurity concentration on the outside of the P-type diffusion layer 2 0. A conductive layer 12 is provided on the surface of each gate electrode 3 and the P + -type diffusion layer 21. In addition, the memory cell structure of the non-volatile semiconductor memory of the 10th embodiment of the present invention is in the channel range 2 5 Set the step This paper size is applicable to China National Standard (CNS) A4 specifications (210 X 297 public love) -60-488064 A7 B7 V. Description of the invention (58) 2 6. After this step difference 2 6, the electrons in the P-type semiconductor substrate 1 are scattered (please read the precautions on the back before filling this page), and they are located in the charge storage layer 4 in a random direction. Therefore, the implantation efficiency of electrons during writing is improved. The non-volatile half 1 _ _ memory of the 10th embodiment of the present invention has a P-type diffusion layer 20 with a source range and a drain range at a low impurity concentration, and a high impurity. A PDD-type diffusion layer with a concentration of 21 is an LDD structure. The gate insulating film is a three-layer stacked film formed by the first gate insulating film 1 3 (lower layer), the second gate insulating film 1 4 (middle layer), and the third gate insulating film 1 5 (upper layer). As a result, the charge storage layers 4 a and 4 b are formed on both ends of the second gate insulating film 14. Electrons are accumulated in the two charge accumulation layers 4 a and 4 b. The accumulation state may be (1) a state where no electrons are accumulated in any of the Xiahe accumulation layers 4a, 4b, (2) a state where electrons are accumulated only in the charge accumulation layer 4a, and (3) only a charge accumulation layer 4 b is the state of accumulating electrons, (4) the charge accumulating layers 4 a and 4 b are the four states of accumulating electrons. Through the existence of the electrons stored in the two charge accumulation layers 4 a and 4 b, the changes in the threshold value generated are divided into the memory information and printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. , 0 1 〃, ''10 〃, 1 1 〃. In addition, in this memory lattice structure, the charge accumulation layers 4 a and 4 b are located above the end of the channel range, and the threshold of the center of the channel range. The voltage is determined only by the impurity concentration of the channel range. Electron accumulation states attached to the charge accumulation layers 4a, 4b. Therefore, it is possible to prevent the excessive elimination of electrons in the charge accumulation layers 4a, 4b from being over-eliminated, thereby preventing occurrence of defective discharge, defective programming, and poor reading due to excessive elimination. In addition, the source range and the paper size are applicable to the national standard (CNS) A4 specification (210 X 297 mm) -61-Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 Α7 Β7 V. Description of the invention (59) The leakage current between the polar ranges can be suppressed by the gate voltage only. The charge storage layers 4 a and 4 b may be formed of a silicon nitride film having a high charge storage capability by the C V D method. By accumulating electrons due to the discrete charge trapping level of the silicon nitride film, it is possible to obtain a charge retention characteristic which is difficult to be affected by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be manufactured inexpensively. Furthermore, the first gate insulating film 1 3 and the third gate insulating film 15 are made of a silicon nitride film (S i 3N4) having a dielectric constant approximately twice that of a silicon oxide film (S i 〇2 film). Film), it is possible to stably realize a very thin gate insulating film with a silicon oxide film conversion film thickness of about 4 to 11 nm. For example, because the silicon nitride film with a thickness of 5 nm is about 10 nm, the direct thickness of the silicon nitride film is not about 10 nm, so tunnel implantation is not an incentive. Therefore, the voltage at the time of implantation and extraction of electrons is reduced, not only the miniaturization of memory cells, but also the miniaturization of peripheral high-voltage operating elements. In the memory cell of the non-volatile semiconductor memory according to the tenth embodiment of the present invention, a P_-type diffusion layer 10 is provided for the purpose of improving the withstand voltage of the source range and the drain range to form an LDD. The structure can be a single-drain structure or a double-drain structure to form a source range and a drain range. The second gate insulating film 14 can prevent leakage between the charge storage layers 4 a-4 b, and can be made of, for example, a silicon oxide film. When a metal oxide film having a high dielectric constant is used for the second gate insulating film 1 4, the current transmission characteristic in the center of the channel range can be improved. Examples of the metal oxide include T i 0 2, Ta205, Al205, PZT, and SBT. In the tenth embodiment of the present invention, the paper size on the source side and the drain side applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling in this Page) -J · ---- 11-^ ---------. -02- 488064 A7 B7 V. Description of the invention (6Q) Two parties, set the step difference 2 6 and only one party. can. In particular, only one bit of information is sufficient. Next, the operation of the non-volatile memory according to the tenth embodiment of the present invention will be described with reference to Figs. 2A and 2B. Figure 24 is a cross-sectional view of a non-volatile memory illustrating a write operation. Fig. 2B is a cross-sectional view of the nonvolatile memory illustrating the erasing operation. As shown in FIG. 24A, when the memory cell is written, the source G is applied with a potential of 5 V and the drain D is applied with -5 V, so that the source S is at a floating potential. In this way, when a voltage is applied, the electrons in the band-to-band tunnel phenomenon are supplied with energy by an electric field near the drain and implanted into the charge storage layer 4 b on the side of the drain. A step difference 26 is set at the channel range 25, and the charge accumulation layer 4b is positioned in the electron injection direction. Therefore, the improvement of the implantation efficiency of the electrons in the charge accumulation layer 4 b can be achieved by increasing the implantation speed and reducing the applied voltage. When implanting electrons in the charge accumulation layer 4 a on the source range side, the voltages applied to the respective drains D and S can be replaced with the above. On the other hand, the memory cell is eliminated as shown in Figure 2 As shown in Figure 4B, a negative voltage (~ -5V) is applied to the gate G, and electrons are extracted from the charge storage layers 4a and 4b by using the FN tunnel current. When the gate electrode 3 is shared by a plurality of memory cells, electrons can be simultaneously extracted from these memory cells. In this case, the source S and the drain D may be at the same potential as the n-type semiconductor substrate 19. When a positive voltage different from the potential of the P-type semiconductor substrate 1 is applied to the drain D and the source S is at a floating potential, electrons can be extracted only from the charge accumulation layer 4a on the side of the drain D. When the electrons are extracted only by the charge accumulation layer 4 b on the source S side, a positive voltage is applied to the source S, so that the drain D is in a floating paper size. The Chinese National Standard (CNS) A4 specification (210 X 297 mm) is applied. (Please read the notes on the back before filling this page)

裝--------訂------— II 經濟部智慧財產局員工消費合作社印製 -03- 488064 經濟部智慧財產局員工消費合作社印製 A7 ___B7__ 五、發明說明（61 ) 電位即可。 又，雖未加以圖示，記億格之讀取係檢測流於源極s 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ， 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 流傳達特性（通道電感）者。對於於源極S、汲極D之何 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態’得4個不 同之電流傳達特性，由此以1個格，可記憶2位元分之資 訊。 接著，將有關本發明之第1 〇之實施形態的非揮發性 半導體記憶體之記憶格之製造方法，使用圖2 5 A乃至圖 2 5 I加以說明。首先，如圖2 5 A所示，將被覆形成通 道範圍2 5之範圍的光阻劑圖案2 7，形成於η型半導體 基板1 9。然後，如圖2 5 Β所示，例如經由R I Ε法， 將η型半導體基板1 9加以蝕刻，形成階差2 6。 接著，如圖2 5 C所示，於η型半導體基板1 9，於 整面，堆積電荷蓄積能力小之矽氮化膜，形成1 〇 nm之 第1閘極電極1 3。電荷蓄積能力小之矽氮化膜之堆積係 例如以J V D法加以進行。形成第1閘極絕緣膜1 3後， 經由C V D法堆積矽氧化膜，形成5〜1 0 n m程度之第 2閘極絕緣膜1 4。接著，經由J V D法，堆積電荷蓄積 能力小之矽氮化膜，形成1 〇 n m程度之第3閘極絕緣膜 15° 接著，如圖2 5D所示，於η型半導體基板19整面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -64 - !-—.—^Ί ^--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 488064 Α7 _ Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（62) 經由L P C V D法，堆積滲雜η型或p型不純物之5 0〜 2 5 0 n m之多結晶矽膜後，經由曝光技術及蝕刻技術加 以圖案化，形成閘極電極3。接著，將閘極電極3做爲光 罩，將形成源極範圍及汲極範圍之範圍的η型半導體基板 1 9之表面的第1閘極絕緣膜1 3、第2閘極絕緣膜1 4 及第3閘極絕緣膜1 5，自我整合地加以乾蝕刻。 接著，如圖2 5 Ε所示，形成爲電荷蓄積層形成之空 間1 7。此空間1 7係使用較第1閘極絕緣膜1 3及第3 閘極絕緣膜1 5 ，第2閘極絕緣膜1 4之鈾刻速度爲大的 触刻液，將第2閘極絕緣膜1 4之端部選擇性地以濕蝕刻 加以形成。於本發明之第1 0之實施形態中，將第1閘極 絕緣膜1 3及第3閘極絕緣膜1 5以矽氮化膜加以構成， 將第2閘極絕緣膜1 4以矽氧化膜加以構成之故，做爲蝕 刻液使用例如氟酸即可。又爲電荷蓄積層形成之空間1 7 係替換使用蝕刻液之濕蝕刻法，以使用包含H F氣體之電 漿乾蝕刻法加以形成亦可。 接著，如圖2 5 F所示，於η型半導體基板1 9整面 ，經由L P CVD法，將電荷蓄積能力高之矽氮化膜1 8 ，完全埋入爲電荷蓄積層形成之空間1 7地加以堆積。然 後，如圖2 5 G所示，對ρ型半導體基板1整面，進行 R I Ε之向異性蝕刻，形成以電荷蓄積能力高之矽氮化膜 所構成之電荷蓄積層4 a及4 b。 接著，如圖2 5H所示，於η型半導體基板1 9整面 ，形成氧化膜1 6之後，形成低不純物濃度之Ρ '型擴散層 --·----------------訂---------線 (請先閱讀背面之注音？事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -65- 488064 A7 B7 五、發明說明（63) (請先閱讀背面之注意事項再填寫本頁) 2 0。p —型擴散層2 0係經由離子植入技術，將閘極電極 3做爲光罩，植入p型不純物，經由之後之熱處理，活化 植入之不純物而形成者。 接著，如圖2 5 I所示，於閘極電極3之側壁，形成 側壁間隔9之後，形成高不純物濃度之p +型擴散2 1。 P 1型擴散層2 1係經由離子植入技術，將閘極電極3及側 壁間隔9做爲光罩，植入η型不純物，經由之後之熱處理 活化植入之不純物而加以形成。 接著，於η型半導體基板1 9之整面，經由CVD法 或濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將 η型半導體基板1 9於不活性氣氛中經由熱處理，於各閘 極電極3、及Ρ+型擴散層2 1之表面，形成以高融點金屬 矽化物所構成之導電層1 2。形成導電層1 2後，除去殘 留於上述以外之範圍的未反應高融點金屬時，可完成圖 2 3所示之記憶格構造。 經濟部智慧財產局員工消費合作社印製 然而，雖未圖示，圖2 3之記憶格構造完成後，順序 經由層間絕緣膜形成工程，連接孔形成工程，配線形成工 程，鈍化膜形成工程等之通常之CM〇S製造工程，完成 最終之非揮發性記憶格。 根據本發明之1 0之實施形態時，可將電荷蓄積層 4 a及4 b自我整合形成於閘極電極3之兩端下方。因此 ，可達格電晶體之閘極長方向之微細化。由此’可提供大 容量、高密度之非揮發性半導體記億體。又每位元之格面 積較以往減少幾近一半，可實現大幅減剃之非揮發性半導 -66- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公嫠） 488064 經濟部智慧財產局員工消費合作社印製 A7 _B7__ 五、發明說明（64) 體記億體。 又，電荷蓄積層4 a及4 b之通道長方向之寬度係經 由第1閘極絕緣膜1 3及第3閘極絕緣膜1 5和第2閘極 絕緣膜1 4之蝕刻速度差，以及蝕刻時間之調節可容易控 制。由此，可對稱配置電荷蓄積層4 a及4 b。然後，電 荷蓄積層4 a和4 b係經由第2閘極絕緣膜1 4電氣性地 完全分離之故，電荷蓄積層1 4 a及1 4 b間之相互作用 不會產生。更且，電荷蓄積層4 a及4 b係自源極範圍、 閘極電極3及通道範圍，經由第1之絕緣膜1 3 ，第3之 絕緣膜1 5及氧化膜1 6完全加以絕緣之故，可提供電荷 保持性優異之非揮發性半導體記憶體。電荷蓄積層4 a及 4 b係自閘極電極3之端部延伸存在於通道範圍方向加以 形成，經由電荷蓄積層4 a及4 b中之通道範圍側部分之 電荷蓄積狀態，幾乎決定記憶格之電流傳達特性。因此’ 將此部分之閘極長方向之長度縮小到極限之時，可提供更 爲微細之非揮發性半導體記億體。 更且，格構造係可容易實現通常之CM〇S工程之故 ，使用既有之製造生產線’可以低成本製造非揮發性半導 體記憶體。 然後，本發明之第1 0之實施形態中，可提升寫入時 之電子植入效率。爲此，可達寫入速度之高速化’寫入時 之施加電壓之減低化。 (第1 1之實施形態） 11- .—:-----------^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -67- 經濟部智慧財產局員工消費合作社印製 488064 A7 B7___ 五、發明說明（65) 接著，對於本發明之第1 1之實施形態加以說明。本 發明之第1 1之實施形態係於上述第1 0之實施形態中， 無需圖2 3之配置於電荷蓄積層4 a和電荷蓄積層4 b間 之第2閘極絕緣膜1 4，採用2個電荷蓄積層4 a及4b 一體化之構成。圖2 6係顯示有關本發明之第1 1之實施 形態的非揮發性記億體之記憶格構造的截面圖。如圖2 6 所示，此記憶格之構造係交換上述第1 0之實施形態之電 荷蓄積層4a、4b及第2閘極絕緣膜14，配置電荷蓄 積層4 f者。 接著，將有關本發明之第1 1之實施形態的非揮發性 半導體記憶體之記憶格之製造方法，使用圖2 7 A乃至圖 2 7 F加以說明。首先，如圖2 7 A所示，將被覆形成通 道範圍2 5之範圍的光阻劑圖案2 7，形成於η型半導體 基板1 9。然後，如圖2 7 Β所示，例如經由R I Ε法， 將η型半導體基板1 9加以鈾刻，形成階差2 6。 接著，如圖2 7 C所示，於η型半導體基板1 9整面 ，堆積電荷蓄積能力小之矽氮化膜，形成1 〇 nm之第1 閘極電極1 3。電荷蓄積能力小之矽氮化膜之堆積係例如 以J V D法加以進行。形成第1閘極絕緣膜1 3後，經由 C V D法堆積矽氧化膜，形成5〜1 0 n m程度之第2閘 極絕緣膜1 4。接著，經由J V D法，堆積電荷蓄積能力 小之矽氮化膜，形成1 0 n m程度之第3閘極絕緣膜1 5 〇 接著，如圖2 7D所示，於η型半導體基板1 9整面 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -68- (請先閱讀背面之注意事項再填寫本頁) -1------^---------^9. 488064 Α7 Β7 五、發明說明（6ό) (請先閱讀背面之注意事項再填寫本頁) 經由L P C V D法，堆積滲雜η型或ρ型不純物之5 0〜 2 5 0 n m之多結晶矽膜後，經由曝光技術及蝕刻技術加 以圖案化，形成閘極電極3。接著，將閘極電極3做爲光 罩，將形成源極範圍及汲極範圍之範圍的P型半導體基板 1之表面的第1閘極絕緣膜1 3、矽氮化膜1 8及第3閘 極絕緣膜1 5，自我整合地加以乾鈾刻。在此，形成電荷 蓄積層4 f。 接著，如圖2 7 E所示，於η型半導體基板1 9整面 ，形成氧化膜1 6之後，形成低不純物濃度之Ρ ^型擴散層 2 0。ρ ^型擴散層2 0係經由離子植入技術，將閘極電極 3做爲光罩，植入Ν型不純物，經由之後之熱處理，活化 植入之不純物而形成者。 接著，如圖2 7 F所示，於閘極電極3之側壁，形成 側壁間隔9之後，形成高不純物濃度之ρ +型擴散層2 1。 Ρ +型擴散層2 1係經由離子植入技術，將閘極電極3及側 壁間隔9做爲光罩，植入η型不純物，經由之後之熱處理 活化植入之不純物而加以形成。 經濟部智慧財產局員工消費合作社印製 接著，於η型半導體基板1 9之整面，經由C V D法 或濺射法，堆積鎢、鈦、鈷等之高融點金屬膜’接著，將 η型半導體基板1 9於不活性氣氛中經由熱處理’於各閘 極電極3、及ρ+型擴散層2 1之表面，形成以高融點金屬 矽化物所構成之導電層1 2。形成導電層1 2後’除去殘 留於上述以外之範圍的未反應高融點金屬時，可完成圖 2 6所示之記憶格構造。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -69- 488064 A7 B7 五、發明說明（ό7) 然而，雖未圖示，圖2 6之記憶格構造完成後，順序 經由層間絕緣膜形成工程，連接孔形成工程，配線形成工 程，鈍化膜形成工程等之通常之CM〇S製造工程，完成 最終之非揮發性記憶格。 (第1 2之實施形態） 接著，對於本發明之第1 2之實施形態加以說明圖 2 8係顯示有關第1 2之實施形態的非揮發性半導體記憶 體之記憶格之構造的截面圖。上述第1 0之實施形態中， 爲於閘極電極3之圖案化使用曝光技術子蝕刻技術，但此 第1 2之實施形態中，於閘極電極3之圖案化，使用化學 性機械性硏磨法之例。 接著，將有關本發明之第1 2之實施形態的非揮發性 半導體記憶體之記憶格之製造方法，使用圖2 9 A乃至圖 29 I加以說明。首先，如圖29A所示，將被覆形成通 道範圍2 5之範圍外的光阻劑圖案2 7，形成於η型半導 體基板1 9。然後，如圖2 9 Β所示，例如經由R I Ε法 ，將η型半導體基板1 9加以蝕刻，形成階差2 6。 接著，如圖2 9 C所示，於η型半導體基板1 9整面 ，堆積電荷蓄積能力小之矽氮化膜，形成1 〇 n m之第1 閘極電極1 3。電荷蓄積能力小之矽氮化膜之堆積係例如 以J V D法加以進行。形成第1閘極絕緣膜1 3後，經由 C V D法堆積矽氧化膜，形成5〜1 0 n m程度之第2閘 極絕緣膜1 4。接著，經由J V D法，堆積電荷蓄積能力 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) ·裝 tr--------- 經濟部智慧財產局員工消費合作社印製 -70- 488064 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（68) 小之矽氮化膜，形成1 〇 n m程度之第3閘極絕緣膜1 5 。更且’於η型半導體基板1 9整面，經由LPCVD法 ，堆積滲雜η型或ρ型不純物之5 Ο η〜5 0 0 nm程度 之多結晶矽膜2 8。 接著’如圖2 9 D所示，經由化學性機械性硏磨方法 ，進行多結晶矽膜1 9之埋入，形成閘極電極3。然而， 將通常殘存於η型半導體基板1 9上的第1閘極絕緣膜 1 3 ’第2閘極絕緣膜1 4及第3閘極絕緣膜1 5，例如 經由濕蝕刻加以除去。 接著，如圖2 9 Ε所示，形成爲電荷蓄積層形成之空 間1 7。此空間1 7係使用較第1閘極絕緣膜1 3及第3 閘極絕緣膜1 5 ，第2閘極絕緣膜1 4之蝕刻速度爲大的 飩刻液，將第2閘極絕緣膜1 4之端部選擇性地以濕鈾刻 加以形成。於本發明之第1 2之實施形態中，將第1閘極 絕緣膜1 3及第3閘極絕緣膜1 5以矽氮化膜加以構成， 將第2閘極絕緣膜1 4以矽氧化膜加以構成之故，做爲鈾 刻液使用例如氟酸即可。又爲電荷蓄積層形成之空間1 7 係替換使用蝕刻液之濕蝕刻法，以使用包含H F氣體之電 漿乾蝕刻法加以形成亦可。 接著，如圖2 9 F所示，於η型半導體基板1 9整面 ，經由L P CVD法，將電荷蓄積能力高之矽氮化膜1 8 ，完全埋入爲電荷蓄積層形成之空間1 7地加以堆積。然 後，如圖2 9 G所示，對η型半導體基板1 9整面’進行 R I Ε之向異性蝕刻，形成以電荷蓄積能力高之矽氮化膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I ------— It------I-- (請先閱讀背面之注意事項再填寫本頁) -71 - 488064 經濟部智慧財產局員Η消費合作社印製 Α7 Β7 五、發明說明（ό9) 所構成之電荷蓄積層4 a及4 b。 接著’如圖2 9H所示，於η型半導體基板1 9整面 ’形成氧化膜1 6之後，形成低不純物濃度之ρ -型擴散層 2 Ο ° Ρ 型擴散層2 0係經由離子植入技術，將閘極電極 3做爲光罩’植入ρ型不純物，經由之後之熱處理，活化 植入之不純物而形成者。 接著’如圖2 9 I所示，於閘極電極3之側壁，形成 側壁間隔9之後，形成高不純物濃度之ρ +型擴散2 1。 Ρ +型擴散層2 1係經由離子植入技術，將閘極電極3及側 壁間隔9做爲光罩，植入η型不純物，經由之後之熱處理 活化植入之不純物而加以形成。 接著，於η型半導體基板1 9之整面，經由CVD法 或濺射法，堆積鎢、鈦、鈷等之高融點金屬膜，接著，將 η型半導體基板1 9於不活性氣氛中經由熱處理，於各閘 極電極3、及Ρ+型擴散層2 1之表面，形成以高融點金屬 矽化物所構成之導電層1 2。形成導電層1 2後，除去殘 留於上述以外之範圍的未反應高融點金屬時，可完成圖 2 8所示之記憶格構造。 然而，雖未圖示，圖28之記憶各構造完成後，順序 經由層間絕緣膜形成工程，連接孔形成工程’配線形成工 程，鈍化膜形成工程等之通常之C Μ 0 S製造工程’完成 最終之非揮發性記憶格。 (第1 3之實施形態） (請先閱讀背面之注意事項再填寫本頁)-------- Order -------- II Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -03- 488064 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ___B7__ V. Description of Invention (61 ). In addition, although not shown in the figure, the reading of 100 million grids is performed by detecting the reading current flowing between the source s and the drain D. Through the accumulation states of the charge accumulation layers 4a and 4b, the current transfer characteristics (channel inductance) in the vicinity of the source range and the drain range are modulated. For biasing between the source S and the drain D, it is sufficient to select a person whose modulation of the current transmission characteristic is significant. Through the four accumulation states of the charge accumulation layers 4a and 4b ', four different current transfer characteristics are obtained, so that one bit can memorize information of two bits. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory according to the tenth embodiment of the present invention will be described with reference to FIGS. 2A to 2I. First, as shown in FIG. 2A, a photoresist pattern 27 covered with a channel range 25 is formed on the n-type semiconductor substrate 19. Then, as shown in FIG. 2B, the n-type semiconductor substrate 19 is etched by, for example, the R IE method to form a step difference 26. Next, as shown in FIG. 2C, a silicon nitride film having a small charge accumulation capability is deposited on the entire n-type semiconductor substrate 19 to form a first gate electrode 13 of 10 nm. The deposition of the silicon nitride film having a small charge accumulation ability is performed by, for example, the J V D method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by the C V D method to form a second gate insulating film 14 of about 5 to 10 nm. Next, a silicon nitride film having a small charge storage capacity is deposited by the JVD method to form a third gate insulating film having a degree of 10 nm at 15 °. Then, as shown in FIG. Standards are applicable to China National Standard (CNS) A4 (210 X 297 mm) -64-! -—.— ^ Ί ^ -------- Order --------- (Please read first Note on the back, please fill in this page again) 488064 Α7 _ Β7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (62) Accumulated η-type or p-type impurities by LPCVD method 5 0 ~ 2 5 0 After the polycrystalline silicon film with a thickness of nm is patterned through an exposure technique and an etching technique, a gate electrode 3 is formed. Next, using the gate electrode 3 as a photomask, the first gate insulating film 1 3 and the second gate insulating film 1 4 on the surface of the n-type semiconductor substrate 19 forming the source range and the drain range are formed. 4 And the third gate insulating film 15 are self-integrated and dry-etched. Next, as shown in FIG. 2 5E, a space 17 formed as a charge accumulation layer is formed. This space 17 uses a contact liquid having a higher uranium etching speed than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 to insulate the second gate. The ends of the film 14 are selectively formed by wet etching. In the tenth embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are formed of a silicon nitride film, and the second gate insulating film 14 is oxidized with silicon. In order to form the film, for example, fluoric acid may be used as the etching solution. The space 17 formed by the charge accumulation layer may be formed by replacing the wet etching method using an etchant and using a plasma dry etching method including an H F gas. Next, as shown in FIG. 2F, the silicon nitride film 1 8 having a high charge storage ability is completely buried in the space formed by the charge storage layer 1 7 on the entire surface of the n-type semiconductor substrate 19 through the LP CVD method. Ground. Then, as shown in FIG. 25G, the entire surface of the p-type semiconductor substrate 1 is anisotropically etched with R I E to form charge storage layers 4 a and 4 b composed of a silicon nitride film having a high charge storage capability. Next, as shown in FIG. 2H, after the oxide film 16 is formed on the entire surface of the n-type semiconductor substrate 19, a P'-type diffusion layer with a low impurity concentration is formed.... ----- Order --------- Line (Please read the note on the back? Matters before filling out this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)- 65- 488064 A7 B7 V. Description of Invention (63) (Please read the notes on the back before filling this page) 2 0. The p-type diffusion layer 20 is formed by implanting the p-type impurity with the gate electrode 3 as a photomask through ion implantation technology, and then activating the implanted impurity by subsequent heat treatment. Next, as shown in FIG. 2I, a p-type diffusion 21 having a high impurity concentration is formed after a sidewall gap 9 is formed on the sidewall of the gate electrode 3. The P 1 type diffusion layer 21 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask, implanting n-type impurities, and activating the implanted impurities by subsequent heat treatment. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the n-type semiconductor substrate 19 by a CVD method or a sputtering method, and then the n-type semiconductor substrate 19 is passed through an inactive atmosphere. Heat treatment forms a conductive layer 12 composed of a high melting point metal silicide on the surfaces of each gate electrode 3 and the P + -type diffusion layer 21. When the conductive layer 12 is formed and the unreacted high-melting-point metal remaining in a range other than the above is removed, the memory lattice structure shown in FIG. 23 can be completed. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. However, although not shown, after the completion of the memory cell structure in Fig. 23, it is sequentially passed through the interlayer insulation film formation project, connection hole formation project, wiring formation project, passivation film formation project, etc. The usual CMOS manufacturing process completes the final non-volatile memory cell. According to the tenth embodiment of the present invention, the charge accumulation layers 4 a and 4 b can be integrated and formed below both ends of the gate electrode 3. Therefore, the miniaturization of the gate electrode in the long direction can be achieved. This' can provide a large-capacity, high-density non-volatile semiconductor memory. In addition, the non-volatile semiconducting area can be reduced by almost half compared to the past, which can achieve a significant reduction in shaving. -66- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 cm) 488064 Ministry of Economic Affairs Printed by A7 _B7__ of the Intellectual Property Bureau's Consumer Cooperatives V. Description of the Invention Further, the widths in the longitudinal direction of the channels of the charge accumulation layers 4a and 4b are caused by the difference in etching speed between the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 and Adjustment of the etching time can be easily controlled. Thereby, the charge storage layers 4 a and 4 b can be arranged symmetrically. Then, since the charge accumulation layers 4 a and 4 b are electrically and completely separated through the second gate insulating film 14, the interaction between the charge accumulation layers 14 a and 14 b is not generated. Furthermore, the charge accumulation layers 4 a and 4 b are completely insulated from the source region, the gate electrode 3 and the channel region through the first insulating film 1 3, the third insulating film 15 and the oxide film 16. Therefore, a nonvolatile semiconductor memory having excellent charge retention can be provided. The charge accumulation layers 4 a and 4 b are formed by extending from the ends of the gate electrode 3 and existing in the channel range direction. The charge accumulation state of the channel range side portions in the charge accumulation layers 4 a and 4 b almost determines the memory cell. The current transfer characteristics. Therefore, when the length of the gate length in this part is reduced to the limit, a finer nonvolatile semiconductor memory can be provided. Moreover, the lattice structure can easily realize the usual CMOS process, and the non-volatile semiconductor memory can be manufactured at a low cost by using the existing manufacturing production line '. Then, in the tenth embodiment of the present invention, the electron implantation efficiency at the time of writing can be improved. Therefore, the writing speed can be increased, and the applied voltage can be reduced. (The 11th embodiment) 11- .-: ----------- ^ --------- (Please read the precautions on the back before filling this page) The paper size Applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -67- Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 B7___ 5. Description of the invention (65) Next, the implementation of the 11th of the invention The form is explained. The eleventh embodiment of the present invention is the above-mentioned tenth embodiment, and the second gate insulating film 14 disposed between the charge accumulation layer 4 a and the charge accumulation layer 4 b shown in FIG. 23 is not needed. The two charge accumulation layers 4 a and 4 b are integrated. Fig. 26 is a cross-sectional view showing a memory cell structure of a non-volatile memory device according to the eleventh embodiment of the present invention. As shown in FIG. 26, the structure of this memory cell is one in which the charge storage layers 4a, 4b and the second gate insulating film 14 of the tenth embodiment described above are exchanged, and a charge storage layer 4f is arranged. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory according to the eleventh embodiment of the present invention will be described with reference to FIGS. 2A to 2F. First, as shown in FIG. 2A, a photoresist pattern 27 covered with a channel range 25 is formed on the n-type semiconductor substrate 19 by coating. Then, as shown in FIG. 27B, for example, the n-type semiconductor substrate 19 is etched with uranium through the R IE method to form a step difference 26. Next, as shown in FIG. 2C, a silicon nitride film having a small charge accumulation ability is deposited on the entire surface of the n-type semiconductor substrate 19 to form a first gate electrode 13 of 10 nm. The deposition of the silicon nitride film having a small charge accumulation ability is performed by, for example, the J V D method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by the CVD method to form a second gate insulating film 14 of about 5 to 10 nm. Next, a silicon nitride film having a small charge storage capacity is deposited by the JVD method to form a third gate insulating film 1 5 of about 10 nm. Next, as shown in FIG. 2D, the entire surface of the n-type semiconductor substrate 19 is formed. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) -68- (Please read the precautions on the back before filling this page) -1 ------ ^ ------ --- ^ 9. 488064 Α7 Β7 V. Description of the invention (6ό) (Please read the precautions on the back before filling in this page) By LPCVD method, 5 0 to 2 5 0 nm of η-type or ρ-type impurities are deposited. After the polycrystalline silicon film is patterned through an exposure technique and an etching technique, a gate electrode 3 is formed. Next, using the gate electrode 3 as a photomask, the first gate insulating film 1 3, the silicon nitride film 18, and the third surface of the P-type semiconductor substrate 1 on the surface of the source range and the drain range are formed. The gate insulating film 15 is self-integrated and dried with uranium. Here, the charge accumulation layer 4f is formed. Next, as shown in FIG. 2E, after the oxide film 16 is formed on the entire surface of the n-type semiconductor substrate 19, a P ^ -type diffusion layer 20 with a low impurity concentration is formed. The ρ ^ -type diffusion layer 20 is formed by using the ion implantation technology, using the gate electrode 3 as a photomask, implanting an N-type impurity, and activating the implanted impurity by a subsequent heat treatment. Next, as shown in FIG. 2F, a sidewall gap 9 is formed on the side wall of the gate electrode 3, and then a p + -type diffusion layer 21 having a high impurity concentration is formed. The P + -type diffusion layer 21 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask, implanting n-type impurities, and activating the implanted impurities by subsequent heat treatment. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Next, a high melting point metal film such as tungsten, titanium, cobalt, etc. was deposited on the entire surface of the n-type semiconductor substrate 19 by CVD method or sputtering method. The semiconductor substrate 19 is heat-treated in an inactive atmosphere on the surface of each gate electrode 3 and the p + -type diffusion layer 21 to form a conductive layer 12 composed of a high melting point metal silicide. After the conductive layer 12 is formed, when the unreacted high-melting-point metal remaining in a range other than the above is removed, the memory lattice structure shown in Fig. 26 can be completed. This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) -69- 488064 A7 B7 V. Description of the invention (ό7) However, although not shown, the sequence of the memory cells in Figure 2 6 is completed. The final non-volatile memory cell is completed through the usual CMOS manufacturing process such as the interlayer insulation film formation process, the connection hole formation process, the wiring formation process, and the passivation film formation process. (Twelfth Embodiment) Next, a twelfth embodiment of the present invention will be described. Fig. 28 is a cross-sectional view showing the structure of a memory cell of the nonvolatile semiconductor memory according to the twelfth embodiment. In the above-mentioned tenth embodiment, the exposure technique is used for the patterning of the gate electrode 3, but in this twelfth embodiment, the gate electrode 3 is patterned using chemical mechanical properties. Example of grinding method. Next, a method for manufacturing a memory cell of a nonvolatile semiconductor memory according to the twelfth embodiment of the present invention will be described with reference to FIGS. 2A to 29I. First, as shown in FIG. 29A, a photoresist pattern 27 covering the channel range 25 is formed on the n-type semiconductor substrate 19. Then, as shown in FIG. 2B, the n-type semiconductor substrate 19 is etched, for example, via the R IE method to form a step difference 26. Next, as shown in FIG. 2C, a silicon nitride film having a small charge accumulation ability is deposited on the entire surface of the n-type semiconductor substrate 19 to form a first gate electrode 13 of 10 nm. The deposition of the silicon nitride film having a small charge accumulation ability is performed by, for example, the J V D method. After the first gate insulating film 13 is formed, a silicon oxide film is deposited by the CVD method to form a second gate insulating film 14 of about 5 to 10 nm. Then, through the JVD method, the accumulated charge accumulation capacity is based on the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Please read the precautions on the back before filling this page.) · Install tr ----- ---- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs-70- 488064 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 Β7 V. Description of the invention (68) The small silicon nitride film forms a 10nm degree The third gate insulating film 1 5. Furthermore, on the entire surface of the n-type semiconductor substrate 19, a polycrystalline silicon film 28 with an amount of 5 0 η to 5 0 0 nm in which n-type or p-type impurities are doped is deposited by the LPCVD method. Next, as shown in FIG. 2D, the polycrystalline silicon film 19 is embedded by a chemical mechanical honing method to form a gate electrode 3. However, the first gate insulating film 1 3 'and the second gate insulating film 14 and the third gate insulating film 15 which are usually left on the n-type semiconductor substrate 19 are removed by, for example, wet etching. Next, as shown in FIG. 2E, a space 17 formed as a charge accumulation layer is formed. This space 17 uses an etching solution having a higher etching rate than the first gate insulating film 13 and the third gate insulating film 15 and the second gate insulating film 14 to etch the second gate insulating film. The end of 14 is selectively formed with wet uranium engraving. In the twelfth embodiment of the present invention, the first gate insulating film 13 and the third gate insulating film 15 are formed of a silicon nitride film, and the second gate insulating film 14 is oxidized with silicon. For the purpose of forming the film, for example, fluoric acid may be used as the uranium etching solution. The space 17 formed by the charge accumulation layer may be formed by replacing the wet etching method using an etchant and using a plasma dry etching method including an H F gas. Next, as shown in FIG. 2F, the silicon nitride film 1 8 having a high charge storage ability is completely buried in the space formed by the charge storage layer 17 on the entire surface of the n-type semiconductor substrate 19 through the LP CVD method. Ground. Then, as shown in FIG. 2G, the entire surface of the n-type semiconductor substrate 19 is anisotropically etched with RI and E to form a silicon nitride film with a high charge storage ability. Specifications (210 X 297 mm) I -------- It ------ I-- (Please read the precautions on the back before filling out this page) -71-488064 Member of the Intellectual Property Bureau of the Ministry of Economic Affairs / Consumption Printed by the cooperative A7 B7 V. Charge accumulation layers 4 a and 4 b formed by the invention description (ό9). Next, as shown in FIG. 2H, after the oxide film 16 is formed on the entire surface of the n-type semiconductor substrate 19, a ρ-type diffusion layer 2 with a low impurity concentration 2 0 ° and a P-type diffusion layer 2 0 are implanted through ions. Technology, the gate electrode 3 is formed as a photomask 'implanted with p-type impurities, and the implanted impurities are activated by subsequent heat treatment. Next, as shown in FIG. 2I, a sidewall gap 9 is formed on the sidewall of the gate electrode 3, and then a ρ + -type diffusion 21 having a high impurity concentration is formed. The P + -type diffusion layer 21 is formed by implanting the gate electrode 3 and the sidewall spacer 9 as a photomask, implanting n-type impurities, and activating the implanted impurities by subsequent heat treatment. Next, a high melting point metal film such as tungsten, titanium, and cobalt is deposited on the entire surface of the n-type semiconductor substrate 19 by a CVD method or a sputtering method, and then the n-type semiconductor substrate 19 is passed through an inactive atmosphere. Heat treatment forms a conductive layer 12 composed of a high melting point metal silicide on the surfaces of each gate electrode 3 and the P + -type diffusion layer 21. When the conductive layer 12 is formed and the unreacted high-melting-point metal remaining in a range other than the above is removed, the memory lattice structure shown in FIG. 28 can be completed. However, although not shown, after the completion of each structure of the memory in FIG. 28, the usual CM 0S manufacturing process such as the wiring formation process, the passivation film formation process, and the like through the interlayer insulation film formation process, the connection hole formation process, and the like are finally completed Non-volatile memory cell. (Issue # 13) (Please read the notes on the back before filling in this page)

裝------訂·丨丨I i. 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -72- 488064 A7 ______B7_ 五、發明說明（70) (請先閱讀背面之注意事項再填寫本頁) 接著’對於本發明之第1 3之實施形態加以說明。於 上述第1乃至第3之實施形態中，未對於記憶格以外之電 晶體的高速化充分加以檢討。另一方面，做爲高速 C Μ 0 S電晶體之構造，於閘極電極和源極·汲極擴散層 間，形成凹上之刻痕，減低閘極電極和擴散層間之容量， 嘗試邏輯聞之筒速化（Τ· Ghani et al·，IEDM99，Ρ415 )。 此第1 3之實施形態係將此構造利用於非揮發性半導體記 憶體，可達混合載置不具有記憶體機能的通常電晶體和非 揮發性半導體記憶體的半導體裝置之大幅高速化。. 圖3 0係顯示有關本發明之第1 3之實施形態的非揮 '發性半導體記憶體之記億格構造的截面圖。此記憶格係以 η型Μ〇S電晶體加以構成。然後，有關本發明第1 3之 實施形態的記憶格之構造中，於Ρ型半導體基板1之表面 ，介由第1閘極絕緣膜1 3，設置閘極電極3。於閘極電 極3之兩端設置凹部，各凹部內，形成電荷蓄積層4 ( 4 a ，4 b )。於電荷蓄積層4和閘極電極3間，形成氧 化膜3 0。於閘極電極3之側面，介由氧化膜1 6，設置 側壁間隔9 ，於此側壁間隔9之下部之？型半導體基板1 經濟部智慧財產局員工消費合作社印製 之主面，設置接觸通道範圍之低不純濃度之η _型擴散層 1 0，和位於此η —型擴散層1 0之外側之高不純物濃度之 η +型擴散層1 1。於各閘極電極3及η+型擴散層1 1之 表面，設置導電層1 2。 有關於本發明之第1 3之實施形態之非揮發性半導體 記憶體之記憶格係具有將源極範圍及汲極範圍以低不純濃 -73- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 經濟部智慧財產局員工消費合作社印製 488064 A7 ___B7___ 五、發明說明（71 ) 度之η —型擴散層1 〇，和高不純物濃度之η +型擴散層 1 1加以構成之L D D構造。然後，於第2閘極電極3之 兩端部，形成電荷蓄積層4 (4a 、4b)。於此2個之 電荷蓄積層4 a及4 b蓄積電子。該蓄積狀態係可有（1 )電荷蓄積層4 a、4 b之任一者皆未蓄積電子之狀態’ (2 )僅電荷蓄積層4 a蓄積電子之狀態，（3 )僅電荷 蓄積層4b蓄積電子之狀態，（4)電荷蓄積層4a ， 4 b皆蓄積電子之狀態之4個狀態。經由保持於此2個之 電荷蓄積層4 a ，4 b之電子之有無，將所產生之臨限値 之變化分，對應於記憶資訊之'' 0 0 〃 ，0 1 〃 ，'' 10〃 ， A 1 1 〃 。又，於此記憶格構造之中，電荷蓄積 層4 a ，4 b係位於通道範圍端部之上方之故，通道範圍 中央部之臨限値電壓係僅以通道範圍之不純物濃度加以決 定，不依附於電荷蓄積層4 a ，4 b之電子之蓄積狀態。 因此，可防止電荷蓄積層4 a ，4 b之電子之過度不足的 過度消除，由此不會產生由於過度消除起因的泄放不良， 程式不良，讀取不良等。又，源極範圍和汲極範圍間之泄 放電流係可僅以閘極電壓加以抑制，實現高可靠性之非揮 發性半導體記憶體。電荷蓄積層4係以C V D法之電荷蓄 積能力高的矽氮化膜加以構成即可。經由於矽氮化膜之離 散性之電荷捕獲準位蓄積電子，可得難以於下部絕緣膜之 膜質影響之電荷保持特性。又，以矽膜，多結晶矽膜加以 構成之時，可便宜地加以製造。更且，將第1閘極絕緣膜 1 3、第3閘極絕緣膜1 5以具有矽氧化膜（S i〇2膜） 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -74 - i ---裝--------訂--------- (請先閱讀背面之注意事項再填寫本頁) 488064 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（72) 之2倍程度之介電率的矽氮化膜（S 1 3 N 4膜）加以構成 時，可將矽氧化膜換算膜厚爲4〜1 1 n m程度之非常薄 的閘極絕緣膜安定實現。例如，矽氧化膜換算膜厚爲5 nm之矽氮化膜之實質膜厚爲1 〇 nm程度之故，直接進 行隧道植入亦不會激勵。因此，電子之植入抽出時之電壓 係被低電壓化，不單是記憶格之微細化，亦可達周邊高電 壓動作元件之微細化。 有關本發明之第1 3之實施形態之非揮發性半導體記 憶體之記憶格中，於源極範圍及汲極範圍之耐壓提升之目 的上，設置η—型擴散層1 〇，以構成LDD構造，以單汲 極構造，雙汲極構造構成源極範圍及汲極範圍亦可。 接著，對於有關本發明之第1 3之實施形態的非揮發 性記憶體之動作，使用圖3 1 Α及圖3 1 Β加以說明。圖 3 1 A係說明寫入動作之非揮發性記憶體之截面圖。圖 3 1 B係說明消除動作之非揮發性記憶體之截面圖。如圖 3 1 A所示，於記憶格之寫入時，於閘極G施加6〜8 V 程度，於汲極D施加4 V〜5 V之程度，將源極S加以接 地。如此地，施加電壓時，以通道熱電子，將電子植入汲 極範圍側之電荷蓄積層4 b。於通道範圍2 5設置階差 2 6地，於電子散亂方向定位電荷蓄積層4 b。爲此，對 於電荷蓄積層4 b之電子之植入效率的提升，可達植入速 度之高速化，施加電壓之減低化。於源極範圍側之電荷蓄 積層4 a植入電子時，將施加於各汲極D、源極S之電壓 與上述之情形加以置換即可，另一方面，記憶格之消除係 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I ^ 一---— — — — — — — — til — — — !- (請先閱讀背面之注意事項再填寫本頁) -75- 經濟部智慧財產局員工消費合作社印製 488064 A7 _ B7 五、發明說明（73) 如圖1 9 B所示，於閘極G施加負電壓（〜一 5 V )，利 用FN型隧道電流，自電荷蓄積層4 a、4b引出電子地 加以進行。又，閘極電極3於複數之記憶格共有之時，自 此等之記憶格可同時引出電子。此時，源極S、汲極D係 呈與P型半導體基板1同電位即可。又，將與p型半導體 基板1之電位不同之正電壓，施加於汲極D，將源極S呈 浮電位之時，可僅由汲極D側之電荷蓄積層4 a引出電子 。僅由源極S側之電荷蓄積層4 b引出電子之時，於源極 S施加正電壓，令汲極D呈浮電位即可。 又，雖未加以圖示，記憶格之讀取係檢測流於源極S 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ， 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 流傳達特性（通道電感）者。對於於源極S、汲極D之何 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態，得4個不 同之電流傳達特性，由此以1個格，可記憶2位元分之資 訊。 接著，對於以P型Μ〇S電晶體構成之本發明之第 1 3之實施形態的非揮發性半導體記億體之記憶格之動作 使用圖3 2Α及圖3 2 Β加以說明。圖3 2Α係說明寫入 動作之非揮發性記憶體之截面圖。圖3 2 Β係說明消除動 作之非揮發性記憶體之截面圖。圖3 2 Α及圖3 2 Β之記 憶格係以P型Μ〇S電晶體加以構成。如圖3 2 A所示， 於記憶格之寫入時，於閘極G施加5 V程度，於汲極D施 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -76- — l·---------1·裝--------訂--------- S— (請先閱讀背面之注意事項再填寫本頁) 488064 A7 B7 五、發明說明（74) 加- 5 V之程度’將源極S呈浮電位。如此地，施加電壓 時，於起因帶間隧道現象的電子，於汲極範圍附近之電場 供予能量，將電子植入汲極範圍側之電荷蓄積層4 b。於 源極範圍側之電荷蓄積層4 a植入電子時，將施加於各汲 極D、源極S之電壓與上述之情形加以置換即可，另一方 面，記憶格之消除係如圖3 2 B所示，於閘極G施加負電 壓（〜一5V)，利用FN型隧道電流，自電荷蓄積層 4 a 、4 b引出電子地加以進行。又，閘極G於複數之記 憶格共有之時，自此等之記憶格可同時引出電子。此時， 源極S及汲極D係呈與η型半導體基板19同電位或呈浮 電位即可。 又，雖未加以圖示，記憶格之讀取係檢測流於源極S 和汲極D間之讀取電流加以進行。經由電荷蓄積層4 a ， 4 b之蓄積狀態，利用調變源極範圍、汲極範圍附近之電 流傳達特性（通道電感）者。對於於源極S、汲極D之何 者進行偏壓，則選擇電流傳達特性之調變顯著表現者即可 。經由電荷蓄積層4 a及4 b之4個蓄積狀態，得4個不 同之電流傳達特性，由此以1個格’可記憶2位元分之資 訊。 本發明之第1 3之實施形態中’如圖3 3所示，可實 現不具記憶機能的通常Μ〇S電晶體。因爲，此Μ〇S電 晶體中，電荷蓄積層4係僅配置於源極·汲極範圍1 0、 1 1上，未配置於通道範圍上。爲此’此Μ〇S電晶體之 傳導特性係於電荷蓄積層4之電荷之保持狀態’不會受任 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝--------訂--------- S! 經濟部智慧財產局員工消費合作社印製 488064 Α7 _ Β7 五、發明說明（75) 何之影響。更且，經由閘極電極3之凹部之存在，減低閘 極-源極·汲極間之寄生容量，具有可Μ〇S電晶體之高 速動作的優點。 (第1 4之實施形態） 接著’對於本發明之第1 4之實施形態加以說明。此 第1 4之實施形態，係於上述之第1 3之賨施形態，一體 化電荷蓄積層4和側壁間隔9之構成。圖3 4係顯示有關 一 本發明之第1 4之實施形態的非揮發性半導體記億體之記 憶格構造的截面圖。此記憶格係以η型Μ〇S電晶體加以 構成。然後，有關本發明第1 4之實施形態的記憶格之構 造中’於ρ型半導體基板1之表面，介由第1閘極絕緣膜 1 3，設置閘極電極3。於閘極電極3之兩端設置凹部， 各凹部內，形成電荷蓄積層4 (4a ，4b)。於電荷蓄 積層4和閘極電極3間，形成氧化膜3 0。於閘極電極3 之側面，介由氧化膜1 6，設置側壁間隔9 ，於此側壁間 隔9之一部份，構成電荷蓄積層4。此側壁間隔9之下部 之P型半導體基板1之主面，設置接觸通道範圍之低不純 濃度之η -型擴散層1 〇，和位於此η -型擴散層1 0之外 側之高不純物濃度之η +型擴散層1 1。於各閘極電極3及 η +型擴散層1 1之表面，設置導電層1 2。 本發明之第1 4之實施形態中，側壁間隔9及電荷蓄· 積層4係以C V D法之電荷蓄積能力高的矽氮化膜加以構 成即可。經由於矽氮化膜之離散性之電荷捕獲準位蓄積電 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 一裝 ----訂--------- 經濟部智慧財產局員工消費合作社印製 -78- 488064 Α7 Β7 五、發明說明（7ό) 子’可得難以於下部絕緣膜之膜質影響之電荷保持特性。 又’以矽膜’多結晶矽膜加以構成之時，可便宜地加以製 造。 (請先閱讀背面之注意事項再填寫本頁) 本發明之第1 4之實施形態中，與上述第1 3之實施 形態相同，如圖3 5所示，可實現通常之Μ〇S電晶體。 在不超出範圍下，經由接受此揭示技術可進行各種之 改變。 【符號說明】 1 ρ型半導體基板 2 閘極絕緣膜 3 第1閘極電極 4、4a、4b、4c、4d、4e、4f 電荷蓄積層 5 第1氧化膜 6 氮化膜 7 第2氧化膜 8 第2閘極電極 9 側壁間隔 經濟部智慧財產局員工消費合作社印製 10 η —型擴散層 11 η +型擴散層 12 導電層 13 第1閘極絕緣膜 14 第2閘極絕緣膜 15 第3閘極絕緣膜 -79- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 488064 A7 B7 五、發明說明（77) 16 氧化膜 17 爲電荷蓄積層形成之空間 18 矽氮化膜 19 η型半導體基板 2 0 ρ ^型擴散層 2 1 ρ +型擴散層 23 隧道絕緣膜 2 4 第4閘極絕緣膜 25 通道範圍 2 6 階差 2 7 光阻劑圖案 3 0 氧化膜 I-------_----IAW» ^ -11-----訂--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -80-Packing ------ Ordering 丨 丨 I i. This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) -72- 488064 A7 ______B7_ 5. Description of the invention (70) (Please read first (Notes on the back page, please fill in this page again) Next, 'the 13th embodiment of the present invention will be described. In the above-mentioned first to third embodiments, the speed of transistors other than the memory cell has not been fully reviewed. On the other hand, as the structure of a high-speed CMOS transistor, a concave notch is formed between the gate electrode and the source-drain diffusion layer, and the capacity between the gate electrode and the diffusion layer is reduced. Canister speeding (T. Ghani et al., IEDM99, P415). This 13th embodiment uses this structure for a non-volatile semiconductor memory, and can achieve a significant increase in the speed of a semiconductor device in which a normal transistor and a non-volatile semiconductor memory without a memory function are mixed. FIG. 30 is a cross-sectional view showing a gigabyte structure of a non-volatile semiconductor memory according to a thirteenth embodiment of the present invention. This memory cell is composed of n-type MOS transistor. Next, in the structure of the memory cell according to the thirteenth embodiment of the present invention, a gate electrode 3 is provided on the surface of the P-type semiconductor substrate 1 through a first gate insulating film 1 3. Recesses are provided at both ends of the gate electrode 3, and a charge accumulation layer 4 (4a, 4b) is formed in each recess. Between the charge accumulation layer 4 and the gate electrode 3, an oxide film 30 is formed. On the side of the gate electrode 3, a sidewall interval 9 is provided through the oxide film 16 below the sidewall interval 9? Type semiconductor substrate 1 Printed on the main surface of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, set a low impurity concentration η _ type diffusion layer 1 0 in the contact channel range, and a high impurity on the outside of this η type diffusion layer 10 Concentration of η + -type diffusion layer 1 1. A conductive layer 12 is provided on the surface of each gate electrode 3 and the n + -type diffusion layer 1 1. The memory cell of the non-volatile semiconductor memory according to the thirteenth embodiment of the present invention has a source range and a drain range with a low impurity concentration -73- This paper standard applies to China National Standard (CNS) A4 (210 X 297 public love) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 ___B7___ V. Description of the invention (71) η-type diffusion layer 1 〇, and η + -type diffusion layer 1 1 with high impurity concentration Structure of the LDD structure. Then, on both ends of the second gate electrode 3, a charge storage layer 4 (4a, 4b) is formed. Electrons are accumulated in the two charge accumulation layers 4a and 4b. This accumulation state may have (1) a state in which neither of the charge accumulation layers 4a, 4b has accumulated electrons' (2) a state in which only the charge accumulation layer 4a has accumulated electrons, (3) a state in which only the charge accumulation layer 4b The states of accumulated electrons, (4) the charge accumulation layers 4a, 4b are all 4 states of the states of accumulated electrons. Through the presence or absence of electrons held in the two charge accumulation layers 4 a and 4 b, the change in the threshold value 产生 generated corresponds to `` 0 0 〃, 0 1 〃 '', and 10 记忆 of the memory information. , A 1 1 〃. In addition, in this memory lattice structure, the charge accumulation layers 4 a and 4 b are located above the end of the channel range, and the threshold of the center of the channel range. The voltage is determined only by the impurity concentration of the channel range. Electron accumulation states attached to the charge accumulation layers 4a, 4b. Therefore, it is possible to prevent excessive elimination of electrons in the charge accumulation layers 4 a and 4 b from being excessively eliminated, thereby preventing occurrence of defective discharge due to excessive elimination, defective programming, poor reading, and the like. In addition, the leakage current between the source range and the drain range can be suppressed by the gate voltage only, and a non-volatile semiconductor memory with high reliability can be realized. The charge storage layer 4 may be constituted by a silicon nitride film having a high charge storage ability by the C V D method. By accumulating electrons due to the discrete charge trapping of the silicon nitride film, it is possible to obtain charge retention characteristics that are difficult to affect by the film quality of the lower insulating film. When a silicon film or a polycrystalline silicon film is used, it can be manufactured inexpensively. In addition, the first gate insulating film 1 3 and the third gate insulating film 15 are provided with a silicon oxide film (Si 02 film). This paper is compliant with the Chinese National Standard (CNS) A4 specification (210 X 297 mm). -74-i --- install -------- order --------- (Please read the precautions on the back before filling out this page) 488064 Employee Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs When printing A7 B7 V. Description of the invention (72) When the silicon nitride film (S 1 3 N 4 film) with a dielectric constant twice as high as that of the silicon oxide film is formed, the thickness of the silicon oxide film can be converted to 4 ~ 1 1 nm A very thin gate insulation film is stably realized. For example, since the silicon nitride film with a thickness of 5 nm is about 10 nm, the thickness of the silicon nitride film is about 10 nm, so it is not exciting to directly perform tunnel implantation. Therefore, the voltage at the time of implantation and extraction of electrons is reduced, not only for the miniaturization of memory cells, but also for the miniaturization of peripheral high-voltage operating elements. In the memory cell of the non-volatile semiconductor memory according to the thirteenth embodiment of the present invention, an n-type diffusion layer 10 is provided for the purpose of improving the withstand voltage of the source range and the drain range to form an LDD. The structure can be a single-drain structure or a double-drain structure to form a source range and a drain range. Next, the operation of the nonvolatile memory according to the thirteenth embodiment of the present invention will be described with reference to Figs. 3A and 3B. FIG. 31 is a cross-sectional view of a non-volatile memory illustrating a write operation. FIG. 31B is a cross-sectional view of the non-volatile memory illustrating the erasing operation. As shown in FIG. 3A, when the memory cell is written, the source G is applied to the gate G by approximately 6 to 8 V, and the source D is applied to the source S by 4 V to 5 V. In this way, when a voltage is applied, electrons are channeled to the hot-electron channel, and the electrons are implanted into the charge accumulation layer 4b on the drain region side. A step 26 is set at the channel range 25, and the charge accumulation layer 4b is positioned in the electron scattering direction. For this reason, the improvement of the implantation efficiency of the electrons in the charge accumulation layer 4 b can be achieved by increasing the implantation speed and reducing the applied voltage. When electrons are implanted in the charge accumulation layer 4a on the source side, the voltages applied to the respective drains D and S can be replaced with the above. On the other hand, the elimination of the memory cell is on the paper scale. Applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) 75- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A7 _ B7 V. Description of the invention (73) As shown in Figure 1 9B, a negative voltage (~ -5 V) is applied to the gate G and the FN tunnel current is used The electron extraction is performed from the charge accumulation layers 4 a and 4 b. When the gate electrode 3 is shared by a plurality of memory cells, electrons can be simultaneously extracted from these memory cells. In this case, the source S and the drain D may be at the same potential as the P-type semiconductor substrate 1. When a positive voltage different from the potential of the p-type semiconductor substrate 1 is applied to the drain D and the source S is at a floating potential, electrons can be extracted only from the charge storage layer 4a on the side of the drain D. When the electrons are extracted only from the charge storage layer 4b on the source S side, a positive voltage is applied to the source S so that the drain D may be at a floating potential. Also, although not shown, the reading of the memory cell is performed by detecting the reading current flowing between the source S and the drain D. Through the accumulation states of the charge accumulation layers 4a and 4b, the current transfer characteristics (channel inductance) in the vicinity of the source range and the drain range are modulated. For biasing between the source S and the drain D, it is sufficient to select a person whose modulation of the current transmission characteristic is significant. Through the four accumulation states of the charge accumulation layers 4a and 4b, four different current transfer characteristics are obtained, so that one bit can memorize the information of 2 bits. Next, the operation of the memory cell of the non-volatile semiconductor memory device according to the thirteenth embodiment of the present invention, which is composed of a P-type MOS transistor, will be described with reference to FIGS. 3A and 3B. Fig. 3 2A is a cross-sectional view of a nonvolatile memory illustrating a write operation. Figure 3 2B is a cross-sectional view of the nonvolatile memory illustrating the erasing operation. The memory cells of Fig. 3 A and Fig. 3 B are composed of P-type MOS transistors. As shown in Figure 3 2A, when writing to the memory cell, apply 5 V to the gate G, and apply the Chinese national standard (CNS) A4 specification (210 X 297 mm) to the drain D. The paper size is- 76- — l · --------- 1 · Installation -------- Order --------- S— (Please read the precautions on the back before filling this page) 488064 A7 B7 V. Description of the invention (74) To the extent of -5 V ', the source S is at a floating potential. In this way, when a voltage is applied, electrons caused by the phenomenon of the inter-band tunneling are supplied with energy in an electric field near the drain region, and the electrons are implanted into the charge accumulation layer 4b on the drain region side. When electrons are implanted in the charge accumulation layer 4a on the source range side, the voltages applied to the respective drains D and S can be replaced with the above. On the other hand, the memory cell is eliminated as shown in Figure 3. As shown in Fig. 2B, a negative voltage (~ -5V) is applied to the gate G, and electrons are extracted from the charge accumulation layers 4a and 4b by using a FN-type tunneling current. In addition, when the gate G is shared by a plurality of memory cells, electrons can be simultaneously extracted from these memory cells. At this time, the source S and the drain D may be at the same potential as the n-type semiconductor substrate 19 or at a floating potential. Also, although not shown, the reading of the memory cell is performed by detecting the reading current flowing between the source S and the drain D. Through the accumulation states of the charge accumulation layers 4a and 4b, the current transfer characteristics (channel inductance) in the vicinity of the source range and the drain range are modulated. For biasing between the source S and the drain D, it is sufficient to select a person whose modulation of the current transmission characteristic is significant. Through the four accumulation states of the charge accumulation layers 4a and 4b, four different current transfer characteristics are obtained, and thus 2 bits of information can be memorized with one division. In the thirteenth embodiment of the present invention, 'as shown in Fig. 33, a normal MOS transistor having no memory function can be realized. This is because, in this MOS transistor, the charge accumulation layer 4 is arranged only on the source and drain ranges 10, 11 and not on the channel range. For this reason, 'the conduction characteristics of this MOS transistor are in the state of charge retention in the charge accumulation layer 4' will not be accepted. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Note on the back, please fill in this page again.) -------- Order --------- S! Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 488064 Α7 _ Β7 V. Description of Invention (75 ) What's the impact. Furthermore, the existence of the recessed portion of the gate electrode 3 reduces the parasitic capacity between the gate-source and the drain, and has the advantage that the MOS transistor can operate at high speed. (Embodiment No. 14) Next, an embodiment No. 14 of the present invention will be described. This 14th embodiment is based on the above-mentioned 13th application mode, and has a structure in which the charge storage layer 4 and the side wall space 9 are integrated. Fig. 34 is a cross-sectional view showing a memory structure of a non-volatile semiconductor memory cell according to a fourteenth embodiment of the present invention. This memory cell is composed of an n-type MOS transistor. Next, in the construction of the memory cell according to the fourteenth embodiment of the present invention, a gate electrode 3 is provided on the surface of the p-type semiconductor substrate 1 through the first gate insulating film 1 3. Recesses are provided at both ends of the gate electrode 3, and in each of the recesses, a charge accumulation layer 4 (4a, 4b) is formed. Between the charge storage layer 4 and the gate electrode 3, an oxide film 30 is formed. On the side of the gate electrode 3, a sidewall interval 9 is provided through an oxide film 16 and a part of this sidewall interval 9 forms a charge accumulation layer 4. The main surface of the P-type semiconductor substrate 1 below the side wall interval 9 is provided with a low impurity concentration η-type diffusion layer 10 in the contact channel range and a high impurity concentration on the outside of the η-type diffusion layer 10. η + -type diffusion layer 1 1. A conductive layer 12 is provided on the surface of each gate electrode 3 and the n + -type diffusion layer 11. In the fourteenth embodiment of the present invention, the sidewall spacer 9 and the charge storage and build-up layer 4 may be formed of a silicon nitride film having a high charge storage capability by the CVD method. Due to the discrete charge trapping level of the silicon nitride film, the electricity is stored in this paper. The paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page). ---- Order --------- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-78- 488064 Α7 Β7 V. Description of the invention (7) It is difficult to affect the film quality of the lower insulating film Charge retention characteristics. When a "silicon film" is used as the polycrystalline silicon film, it can be manufactured inexpensively. (Please read the precautions on the back before filling in this page) In the fourteenth embodiment of the present invention, the same as the above-mentioned embodiment of the thirteenth, as shown in Figure 35, ordinary MOS transistors can be realized . Various changes can be made without departing from the scope of this disclosure technique. [Symbol description] 1 ρ-type semiconductor substrate 2 Gate insulating film 3 First gate electrode 4, 4a, 4b, 4c, 4d, 4e, 4f Charge accumulation layer 5 First oxide film 6 Nitride film 7 Second oxide film 8 2nd gate electrode 9 Side wall spacer Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10 η-type diffusion layer 11 η + -type diffusion layer 12 Conductive layer 13 First gate insulating film 14 Second gate insulating film 15 3 Gate insulation film -79- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) 488064 A7 B7 V. Description of the invention (77) 16 Oxide film 17 Space formed by charge storage layer 18 Silicon Nitride film 19 η-type semiconductor substrate 2 0 ρ ^ type diffusion layer 2 1 ρ + type diffusion layer 23 Tunnel insulating film 2 4 Fourth gate insulating film 25 Channel range 2 6 Step difference 2 7 Photoresist pattern 3 0 Oxidation Membrane I -------_---- IAW »^ -11 ----- Order --------- (Please read the precautions on the back before filling out this page) Ministry of Economy Wisdom The paper size printed by the Property Cooperative Consumer Cooperative is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) -80-

Claims (1)

經濟部智慧財產局員工消費合作社印製 488064 A8 B8 C8 D8 六、申請專利範圍 —·— ^ΐιι(ί^ 第89 1039 1 8號專利申請案^t /Γ：：：1 i\\^ μ (-? 中文.申請專利範圍修正本I 〈 ； I —...丄:^ 民國91年3月修ΐ 1 · 一種非揮發性半導體記憶裝置，其特徵係包含以 下之構成 (a )於半導體基板之主面上，介由閘極絕緣膜，加 以配置之第1之閘極電極， 和（b )配置於該第1之閘極電極之側面上的電荷蓄 積層， 和（c )於前述第1之閘極電極之側面上，介由前述 電荷蓄積層，加以配置之第2之閘極電極， 和（d )將前述第1之閘極電極和前述第2之閘極電 極電氣性連接之導電層。 2 ·如申請專利範圍第1項之非揮發性半導體記憶裝 置’其中’前述電荷蓄積層係矽氧化膜和矽氮化膜之堆積 層所成者。 3 ·如申請專利範圍第1項之非揮發性半導體記憶裝 置’其中，前述電荷蓄積層係由第1之矽氧化膜，矽氮化 膜及第2之矽氧化膜之3層所成。. · 4 · 一種非揮發性半導體記憶裝置之製造方法，其特 徵係包含以下之構成 (a )於半導體基板之主面上，介由聞極絕緣膜，形 成第1之閘極電極之工程， 本i張尺度適用巾國國家標準（CNS ) Α4· ( 21〇χ297公羡) ~ ： -- ------------- I 裝-------訂------線 (請先閲讀背面之注意事項界¾寫本頁) 488064 A8 B8 C8 _ D8 六、申請專利範圍 和（b )於該第1之閘極電極之側面上，順序形成電 荷蓄積層及第2之閘極電極的工程， 和（c )形成令前述第1之閘極電極和前述第2之閘 極電極電氣性連接之導電層之工程。 5 . —種非揮發性半導體記憶裝置，其特徵係包含以 下之構成 (a )配置於半導體基板之主面上，由第1、第2及 第3之絕緣膜所成之閘極絕緣膜， 和（b )配置於前述第2之絕緣膜之端部的電荷蓄積 層， 和（c )配置於前述閘極絕緣膜上之閘極電極。 6 ·如申請專利範圍第5項之非揮發性半導體記憶裝 置，其中，前述電荷蓄積層係由矽氮化膜所成。 7 .如申請專利範圍第5項之非揮發性半導體記憶裝 置，其中，前述第1及第3之絕緣膜之蝕刻速度和前述第 2之絕緣膜蝕刻速度不同者。 、 8 . —種非揮發性半導體記憶裝置之製造方法，其.特 徵係包含以下之構成 (a )於半導體基板之主面上，順序形成第1 、第2 及第3之絕緣膜，形成該第1、第· 2及第3之絕緣膜所成 閘極絕緣膜的工程， 和（b )於該閘極絕緣膜之上部，堆積閘極電極構成 材料之後，經由圖案化該閘極電極構成材料及閙極絕緣膜 ，形成閘極電極之工程， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝· 、1T 經濟部智慧財產局員工消費合作社印製 -2 - 488064 A8 B8 C8 D8 7、申請專利範圍 和（c )將前述第2之絕緣膜之端部選擇性地去除’ 形成空間之工程，. 和（d )於該空間形成電荷蓄積層之工程。 9 ·如申請專利範圍第8項之非揮發性半導體記憶裝 置之製造方法，其中，前述空間形成工程係包含利用前述 第1及第3之絕緣膜與前述第2之絕緣膜的鈾刻速度差， 僅選擇性蝕刻前述第2之絕緣膜的工程者。 1 0 ·如申請專利範圍第8項之非揮發性半導體記憶 裝置之製造方法，其中，包含前述電荷蓄積層形成工程係 被覆前述閘極電極地，堆積電荷蓄積層構成材料的工程， 和向異性鈾刻該電荷蓄積層構成材料的工程。 1 1 · 一種半導體記憶裝置，其特徵係包含以下之構 成者 (a )爲非揮發性半導體記憶裝置，包含下述構成 (i )配置於半導體基板之主面上的第1之下部絕 緣膜， 和（ϋ )配置於該第1之下部絕緣膜之中央上部的第 1之中間絕緣膜， 和（ffi )配置於前述第1之下部絕緣膜之端部之上部 的第1之電荷蓄積層， · 和（iv )配置於前述第1之中間絕緣膜及第.1之電荷 蓄積層之上部的第1之上部絕緣膜， 和（v )配置於第1之上部絕緣膜之上部的第1之閘 極電極， ^紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐） ------- (請先閱讀背面之注意事項再填寫本頁) 訂 -線 經濟部智慧財產局員工消費合作社印製 -3- 488064 8 8 8 8 ABCD 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 (b )爲揮發性半導體記憶裝置，包含下述構成 (i )配置於前述半導體基板之主面上，與前述 第1之中間絕緣膜同一材料所成之第2之下部絕緣膜， 和（U)於前述半導體基板之主面上，且配置於該第 2之下部絕緣膜之端部的極薄絕緣膜， 和（ffi )配置於前述極薄絕緣膜之上部，與前述第1 之電荷蓄積層同一材料所成之第2之電荷蓄積層， 和（iv )配置於前述第2之下部絕緣膜及第2之電荷 蓄積層之上部，與前述第1之上部絕緣膜同一材料所成之 第2之上部絕緣膜， 和（v )配置於該第2之上部絕緣膜之上部的第2之 閘極電極。 1 2 ·如申請專利範圍第1 1項之半導體記憶裝置， 其中，前述第1之下部絕緣膜及第1之上部絕緣膜之蝕刻 速度與前述第1之中間絕緣膜蝕刻速度不同，前述第2之 下部絕緣膜之蝕刻速度與前述第2之上部絕緣膜之蝕刻速 度不同者。 1 3 ·如申請專利範圍第1 1項之半導體記憶裝置， 其中，前述第1及第2之電荷蓄積層係由矽氮化膜所成者 〇 1 4 .如申請專利範圍第1 1項之半導體記憶裝置， 其中，前述極薄絕緣膜係具有可產生直接隧道現象的膜厚 者。 1 5 . —種半導體記憶裝置，其特徵係包含以下之構 本&amp;張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 線- -4- 488064 經濟部智慧財產局員工消費合作社印製 A8 B8 &gt; C8 · D8六、申請專利範圍 成者 (a )爲非揮發性半導體記憶裝置，包含下述構成 (i )配置於半導體基板之主面上的第1之下部絕 緣膜， 和（U )配置於該第1之下部絕緣膜之中央上部的第 1之中間絕緣膜， 和（iii )配置於前述第1之下部絕緣膜之端部之上部 的第1之電荷蓄積層， 和（iv )配置於前述第1之中間絕緣膜及第1之電荷 蓄積層之上部的第1之上部絕緣膜， 和（v )配置於第1之上部絕緣膜之上部的第1之閘 極電極’ (b )爲揮發性半導體記憶裝置，包含下述構成 (i )配置於前述半導體基板之主面上之極薄絕 緣膜， 和（ϋ )配置於前述極薄絕緣膜之上部，與前述第1 之電荷蓄積層同一材料所成之第2之電荷蓄積層， 和（iii)配置於前述第2之電荷蓄積層之第2之上部 絕緣膜， 和（iv )配置於該第2之上部絕緣膜上的第2之閘極 電極。 1 6 .如申請專利範圍第1 5項之半導體記憶裝置， 其中，前述第1之下部絕緣膜及第1之上部絕緣膜之蝕刻 速度與前述第1之中間絕緣膜蝕刻速度不同者。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） · ' -5- (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 一線- 488064 A8 B8 , C8 · D8 六、申請專利範圍 1 7 ·如申請專利範圍第1 5項之半導體記憶裝置， 其中，前述第1及第2之電荷蓄積層係由矽氮化膜所成者 〇 1 8 .如申請專利範圍第1 5項之半導體記憶裝置， 其中，前述極薄絕緣膜係具有可產生直接隧道現象的膜厚 者。 1 9 · 一種揮發性半導體記憶裝置，其特徵係包含以 下之構成 (a )配置於半導體基板之主面上的下部絕緣膜， 和（b )於前述半導體基板之主面上，且配置於該下 部絕緣膜之兩端的極薄絕緣膜， 和（c )配置於該極薄絕緣膜之上部的電荷蓄積層， 和（d )配置於前述下部絕緣膜及電荷蓄積層之上部 的上部絕緣膜， 和（e )配置於該上部絕緣膜之上部的閘極電極。 2 0 . —種揮發性半導體記憶裝置，其特徵係包含以 下之構成 (a )配置於半導體基板之主面上的極薄絕緣膜， 和（b )配置於該極薄絕緣膜上之電荷蓄積層， 和（c )配置於該電荷蓄積層之上部絕緣膜， 和（d )配置於該上部絕緣膜上的閘極電極。 2 1 . —種半導體記憶裝置之製造方法，其特徵係包 含以下之構成 (a )於半導體基板之主面上之一部分，形成第1之 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝· 訂 經濟部智慧財產局員工消費合作社印製 -6 - 488064 A8 B8 C8 D8 六、申請專利範圍 絕緣膜工程， (b )前述第1之絕緣膜之上部及前述半導體基板之 主面之一部分以外，順序形成第2及第3之絕緣膜的工程 經濟部智慧財產局員工消費合作社印製 和（c )於前述第3之絕緣膜之上部，堆積閘極電極 構成材料之工程， 和（d )經由圖案化前述閘極電極構成材料，前述第 3之絕緣膜、前述第2之絕緣膜及前述第1之絕緣膜，形 成第1之閘極電極的工程， 和（e )經由圖案化前述閘極電極構成材料，前述第 3之絕緣膜及則述％ 2之絕緣膜’形成第2之聞極電極構 成材料的工程， 和（f )將前述第1及第2之閘極電極之兩方之第2 之絕緣膜之端部選擇性地去除，形成空間之工程， 和（g )於前述空間形成電荷蓄積層之工程。 2 2 ·如申請專利範圍第2 1項之半導體記憶裝置之 製造方法，其中，前述空間形成工程係包含利用前述第.1 及第3之絕緣膜與前述第2之絕緣膜的蝕刻速度差，僅選 擇性蝕刻前述第2之絕緣膜的工程者。 2 3 .如申請專利範圍第2 1項之半導體記憶裝置之 製造方法，其中，前述電荷蓄積層形成工程係包含被覆前 述閘極電極地，堆積電荷蓄積層構成材料的工程，和向異 性蝕刻該電荷蓄積層構成材料的工程。 2 4 一種半導體記憶裝置之製造方法，其特徵係包Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 488064 A8 B8 C8 D8 6. Scope of Patent Application —… ^ ΐιι (ί ^ 89 1039 1 Patent Application No. 8 ^ t / Γ :: 1 i \\ ^ μ (-? English. Amendment to the scope of patent application I <; I —... 丄: ^ Revised in March 91, Republic of China 1 · A non-volatile semiconductor memory device, which features the following components (a) in semiconductors The first gate electrode disposed on the main surface of the substrate through a gate insulating film, and (b) a charge accumulation layer disposed on a side surface of the first gate electrode, and (c) described above. The second gate electrode disposed on the side of the first gate electrode via the charge accumulation layer, and (d) electrically connecting the first gate electrode and the second gate electrode The conductive layer of the non-volatile semiconductor memory device according to item 1 of the patent application, where the aforementioned charge accumulation layer is formed by a stacked layer of a silicon oxide film and a silicon nitride film. 3 The nonvolatile semiconductor memory device according to item 1, wherein the aforementioned The accumulation layer is composed of three layers of the first silicon oxide film, the silicon nitride film, and the second silicon oxide film .. · 4 · A method for manufacturing a nonvolatile semiconductor memory device, which has the following features (a) On the main surface of the semiconductor substrate, the first gate electrode is formed through the odor insulation film. This standard is applicable to the national standard (CNS) Α4 · (21〇χ297 public envy) ~ ： --------------- I install ------- order ------ line (please read the precautions on the back first ¾ write this page) 488064 A8 B8 C8 _ D8 6. The scope of patent application and (b) on the side of the first gate electrode, the process of sequentially forming the charge accumulation layer and the second gate electrode, and (c) forming the first gate The process of electrically connecting the electrode to the conductive layer of the second gate electrode described above. 5. A non-volatile semiconductor memory device, characterized in that it includes the following structure (a) arranged on the main surface of a semiconductor substrate, A gate insulating film formed by the first, second, and third insulating films, and (b) a charge accumulation layer disposed at an end portion of the second insulating film And (c) a gate electrode disposed on the aforementioned gate insulating film. 6 · The non-volatile semiconductor memory device according to item 5 of the patent application scope, wherein the aforementioned charge accumulation layer is made of a silicon nitride film. 7 The non-volatile semiconductor memory device according to item 5 of the patent application scope, wherein the etching speed of the first and third insulating films is different from the etching speed of the second insulating film. A method for manufacturing a semiconductor memory device, which includes the following features (a): forming the first, second, and third insulating films on the main surface of a semiconductor substrate in sequence, and forming the first, second, and third insulating films; The process of the gate insulating film formed by the insulating film of 3, and (b) forming a gate electrode constituent material on the gate insulating film, and then patterning the gate electrode constituent material and the pseudo insulating film to form For the gate electrode project, this paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling out this page) Printing -2-488064 A8 B8 C8 D8 7. The scope of the patent application and (c) the project of selectively removing the ends of the aforementioned second insulation film to form a space, and (d) forming a charge in the space Accumulation layer works. 9. The method for manufacturing a non-volatile semiconductor memory device according to item 8 of the scope of patent application, wherein the space forming process includes using a difference in uranium etch rate between the first and third insulating films and the second insulating film Only engineers who selectively etch the second insulating film. 10 · The method for manufacturing a non-volatile semiconductor memory device according to item 8 of the scope of patent application, which includes the above-mentioned charge accumulation layer forming process covering the gate electrode ground, depositing the charge accumulation layer constituent material, and anisotropy The process of engraving this charge accumulation layer constituting material. 1 1 · A semiconductor memory device characterized by including the following components (a) as a non-volatile semiconductor memory device including the following configuration (i) a first lower insulating film disposed on the main surface of a semiconductor substrate, And (ϋ) a first intermediate insulating film disposed on a central upper portion of the first lower insulating film, and (ffi) a first charge storage layer disposed on an upper portion of an end portion of the first lower insulating film, And (iv) the first upper insulating film disposed on the above first intermediate insulating film and the charge accumulation layer of the first .1, and (v) the first upper insulating film disposed on the upper portion of the first upper insulating film Gate electrode, ^ Paper size applies to China National Standard (CNS) A4 specification (210X297 mm) ------- (Please read the precautions on the back before filling this page) Order-Intellectual Property Bureau, Ministry of Economic Affairs Printed by Employee Consumer Cooperatives -3- 488064 8 8 8 8 ABCD Printed by Employee Consumer Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs VI. Patent application scope (b) is a volatile semiconductor memory device, including the following components (i) arranged on the aforementioned semiconductor The main surface of the substrate A second lower insulating film made of the same material as the first intermediate insulating film, and (U) is extremely thin on the main surface of the semiconductor substrate and is disposed at the end of the second lower insulating film The insulating film, and (ffi) are arranged on the upper part of the ultra-thin insulating film, the second charge storage layer made of the same material as the first charge storage layer, and (iv) are arranged on the second lower insulation film. And the upper part of the second charge storage layer, the second upper part insulating film made of the same material as the first upper part insulating film, and (v) the second gate disposed on the upper part of the second upper part insulating film Electrode. 1 2 · If the semiconductor memory device according to item 11 of the patent application scope, wherein the etching speed of the first lower insulating film and the first upper insulating film is different from the etching speed of the first intermediate insulating film, the second The etching rate of the lower insulating film is different from the etching rate of the second upper insulating film. 1 3 · If the semiconductor memory device in the scope of patent application No. 11, wherein the first and second charge accumulation layers are formed of silicon nitride film 〇 4. In the semiconductor memory device, the ultra-thin insulating film has a film thickness capable of causing a direct tunneling phenomenon. 1 5. — A semiconductor memory device, which is characterized by the following components &amp; Zhang scales are applicable to Chinese National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling this page) Ordering--4- 488064 A8 B8 &gt; C8 · D8 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6. The applicant for the patent application (a) is a non-volatile semiconductor memory device, which includes the following configuration (i) configuration A first lower insulating film on the main surface of the semiconductor substrate, and (U) a first intermediate insulating film arranged on the upper center of the first lower insulating film, and (iii) a first insulating film disposed on the first lower portion The first charge accumulating layer on the upper part of the end portion of the insulating film and (iv) are disposed on the first first insulating film and the first upper insulating film on the upper portion of the first charge accumulating layer, and (v) are disposed The first gate electrode '(b) above the first upper insulating film is a volatile semiconductor memory device and includes the following constitution (i) an extremely thin insulating film disposed on the main surface of the semiconductor substrate, and (Ϋ) placed in the aforementioned extremely thin insulation The second upper charge storage layer made of the same material as the first charge storage layer, and (iii) the second upper insulation film disposed on the second charge storage layer, and (iv) disposed on the upper part of the film, and A second gate electrode on the second upper insulating film. 16. The semiconductor memory device according to item 15 of the scope of patent application, wherein the etching speed of the first lower insulating film and the first upper insulating film is different from the etching speed of the first intermediate insulating film. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297mm) · '-5- (Please read the precautions on the back before filling this page)-Binding · Ordering-488064 A8 B8, C8 · D8 The scope of patent application 17 • For the semiconductor memory device of the scope of patent application No. 15, wherein the first and second charge storage layers are formed by silicon nitride film 008. As the first scope of patent application The semiconductor memory device according to item 5, wherein the extremely thin insulating film has a film thickness capable of causing a direct tunneling phenomenon. 1 9 · A volatile semiconductor memory device, characterized in that it comprises the following components (a) a lower insulating film disposed on a main surface of a semiconductor substrate, and (b) a main surface of the semiconductor substrate, and disposed on the main surface An ultra-thin insulating film at both ends of the lower insulating film, and (c) a charge accumulation layer disposed above the ultra-thin insulating film, and (d) an upper insulation film disposed above the lower insulation film and the charge accumulation layer, And (e) a gate electrode disposed above the upper insulating film. 2. A volatile semiconductor memory device, which is characterized by comprising (a) an ultra-thin insulating film disposed on the main surface of a semiconductor substrate, and (b) a charge accumulation disposed on the ultra-thin insulating film And (c) an insulating film disposed on the upper part of the charge accumulation layer, and (d) a gate electrode disposed on the upper insulating film. 2 1. A method for manufacturing a semiconductor memory device, which is characterized by including the following components (a) on a main surface of a semiconductor substrate, forming the first paper size applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page)-Binding and printing printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs-488064 A8 B8 C8 D8 b) Printed on top of the above first insulating film and part of the main surface of the aforementioned semiconductor substrate in order to form the second and third insulating films in sequence by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Engineering and Economy and (c) printed on the aforementioned first The process of depositing the gate electrode constituent material on the insulating film of 3, and (d) patterning the gate electrode constituent material, the third insulating film, the second insulating film, and the first insulating film. The process of forming the first gate electrode, and (e) forming the second gate electrode by patterning the gate electrode constituent material, the third insulating film and the insulating film ′ (F) the process of selectively removing the ends of the second insulating film on both sides of the first and second gate electrodes, and (g) the process of forming a space, and (g) the aforementioned space The process of forming a charge accumulation layer. 2 2 · The method for manufacturing a semiconductor memory device according to item 21 of the scope of patent application, wherein the aforementioned space formation process includes utilizing a difference in etching speed between the aforementioned insulating films of .1 and 3 and the aforementioned insulating film, A person who selectively etches only the second insulating film. 2 3. The method for manufacturing a semiconductor memory device according to item 21 of the scope of patent application, wherein the charge accumulation layer forming process includes a process of covering the gate electrode ground, depositing a charge accumulation layer constituent material, and anisotropically etching the Engineering of materials for charge accumulation layers. 2 4 A method for manufacturing a semiconductor memory device, characterized in that (請先閱讀背面之注意事項再填寫本頁) •裝· 訂 線- 488064 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 1 . _ D8六、申請專利範圍 含以下之構成 (a )於半導體基板之主面上，順序形成第1、第2 及第3之絕緣膜的工程， 和（b )於前述第3之絕緣膜之上部，堆積第1之閘 極電極構成材料之後，經由圖案化前述第3之絕緣膜，前 述第2之絕緣膜及第1之絕緣膜，形成第1之閘極電極之 工程， t 和（C )與前述第1之閘極電極形成工程同時進行之 工程中’於前述半導體基板之主面之一部分，經由除去前 述閘極電極構成材料、前述第3之絕緣膜，前述第2之絕 緣膜及第1之絕緣膜，形成第2之閘極電極形成範圍的工 程， 和（d )將前述第χ之閘極電極之第2之絕緣膜之端 部選擇性地去除，形成空間之工程， 和（e )於前述半導體基板之主面上，形成極薄絕緣 膜之工程， 和（ί )於前述半導體基板之主面上，堆積構成電荷 蓄積層之材料後，將該電荷蓄積層構成材料向異性蝕刻地 ，於前述第1之閘極電極之空間形成電荷蓄積層的工程， 和（g )於前述半導體基板之主面上，堆積第4之絕 緣膜及第2之閘極電極構成材料後，經由圖案化前述第4 之絕緣膜，前述電荷蓄積層構成材料及極薄絕緣膜地，形 成第2之閘極電極的工程。 · 2 5 · —種非揮發性半導體記憶裝置，其特徵係包含 本i張尺度適用中關家標準（CNS) A4^ (21GX297公楚） —- -8 - (請先閲讀背面之注意事項再填寫本頁) 裝· 、1T 線- A8 B8 C8 r ' ^_______ D8 六、申請專利範圍 &amp;下之構成 (a )配置於半導體基板之主面上的凸部， 和（b )配置於包含前述凸部之前述半導體基板上， @第1、第2及第3之絕緣膜所成之閘極絕緣膜， 和（c )配置於前述第2之絕緣膜之端部的電荷蓄積 層， 和（d )配置於前述閘極絕緣膜上的閘極電極。 2 6 .如申請專利範圍第2 5項之非揮發性半導體記 憶裝置，其中，前述電荷蓄積層係由矽氮化膜所成者。 2 7 .如申請專利範圍第2 5項之非揮發性半導體記 憶裝置，其中，前述第1及第3之絕緣膜之蝕刻速度與前 述第2之絕緣膜蝕刻速度不同。 2 8 . —種非揮發性半導體記憶裝置之製造方法，其 特徵係包含以下之構成 (a )於半導體基板之主面上，形成凸部之工程， 和（b )於包含前述凸部之前述半導體基板之主面上 ，順序形成第1 、第2及第3之絕緣膜，形成由前述第1 . 、第2及第3之絕緣膜所成閘極絕緣膜的工程， 和（c )於前述閘極絕緣膜之上部，堆積閘極電極構 成材料之後，經由圖案化前述閘極電極構成材料及閘極絕 緣膜，形成閘極電極之工程， 和（d )將前述第2之絕緣膜之端部選擇性地去除， 形成空間之工程， 和（e )於前述空間，形成電荷蓄積層之工程。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） : 一 -9 - (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 線· 經濟部智慧財產局員工消費合作社印製 A8 B8 r C8 ___ D8 ______ $、申請專利範圍 2 9 .如申請專利範圍第2 8項之非揮發性半導體記 憶裝置之製造方法，其中，前述空間形成工程係包含利用 前述第1及第3之絕緣膜與前述第2之絕緣膜的蝕刻速度 差，僅選擇性蝕刻前述第2之絕緣膜的工程者。 3 0 ·如申請專利範圍第2 8項之非揮發性半導體記 憶裝置之製造方法，其中，前述電荷蓄積層形成工程係包 含被覆前述閘極電極地，堆積電荷蓄積層構成材料的工程 ’和向異性蝕刻該電荷蓄積層構成材料的工程。 3 1 _ —種非揮發性半導體記憶裝置，其特徵係包含 以下之構成 (a )配置於半導體基板之主面上的凸部， 和（b )配置於包含前述凸部之前述半導體基板上， 由第1及第2之絕緣膜所成之閘極絕緣膜， 和（c )配置於前述第1及第2之絕緣膜間的電荷蓄 積層， 和（d )配置於前述閘極絕緣膜上的閘極電極。 3 2 ·如申請專利範圍第3 1項之非揮發性半導體記 憶裝置，其中，前述電荷蓄積層係由矽氮化膜所成者。 3 3 · —種非揮發性半導體記憶裝置之製造方法，其 特徵係包含以下之構成 . (a )於半導體基板之主面上，形成凸部之工程， 和（b )於包含前述凸部之前述半導體基板之主面上 ’順序形成第1之絕緣膜、電荷蓄積層構成材料，及第3 之絕緣膜的工程， (請先聞讀背面之注意事項再填寫本頁) 裝· 訂 線 &lt; 經濟部智慧財產局員工消費合作社印製 10- 488064 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 ’ &lt; D8六、申請專利範圍 和（c )經由圖案化前述第1之絕緣膜、電荷蓄積層 構成材料及第3之絕緣膜，形成閘極電極之工程。 3 4 · —種非揮發性半導體記憶裝置，其特徵係包含 以下之構成 (a )配置於半導體基板之主面上的凹部， 和（b )配置於包含前述凹部之前述半導體基板上， 由第1、第2及第3之絕緣膜所成之閘極絕緣膜， 和（c )配置於前述第2之絕緣膜之端部的電荷蓄積 層， 和（d )配置於前述閘極絕緣膜上的閘極電極。 3 5 .如申請專利範圍第3 4項之非揮發性半導體記 憶裝置，其中，前述電荷蓄積層係由矽氮化膜所成者。 3 6 .如申請專利範圍第3 4項之非揮發性半導體記 憶裝置，其中，前述第1及第3之絕緣膜之蝕刻速度與前 述第2之絕緣膜蝕刻速度不同。 3 7 . —種非揮發性半導體記憶裝置之製造方法，其 特徵係包含以下之構成 (a )於半導體基板之主面上，形成凹部之工程， 和（b )於包含前述凹部之前述半導體基板之主面上 ，順序形成第1、第2及第3之絕緣膜，形成由前述第1 、第2及第3之絕緣膜所成閘極絕緣膜的工程， 和（c )於前述閘極絕緣膜之上部，堆積閘極電極構 成材料之後，經由圖案化前述閘極電極構成材料及閘極絕 緣膜，形成閘極電極之工程， 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) -裝· 訂 線 -11 - 488064 經濟部智慧財產局員工消費合作社印製 A8 B8 , C8 r D8 _六、申請專利範圍 和（d )將前述第2之絕緣膜之端部選擇性地去除’ 形成空間之工程，. 和（e )於前述空間，形成電荷蓄積層之工程。 3 8 .如申請專利範圍第3 7項之非揮發性半導體記 憶裝置之製造方法，其中，前述空間形成工程係包含利用 前述第1及第3之絕緣膜與前述第2之絕緣膜的蝕刻速度 差’僅選擇性蝕刻前述第2之絕緣膜的工程者。 3 9 ·如申請專利範圍第3 7項之非揮發性半導體記 憶裝置之製造方法，其中，前述電荷蓄積層形成工程係包 含被覆前述閘極電極地，堆積電荷蓄積層構成材料的工程 ，和向異性蝕刻該電荷蓄積層構成材料的工程。 4 0 · —種非揮發性半導體記憶裝置，其特徵係包含 以下之構成 (a )配置於半導體基板之主面上的凹部， 和（b )配置於包含前述凹部之前述半導體基板上， 由第1及第2之絕緣膜所成之閘極絕緣膜， 和（c )配置於前述第1及第2之絕緣膜間的電荷蓄 積層， 和（d )配置於前述閘極絕緣膜上的閘極電極。 4 1 . 一種非揮發性半導體記憶裝置之製造方法，其 特徵係包含以下之構成 (a )於半導體基板之主面上，形成凹部之工程， 和（b )於包含前述凹部之前述半導體基板之主面上 ，順序形成第1之絕緣膜、電荷蓄積層構成材料，及第3 (請先閱讀背面之注意事項再填寫本頁) -裝- 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇χ297公釐） -12- 488064 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 * ___ D8六、申請專利範圍 之絕緣膜的工程， 和（C )經由圖案化前述第1之絕緣膜、電荷蓄積層 構成材料，及第3之絕緣膜，形成閘極電極之工程。 4 2 · —種非揮發性半導體記憶裝置之製造方法，其 特徵係包含以下之構成 (a )於半導體基板之主面上，形成凹部之工程， 和（b )於包含前述凹部之前述半導體基板之主面上 ，順序形成第1、第2及第3之絕緣膜，形成由前述第1 、第2及第3之絕緣膜所成閘極絕緣膜的工程， 和（c )於前述閘極絕緣膜之上部，堆積閘極電極構 成材料之後，經由將前述閘極電極構成材料以機械性硏磨 方法加以除去，形成埋入於前述凹部的閘極電極之工程， 和（d )將前述第2之絕緣膜之端部選擇性地去除， 形成空間之工程， 和（e )於前述空間，形成電荷蓄積層之工程。 4 3 · —種非揮發性半導體記憶裝置之製造方法，其 特徵係包含以下之構成 (a )於半導體基板之主面上，形成凹部之工程， 和（b )於包含前述凹部之前述半導體基板之主面上 ，順序形成第1之絕緣膜、電荷蓄積層構成材料，及第3 之絕緣膜的工程， 和（c )於前述第3之絕緣膜之上部，堆積閘極電極 構成材料之後，經由將前述閘極電極構成材料以機械性硏 磨方法加以除去，形成埋入於前述凹部的閘極電極之工程 本、尺度適用中國國家標準（CNS ) A4規格(210X297公釐） &quot; ： -13- (請先閲讀背面之注意事項再填寫本頁) •裝· 、11 線_ 488064 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 * . D8六、申請專利範圍 〇 4 4 · 一種非揮發性半導體記憶裝置，其特徵係包含 以下之構成 (a )於半導體基板之主面上，介由閘極絕緣膜，加 以配置之閘極電極， 和（b )配置於前述聞極電極之端部的凹部， 和（c )於前述凹部，介有絕緣膜，加以配置之電荷 蓄積層， 其中，前述電荷蓄積層係配置於通道範圍及源極汲極 範圍之兩者之上部者。 4 5 ·如申請專利範圍第4 4項之非揮發性半導體記 憶裝置，其中，前述電荷蓄積層係與配置於前述閘極電極 之側面的側壁一體化者。 4 6 .如申請專利範圍第1項記載之非揮發性半導體 記憶裝置，其中，前述電荷蓄積層係配置於前述第1之閘 極電極之兩側面上。 4 7 .如申請專利範圍第5、2 5、3 4項之任一項. 記載之非揮發性半導體記憶裝置，其中，前述電荷蓄積層 係配置於前述第2之絕緣膜之兩端部。 4 8 .如申請專利範圍第1 1項記載之半導體記憶裝 置，其中，前述第1之電荷蓄積層係配置於前述第1之下 部絕緣膜之兩端部之上部， 前述第2之電荷蓄積層係配置於配置在前述第2之下 部絕緣膜之兩端部的前述極薄絕緣膜上部。 本#^張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ~' -14- (請先閱讀背面之注意事項再填寫本頁) •裝· 訂 -線· 488064 經濟部智慧財產局員工消资合作社印製 A8 B8 · · C8 D8六、申請專利範圍 4 9 .如申請專利範圍第1 5項記載之半導體記憶裝 置，其中，前述第1之電荷蓄積層係配置於前述第1之下 部絕緣膜之雨端部之上部。 5 〇 ·如申請專利範圍第1 9項記載之揮發性半導體 記憶裝置，其中，前述電荷蓄積層係配置於前述下部絕緣 膜之兩端部之兩端部的前述前述極薄絕緣膜上部。 5 1 .如申請專利範圍第2 0項記載之揮發性半導體 記憶裝置，其中，，蓄積於前述電荷蓄積層之資料係再寫入 於更新期間內者。 5 2 .如申請專利範圍第4項記載之非揮發性半導體 記憶裝置之製造方法，其中，順序形成前述電荷蓄積層及 第2之閘極電極的工程係於前述第1之閘極電極之兩側面 上，順序形成前述電荷蓄積層及第2之閘極電極的工程者 〇 53.如申請專利範圍第8項記載之非揮發性半導體記憶裝 置之製造方法，其中，形成前述空間之工程係選擇性除去 前述第2之絕緣膜之兩端部，形成空間之工程， 形成前述電荷蓄積層之工程係於經由前述選擇除去所形 成之兩空間，形成電荷蓄積層之工程者。 5 4 ·如申請專利範圍第2 Γ項記載之半導體記憶裝 置之製造方法，其中，形成前述空間之工程係選.擇性除去 前述第1及第2之閘極電極之兩者之前述第2之絕緣膜之 兩端部，形成空間之工程， 形成前述電荷蓄積層之工程係於經由前述選擇除去所 本紙張尺度適用中國國家梂準（CNS ) A4規格（210X297公釐） &gt; -—-1- ί · (請先閱讀背面之注意事項再填寫本頁) ——· --訂 ------- -15- 488064 A8 B8 C8 D8 六、申請專利範圍 开多，或之兩空間，形成電荷蓄積層之工程者。 5 5 ·如申請專·利範圍第2 4項記載之半導體記憶裝 置之製造方法，其中，形成前述空間之工程係選擇性除去 前述第1之閘極電極之第2之絕緣膜之兩端部，形成空間 之工程， 开多$前述電荷蓄積層之工程係於經由前述選擇除去所 形成之兩空間，形成電荷蓄積層之工程者。 5 6 ·如申請專利範圍第2 8、3 7、4 2項之任一 項記載之非揮發性半導體記憶裝置之製造方法，其中， 形成前述空間之工程係經由選擇性除去前述第2之絕 緣膜之兩端部，形成空間之工程， 形成前述電荷蓄積層之工程係於經由前述選擇除去所 形成之兩空間，形成電荷蓄積層之工程者。 (請先閲讀背面之注意事項再填寫本頁) 裝· 訂 線 經濟部智慧財產局員工消脅合作社印製 本紙張尺度逋用中國國家梂準（CNS ) A4規格（210X297公釐） -16-(Please read the precautions on the back before filling out this page) • Binding and Binding-488064 Printed by Employee Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 1. _ D8 VI. The scope of patent application includes the following components (a) in The process of sequentially forming the first, second, and third insulating films on the main surface of the semiconductor substrate, and (b) depositing the first gate electrode constituent material on the upper portion of the third insulating film, and then patterning The process of forming the third insulating film, the second insulating film, and the first insulating film to form the first gate electrode, and t and (C) are performed simultaneously with the first gate electrode forming process. In a part of the main surface of the semiconductor substrate, the second gate electrode formation range is formed by removing the gate electrode constituent material, the third insulating film, the second insulating film, and the first insulating film. And (d) the process of selectively removing the end of the second insulating film of the χth gate electrode and forming a space, and (e) forming an extremely thin film on the main surface of the semiconductor substrate Engineering of insulating films, and ί) a process of forming a charge accumulation layer in the space of the first gate electrode by anisotropically etching the charge accumulation layer constituting material after depositing the material constituting the charge accumulation layer on the main surface of the semiconductor substrate, and (G) After depositing the fourth insulating film and the second gate electrode constituent material on the main surface of the semiconductor substrate, the pattern of the fourth insulating film, the charge accumulation layer constituent material, and the ultra-thin insulating film are patterned. Ground, the process of forming the second gate electrode. · 2 5 · —A kind of non-volatile semiconductor memory device, which is characterized by the application of Zhongguanjia Standard (CNS) A4 ^ (21GX297) for this i-scale. —- -8-(Please read the precautions on the back before (Fill in this page) Assembly, 1T line-A8 B8 C8 r '^ _______ D8 6. The scope of the patent application &amp; (a) The convex portion disposed on the main surface of the semiconductor substrate, and (b) the A gate insulating film formed by the @ 1st, 2nd, and 3rd insulating films on the aforementioned semiconductor substrate of the aforementioned raised portion, and (c) a charge accumulation layer disposed at an end portion of the aforementioned second insulating film, and (D) A gate electrode disposed on the gate insulating film. 26. The non-volatile semiconductor memory device according to item 25 of the patent application scope, wherein the aforementioned charge accumulation layer is made of a silicon nitride film. 27. The non-volatile semiconductor memory device according to item 25 of the patent application scope, wherein the etching speed of the first and third insulating films is different from the etching speed of the second insulating film. 28. A method for manufacturing a non-volatile semiconductor memory device, which is characterized by including the following structures (a) a process of forming a convex portion on the main surface of a semiconductor substrate, and (b) the aforementioned portion including the aforementioned convex portion The process of forming the first, second, and third insulating films in order on the main surface of the semiconductor substrate, and forming a gate insulating film formed by the aforementioned first, second, and third insulating films, and (c) in After the gate electrode constituent material is deposited on the gate insulating film, the gate electrode is formed by patterning the gate electrode constituent material and the gate insulating film, and (d) the step of forming the second insulating film The process of selectively removing the ends to form a space, and (e) the process of forming a charge accumulation layer in the aforementioned space. This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm): 1-9-(Please read the precautions on the back before filling out this page) Binding · Threading · Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 r C8 ___ D8 ______ $, patent application scope 2 9. For the manufacturing method of the non-volatile semiconductor memory device of the patent application scope item 28, wherein the aforementioned space formation engineering includes the use of the aforementioned first and third The etching rate between the insulating film and the second insulating film is different, and only the engineer who selectively etches the second insulating film. 30. The method for manufacturing a non-volatile semiconductor memory device according to item 28 of the scope of patent application, wherein the charge accumulation layer forming process includes a process of covering the gate electrode ground and depositing a charge accumulation layer constituent material. A process of anisotropically etching the constituent material of the charge accumulation layer. 3 1 _ —A non-volatile semiconductor memory device, which is characterized by including the following structures (a) a convex portion disposed on the main surface of a semiconductor substrate, and (b) a convex portion disposed on the semiconductor substrate including the convex portion, The gate insulating film formed of the first and second insulating films, and (c) a charge accumulation layer disposed between the first and second insulating films, and (d) disposed on the gate insulating film. Gate electrode. 32. The non-volatile semiconductor memory device according to item 31 of the scope of patent application, wherein the aforementioned charge accumulation layer is made of a silicon nitride film. 3 3-A method for manufacturing a non-volatile semiconductor memory device, which is characterized by including the following constitutions: (a) a process of forming a convex portion on the main surface of a semiconductor substrate, and (b) a process including the aforementioned convex portion In the process of forming the first insulating film, the charge accumulation layer constituent material, and the third insulating film in order on the main surface of the aforementioned semiconductor substrate, (please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 10- 488064 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A8 B8 C8 '&lt; D8 6. Scope of patent application and (c) by patterning the aforementioned first insulating film, The process of forming the charge storage layer constituting material and the third insulating film to form a gate electrode. 34. A non-volatile semiconductor memory device, which is characterized by including the following components (a) a recessed portion disposed on a main surface of a semiconductor substrate, and (b) a recessed portion disposed on the semiconductor substrate including the recessed portion. 1. The gate insulating film formed by the second and third insulating films, and (c) a charge accumulation layer disposed at an end portion of the second insulating film, and (d) disposed on the gate insulating film. Gate electrode. 35. The non-volatile semiconductor memory device according to item 34 of the patent application scope, wherein the aforementioned charge accumulation layer is made of a silicon nitride film. 36. The non-volatile semiconductor memory device according to item 34 of the scope of patent application, wherein the etching rate of the first and third insulating films is different from the etching rate of the second insulating film. 37. — A method for manufacturing a non-volatile semiconductor memory device, characterized in that it includes the following constitutions (a) a process of forming a recess on the main surface of a semiconductor substrate, and (b) the aforementioned semiconductor substrate including the aforementioned recess On the main surface, a process of forming first, second, and third insulating films in sequence, forming a gate insulating film formed by the aforementioned first, second, and third insulating films, and (c) forming the gate electrode After the gate electrode constituent material is deposited on the upper part of the insulating film, the gate electrode is formed by patterning the gate electrode constituent material and the gate insulating film, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297). (%) (Please read the precautions on the back before filling this page)-Binding · 11-488064 Printed by A8 B8, C8 r D8 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs _ 6. Scope of Patent Application and (d) The process of selectively removing the end of the aforementioned second insulating film to form a space, and (e) a process of forming a charge accumulation layer in the aforementioned space. 38. The method for manufacturing a non-volatile semiconductor memory device according to item 37 of the scope of patent application, wherein the aforementioned space forming process includes using the etching rates of the aforementioned first and third insulating films and the aforementioned second insulating film. The difference is only the engineer who selectively etches the second insulating film. 39. The method for manufacturing a nonvolatile semiconductor memory device according to item 37 of the scope of patent application, wherein the charge storage layer forming process includes a process of covering the gate electrode ground, depositing a charge storage layer constituent material, and A process of anisotropically etching the constituent material of the charge accumulation layer. 4 0 · A non-volatile semiconductor memory device, which is characterized by including the following components (a) a recessed portion disposed on a main surface of a semiconductor substrate, and (b) a recessed portion disposed on the semiconductor substrate including the recessed portion. The gate insulating film formed by the first and second insulating films, and (c) a charge storage layer disposed between the first and second insulating films, and (d) a gate disposed on the gate insulating film. Electrode. 41. A method for manufacturing a non-volatile semiconductor memory device, which is characterized by including the following steps (a) forming a recess on the main surface of a semiconductor substrate, and (b) forming the semiconductor substrate including the aforementioned recess On the main surface, the first insulating film, the charge accumulation layer constituent material, and the third (please read the precautions on the back before filling out this page) are sequentially formed.-Binding-Threading This paper applies the Chinese National Standard (CNS) A4 Specifications (21 × 297 mm) -12- 488064 Printing of A8 B8 C8 * ___ D8 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs VI. The patented insulation film project, and (C) the first The process of forming an insulating film, a charge storage layer constituent material, and a third insulating film to form a gate electrode. 4 2 · A method for manufacturing a non-volatile semiconductor memory device, which is characterized by including (a) a process of forming a recess on a main surface of a semiconductor substrate, and (b) a semiconductor substrate including the aforementioned recess On the main surface, a process of forming first, second, and third insulating films in sequence, forming a gate insulating film formed by the aforementioned first, second, and third insulating films, and (c) forming the gate electrode After the gate electrode constituent material is deposited on the upper part of the insulating film, the gate electrode constituent material is removed by mechanical honing to form a gate electrode buried in the recess, and (d) the first The process of selectively removing the ends of the insulating film 2 to form a space, and (e) the process of forming a charge accumulation layer in the aforementioned space. 4 3 · A method for manufacturing a non-volatile semiconductor memory device, which is characterized by including (a) a process of forming a recess on a main surface of a semiconductor substrate, and (b) a semiconductor substrate including the aforementioned recess On the main surface, the first insulating film, the charge storage layer constituent material, and the third insulating film are sequentially formed, and (c) after the gate electrode constituent material is deposited on the third insulating film, After removing the gate electrode constituent material by mechanical honing, the engineering version and dimensions of the gate electrode embedded in the recess are applied to the Chinese National Standard (CNS) A4 specification (210X297 mm) &quot;:-- 13- (Please read the precautions on the back before filling out this page) • Packing ·, 11 lines _ 488064 Printed by A8, B8, C8 *, Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. A volatile semiconductor memory device is characterized in that it includes the following structure (a) a gate electrode arranged on a main surface of a semiconductor substrate through a gate insulating film, and (b) A concave portion at the end of the aforementioned smell electrode, and (c) a charge accumulation layer disposed in the concave portion via an insulating film, wherein the charge accumulation layer is disposed between the channel range and the source-drain range Those who are above. 45. The non-volatile semiconductor memory device according to item 44 of the patent application scope, wherein the charge storage layer is integrated with a sidewall disposed on a side surface of the gate electrode. 46. The non-volatile semiconductor memory device according to item 1 in the scope of the patent application, wherein the charge storage layer is disposed on both sides of the first gate electrode. 47. The non-volatile semiconductor memory device according to any one of items 5, 25, and 34 in the scope of patent application, wherein the charge storage layer is disposed at both ends of the second insulating film. 48. The semiconductor memory device according to item 11 in the scope of the patent application, wherein the first charge storage layer is disposed above both ends of the first lower insulating film and the second charge storage layer The upper part of the extremely thin insulating film is disposed on both ends of the second lower insulating film. This # ^ 张 yard applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ~ '-14- (Please read the precautions on the back before filling out this page) • Binding · Binding-Thread · 488064 Intellectual Property Bureau of the Ministry of Economic Affairs Printed by employees' cooperatives A8 B8 · · C8 D8 VI. Patent application scope 4 9. For the semiconductor memory device described in item 15 of the patent application scope, wherein the first charge accumulation layer is arranged in the first one Above the rain end of the lower insulation film. 50. The volatile semiconductor memory device according to item 19 in the scope of the patent application, wherein the charge storage layer is disposed on the upper part of the extremely thin insulating film at both ends of both ends of the lower insulating film. 51. The volatile semiconductor memory device described in item 20 of the scope of patent application, wherein the data accumulated in the aforementioned charge accumulation layer is written again during the update period. 5 2. The method for manufacturing a nonvolatile semiconductor memory device according to item 4 in the scope of the patent application, wherein the process of sequentially forming the charge storage layer and the second gate electrode is performed on two of the first gate electrode. On the side, an engineer who sequentially forms the aforementioned charge accumulation layer and the second gate electrode. 53. The manufacturing method of the non-volatile semiconductor memory device described in item 8 of the scope of patent application, in which the process of forming the aforementioned space is selected The process of removing both ends of the second insulating film to form a space, and the process of forming the charge accumulation layer are those who form the charge accumulation layer by removing the two spaces formed by the aforementioned selection. 5 4 · The method for manufacturing a semiconductor memory device as described in item 2 Γ of the scope of patent application, wherein the engineering to form the aforementioned space is selected. The aforementioned second to selectively remove both the first and second gate electrodes. Both ends of the insulating film are used to form a space. The process of forming the aforementioned charge accumulation layer is based on the selection and removal of the paper. The Chinese paper standard (CNS) A4 (210X297 mm) is applicable. &Gt; --- 1- ί (Please read the precautions on the back before filling this page) —— · --Order ------- -15- 488064 A8 B8 C8 D8 VI. Apply for more patents, or two spaces Engineers who form charge accumulation layers. 5 5 · The method for manufacturing a semiconductor memory device according to item 24 of the patent application scope, wherein the step of forming the space is to selectively remove both ends of the second insulating film of the first gate electrode. The project of forming a space, the project of opening the aforementioned charge accumulation layer is an engineer who forms the charge accumulation layer by removing the two spaces formed by the aforementioned selection. 5 6 · The method for manufacturing a non-volatile semiconductor memory device according to any one of the items 28, 37, 42 in the scope of the patent application, wherein the process of forming the aforementioned space is performed by selectively removing the aforementioned second insulation The process of forming a space at both ends of the film, and the process of forming the aforementioned charge accumulation layer are those who remove the two spaces formed by the aforementioned selection to form a charge accumulation layer. (Please read the precautions on the back before filling in this page.) Binding and printing. Printed by the Employees' Co-operative Society of the Intellectual Property Bureau of the Ministry of Economic Affairs. This paper is in the size of China National Standard (CNS) A4 (210X297 mm).
TW089103918A 1999-03-08 2000-03-04 Nonvolatile semiconductor device and manufacturing method, nonvolatile semiconductor memory device and manufacturing method, and semiconductor memory device mixed with nonvolatile and volatile semiconductor memory devices and manufacturing method TW488064B (en)

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