TW484110B - Video frame rendering engine - Google Patents

Abstract

A circuit is provided which contains memory, logic, arithmetic and control circuitry needed to generate all or part of a frame for use in video processing, and animation as well as digital signal and image processing. One or more such circuits are provided on an integrated circuit. A video or image frame generation system is constructed from one or more of these integrated circuits, optionally with additional memory circuitry, to provide exceptional performance in frame production for animation, particularly 3-D and other high performance applications such as medical imaging, virtual reality and real-time scene generation in video games and simulation environments. The circuit(s) are used to process high speed object-oriented graphics related streams such as proposed by MPEG 4, as well as act as a single chip JAVA engine with highly optimized numeric performance.

Description

484110 Λ7 V. Statement of Invention (ί) Relevant Application Statements: This patent application claims priority to US provisional application number: 60 / 033,476, filed on December 19, 1996, and case number: 60 / 050,396, filed on June 20, 1997, the entire contents of these provisional applications are hereby incorporated by reference. BACKGROUND OF THE INVENTION The present invention relates to some circuits. More specifically, the present invention relates to a high-performance integrated circuit suitable for video frame generation work and digital signal processing (DSP) work. A major problem in the graphics industry is generating frames, each of which is a rectangular pixel array, usually containing more than one million pixels. Regarding animation, especially three-dimensional animation, millions to billions of calculations are generally required to produce one pixel. Similarly, drawing applications, such as medical imaging, need to produce one or more frames, and more often, they are generated in the order of animation. Consider an example of an animation "T 〇 y story" created by the results published by Pi X a r in 1995. There are 1 100 frames in this animation ◊ Pi X a r uses 8 7 groups of dual processors 100 megahertz (ΜΗZ) Sparc20 ′ s and 30 groups of four processors 100 megahertz Sparc 20 4s. All are 2 9 4 central processing units (CPUs). Each central processing unit has an average of 96 million bytes of random access memory and each processing node has a 3 to 5 gigabyte (g i g a b y t e) regional disk drive. These drives and their servers are not related to this patent, but the system is quite large. The entire animation needs to be calculated for 4 to 6 days and an average frame takes 1 to 3 hours of processor time in the SPa r c central processing unit. See reference [1]. This paper size is applicable to China National Standard (CNS) A4 (21〇 × 29 * 7 公 漦) π Please read the precautions on the back first ^ Write this page)

Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs L 84 4 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 __ B7 __ V. Description of the Invention (v) Although the "T 〇y Story" is not as true as a photo, it Represents an important technological breakthrough. "Toy Story" is the first full-length feature film animation. The entire story animation is produced by 3D computer animation technology. ◊Photo-like reality requires at least ten times more calculation than such a movie. Assume that these photo-like real frames are calculated in 30 hours. There are many different programs used to generate frames. See references [1 9] to [2 3]. These programs are complex and must be efficient. They were created with high-level procedural and object-oriented computer programming languages such as C, C ++, and FORTRAN. Only the most important performance-critical parts of these programs may be written directly in assembly / machine language based on the rendering engine hardware, because the cost is too expensive and it is difficult to program in assembly / machine language. Because floating-point arithmetic has a wide dynamic range and easy programming, floating-point arithmetic is popular in these programs. There is a great need to improve performance. The best video editing system requires one frame per second. Real-time virtual reality must reach 30 frames per second. The performance improvements required to meet these two applications have been increased to 1 800 0 times (= 30 hours / frame X 360 seconds / hour) for video editing and virtual reality. The speed is increased to 3 240,000 times (two 30 * video editing). A similar situation exists in high-performance digital signal processing. Typical requirements include processing images, usually collecting signals from 2D and 3D sensor array groups and rendering images of internal matter, including human bodies and machine tools. ______5_ This paper size applies to China National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 484110 Λ__L7 ____ One 5. Description of the invention ()) These multi-dimensional signal processing applications draw images from the ultrasonic or magnetic contrast sensor library. This has the same performance requirements for frame generation. These applications have the purpose of analytical features in the reproduction / simulation of a three-dimensional or four-dimensional environment (note: the so-called four-dimensional meaning system here is the observation / simulation of the three-dimensional domain on the time axis). Feature resolution is the accumulation of input sensor resolution, the depth of fast Fourier transform (F F T) analysis that can be calculated within a certain period of time, the control of rounding errors, and the rounding errors processed through these data frames. High-definition feature resolution in a very short period of time results in each pixel or each data point of the output performing millions and often billions of arithmetic operations. The use of floating point arithmetic is used to provide a dynamic range Control and flexible rounding error control are quite common. The flexibility of the calculus is preferred because of the continuous software development and the availability of many different applications. These different applications often require a variety of software. These application software development requirements are quite consistent. In particular, most applications require many programs, most of which are written in procedural computer programming languages such as C ', C ++, and FORT RAN (see reference [1 1]- [1 8]); and the use of machine-level programming is limited to the most critical performance parts of such programs. These algorithms will have the following common characteristics: processing every ~ elements requires a lot of memory, usually 100 million bytes (Μ B) range; every ~ output 値 (pixels, data points, etc.) ) Requires a large number of arithmetic calculations; According to the large number of calculations and calculations required by most inputs 値 (pixels, data points, etc.); and requires only a small communication burden compared to the computing power ◊ This paper scale applies to China) Ａ 视 格 — （21〇χ297 公 楚） " (Please read the notes on the back before filling this page} 'Order__ 484110 Λ7 B7 V. Description of the invention (+) Support for high-resolution drawing has been developed at least More than 30 years. Preliminary results in the 1960s and early 1970s, such as the computer graphics system built with a small amount of specific hardware, as described in reference [40]. At that time, there was little or no Circuit). With the support of semiconductor devices for the graphics industry, the focus has been on the following topics: A. Support for input / output (I / 〇) devices, support for screen display devices that consume a lot of effort . This led to the development of specific integrated circuits that control the screen. See reference [2]. Β. The development of high-speed microprocessors and digital signal processors. C. The development of high-speed and high-density memory devices, especially dynamic random. Access memory (DRAM), video memory (VRAM), etc. D. Special purpose components are designed for real-time image processing and frame generation applications. These efforts have basically encountered some bottlenecks, as described below. Printed by the Bureau of Consumer Standards of the Bureau of Standards · The controller of the display device is limited by the fact that each frame is generated by a fixed execution structure machine within a specific period of time. Therefore, various frame algorithms are bound to be limited. B · High-speed micro Processors and digital signal processors have a great deal of inherent algorithmic flexibility and are therefore used in high-speed dedicated frame drawing architectures such as generating "Ding Oy Story" SUN (Sun) networks. See reference [1]. With the appearance of the Inte 1 Pentium microprocessor, 484110 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, printed B7 V. Invention Description ($) brought RISC (Reduced Instruction Set Computer) combines all performance strategies of the group. Appendix D in Reference [30]: Replacement of Reduced Instruction Set Computer: INTEL80X86) and "Appendix: An Ultrapure in Reference [3 1]" Amount 3 8 6 "provides a good reference in this regard. Reference [30], "Appendix C: A Review of the Reduced Instruction Set Computer Architecture" provides a good overview. However, commercial microprocessors and digital signal processor systems are limited by their large number of additional circuits. In modern ultrascalar computers, this additional circuit may be substantially larger than these arithmetic units. See references [3 0] and [3 1] for a discussion of comparative evaluation of architecture efficiency / cost. C. High-performance memory system is necessary, but it does not guarantee the generation of fast frames. Because high-performance memory cannot generate data, it is only used to store data. D. Several types of special-purpose components have been proposed. These special-purpose components are It is tightly integrated into the data processing element and is connected to the integrated circuit of a high-performance memory (usually dynamic random access memory). However, all these efforts have encountered bottlenecks. The circuit discussed in reference [3 2] uses a fixed-point arithmetic engine with limited precision. The circuit discussed in reference # 32 [3 2] is limited to the performance of floating point execution 'and the processing program is larger than the area memory of a single processor. The special purpose components mentioned above are optimized to perform several gastrointestinal methods. These components include: D 1 · Image compression / decompression processor. Although these circuits are important, they are very specialized and do not provide general § @ for a variety of algorithms. (Please read the notes on the back before filling out this page.) The paper size of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 (Mm) 484110 V. Explanation of invention (fe). For example, such an engine is bound to be difficult to effectively program in higher-level programming languages such as C, C ++, and FORTR A N. The need to use component languages for their program design means that these units will not be able to meet the general purpose needs of multi-dimensional imaging and drawing frame generation because software development requires a large amount of funding, see references [2 4] and [2 5]. D 2 · The processor provides drawing algorithm optimizations such as fractal geometry, Z-axis buffers, G 0 u I * a u d shadow effects, and more. These circuits are not optimized for a wide range of graphics frame generation and image processing needs. See references [26] to [2 9]. D3. Signal processing pre-processor accelerators such as wavelets and other filters, the fundamental wave passes through a base of 4, 8 or 16 fast Fourier transform (F F T) and so on. 1D and 2D discrete cosine transformation engines. These circuits are very difficult to efficiently perform various large-size frame generation programs. D 4 · Multi-processor image processor. These processors include hybrid multiple instruction multiple data path (M I MD) and single instruction multiple data path (S I MD) systems, these systems are not suitable for general purpose programming. See references [24] and [41] to [43]. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. These processors also include VLIW (Very Long Instruction Word Processor) single instruction multiple data path (SIMD) integrated circuits such as C hr 〇m at ic 's MPA CT integrated circuits . Such integrated circuits also cannot provide the calculation flexibility required by a large number of 3D animation software programs used in industrial applications, which requires efficient compiler assistance. See references [3 4] and [3 9]. D 5 · Multimedia signal processor. These processors also have a variety of paper size standards applicable to Chinese National Standards (CNS) A4 specifications (210X29? Mm) Printed by the Staff Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 484110 Λ7 B7 5. Invention Description (7) Point support, lack of broadband external data memory interface access bandwidth for large external memory, lack of command processing flexibility and data processing multifacetedness, and rely on vector processors. There is no very consistent data accumulation, so data access mechanisms are not efficient and difficult to perform programmatic operations. See references [3 5]-[3 8]. What is needed is a computing engine that avoids the aforementioned limitations on video frame rendering and digital signal processing tasks. Summary of the present invention: A circuit system is provided, which includes memory, logic, arithmetic and control circuits required for generating all or part of a frame for video processing, animation, digital signal and image processing, etc. An integrated circuit is equipped with one or more such circuits. A video or image frame generation system is composed of one or more integrated circuits among these integrated circuits, and optionally has additional memory circuits, which can provide superior performance in the production of frames on animation, especially 3D and Instant production of other high performance applications such as medical imaging, virtual reality, video and video games, and virtual environments. The (etc.) circuit is used to process high-speed object-oriented drawing-related information flow such as processing MP E G 4 information flow, and as a single chip: i AVA engine can have good optimized data performance. Brief description of the drawings: FIG. 1 is a block diagram of a basic circuit according to an embodiment of the present invention. FIG. 2 is a block diagram of the array processor of FIG. 1 according to an embodiment of the present invention. Fig. 3 is related to the array processing of Fig. 1 according to another embodiment of the present invention _____ 10 This paper size is applicable to China) A4 specification (21〇X 297 / > fl '~~ (Please read the precautions on the back before filling (This page)

1T 484110 Λ7 V. Block diagram of the invention description (f). FIG. 4 is a block diagram of the embedded microprocessor of FIG. 1. FIG. Fig. 5 is a block diagram of an integrated circuit, which has two sets of basic circuit entities of Fig. 1 and has independent external memory interfaces. Fig. 6 is a block diagram of an integrated circuit, which has two sets of basic circuit entities of Fig. 1 and shares an external memory interface. Figure 7 is a block diagram of an integrated circuit, which has four sets of the basic circuit entities of Figure 1 and has independent external memory interfaces. Figure 8 is a block diagram of an integrated circuit, which has four sets of Figure 1 The basic circuit entity also shares an external memory interface. Fig. 9 is a block diagram of an integrated circuit, which has four sets of the basic circuit entities of Fig. 1 and shares two sets of external memory interfaces. Fig. 10 is a block diagram of an integrated circuit, which has four sets of basic circuit entities of Fig. 1 and two sets of shared external memory interfaces and fully interconnected message ports. _ Figure 11 is a block diagram of an integrated circuit, which has sixteen sets of the basic circuit entities of Figure 1 and four sets of shared external memory interfaces. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Group shared memory interface. Fig. 13 is a block diagram of a printed circuit board, showing the integration of the basic circuit entities of Fig. 1 with the memory modules corresponding to them on a circuit board. Fig. 14 is a block diagram of another printed circuit board, showing the integration of the basic circuit entities of Fig. 1 and their corresponding memory modules on a circuit board. __ This paper standard applies to the Chinese National Standard (CNS) Α4 Specifications (210X 297mm) 484110 V. Description of the Invention (?) Definition: Conductor: A conductor is a mechanism that shares the state among multiple nodes in a circuit. This state is based on the limited characters of some practical situations. It includes but is not limited to these: voltage, current, phase, spectral decomposition, photon amplitude. A symbol is an individual element of a character. The range of all measurements corresponding to the actual situation is typically a coded symbol. The most commonly used character system is the {0,1} set, which is a binary symbol set. Binary systems exist that utilize all of the above schemes. Other commonly used characters include three-symbol characters, for example, 丨 0,1,2,}, multiple binary characters, for example, {〇〇, 01,10,11}, etc. β and other characters. A wire can be used to make For example, such as a metal wire (for example, in an integrated circuit or on a circuit board), an optical fiber, or a microwave channel (sometimes referred to as a micro-channel) ° wiring harness: a wiring harness system A set of one or more wires. Busbar: Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A busbar is a wiring harness with a busbar agreement. The busbar agreement specifies the communication between the circuits connected by the busbar. A busbar will typically consist of wiring harnesses between components, and one or more of the wiring harnesses between components will determine which components are connected and which receive and determine the wiring harnesses between the other one or more components. Those are teleportation. Floating point: Floating point notation includes a set of states representing a number of entities. These status sets include a subset of the positive and negative signs, false numbers, and indices defined by the definition __12 This paper size applies to the Chinese National Standard (CNS) Α4 specification (210 × 297 public ty printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives) 484110 V. Description of the invention (⑼). Such a floating-point representation includes not only binary systems but also but not limited to these: IEEE (Institute of Electrical and Electronics Engineers) standard floating-point and includes but is not limited to these: References to this specification The floating-point representation of the other special purpose in question. A floating-point representation includes not only the above-mentioned notation and therefore has two subsets, each of which, as described above, includes a positive sign, a false number, and an exponent. The notation system uses numbers to represent separated data. A floating-point representation also includes non-binary systems, where false numbers and exponents are about the power of a number other than 2. Programmable finite state machine: Programmable finite state machine A register including a state register and possibly one or more additional registers in which state conditions, data, etc. exist, In addition, through a mechanism, the status register, additional registers, and external inputs are generated for the status register and possibly additional registers under a single instruction multiple data path (SIMD): A single-instruction, multiple-data-path architecture executes the same instruction on more than one data path during the same instruction execution cycle. A typical extension of this basic idea is to incorporate "status flag bits" for each data path. These flags The standard determines whether a particular data path can or cannot execute some or all of the shared instructions. When multiple data streams need to be processed the same, the single instruction multiple data path (SIMD) architecture is optimal. These data streams will be available due to internal synchronization. It often has the advantage of simplifying communication control. However, when the data processing between data paths becomes different, the single instruction multiple data path (SIMD) architecture will become ______13 This paper standard applies Chinese National Standard (CNS) Α4 specification (210 × : 297 mm) (Please read the precautions on the back before filling out this page), -port 484110 V. The description of the invention (fl) is invalid The single instruction multiple data path (S I MD) architecture requires a relatively small instruction processing burden because only one instruction processing organization is shared by these data paths. The instruction processing organization has an instruction fetching organization. The data path Groups typically require only one instruction memory. Multiple instruction multiple data path (MIMD): A multiple instruction multiple data path architecture executes different instructions on different data units. The main advantage of this processing method is flexibility. Any data The processing unit can execute its own instructions, which has nothing to do with other data processing units. However, this flexible approach increases costs. In particular, each data processing unit must have its own instruction fetching, decoding, and sequencing mechanism. This instruction The retrieval mechanism often has at least one small memory located in the data processor. This area of memory is usually a cache memory. (Ultra) long instruction character processors (VLIW and LIW respectively): Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) A framework whereby a single instruction processing mechanism includes a program counter capable of common operations, such as branching by condition codes, and multiple instruction fields individually control these data path units. In these architectures, the structure or function of the data path units is often different. Array processor: An array processor refers to a long instruction word processor (LIW) or a very long instruction word processor (VLIW) instruction processing architecture. It has multiple data path units and is arranged into one or more data path sets. ◊In the embodiment of the present invention, as will be explained, these data path sets can be received and accepted at _14_ This paper size is applicable to China National Standard (CNS) A4 specifications (210X297 mm) Employees ’Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Print Λ7 —---------— —_ B7 V. Description of the Invention (fL) — — f operates on operands, where the common operands pass through a common arithmetic unit with a transmission unit. Row receiving; each data path receives one or more additional operands from a memory; each data path set includes an instruction memory processing instruction field that controls the operation of elements controlled by the program; each data path includes a Or multiple multipliers, accumulators (MACs); and each multiplier / accumulator (MA C) handles many accumulation registers. Multiplier / accumulator: A multiplier / accumulator is an arithmetic circuit that simultaneously performs the product of two operands and adds (or subtracts) one or more of the other operands. Fast Fourier Transform (F F T): A fast Fourier transform is a fairly good algorithm for performing many important operations on the frequency spectrum of a signal. See references [1 1], [1 1], and [1 5] for more details on the topics discussed. Vector processor: A vector processor is a framework designed for computing vector data. A typical'-vector processor is heavily pipelined. There is a large amount of literature dedicated to investigating vector processing, see references [4 6]-[5 3]. Appendix B, "Vector Processing" in reference [30] provides a description of the specific embodiment. The present invention provides a low-cost and effective basic circuit 'this circuit encapsulates memory, logic unit' arithmetic unit And special circuits and controls _______ This paper size applies to China National Standard (CNS) A4 specifications (210X 297 mm) (Please read the precautions on the back before filling this page) Order 484110

Printed by the Central Government Bureau of the Ministry of Economic Affairs of the People's Republic of China on consumer cooperation. 5. Description of the Invention (〇) The unit is particularly suitable for supporting multiple algorithms, especially for video frame drawing. Duplicating this basic circuit increases computing capacity and creates the ability to support very high performance requirements. The difference between high performance is usually the same between multidimensional signal processing and high performance frame drawing. When referring to these figures, there are special notes describing the differences in application of the invention. FIG. 1 is a block diagram of a basic circuit 1 according to an embodiment of the present invention. In the basic circuit 1, one or more controllers 2 serve as external area memories to provide access to an area external memory (shown in the later figure) associated with the basic circuit 1. Here, The external memory of a region is preferably 100 million bytes or more of memory (see ΤΥΥ story, reference [1]), for example, one billion bytes of memory. A main memory interface and controller (MM IC) 6, also known as a "large-memory wide interface circuit" 6, controls the data flow between the (and other) external area memory interface 2 and various other components, The information includes instructions. The main memory interface and controller (MM I C) 6 also controls access to an internal area memory 4. The basic circuit 1 also includes a general external bus interface (G Ε Β I) 7, an embedded microprocessor subsystem 8, a digital signal processor (DSP) (array processor) 9, and adjacent circuit communication. Port 10, special purpose circuit 1 1 (for example, special frame generator circuit, content addressable memory (CAM), bit code parser, etc.), and wiring harness 3, 5, 12, 13, 14, 15, 16, and 7 'These interconnects interconnect these circuits as shown in Figure 1. The overall external bus interface (G Ε Β I) 7 is provided to the outer ring-16 paper sizes apply Chinese National Standard (CNS) a4 specifications (210X 297 mm) (Please read the precautions on the back before filling this page ) -Port 484110 Λ7 V. Description of the invention (4) (Please read the notes on the back before filling this page). The external bus may be a standard computer bus such as the well-known Peripheral Component Interconnect (PCI), Graphics Acceleration Port (AGP), Universal Serial Bus (USB), Institute of Electrical and Electronics Engineers (IEEE) 1394 (Previously, Firewire) 'or Fibre Channel; or a special purpose bus used to support communication between an external controller, a host, and various entities of the invention. The embedded microprocessor subsystem 8 controls the operation of the basic circuit 1 but does not perform calculations on a digital signal processor (array processor) 9 or a special purpose circuit 11. The microprocessor subsystem 8 is discussed in more detail below. The digital signal processor (array processor) 9 performs floating-point calculations. In one embodiment of the present invention, the digital signal processor (array processor) 9. is shown and discussed in US Patent Application No. 60 / 050,396, filed on June 20, 1997. Yes, the contents of the patent number are incorporated herein by reference. The Digital Signal Processor (Array Processor) 9 Series will be discussed in more detail below. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The (and other) adjacent circuit communication port 10 provides communication between the basic circuit 1 and other entities in the system. In a system application in which the basic circuit 1 is used as a real system, these ports 10 are unnecessary. There is an exception to the previous sentence in a specific embodiment. 'Some of the ports 10 provide communication with other components (not shown). These components are not the entities of the basic circuit 1 but are very convenient to communicate with the entities of the basic circuit 1 or via The entities of the basic circuit 1 are traded together. Applications with multiple entities of basic circuit 1 usually require high speed __17______ The clever scale is applicable to the Zhongguanjia Standard (CNS) A4 specification (210X297 male feet) " ^ 484110

Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. The description of the invention (β) is executed, and the entities in the basic circuit 1 communicate at the same time. By providing the (etc.) communication (10), the basic circuit (1) in the overall external bus interface (GEBI) (7) will reduce possible congestion (in a specific embodiment, the (etc.) communication port (10) Dedicated communication is provided between exactly two entities; therefore, the protocol used on each port may be simpler than, for example, the bus protocol used in the external bus interface 7. Usually the 'standard method is used to communicate between entities. For example, various communication schemes based on messaging protocols can be used ', and there is a lot of literature on this technology. Similarly, any of several "flag" systems or "handshake" systems can be used to provide the ability to synchronize and control simultaneous sequential processing (c SP) operations between different entities. The special purpose circuit 11 exists in various embodiments as a way to provide increased efficiency. In other words, it is necessary for a computationally complex or time-consuming operation system. Examples of such circuits include, but are not limited to only these: one frame The generator is used to accelerate the operation of the Z-axis buffer, the triangle ocher “B it B 1 ts” and the surface texture; a content-addressable memory (C AM) is used to accelerate the graphic matching, for example, by shredding Geometric compression or conversion of a compressed symbol into a standard disposal tag into a hash table; and a one-byte parser that decodes commands and information for highly compressed communication schemes such as M PEG (animation expert group) Headers and languages such as JaVaTM, which are trademarks of a Su η microsystem. The internal memory bank 4 includes one or more random access memory (RAM) array banks. In the embodiment of the present invention, these memory systems are practical dynamic random access memory (DRAM). However, other types of memory Billion body __ —_____ 18 _______ This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

484110 Λ7 B7 V. Description of the invention (J) can also be used. In a preferred embodiment, it is provided that the total memory is 1 to 32 2 megabytes (MB) to form a wide configuration. It is expected to reach a width of 10 24 bits (1 K bits). Widths greater than 64 bits are considered "wide." The following memories include better configurations but are not limited to these: 32KX64, χ128, x256, X512 and x1K bits; 64KX64, X128, X256, X512 and X1K bits; 128KX64, xl28, X256 bits , X512 and X1K bits; 256KX64, xl28, x256, x512 and X1K bits; etc. It should be noted that a configuration that provides access to data lengths other than the power of 2 such as 7 2 can have many advantages ◊These configurations support error detection and correction schemes implemented by standard logic within the main memory interface and controller (MM IC) 6. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The main memory interface and controller (MM I C) 6 is a digital logic circuit that supports some functions. If the internal memory bank 4 is a dynamic random access memory or needs to be updated like a dynamic random access memory, the main memory interface and the controller (MM IC) 6 automatically updates the internal random access memory bank 4. The main memory interface and controller (MM IC) 6 allows and controls access to the internal random access memory bank 4 for the overall external bus interface (GEBI) 7. Embedded microprocessor 8, digital — _______19 paper size Applicable to Chinese National Standard (CNS) A4 specification (2ι〇 × 297 mm) 48411 ° κι

Jade, description of the invention (q) Signal processor 9 (array processor), and the physical and special-purpose circuit 11 1 that can communicate via adjacent circuits 读取 1 0 read and write. The main memory interface and controller (MM IC) 6 also allows and controls the overall external bus interface (GEBI) 7, embedded microprocessor 8, digital signal processor 9 (array processor), and possibly via The entity of the adjacent circuit communication 10 and the special-purpose circuit 11 access the external port area memory interface 2. In a preferred embodiment of the present invention, the main memory interface and controller (MM I c) 6 includes a finite state machine (f SM) received from the modules 7, 8, 9, 10, and 11 For the request of data and / or instructions in the external area memory to control the data and instruction flow, the main memory interface and controller (MM I c) 6 is based on the decisions encoded in the finite state machine (FS Μ). Algorithm to satisfy the above request. The control of the data / instruction flow by a finite state machine (F SM) is well known. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the precautions on the back before filling this page)

1T In a preferred embodiment of the present invention, separate instructions and data streams are provided for each unit of the embedded microprocessor 8, digital signal processor 9 (array processor), and special purpose circuit 11. These instructions and data streams typically reside on external area memory during program initialization and operation 'after being loaded from the General External Bus Interface (GEBI) 7'. These instructions and data streams are typically generated based on one or more of the known compiler techniques and may incorporate some handshake protocols according to known methods.

In addition to the main memory interface and the controller (MM IC) 6, there is also an embedded microprocessor 8 and an overall external bus interface (GEBI) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm Ministry of Economic Affairs) Printed by the Central Procurement Bureau for employee cooperation 484110 kl B7 V. Description of the invention () 7 Provides direction of control of data / instruction flow in a known technology. For example, the microprocessor 8 may occupy a limited amount first Control of the state machine (F SM), for example, error control, initialization, and capture of bus error transactions on the overall external bus interface (GEBI) 7. Controller 2 (or E LM I) of the external area memory interface 2) Access to one or more types of external integrated circuit (IC) memory provides external timing and interface protocol support. For example, the (and other) external area memory interface (E LM I) 2 provides access to Read and write random access memory, and read invariant memory. If some or all of the external memory system is about dynamic random access memory (see Chapters 6 and 5 in Reference [5 4]) Chapter 7), the (and other) external area memory interface (E LM I) 2 supports automatic memory update. Optimally, the (and other) external area memory interface (E LM I) 2 is during the update Provide a queue of access requests. The external memory interface (E LM I) 2 can also optionally provide a queue of access requests during write, erase, and other possible slow operations. In these embodiments, at least some of the external memory systems are programmable and immutable (see chapters 10, 11 and 12 in reference [5 4]), the (etc.) external area memory The body interface (E LM I) 2 provides the writing of specific characters and the proportional erasure of the character blocks. Optionally, the (or other) external area memory interface (EL M I) 2 can provide the Additional functions that are well known in the art, such as suspending the erasing of invariable memory operations, are provided to facilitate the execution of certain applications. Although not specifically shown in FIG. 1, 'this in another embodiment_21 This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 male) ) (Please read the notes on the back before filling out this page), 1T 48411 ° Printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, Hi B7 7. Invention Description (d) d This circuit 1 includes one or more analog interface components, Such as analog-to-digital (A / D) converters, and digital-to-analog (D / A) converters, voltage-controlled oscillators (V 0 C 〇), etc., and their corresponding wiring harnesses. In another embodiment The additional second support circuits included, but are not limited to these: internal clock multiplier, phase locked loop (PLL), clock distribution network, built-in self-test (Bΐ $ τ) circuit, boundary trace path, etc. These circuits are well known in the related art. The basic circuit 1 has an optimized design that provides a high-performance computing engine for frame rendering and similar tasks in a variety of ways. Importantly, the embedded microprocessor 8, digital signal processor 9 (array processor), and special purpose circuit 11 are provided with circuit resources to process their individual instructions and data at the same time. With instructions while suspended. This efficiency arises from, for example, overall design and individual module design, as described above and below. For example, the wiring harness 1 3 provides a dedicated path for interaction between the overall external bus 7 and the embedded microprocessor 8, such as control, to reduce the main bus interface (main memory). The physical interface is related to the bandwidth of the controller (mm Ic) 6, and the wiring harness 12, 14, 15, 16, 17). The wiring harness 13 is not related to the main traffic transactions on the main bus interface. In this way, It can save the bandwidth of the main bus interface. In a preferred embodiment, the basic circuit 1 is implemented as an integrated circuit (IC). Importantly, the basic circuit 1 can be implemented with less integrated circuit surface area due to its design. And this structure is simple _____22_ This & Zhang scale is applicable to China ^^ ((: milk 7 ^ 1 grid (21 () \ 297mm) ~ '" (Please read the precautions on the back before filling this page ) Clothing

， 1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. The description of the invention (/) is flexible enough to enable the compiler to efficiently compile its computing unit, especially the microprocessor and the array processor. FIG. 2 is a block diagram of the array processor 9 of FIG. 1 according to an embodiment of the present invention. As will be discussed in detail below, the array processor 9 is capable of performing conventional techniques using vector processing techniques and cannot efficiently perform parallel Calculations, as discussed in the cited references. These calculations include, for example, the need to calculate several shorter vectors. For example, calculate a complex unitary function, such as X = (az + b) / (cz + d), where a'b, c, d, and z are all complex floating-point numbers. As everyone knows, these calculations and Similar calculations are common in frame rendering. To calculate these functions, aO, bO, cO'd〇 'z 〇 and X 〇 are defined as the real part and relative, a 1, b 1,. C 1, d 1, z 1 and x 1 are It is defined as the imaginary part. Before calculation, before entering a floating-point division circuit, two-pass multiplication and accumulation are performed. In the first pass, the calculation is as follows:

AO = a〇 氺 z〇 — a 1 氺 z 1 + bO A1 two a〇 氺 z 1 + a l * z〇 + bl

B〇 two c〇 氺 z〇 — c 1 氺 z 1 + dO

Bl = c〇 氺 z 1 + c 1 氺 zO + dl In the second pass, the results of B 0 and B 1 are sent back to the multiplier / accumulator (discussed later) as a shared operand: C〇- A〇 * B〇-Al * Bl C1 = A1 氺 B0 + A0 * B1 D = B〇 氺 B0 + B1 氺 ___23__ This paper size applies to Chinese national standards (CNS> A4 size (210X297 mm) (Please read first (Notes on the back, please fill out this page) -1¾.

, 1T Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 484110 V. Description of the Invention () Finally, the division is performed:

X 0 = C 0 / DX 1 = C 1 / D According to the embodiment of FIG. 2, an array processor interface circuit (APIC) 9 6 5 controls commands issued from the main memory interface and the controller (MM IC) 6 Request and receive data and send data to the main memory interface and controller (MM IC) 6. In this embodiment, the array processor 9 has a single group 9 7 0 including multiple data path processing units 9 0 0. These data path processing units 900 are also referred to as data paths 900. The group 9 7 0 forms an arithmetic processing unit (A P U) 9 7 0. In the arithmetic processing unit 970, an internal floating-point representation system is used. This internal floating-point representation may be the same or may be different from the floating-point representation used externally. Generally, the arithmetic processing unit 970 is suitable for predicting at least one standard external representation, for example, the International Institute of Electrical and Electronics Engineers (IEEE) floating point notation. In a preferred embodiment, the floating-point representation used is a simplified representation. This representation does not include, for example, the standard International Institute of Electrical and Electronics Engineers (IEEE) floating-point representation exception. Using this simplified notation can have higher internal efficiency, for example, by considering circuit size, by avoiding complex exceptions. Using a simplified notation system is indeed possible, because exceptions typically do not have much to do with frame rendering and digital signal processor applications. The arithmetic processing unit 9 7 0 includes a shared arithmetic element circuit (s 〇 ___24 ______ This paper size applies the Chinese National Standard (CNS) A4 specification (21〇'297297 嫠) (Please read the precautions on the back before filling (This page)

484110 Λ7 B7 V. Description of the invention (〆) C) 9 1 0. This shared operand circuit is used as a multiplier input circuit. Optionally, the shared arithmetic element circuit 9 10 includes a random access memory circuit with address control to determine whether the random access memory can be used as an arithmetic cache memory or a first-in-first-out memory. Out (FIF 0) queue. The first sub-circuit (not shown in the figure) of the shared arithmetic element circuit 9 1 0 includes a plurality of input registers for receiving and capturing the state of the wiring harness 9 0 2 ° The shared arithmetic circuit 9 1 0 A second sub-circuit (not shown) is coupled to the register in the first sub-circuit. Each sub-circuit package includes each integer arithmetic logic unit (ALU) (not shown). The second sub-circuit performs fixed-point addition / subtraction operations on the status field of the wiring harness 902 selected by these registers (in Arithmetic Logic Unit). The second sub-circuit also converts the fixed-point result obtained by the addition / subtraction operation or the fixed-point result of the field selected by the input register into an internal floating-point representation according to a known conversion algorithm. Therefore, the second sub-circuit system includes a floating-point conversion unit (not shown). Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page) The arithmetic processing unit 9 7 0 also includes two or more multipliers / accumulators (MA C) 9 0 0 The path processing unit 9 0 0 ◊ multiplier / accumulator (MA C) is well known in the related art. Each multiplier / accumulator (MA C) 9 0 0 is coupled to the wiring harness 9 0 6 to receive a shared operand from the shared operand circuit 9 10. Each multiplier / accumulator (MA C) 9 0 0 is also coupled to a corresponding area data storage 9 2 0. Generally, the number of area data memory circuits 9 2 0 is as many as the number of multiplier / accumulator (MAC) 900. ________25__ This paper size applies to China National Standard (CMS) A4 specification (210X 297 mm) 484110

Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) During the operation, each multiplier / accumulator (MA C) 9 0 〇 receives 3 numbers in a certain number format: X, Y and Z , Where X is the shared operand received from wiring harness 9 06, and γ and z are received from the area data storage 9 2 0 via wiring harness 9 0 9. Each multiplier / accumulator (MA C) 9 0 0 has two or more registers', preferably at least four registers. Each multiplier / accumulator (MA C) 9 0 〇 can perform a multiplication and an addition / subtraction operation in each clock cycle to thereby take from (possibly) the X, Y, and Z 値 produces XY + Z or XY — Z. Each multiplier / accumulator (MA C) 9 0 0 stores the generated result in one of the registers it owns according to the situation ^ The arithmetic processing unit 9 7 0 further steps include a shared output And feedback interface (S 0 FI) 9 4 0. The shared output and feedback interface (S 0 FI) 9 4 0 includes a floating-point conversion unit (not shown). This floating-point conversion unit is suitable for internally digitizing a wiring harness (9 0 7) using standard technology. The format is converted to the necessary floating point (for example, the Institute of Electrical and Electronics Engineers (IEEE) floating point) or externally required fixed-point representation (of course, in those embodiments where the internal floating-point representation is equal to the external representation) It is not necessary to perform this special conversion. The shared output and feedback interface (S 0 F I) 9 4 0 controls a wide bus 9 0 1 to transfer the results converted above to the array processor interface circuit 9 6 5. In a special embodiment, the shared output and feedback interface (S 0 F I) 9 40 must also temporarily store such results before transmission. The data memory 9 2 0 has a corresponding address generator 26. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling in this page) sip 84 4 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 __B? 5. The description of the invention (呻) (for example, in module 950 discussed below) is used to provide an address for easy access. These addresses are used to extract the Y and Z operands, which may be the same or different. By supporting the generation of different addresses, it provides an advantage in many application requirements, such as fast Fourier transform (FFT). The arithmetic processing unit 9 7 0 includes an overall control, synchronization circuit, and instruction storage unit (CSIS) 9 5 0. The overall control, synchronization circuit, and instruction storage unit (C S I S) 950 performs arithmetic processing unit 970 control and synchronization of various modules and includes instruction storage. The architecture of the arithmetic processing unit 970 is shown in Figure 2 and will be discussed here. The overall control, synchronization circuit, and instruction memory (CSSI) 950 has a suitable structure for performing its work. Specifically, the overall control, synchronization circuit, and instruction storage unit (CSIS) 9 5 1 includes (not shown in FIG. 2) a state register, a program counter, two or more loop counters, and Multiplier / accumulator (MAC) 9 0 0 At least one index register, an instruction register, and an instruction memory of each Y and Z operand region memory 9 2 0, all of these components are Everyone familiar with this technology is familiar. The instruction characters have different fields for each input, output allocation, multiplier / accumulator (MAC) 900.

The state register selectively retains at least a large number of line states. These line states include at least the status condition bits of the echo counter, the zero detection signal from the integer arithmetic logic unit of each shared operand circuit 910, and the shared output and feedback interface of each arithmetic processing unit 9 7 0 (s 0 F _____ 27 __ ^ ____ This paper size applies Chinese National Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page)

484110 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 V. Conditional Bits of the floating-point conversion unit of the invention description (y <) 1) 9 4 0. The overall control, synchronization circuit, and instruction storage unit (cs 1 s) are suitable for requesting instructions (via the main memory interface and controller (MM 1 C) 6 and array processor interface circuit 9 6 5) and temporarily storing these instructions To its instruction memory. The wiring harness 9 0 3 provides input to the area data storage 9 2 0. The wiring harness 903 includes at least: an address of a component memory for each area data memory 920, and a read / write control and page interleaving control signal for each area data memory 920. Each arithmetic processing unit 9 7 0 operates on the form of two vectors' as in the form of "vector plus vector" or operates on the form of a vector and a scalar, such as "scalar multiplied by a vector Element ". The arithmetic processing unit 970 has a lot of uses because an input operand system is shared between multiple multipliers / accumulators (MA C) and because of an area memory circuit (920) or another The state of the register of a multiplier / accumulator (MAC) provides two other operands. According to the present invention, the array processor 9 can calculate the efficiency that cannot be achieved using other types of processors (for example, vector processors). Calculations performed. For example, in the calculation of several discrete wavelet transform filters (DWT F), it is often necessary to share several different scalars across several subcomponents of a vector. Usually vector processors need as many cycles as the number of scalars being shared to perform this work. In these discrete wavelet transform filters, each even-numbered input will affect all filter outputs, and these odd-numbered inputs only affect __— _28___ This paper standard applies to China National Standard (CNS) A4 specification (21〇 × 297 Mm) (Please read the notes on the back before filling this page)

、 1T 484110 Printed by the Consumers' Cooperative of the Central Bureau of Economic Standards B7--1--*--------------------------------------------------------------------------------(5) Invention Description (4) half filter Output. Processing four inputs in this way has the disadvantage that odd-numbered items cannot be processed simultaneously using the vector processor method. However, in the array processor 9, these problems are minimized, for example, because the array processor can send two (or more) odd-numbered scalar elements to different components of a vector. (FFT) provides sum and difference to different components of a vector. The present invention can obtain results in one cycle by providing these individual components to the vector in parallel instead of requiring two cycles for each pair of elements as the vector processor. FIG. 3 is a block diagram of the array processor 9 of FIG. 1 according to another embodiment of the present invention. As shown in FIG. 3, the array processor 9 has two arithmetic processing units 9 7 0. This architecture provides parallel operations for application addition. 'For other calculations performed by other modules (eg, embedded microprocessors) Floating-point calculations are expected to be particularly useful. In another embodiment, the number of arithmetic processing units 970 in the basic circuit 1 can be increased to two or more. The array processor 9 according to FIG. 3 is used in a preferred embodiment (refer to FIG. 1). The basic circuit 1 efficiently includes the array processor 9 according to FIG. General external bus interface (GEBI) 7. The external area memory interface (E LM I) 2. Embedded microprocessor subsystem 8 and adjacent circuit communication port 1 0 'However, no special purpose circuit 1 is attached 1. There is no memory bank 4. Therefore, 'a main interface and control M IC) 6 It omits the main memory interface and the memory controller of the controller (MM IC) 6. FIG. 4 is a block diagram of the embedded microprocessor subsystem 8 of FIG. 1. The size of this paper is applicable to China National Standard (CNS) Α4 specification (21〇297297χ (please read the precautions on the back before filling this page) Order 484110 Λ7 Β7 V. Description of Invention (V) The related art is well known, as shown in FIG. 4 'The embedded microprocessor subsystem 8 includes a microprocessor 800. The microprocessor 800 can be used as a one-digit group code machine, such as A J ava or MPEG-4 engine 'a Programmable Finite State Machine (PFS M), or a reduced instruction set computer engine, preferably a 16-bit instruction set. The reduced instruction set computer has a 32-bit data path. , Such as A RM 7 T DM I (see reference [5 6]) or M IPS 16 (see reference [5 5]). The embedded microprocessor subsystem 8 also includes an optional area cache memory The body 8 1 0 is preferably a 2 to 4 branch interleave and has at least 64 pages and a total memory of at least 1 K characters. Typically, the cache memory 8 1 0 is arranged to have, For example, 32-bit characters. The cache memory 8 1 0 may include two parts of cache memory. One is the instruction cache and the other is the data cache. The embedded microprocessor subsystem 8 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs also includes additional optional area memory, such as a random memory. Take the memory 8 2 0 or a read-only memory 8 3 0. According to the related technology, the read-only memory 8 3 0 may include, for example, the microprocessor subsystem 8 and / Or the initial information of the basic circuit 1. In a preferred embodiment, the (and other) microprocessor 800 provides two instruction sets: a length of 16 bits, which includes code generated by compiler technology The most commonly used instructions are 32 bits in length. Such a microprocessor is known from related technologies. The advantages of such a microprocessor are that most of the generated code will be 16 bits The format of this paper is in accordance with the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 484110 Printed by A7, Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of invention (>?). At each microprocessor 8 0 0 Medium, 2 each Or more instruction fetches can be provided to the next 1 to 3 instructions without relying on further instruction memory access. According to the basic circuit 1 and array processor 9 discussed in this paper, the architecture or type of the circuit is revealed to have many注意 Notable advantages ° One of the advantages is that the performance of such an algorithm on a printed circuit board of a similar size using a microprocessor or traditional digital signal processor is better than that of a circuit that performs a specific computationally heavy algorithm 1 has a very high efficiency. Generally, the basic circuit 1 has a lower demand in terms of circuit size than other mechanisms that can achieve the same result. Therefore, the basic circuit 1 is cheaper than other institutions in achieving the same result. One of the factors in the small circuit size requirements of the array processor 9 is that the division operation is not implemented directly, and it is indeed uncommon to design such a large number of frames of interest and digital signal processing algorithms. In the embodiment of the array processor 9, the multipliers / accumulators (MA C) are constructed to support only single-precision arithmetic, and are generally sufficient for most frame rendering and digital signal processor applications. The circuit size requirement of the array processor 9 is substantially further reduced. The architecture of the array processor 9 provides the "front end" of fixed-point addition / subtraction, followed by floating-point conversion (for example, in shared operand circuit 9 10), and then multiplication and accumulation (in the multiplier / accumulator ( MAC) 9 0 0). This "front-end" executable preliminary operation involves symmetric, asymmetric FIR ', and some low-cardinality fast Fourier transform (F F T) calculations. These i paper sizes are in accordance with the Chinese National Standard (CNS) A4 specifications (21〇 > < 297g ^) (Please read the precautions on the back before filling this page) Order-Quan-484110 Staff Consumption Cooperative printed M. 5. Description of the invention (1) The operation is very useful in specific digital signal processing applications. The data is usually received in a certain point form from the sampling circuit. Typically, this sampling circuit generates 8 to 16 bits. Yuanzhi fixed-point accuracy. Another advantage of the array processor 9 is the general phenomenon related to accumulated rounding errors. It is important that digital signal processor algorithms maintain the accuracy of the arithmetic results. To improve efficiency, many early digital signal processors used algorithms that performed fixed-point arithmetic. Such fixed-point arithmetic requires careful management of rounding errors to maintain accuracy. In comparison, the array processor 9 can efficiently perform floating-point calculations. Floating-point calculations have the advantage of providing a larger dynamic range, but they are easier to execute programmatically for results with the same accuracy. It is meaningful to analyze the performance of one specific, embodiment of the array processor 9. In the exemplary embodiment, the array processor 9 (according to FIG. 3) receives at least 1 2 from the main memory interface and the controller (MM I c) in its array processor interface circuit 9 6 5. 8 bits. The shared operand circuit 9 10 of each arithmetic processing unit 970 can receive at least 64 bits (preferably 128 bits) at the same time. The shared operand circuit 9 10 can decompose the received data into fixed 8-bit or 16-bit integer fields. The shared operand circuit 910 can perform addition or subtraction on data of up to 4 columns at the same time. The architecture of this exemplary embodiment can achieve considerably higher performance when calculating the base 4 fast Fourier transform (F F T) than other calculations. In the exemplary embodiment, the array processor subsystem 9 has an internal clock rate of ~ 200 million hertz (μηz). Subsequent lotus calculations (please read the precautions on the back before filling this page) ^^ clothing, and paper size ^^? TcNS) Α4 specifications (2 like 297 public funds) " " ~ 484110 Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the Ministry of Λ7 V. Invention description (P) can be executed in each clock cycle: four single-precision floating-point multiplications and four single-precision floating-point additions; an integer / fixed-point addition / Subtraction, integer / fixed-point to floating-point conversion; and floating-point to fixed-point conversion. In this exemplary embodiment, the area data storage 920 is a dual-branch cross, which can support the currently loaded data received through the main memory interface and the controller (MM IC) 6 to simultaneously extract Y and Z operand gives the corresponding multiplier / accumulator (MAC) 900 ^ In this exemplary embodiment, a communication scheme includes the overall external bus interface (GEBI) 7. The main memory interface and the controller (MM) IC) 6, embedded microprocessor subsystem 8, external area memory interface (ELM I) 2 and the array processor interface circuit 9 6 5 of the array processor 9 in the implementation of standard technology, allowing the Array processor 9. Can maintain full operation in 7 5% of time and execute foreseen frame drawing and digital signal processor applications. The assumption of this performance is based on the data location of basic circuit 1 and its internal array processor 9. It is reasonable. From the performance obtained by this exemplary embodiment, the above assumptions will be one to three billion floating-point operations per second for many digital signal processors and specific frame rendering algorithms (per billion executions per second) (Floating-point arithmetic) ° Assuming that the basic circuit 1 is implemented in a standard integrated circuit (I c) package such as a TQ F RP (thin square flat package) with 176 pins, then each integrated circuit will take up Approximately one square inch of printed circuit board area, so 'the embodiments of the present invention can be implemented as a peripheral component interconnect (PCI) bus card capable of accommodating up to 32 such integrated circuits, -_______ 33 copies Paper size is suitable for financial affairs ^^ — CNS) Α4 specification (210 ^^ " --- (Please read the notes on the back before filling out this page) Order 484110 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 5. [Explanation] The invention takes about 16 times the performance of a video technology company workstation (see τ 〇y story 'Reference [1]) in terms of delivery speed and is far lower than the cost of the video technology company workstation. The Department of Invention is particularly applicable Use applications involving java (see references [6 4] to [6 5]) and parent interactive audiovisual signal languages such as μ pe G-4 (see references [57] to [63]). The PEG -4 The standard action system develops an environment of various algorithms to enable execution on the hardware of the model used by the customer .: ί a ν a is essentially machine-independent in its definition and possesses semantic capabilities. Expensive algorithms: The present invention provides high-performance digital signal processing to support network equipment. Supplementary description of certain embodiments: .Some embodiments of the present invention can use the simplified form of integrated circuits to supplement the description here. , Which includes: a large memory wide interface circuit, wherein the large memory may be disposed in the integrated circuit or outside the integrated circuit, the large memory wide interface circuit is provided by including a wiring harness D 〇The bus B 〇 is connected to the large memory, wherein: the bidirectional transceiver in the large memory wide interface circuit is connected to the wiring harness D 〇 of the bus B 〇, providing a large Data transfer between the memory wide interface circuit and the large memory; one or more data processing circuits include: a programmable finite state machine (PFS M) or a microprocessor; and a data processor interface circuit connected to The large-memory wide interface 34-inch scale is applicable to China National Standard (CNS) Α4 specifications (210X 297 male thin 1 " '(Please read the precautions on the back before filling this page)

1T 484110 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 V. Description of the Invention (β) The data processor circuit is connected to a large-memory wide interface circuit through a bus B1. It includes: a two-way transceiver system connected to the wiring harness branch line D 1 of the busbar B 1; and the area memory circuit can provide a response and / or sense to the wiring harness branch line D 1 of the bus line B 1 in the area memory circuit. Measured state storage: The state information is retained after the state may no longer be issued, so the state of the wiring harness branch line D1 of the busbar B1 can be read out; among them, the signal status of the wiring harness D1 of the busbar B1 includes Some or all of the signal states of D 0 transmitted in a forward or reverse direction on time, that is, an organization that can transmit data to or receive data from the wiring harness D 0 of the bus B 0; . One or more array processors, each array processor includes an array processor interface circuit connected to the large memory wide interface circuit, a shared operand input circuit, multiple multipliers / tires An adder, a shared multiplier output circuit, and an instruction decoder circuit, wherein: the array processor interface circuit is connected to a large memory; the wide interface includes a bus B 2; the array processor interface circuit and the large memory The wide interface circuit includes: a bidirectional transceiver is connected to the wiring harness branch D 2 of the bus B 2; and the area memory circuit can provide the wiring harness branch D 2 of the bus B 2 in the region memory circuit. The issued and / or sensed status is stored in $, and the status information is retained after the status may no longer be issued. 'So I can buy 35 ^^ 5 ^ using Chinese National Standard (〇 奶) 8 4 specifications (210' / 297 mm) (Please read the precautions on the back before filling this page). Vu Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 484110 Λ7 __B7 V. Description of the invention (4) The wiring harness of the bus B 2 The state of the line d 2; the signal state of the wiring harness D 2 of the bus B 2 includes some or all of the signal states of D 0 transmitted in a forward or reverse direction on time, that is, data can be transmitted to the bus B 0 Wiring harness D 〇 or from the sink A mechanism for receiving data in the wiring harness D 0 of row B 0; the shared operand input circuit is connected to the array processor interface circuit through a bus B 3; furthermore, the shared operand input circuit is connected to the array The shared multiplier output circuit and the regional data memory circuits are connected to each multiplier / accumulator via a bus B 4, wherein: the shared operand input circuit receives wiring Some or all of the status information; each multiplier / accumulator contains a multiplication and addition mechanism, plus two mutually independent addressable random access memories, where: the multiplication and the addition mechanism share a multiplier input and Provide another two inputs from two mutually independent addressable random access memories, these two mutually independent addressable random access memories may be read-only memory or not read-only memory; each random access The memory address and the control wiring harness are part of the control wiring harness (CWB); the multiplication and addition mechanism has an output driver connected to a wiring harness M0 This wiring harness M0 is shared by the multiplier / accumulator and the output circuit of the multiplier; and each output driver is controlled by the wiring harness of the control wiring harness (CWB). 36 This paper size applies to the Chinese national standard (〇 奶). 4 specifications (210, / 297 Gongchu) (Please read the precautions on the back before filling out this page), 1 · · 484110

V. Description of the invention (4) Printed branch control by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs; and the output circuit of the multiplier includes a wiring harness interface, a multiplier output memory circuit, and a multiplier output interface, where: Μ 〇The wiring harness interface includes an input circuit connected to the μ 〇 wiring harness; the multiplier output circuit is connected to the input circuit of the 〇 wiring harness interface circuit, and in this way provides the storage circuit in the memory circuit. Data; and the memory output circuit is connected to the multiplier output interface so that the state of the memory circuit can be output from the memory output interface to a wiring harness branch line or the entire busbar B3. In an embodiment, the bus bar B 〇 further includes a wiring harness branch line d 〇 A and D 〇C, wherein: an output driver in the large-memory wide interface circuit is connected to the wiring harness D 〇A of the bus B 〇 , Can provide the address signal required to access the large memory data: and the output driver in the large memory wide interface circuit to connect the wiring harness DO C of the bus B, can provide access to the large memory data Required control signals. In another alternative embodiment, the bus bar B 0 further includes a wiring harness branch line D oF, wherein: the input driver in the large-memory wide interface circuit is connected to the wiring harness D 0 of the pupil bus bar B 0 F, can provide feedback signals used to communicate the status of large memory data access. ____ 37 ----- This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page)

Printed by the Central Consumers Association of the Ministry of Economic Affairs, Consumer Cooperatives 484110 V. Description of the Invention (β) In one embodiment, at least one of the communication interfaces is external to an external circuit to provide a communication interface to a bus, which mentions The circuit works like the same bus master. In an embodiment, at least one of the communication interfaces is externally connected to an external circuit to provide a communication interface to a bus, and the circuits mentioned therein act as the same bus controller. Figures 5 to 12 illustrate the use of the device of the present invention to provide near linear accelerated video frame drawing work and other major parallel calculations. Since the degree of accumulation is progressing, the communication paths of the external memory interface are integrated into a shared external memory interface There are significant benefits. Each external memory interface can save a lot of product price by adding a lot of pins to each integrated circuit. This affects not only wafer size but also heat dissipation and power consumption. Sharing an external memory interface in this way can optimize communication bandwidth and save manufacturing costs. Figure 5 is a block diagram of an integrated circuit, which has two sets of basic circuit entities of Figure 1 and independent external memory. Body interface. Figure 6 is a block diagram of an integrated circuit, which has two sets of basic circuit entities of Figure 1 and shares an external memory interface, Figure 7 is a block diagram of an integrated circuit, which has four sets of basic Figure 1 The circuit entity does not have an independent external memory interface. FIG. 8 is a block diagram of an integrated circuit, which has four sets of basic circuit entities of FIG. 1 and shares an external memory interface. Fig. 9 is a block diagram of an integrated circuit, which has four sets of the basic circuit entities of Fig. 1 and shares two sets of external memory interfaces. This standard applies the Chinese National Standard YCNS) 8 4 specifications (21〇 < 297 Gongyi)-a -------- # 衣 ------, order ------ ^ (Please read the notes on the back before filling in this page) 484110 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Description of the invention (4) Figure 10 is a block diagram of an integrated circuit, which has four groups The basic circuit entity in Figure 1 does not have two sets of shared external memory interfaces and fully interconnected message ports. Figure 1 1 is a block diagram of an integrated circuit, which has sixteen sets of basic circuit entities of Figure 1 and has four sets of shared external memory interfaces. Figure 12 is a block diagram of an integrated circuit, which has ten There are six sets of basic circuit entities in Figure 1 and two sets of shared memory interfaces. Fig. 13 is a block diagram of a printed circuit board, showing the integration of the basic circuit entities of Fig. 1 with the memory modules corresponding to them on a circuit board. Fig. 14 is a block diagram of another printed circuit board, showing the integration of the basic circuit entities of Fig. 1 and their corresponding memory modules on a circuit board. References: 1: U b ois, J eff, "Rizhao Hollywood · 丄 丄 7 SPARC station shows" Toy Story ", the earliest full-length computer animated film" Sunwor Id 〇nline, January 1995, see http: // ww · sun · C 0 m / sunw 0 r 1 d 1 ine / s wo 1-1 1- 1995 / swo l-χ 1-pi xa r • htm 1. 2-Fuchs, Henry, USPTN 4, 9 5 0 '4 6 5 '"Graphics display system using pixel logic unit with enhanced logic", application was made on January 18, 1982, and was approved on May 20, 1986. 39 This paper size applies the Chinese National Standard (CNS) A4 specification ( 21 〇X 297 mm) (Please read the notes on the back before filling out this page), \ 一-口 484110 V. Description of the invention (β) 3-Andrews? David Η ·, et-al • USPTN 4,646,075, "Use "Systems and Methods in a Data Processing Pipeline", filed on November 3, 1983, and February 24, 1987 4 * Lit. t lefield, Richard, US PTN4,949,280, "Parallel Processor-Based Scanning Line Graphics System Architecture", filed on May 10, 1988, August 1990 Approved on April 4. 5. Hedley, David, et.al., U SPTN 4,953, 107, "Video Signal Processing", application was made on August 28, 1989, and approved on August 28, 1990. , 6-Westberg »Thomas jet * al •, USPTN 5, 101, 365," A device for expanding the window using Z-axis buffer memory ", application was made on November 7, 1990, and approved on March 31, 1992. 7 * Cawley, Robin, USPTN5, 1 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) 0 3, 2 1 7, "Electronic Image Processing", 1988 1 The application was filed on January 29, and approved on April 7, 1992. 8 * Liang, Bob, et .al ·, USPT N 5, 1 8 2, 7 9 7, "Multiprocessor graphics display system for displaying hierarchy File structure ", application was made on May 27, 1992, and was approved on January 26, 1993.

9 * S〇kai, T〇shi〇, et, al ·, U This paper size is applicable to the national standard of China (210-X297 mm)-484110 Λ7 B7 V. Description of the invention (/) SPTN5,594,844, "Use Ray tracing uses three-dimensional views divided by vowels and numerically uses target-based parameters. "19 Application was made on January 25, 1994, and was approved on January 14, 1997. 010, Uhl in, Keith, USPTN5, 6 3 Ο, Ο 4 3, "Apparatus and method for producing texture maps for animation of 3D image display", application was made on May 11, 1995, and was approved on May 13, 1997.

11-Oppenheim ^ Alan & Schaf e r, R ο n a 1 d, "Digital Signal Processing", 1975, Prentice Hall, Engle wood C 1 i f i s, N · J ·. .12-Oppenheim ^ Alan & Schafer, R na 1 d, "Discrete-Time Signal Processing", 1989, Prentice Hall, ISBN 0-11 3-2 1 6292-Central Bureau of Standards, Ministry of Economic Affairs Printed by an employee consumer cooperative (please read the notes on the back before filling this page) 13 ^ Barns ley ^ Michael & Hur d, Lyma η, Fragmented Geometric Image Compression, 193, AK Peters, Ltd., Wei Is ley, MA 0 2 1 8 1, ISBN 1 — 56881 — 000 — 8. 14 * Daubechies, Ingrid, Ten Lecture Notes on Wavelets, 1982, Society of Industrial and Applied Mathematics, ISBN 0—89871—274—2. _41_ This paper size applies to China National Standard (CNS) A4 (210X297 mm)

I Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Invention Description (β) 15.Kaiser, Gerald, Easy-to-understand Introduction to Wavelets, 1994, Birkhauser, Boston, ISBN 0 — 8176 — 3711 — 7. 16 · F i s hr, Yu v a 1 (e d ·), fractal geometric image compression, 1995 Springer — Ver 1 ag, New York, ISBN 0 — 3 87 — 94211 — 4. 17 * Mcgregor, D, R * et, al · "Faster Faster Compression of Fragmented Geometry", D r · D 〇bb £ s Journal, January 1996, page 34, etc. 1 8 ♦ L im, Jae, Two-Dimensional Signal and Image Processing, 1990, Prentice Hall, ISBN 0, -13-935322-4. 19.Glassner, Andrew, Principles of Digital Image Synthesis, Volumes 1 and 2, 1995, Morgan Kauffmann Press, Inc., ISBN 1 — 55860 — 276 — 3 ◊ 20 * Foley, James , Et * al ·, Computer Graphics: Principles and Implementation of C ++ Language, 196, 190, Addis on—Wesley Publishing Company, ISBN 0 — 201 — 8 4 840 — 6. 21.Watt, Alan, 3D Computer Graphics, Second Edition, 1993, Addison—Wesley Publishing Co., Ltd., International Standard Book No. 0 — 201 — 63186 — _42_ This paper size applies to China National Standard (CNS) A4 specifications ( 210X297 mm) (Please read the notes on the back before filling out this page) • Clothing ·

1T 484110 Λ7 B7 V. Description of the invention (w) 5. 22 * Watt 'Alan & Watt, Mark, Advanced Animation and Drawing Technology, 1992, ACM Press, ISBN 0—2 0 1 23 * Prusinki ewicz? Prezmy slaw & Lindenayer, Arist · id, et · a 1 · , Algorithms for Plants' Beautiful Colors, 1990, Springer — Ver 1 ag New York, Inc., International Standard Book Number 0 — 387 — 97297 — 8. 24 · Iwatz, Eiji, et-al *, "a 2 · 2 GOPS video digital signal processor 2—reduced instruction set computer multiple instruction multiple data path, 6-PE single instruction multiple data path architecture for real-time MPEG 2 video encoding / Decoding ", 1997 International Society of Electrical and Electronics Engineers (I Ε Ε Ε) International Solid-State Circuits Symposium, 1977 I Ε Ε Ε, International Standard Book Number 0_ 7 8 0 3 — 3 721 — 2, pp. 258 — 259. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page) 25 * Silverbrook, Kia, USPT N5, 590, 252, "Video Processor System and Audio Processor System", 1 The application was submitted on April 28, 1993, and was approved on February 31, 1996. 26 * Uhlin, Keith, USPTN5, 6 3 0 '0 4 3, "Apparatus and method for producing texture maps for animation of three-dimensional image display", application was made on May 11, 1995, May 1, 1997 Approved. ------- 43 _ This paper size applies to China National Standard (CNS) A4 (210X 297 mm) 484110 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Invention Description (M) 27 * Sakai , Toshio, et * al ·, USPTN 5,594,844, "Using Ray Tracing to Three-Dimensional Views Divided by Vowels and Using Target-Based Parameters in Numbers", Filed on January 25, 1994, January 1997 Approved on the 14th. 28 * Greene, Edward, et * al ·, USPTN5,579,455, "Description of Three-Dimensional Scenery on a Display Using Hierarchical Z-Buffers," Filed on July 30, 1993, Application, 1996 Was approved on November 26 of the year. 29- Poultn, John, et.al.,! ! SPTN5,481,669, "Architecture and Installations Using Enhanced Memory Elements for Image Generation", filed on April 28, 1993, and was approved on December 31, 1996. 30- Patterson, David & Henn essey, John, "Computer Architecture: A Quantitative Discussion (Second Edition) '1990', 1996, Morgan Kan ffma η Publishing House, Inc., ISBN 55860- 329-8 〇31.jr〇hnson, Mike, "Ultra-Scalar Microprocessor Design", 1991, PTR Prentice-H a 1 1, Inc., Englew (3d Ciiffs, NJ, International Standard Book No. 〇-13 一 8756 3 1-1 ° 32 • Murakami ^ Kazuaki 5et. · 44 This paper size is applicable to China National Standard (CNS) A4 specification ((Please read the precautions on the back before filling this page), τ 84 4 / | \ Λ7 B7 V. Description of the invention (P) a 1 · "Dynamic random processing memory with 256 million bits and parallel processing random access memory chip with four-way multiplex processor", 19 1997, IEEE International Solid-State Circuits Symposium, pages 228-229, ISBN 0 — 7803-3721-2 ^ 3 3-Amimoto? Yoshiharu? Et. • a 1 ·, "One 7 · 6 8 GIP 3 · 8 4 GB / s 1W parallel For example, the processing of random access memory integrates a 16 million-bit dynamic random processing memory and a 128 processor. "In 1996, the International Society of Electrical and Electronics Engineers (IEEE) International Solid-State Circuits Symposium, 372 — 373 pages, ISBN 0 — 7 8 0 3 — 3 13 6-2., 34 * Yao, Yong, “Chromatic's Μ PACT 2 accelerates 3D calculations: M pact / 3 0 0 0 becomes first Media Processor in Storage Media ", pages 1, 6-10, Microprocessor Report, Volume 10, No. 15, November 18, 1996, 1996, Micro Design Resources ◊ Central Standards of the Ministry of Economic Affairs Printed by the Bureau ’s Consumer Cooperative (please read the notes on the back before filling out this page) 35 * Shimizu, Tonu, et * al ·, "A multimedia 3 with 16 million bits of dynamic random access memory Meta Reduced Instruction Set Computer (RISC) Microprocessor ", 1996, International Society of Electrical and Electronics Engineers (IEEE) International Solid-State Circuits Symposium, pages 2 16 — 2 17, International Standard Book Number 0 — 7 803-3136-2. 36 * Glaskowsky, Peter, "Fuji_45 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm) 484110 Λ7 V. Description of the invention (A) Passive media processor: Diversified digital light ^: Multi-Module Access Combination of Long Instruction Word Cores, Integrating Peripherals ", 1 1-13 pages of" Microprocessor Report, Volume 10, No. 15 "November 18, 1996," 199 6 years, micro design resources ° 37 ·, Sam Sung's Multimedia Signal Processor 'Johnpeddie Member's Report on Personal Computer Graphics, August 20, 1996, 1996, John Peddi e Associates, Tiburon' CA94 920, pages 1153-1156. 38.Ya〇, Yong, "Samsung's Media Processor: Mass Storage Processor is designed to work with Microsoft Heart's three-dimensional software architecture,", pages 1, 6 — Θ, Microprocessor Report, Volume 10, No. 11, August 26, 1996, 1996, Micro Design Resources.

3 9 · "Chromatic rolls out Extend Mpact", a member of Joon Peddi's report on personal computer graphics, '1996'J August 27, 1996 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the note on the back first) Please fill in this page for more details) 〇h η Peddie Associates 'Tib uron, CA94920' 1182-1183. 40. Romney, Gordon ′ et · β1 ”USPTN 3,621,214,“ Transmission by Electronic Device ”, filed on November 13, 1968, and approved on November 16, 1971. 41 .Gove. Robert 'USPTN5' 4 _46_______ This paper size applies to Chinese National Standard (CNS) A4 (210X 297 mm) 484110 Λ7 B7 V. Description of the invention (1 0, 6 4 9 "Image Computer System and Network", 1 9 An application was filed on January 29, 2002, and approved on April 25, 1995. 42 * GovecRobert, USPTN5, 5 2 2, 0 8 3, "Reconfigurable operation in single instruction multiple data path (SIMD) mode Multiprocessors use one processor to fetch instructions and use the remaining processors to perform multipath operations. "Applications were made on January 22, 1994, and approved on May 28, 1996. 43." TMX320C6201 Digital Signal Processor, Product Preview ", SPRS051 · pdf, January 1997, 1997. Texas Instruments, available from Texas Instruments website http: www.ti.com 0 44-Weinreb, Dani e 1 and Moon, D avid, Features: incoming message L isp machine, artificial intelligence memo 6 02, November 1980, M · I · T · artificial intelligence laboratory. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) 4 5 · D a 1 ley, Wi 1 liam, et * al •, Message Driven Processor Architecture, 11th Edition, Artificial Intelligence Memorandum 1 0 69, August 1988, M.I.T. Artificial Intelligence Lab. 46 · Cray, Seymour, USPTN4, 128 , 880, filed on January 30, 1976, and was approved on February 5, 1978. 47 * Beard, Douglas, et · a 1 · USPTN 5,544,337, "With the control of the vector register Vector Processor for Register ", filed on January 7, 1995 _ £ 7_ This paper size applies to China National Standard (CNS) A4 (210X 297 mm) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 484110 5 I. Description of the Invention (β) Please, approved on August 6, 1996. 48 * Yoshinaga, Toru and Shinj 〇, Naoki, USPTN 5,598,574, "Vector Processing Device", filed March 18, 1996 The application was approved on January 28, 1997. 49 · Cray 'Seym our, USPTN3, 8 3 3, 8 89, "Multimodal Data Processing System", application was made on March 8, 1973 , Approved on September 3, 1974. 50 * Porter, John, et · a 1 ·, U SPTN4,589,067, "Full Floating Point Vector Processor with Dynamic Reconfigurable Multifunction Pipeline Arithmetic Logic Unit", May 27, 1983 He filed an application and was approved on May 13, 1986. , 51 * Ellis, James, et-ai ·, U SPTN5,418,973, "Digital computer system with cache memory controller coordinate vector and scalar operation", filed on January 22, 1992, 1 9 9 Approved May 23rd, 5 years. 52 * Omoda, Koichior, et., Al •, USPTN 4,651,274, "Vector Data Processor", filed on March 28, 1984, and was approved on March 17, 1987. 53-Gal lup, Michael, et · a 1 •, USPTN 5, 600, 846, "Data Processing System and Related Methods", filed on February 17, 1999, February 4, 1997 Approved. _48 ____ This paper size applies to China National Standard (CNS) A4 (2! 〇X 297 mm) " (Please read the precautions on the back before filling out this page) Clothes · Order 484110 Staff Consumer Cooperatives, Central Standards Bureau, Ministry of Economic Affairs Printed Λ7 B7 5. Description of the Invention (M) 54. Prince'Betty, "Semiconductor Memory: A Handbook of Design, Manufacturing, and Application, Second Edition", 1 9 9 3, 1 9 9 1 John Wiley & Sons, Ltd. , ISBN 0 — 471 — 94295 — 2. 5 5 · "Product Description: MI PS 1 6 Extension of Specific Applications", v 1 · 1, found on the website of Video Computing Technology, July 24, 1997, http: //www·sgi.com/MIP S / mipsl6-pdf. 5 6 · "Introduction to ThumbTM, Version 2.0", issued March 1996, Advanced RISC Machines Ltd. (ARM) 1 995 5 0 5 · "Volume One Review", Video Newsletter: Special Discussion on M PEG — 4, downloaded July 24, 1997, from htt P: / / drog ο / cse 1 t · ste t. · It / υ fv / 1 e ο nardo / icjfi 1 es / mepg — 4 _ si / paperO · 58-Koenen jRob ^ Pere i ra ^ F •, and Chiarig 1 i 〇ne, L · "Μ PEG 4: Content and Purpose", Video Communications Journal: Special Discussion on MPEG-4, Download Date 19 9 July 17, 2007, from ^ 1 | .1?: // (1 rogo / cselt · stet · it / ufv / le onardo / icjfi 1 es / mepg-4 — si / paper 1 · htm.

59 * Contin, L, et * al ·, "Test M _____ 49 This paper size applies to China National Standard (CNS) A4 specifications (210X297 mm) '--丨: II (Please read the precautions on the back before filling in this page)

1T 484110 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs Λ7 B7 V. Description of Invention (A) Peg-4 Audio Coding / Decoding Suggestions ", Journal of Video Communications: Special Discussion on PEG-4, Download Date July 1997 On the 17th, from htt ρ: // dr 〇g 〇 / cse 1 t · stet · it / ufv / leonardo / icj fi les / 111 e P g — 4 — si / paper 3 · htm. 60. Osterman, J〇 rn, "Operational Methods for Video Tools and Algorithms in Calculating M PEG-4", Journal of Image Communications: Special Discussion on M PEG-4, Download Date July 17, 1997, from ht tp : // drogo / cse 1 t stet it / ufv / leonardo / icj fi lesXmepg-4_s i // paper4 * htm 〇.61 # Ebrahimi ^ Touradj? "MP EG-4 video verification mode: according to the content representation "Video Encoding / Decoding Algorithm", Journal of Image Communications: Special Discussion on PEG-4, download date: July 17, 1997, http: // dr 〇g〇 / cselt * stet · it / ufv / leo nardo / · icjfi 1 es / mepg — 4 — si / paper5.htm. 62 * Avaro, 0.et, al ♦, “This And other MP EG-4 systems and description languages: a way to go beyond audio visual information representation ", Journal of Image Communications: Special Discussion on M PEG-4, download date is July 17, 1997, from http: / / dr 〇go / cselt · stet. · it / ufv / leon __ _ 50 This paper size applies to Chinese National Standard (CNS) M specification (21〇x297 公 # ·) (Please read the precautions on the back before filling this page ) Order 484110 Λ7 B7 V. Description of the invention (J) ard 〇 / icjfi les / mepg- 4_si / p aper6.htm. 63-Doenges-et * al ·, "M PEG-4: Audio / Video for mixed media And Synthetic Graphics / Audio ", Video Communication Journal: Special Discussion on MPEG-4, Download Date July 17, 1997, http: // dr 〇g 〇 / cselt · stet · it / uiv / leonard o / icjfi 1 es / mepg — 4_s i / pape r 7 · htm ^ 64 * Gosling, James ° Joy, Bi l] ^ C! Steele, Guy, "JavaTM Language Manual", 1 9 6 6 Sun Microsystems Co., Ltd. , Published by A ddis ο n—We s 1 ey publishing house, ISBN 〇 201-63451-1 °

65 · Αι: ηο1 (1, K6η and Gos 1 ing, James, "* 1 ava TM programming language", 1 9 9 β Sun Microsystems Co., Ltd. 'by Add i son — Central Bureau of Standards, Wesley Ministry of Economic Affairs Printed by employee consumer cooperatives (please read the notes on the back before filling this page) Published by the publisher, ISBN 0 — 201 — 6345 5 — 4 〇6 6 · I nte 1, “Accelerated Graphics Port Interface Manual”, Version 0, Indale Corporation, July 31, 1996. 67 · "Common Serial Bus Specification", 1.0 Revision, Comp Comp, Digital Equipment Corporation 'IBM Computer Corporation, Indale, Microsoft, NEC 'Northern Telecom This paper size is suitable for financial standards (CNS) A4 specification (21GX29 ^ mm)-484110 Λ7 B7 .70-Papaicha 1 is, Pan John, V. Description of invention (called) and other companies , January 15, 1996. 68 * Soari 'Edward and 11, George, "Peripheral Component Interconnect (p C 丨) Hardware and: Second, Third Edition", 1994, 1995, 1996, * An = abo〇ks, San Diego, CA, National Shaanxi Book No. 0-92392-32 January 9, Fifteenth Brush, "Milk 9 January ◊ 9 69 · Shanley, Tom, Anders 'D ο η," Peripheral Component Interconnect (pc I) System Architecture, Key = n "Version"' 1995Mindshare Co., Ltd., International Automobile Standard Book No. 0—201—4099 3—3, the first brush 1 '5 February. 〇s and s 〇6 using TMS32020 to implement a fast Fourier transform algorithm ”, pages 84 to 85, using TMS320 series executes digital signal processing applications, 1 9 8 6 Texas Instruments Co., Ltd. 0 ---------- jml clothing — C Please read the precautions on the back before filling in this page j, -5:- τ > Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 52 CN

I centimeter 7 9 2 X Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 484110 A7 B7 V. Description of the invention () Brief description of the representative symbols of the main parts: 1 Basic circuit 2 Controller 3, 5, 12, 13, 14 , 15, 16, 17 Wiring harness 4 Internal area memory 6 Main memory interface and controller (MM IC) 7 Overall external bus interface (GEBI) 8 Embedded microprocessor subsystem 9 Digital signal processor (array Processor), 10 adjacent circuits, communication port 11 special purpose circuit 8 0 0 microprocessor 810 cache memory, 8 2 0 random access memory 8 3 0 read-only memory 900 data path processing unit 9 0 1 Busbar, 9 0 2 Wiring harness 9 0 3 Wiring harness 9 0 6 Wiring harness 9 0 7 Wiring harness 909 Wiring harness 9 1 0 Shared operand circuit (SOC) 9 2 0 Area data storage (please read the back first (Notes for filling in this page)

\ This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 484110 A7 A7 B7 V. Description of the invention () 9 4 0 Shared output and feedback interface (S0FI) 9 5 0 module 殳5 1 Synchronization circuit and instruction storage unit (cs I sr 9 6 5 Array processor interface circuit (APIC) 9 7 0 Group ... (Please read the precautions on the back before filling this page) Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Cooperative printed II ^ --------- line 丨 continued --------.-------------- This paper size applies to China National Standard (CNS) A4 size (210 X 297 mm)

Claims (1)

484110 A8 B8 C8 D8 VI. Patent application scope 1 · An integrated circuit that works with memory during operation. The integrated circuit includes: An interface circuit is configured to control access to the memory. An interface circuit is coupled to the memory; an embedded microprocessor is configured to control the integrated circuit, and the embedded processor is coupled to the interface circuit to receive information from the interface circuit. The array processor is used for performing arithmetic calculations. The array processor is coupled to the interface circuit to receive information from the interface circuit. 2 ♦ The integrated circuit of item 1 in the scope of patent application, wherein the array processor includes: a plurality of multipliers / accumulators; and a shared operand circuit is coupled to and provides a shared operand to the majority At least two of the multipliers / accumulators. 3. The integrated circuit of item 1 in the scope of patent application, wherein the interface circuit includes a wiring harness to provide wide access. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling out this page) 4 · If the integrated circuit of item 3 of the patent application, the wiring harness contains at least 256 wires. 1 This paper size applies to China National Standard (CNS) Α4 specification (210 × 297 mm)