[ 46嚇 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（/ ) 本發明是有關於一種雙晶片構裝之結構與其製造方 法’且特別是有關於一種以金屬栓與銲球作爲對外連接之 媒介的雙晶片構裝·^ 高效能、高積集度、低成本、輕薄短小皆爲長久以 來電子產品設計製造上所追尋之目標。對半導體製造而 言，現今已邁入0.18微米量產的時代，其積集度自不待言。 然而對於構裝（packaging)之積集度而言，如何提高承載器 (earner)密度，縮小整體構裝之體積，均是重要課題。此外， 不管在電腦上或民生用品上之應用，爲了縮小產品體積及 節省構裝成本，將二個以上的晶片封裝在一起的技術，將 疋;未來的趨勢之一。多晶片構裝可以將處理器（pr0cess0r) 晶片及記憶體（memory)晶片’或者邏輯電路（Logic)晶片及 記體晶片（包括DRAM及Flash Memory)封裝在一起，不 但可以降低成本，縮小構裝體積’並可縮短訊號傳輸路徑， 提咼效能，並可使不同製程之晶片，合爲—構裝中，而無 需使用特殊整合製程生產。 請參照第1圖’其繪示一種習知雙晶片構裝的結構。 此種結構已揭露於日本實用新型專利申請案，公開號：實 開昭62-147360的文獻中。二晶片1〇〇、1〇2分別貼附於晶 片座l〇4(die pad)的二表面，並以導線108(wlre)與接腳 l〇6(lead)連接，再以封裝材料11〇包覆晶片i〇〇、1〇2，接 腳106的內接腳部分(inner iead)與導線1〇8。然而此種雙晶 片構裝結構，由於採用傳統導線架(丨eadframe)作爲承載器， 其積集度受到限制，訊號路徑亦較長。組裝時，在一晶片 木’我張尺度適用令國國家標準（CNS ) A4规格（2l〇x297公着 ~ -- —^ϋ n^—. I ILn IB _^pn l m> \OJ (諳先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 6 665 1 5 1 7 .11 ιλ f ti o c / Ο Ο 0 A 7 _ B7 五、發明説明（之） 打完導線後，需要特定之治具夾持，才能進行另一晶片的 黏附（die attaching)與打導線（wire bonding)製程，徒增製程 成本及複雜度。 因此本發明的目的之一就是在提供一種雙晶片構裝 .結構，具有較高之積集度及較短之訊號路徑。 本發明的目的之二在於提出一種雙晶片構裝結構， 縮小整體構裝體積。 本發明的目的之三在於提出一種雙晶片構裝的製造 方法，可以簡化製程，並節省額外治具之花費。 爲達成本發明之上述和其他目的，提出一種雙晶片 構裝結構，包括‘·晶片座，其二表面分別配置一晶片。晶 片座外圍有多個第一金屬栓；而第一金屬栓之外圍有多個 第二金屬栓；多條導電跡線，則分別連接第一金屬栓與第 二金屬栓。晶片座二面之晶片分別以導線與第一金屬栓對 應之一端連接，絕緣材料則包覆晶片、晶片座、第一金屬 栓，導電跡線及第二金屬栓的一端，僅暴露出第二金屬栓 的另一端。多個銲球分別植接於第二金屬栓之另一端。 爲達成本發明之上述和其他目的，提出一種雙晶片 構裝之製造方法，包括：首先提供一導電基板，其具有第 一表面與第二表面，並具有晶片座區，其外圍有多個第一 金屬栓區，多個第二金屬栓區位在第一金屬栓區外圍，及 多個導電跡線區分別連接第一金屬栓區與第二金屬栓區。 接著形成罩幕層，覆蓋第一表面之晶片座區、第一金屬栓 區、第二金屬栓區及導電跡線區。半鈾刻導電基板的第一 4 I - I — - - I I JH ^^1 I - I —H 1 - - - 1 I---— ——I. I ^^1 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） A7 B7 五、發明説明（$ ) 表面，使得未被罩幕層覆蓋區域僅殘留一預定厚度。貼附 第一晶片於第一表面之晶片座區，以導線連接第一晶片與 第一金屬栓區。形成第一絕緣層覆蓋第一表面，並蝕刻第 二表面，以暴露出第一絕緣層，此時即形成晶片座、第一 金屬栓、第二金屬栓及導電跡線於對應之區域。貼附第二 晶片於第二表面之晶片座，並以導線連接第二晶片與第一 金屬栓/形成第二絕緣層覆蓋第二表面，並暴露出第二表 面之第二金屬栓的部分。將多個銲球分別植接於第二表面 中暴露出之第二金屬栓上。 爲讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作 詳細說明如下： 圖式之簡單說明： 第1圖繪7K —種習知雙晶片構裝的結構。 第2圖至第7圖繪示依照本發明一較佳實施例的一種 雙晶片構裝的製程剖面示意圖。 第8圖繪示未採用鍍層的雙晶片構裝結構。 第9圖繪示雙晶片構裝結構金屬栓之配置示意圖。 圖式之標示說明： 100，丨02、220、240 :晶片 104 :晶片座 L06 :接腳 108 :導線 5 t請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) A4現格（210 X W7公釐) "~~' 466651 5 t 73tivf doc/ΟΟίι B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（七） 110 :封裝材料 200 :導電基板 202 :晶片座區 204 :第一金屬栓區 206 :第二金屬栓區 208 :導電跡線區 210 :鍍層 212、214 :表面 216、218 :光阻層 222、242 :主動表面 224、244 :背面 226、246 :焊墊 228 ' 248 :導線 230、250 :絕緣材料 232、232a :晶片座 234、234a :第一金屬栓 236、236a :第二金屬栓 238、238a :導電跡線 252 :銲球 實施例 請參照第2圖至第7圖，其繪示依照本發明一較佳實 施例的一種雙晶片構裝的製程剖面示意圖。首先請參照第 2圖，先提供一導電基板200，其材質包括銅、鐵、銅合 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙掁尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） 4. 6 6 6 5 1 17 31» »c/〇0( A7 B7 五、發明説明（<) 金（〇15卜〇194、〇7025、：^〇?125、已卩丁£(：等）或鐵鎳合金（1^-卜 42 Alloy)等。整個導電基板200至少包括幾個區域：晶片 座區202，第一金屬栓區204、第二金屬栓區206及導電跡 線區208。晶片座區202爲欲形成晶片座的區域；第一金 屬栓區204位於晶片座區202之外圍，爲欲形成第一金屬 栓的區域，第一金屬栓(first metal stud)用來與晶片之焊墊 (bonding pad)連接。第二金屬栓區206位於第一金屬检區204 外圍，爲欲形成第二金屬栓(second metal stud)的區域，第 二金屬栓用來作爲將來銲球(solder ball)的接點。導電跡線 區208爲欲形成導電跡線的區域，導電跡線（trace line)用 以分別連接第一金屬栓與對應之第二金屬栓。爲了顧及後 續製程的接合性（bondability)與焊接性（soMerability) ’可以 在第一金屬栓區204與第二金屬栓區206形成鍍層210， 形成方法比如先在導電基板200之二表面212、214形成光 阻層216，透過曝光顯影，暴露出第一金屬栓區204及第 二金屬拴區206，再經過電鍍或者無電鍍的方法形成鍍層 21〇。鍍層210之材質包括鎳、鎳鈀合金’金、鈀、銀等。 請參照第3圖，剝除第2圖中的光阻層216，再進行 一次微影製程，形成光阻層218。此時表面212的部分， 光阻層218至少需覆蓋晶片座區202、第一金屬栓區204、 第二金屬栓區2〇6及導電跡線區208。表面214的光阻層218 可以將表面214完全覆蓋，然而若後續蝕刻製程係採用單 面餓刻的方式，則表面214無須覆蓋光阻層。 請參照第4圖，以第3圖中光阻層218爲罩幕層(mask ) A4ig ( 210X297公釐） ---------略1 (請先閱讀背面之注意事項再填寫本頁)[46 scared A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (/) The present invention is related to a dual-chip structure and its manufacturing method ', and in particular to a method using metal pins and solder balls Dual-chip mounting as a medium for external connections. High efficiency, high integration, low cost, thinness, and shortness are all the goals pursued by electronics design and manufacturing for a long time. As far as semiconductor manufacturing is concerned, today has entered the era of mass production at 0.18 microns, and its accumulation is self-evident. However, for the accumulation of packaging, how to increase the density of the carrier and reduce the volume of the overall packaging are important issues. In addition, regardless of the application on computers or consumer products, the technology of packaging more than two chips together in order to reduce product volume and save assembly costs will be one of the future trends. Multi-chip configuration can package the processor (pr0cess0r) chip and memory chip 'or logic circuit (Logic) chip and memory chip (including DRAM and Flash Memory) together, which can not only reduce costs, reduce the size of the package The volume can shorten the signal transmission path, improve the efficiency, and enable the chips of different processes to be integrated into the structure without using a special integrated production process. Please refer to FIG. 1 ', which illustrates a conventional dual-chip structure. Such a structure has been disclosed in Japanese Utility Model Patent Application Publication No. 62-147360. The two wafers 100 and 102 are respectively attached to the two surfaces of the die pad 104 (die pad), and are connected to the lead 106 (lead) with a wire 108 (wlre), and then packaged with 11 The wafers 100 and 102 are covered, the inner pin portion of the pin 106 and the lead 108 are covered. However, such a dual-chip structure has a limited accumulation degree and a long signal path due to the use of a conventional lead frame as a carrier. At the time of assembly, the size of one piece of wood applies to the national standard (CNS) A4 specification (2l0x297) ~-— ^ ϋ n ^ —. I ILn IB _ ^ pn l m > \ OJ (谙(Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 665 1 5 1 7 .11 ιλ f ti oc / Ο Ο 0 A 7 _ B7 V. Description of the invention (of) Finished After the wire, a specific jig is required to carry out another die attaching and wire bonding process, which increases the cost and complexity of the process. Therefore, one of the objectives of the present invention is to provide a The structure of the dual-chip structure has a higher accumulation degree and a shorter signal path. Another object of the present invention is to propose a dual-chip structure to reduce the overall structure volume. A third object of the present invention is to provide A manufacturing method of a dual-chip structure can simplify the manufacturing process and save the cost of additional fixtures. In order to achieve the above and other objectives of the invention, a dual-chip structure is proposed, which includes a wafer holder, and the two surfaces are arranged separately. A wafer. There are a plurality of first metal bolts on the periphery of the chip holder; and a plurality of second metal bolts on the periphery of the first metal bolt; and a plurality of conductive traces are respectively connected to the first metal bolt and the second metal bolt. The chip is connected with the corresponding end of the first metal pin by a wire, and the insulating material covers one end of the chip, the chip holder, the first metal pin, the conductive trace, and the second metal pin, and only the other end of the second metal pin is exposed. A plurality of solder balls are respectively implanted at the other end of the second metal bolt. In order to achieve the above and other objectives of the present invention, a manufacturing method of a dual wafer structure is provided, which includes: firstly providing a conductive substrate having a first surface And the second surface, and having a wafer seat region, a plurality of first metal bolt regions are located on the periphery thereof, a plurality of second metal bolt regions are located on the periphery of the first metal bolt region, and a plurality of conductive trace regions are respectively connected to the first metal bolt region Area and the second metal plug area. Next, a mask layer is formed to cover the wafer seat area, the first metal plug area, the second metal plug area, and the conductive trace area of the first surface. The first 4 I of the conductive substrate is semi-uranium-etched. -I —--II JH ^^ 1 I-I —H 1---1 I ----- ——I. I ^^ 1 (Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210X297mm) A7 B7 5. Description of the invention ($) Surface, leaving only a predetermined thickness of the area not covered by the cover layer. The first wafer is attached to the wafer seat of the first surface, and the first wire is connected to the first The wafer and the first metal plug area. A first insulation layer is formed to cover the first surface, and the second surface is etched to expose the first insulation layer. At this time, a wafer holder, a first metal plug, a second metal plug, and a conductive layer are formed. Traces are in the corresponding areas. Attach the second wafer to the wafer holder on the second surface, and connect the second wafer and the first metal plug with a wire / form a second insulating layer to cover the second surface, and expose a part of the second metal plug on the second surface. A plurality of solder balls are respectively implanted on the second metal pins exposed in the second surface. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Draw 7K-a conventional dual-chip structure. FIG. 2 to FIG. 7 are schematic cross-sectional views illustrating a manufacturing process of a dual-chip structure according to a preferred embodiment of the present invention. FIG. 8 shows a two-wafer structure without a plating layer. FIG. 9 is a schematic diagram showing the configuration of the metal pins of the dual-chip structure. Description of the drawing: 100, 02, 220, 240: Wafer 104: Wafer holder L06: Pin 108: Wire 5 t Please read the precautions on the back before filling this page) Order the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed paper standards are in accordance with Chinese National Standards (CNS) A4 (210 X W7 mm) " ~~ '466651 5 t 73tivf doc / ΟΟίι B7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 7) 110: Packaging material 200: Conductive substrate 202: Wafer area 204: First metal bolt area 206: Second metal bolt area 208: Conductive trace area 210: Plating layer 212, 214: Surface 216, 218: Photoresist layer 222, 242: Active surfaces 224, 244: Back surfaces 226, 246: Pads 228 '248: Wires 230, 250: Insulating materials 232, 232a: Wafer holders 234, 234a: First metal pins 236, 236a: Second metal pins 238, 238a: conductive traces 252: solder ball embodiments Please refer to FIG. 2 to FIG. 7, which are schematic cross-sectional views illustrating a manufacturing process of a dual-chip assembly according to a preferred embodiment of the present invention. First, please refer to Figure 2. First, a conductive substrate 200 is provided. Its material includes copper, iron, and copper (please read the precautions on the back before filling this page). The size of the paper is applicable to the Chinese National Standard (CNS) Α4 specification ( 210X297 mm) 4. 6 6 6 5 1 17 31 »» c / 〇0 (A7 B7 V. Description of the invention (&); Gold (〇15 卜 〇194, 〇7025 ,: ^ 〇? 125, Hastings) £ (: etc.) or iron-nickel alloy (1 ^ -Bu42 Alloy), etc. The entire conductive substrate 200 includes at least several areas: a wafer seat area 202, a first metal plug area 204, a second metal plug area 206, and a conductive trace. Line area 208. Wafer area 202 is the area where the wafer base is to be formed; the first metal stud area 204 is located on the periphery of the wafer area 202, and is the area where the first metal stud is to be formed. It is connected to the bonding pad of the wafer. The second metal stud area 206 is located around the first metal inspection area 204, and is the area where a second metal stud is to be formed. The second metal stud is used as a future A contact point of a solder ball. The conductive trace area 208 is an area where a conductive trace is to be formed. (Trace line) is used to connect the first metal bolt and the corresponding second metal bolt respectively. In order to take into account the bondability and solderability (soMerability) of subsequent processes, the first metal bolt region 204 and the second metal bolt may be used. The plating layer 210 is formed in the region 206. For example, a photoresist layer 216 is formed on the two surfaces 212 and 214 of the conductive substrate 200, and the first metal bolt region 204 and the second metal bolt region 206 are exposed through exposure and development. The plating layer 21 is formed by electroless plating. The material of the plating layer 210 includes nickel, nickel-palladium alloy, gold, palladium, silver, etc. Please refer to FIG. 3, strip the photoresist layer 216 in FIG. 2 and perform lithography again. During the manufacturing process, a photoresist layer 218 is formed. At this time, on the surface 212, the photoresist layer 218 needs to cover at least the die pad area 202, the first metal plug area 204, the second metal plug area 206, and the conductive trace area 208. Surface The photoresist layer 218 of 214 can completely cover the surface 214. However, if the subsequent etching process uses a single-sided engraving method, the surface 214 need not be covered with the photoresist layer. Please refer to FIG. 4 and FIG. 3 for the photoresist layer 218 is mask A4ig (210X297 mm) --------- Slightly 1 (Please read the notes on the back before filling this page)
，1T 經濟部智慧射員工消費合作社印製 本紙浪 4 6 66 5,1 I 73t\vl'.d〇c/006 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（6 ) layer)，對導電基板200進行半蝕刻(half etching)，餓刻表 面212中暴露的區域，使其僅殘留一預定厚度D。然後剝 除光阻層（第3圖中之218)，此時晶片座' 第一金屬栓與 第二金屬栓及導電跡線的雛形已依稀可見。 請參照第5圖’進行第一次晶片黏貼（die attachmg)及 打導線（wire bonding)製程。將晶片220貼附於表面212的 晶片座區202，其中晶片220具有一主動表面222及一背 面224 ’比如利用導電膠或絕緣膠(未繪示）將背面224貼附 於表面212之晶片座區202。主動表面222上具有焊墊226， 進行打導線製程，以導線228連接焊墊226與表面212之 第一金屬栓區204。導線228的材質包括金、鋁、銅。然 後’進行第一次封膠製程（encapsulating)，將表面212覆蓋 以絕緣材料230 ’包覆晶片220、第一金屬栓區204 '第二 金屬栓區206、導電跡線區208，以及導線228等。絕緣材 料230之材質包括樹脂(resin)、環氧樹脂(epoxy)、液態封 膠材料（HqUld compound)等’比如利用塗佈（ca〇ting)及固化 (curing)的方式形成。 請參照第6圖’接著對導電基板2〇〇之表面214進行 触刻’由於表面212有絕緣材料230包覆，而表面214之 第一金屬栓區204與第二金屬栓區206有鍍層210之保護， 因而不被蝕刻。其餘部分透過蝕刻，去除原殘留之厚度D， 直至暴露出表面214之絕緣材料23〇。此時晶片座區202 形成晶片座232 ;第一金屬栓區204形成第一金屬栓234 ; 弟一金屬栓區206形成第二金屬栓236:導電跡線區208 8 本紙張尺度逋用中國圏家樣準（CNS) M规格（210><297公竣） (請先閱讀背面之注意事項再填寫本頁) 訂 Λ6 665 5 1 73twr.tUu;/0〇(i A7 B7 五、發明説明（7 ) 形成導電跡線238。 請參照第7圖’進行第二次晶片黏貼及打導線製程。 將晶片240貼附於表面2丨4的晶片座232，其中晶片240 具有-—主動表面242及一背面244，比如利用導電膠或絕 緣膠（未繪示）將背面244貼附於表面214之晶片座232。主 動表面242上具有焊墊246，進行打導線製程，以導線248 連接焊墊246與表面2M之第一金屬栓234。導線248的 材質包括金、鋁、銅。然後，進行第二次封膠製程’將表 面214覆蓋以絕緣材料25〇，包覆晶片24〇 '第一金屬栓 234、導電跡線238 ’以及導線248等，而暴露出第二金屬 栓236在表面214的部分。絕緣材料25〇之材質包括樹脂、 環氧樹脂、液態封膠材料等，比如利用網版印刷（screen printing)及固化（cunng)或者鑄模（m〇lding)的方式形成。接 著則進行植球的製程，將銲球252分別植接於暴露出的第 二金屬栓236上’作爲整體構裝對外之接點，其中銲球252 的材質包括錫鉛合金。上述製程應用於量產時，可以在一 導電基板上同時形成多個雙晶片構裝，最後在進行切割分 離的步驟。 另外本發明尙有其他之製程選擇，比如上述鍍層21〇 的部分係爲選擇性的製程，若不採用鍍層21〇，亦可以由 光阻層取代’作爲蝕刻罩幕層，然而最終金屬栓的厚度會 較薄。請參照第8圖，其繪示未採用鍍層的雙晶片構裝結 構。在第一金屬栓234a及第二金屬栓236a二端表面，均 未覆蓋鍍層’其厚度則與導電跡線238a相同。在製程上， I-----.---f-γ^------訂-------味 (請先閱讀背面之注項再填寫本頁) 經濟部智慧財產局工消費合作社印製 9， 1T Printed by the Ministry of Economic Affairs ’Smart Consumers Cooperatives 4 6 66 5,1 I 73t \ vl'.d〇c / 006 A7 B7 Printed by the Consumer ’s Cooperatives of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (6) layer ), Performing half etching on the conductive substrate 200, and etching the exposed area of the surface 212 so that only a predetermined thickness D remains. Then strip the photoresist layer (218 in Figure 3). At this time, the prototypes of the first metal plug and the second metal plug of the wafer holder and the conductive traces are faintly visible. Please refer to FIG. 5 'for the first die attach and wire bonding process. The wafer 220 is attached to the wafer seat 202 of the surface 212. The wafer 220 has an active surface 222 and a back surface 224. For example, the back surface 224 is attached to the wafer holder of the surface 212 by using a conductive adhesive or an insulating adhesive (not shown). Area 202. The active surface 222 is provided with a solder pad 226 for conducting a wire bonding process, and the wire 228 is used to connect the solder pad 226 and the first metal plug region 204 of the surface 212. The material of the lead 228 includes gold, aluminum, and copper. Then 'the first encapsulating process is performed to cover the surface 212 with an insulating material 230' to cover the wafer 220, the first metal plug region 204 ', the second metal plug region 206, the conductive trace region 208, and the wire 228 Wait. The material of the insulating material 230 includes a resin, an epoxy, a HqUld compound, and the like, and the like is formed by a method such as coating and curing. Please refer to FIG. 6 and then “etching the surface 214 of the conductive substrate 2000”. Since the surface 212 is covered with an insulating material 230, the first metal plug region 204 and the second metal plug region 206 of the surface 214 have a plating layer 210 It is protected from being etched. The remaining part is etched to remove the original remaining thickness D until the insulating material 23 of the surface 214 is exposed. At this time, the wafer seat region 202 forms the wafer seat 232; the first metal pin region 204 forms the first metal pin 234; the first metal pin region 206 forms the second metal pin 236: conductive trace region 208 8 Home sample (CNS) M specification (210 > < 297) (Please read the notes on the back before filling out this page) Order Λ6 665 5 1 73twr.tUu; / 0〇 (i A7 B7 V. Description of the invention (7) Form conductive traces 238. Refer to Figure 7 for the second wafer sticking and wire routing process. Attach the wafer 240 to the wafer holder 232 on the surface 2 and 4, where the wafer 240 has an active surface 242 And a back surface 244, for example, the back surface 244 is attached to the wafer holder 232 on the surface 214 by using conductive adhesive or insulating glue (not shown). The active surface 242 has a pad 246 for conducting a wire process, and the wire 248 is connected to the pad 246 and the first metal plug 234 on the surface 2M. The material of the lead 248 includes gold, aluminum, and copper. Then, a second sealing process is performed to cover the surface 214 with an insulating material 25 ° and cover the wafer 24 °. Metal pin 234, conductive trace 238 ', and wire 248, etc., exposing the second The part of the metal bolt 236 on the surface 214. The material of the insulating material 25 includes resin, epoxy resin, liquid sealing material, and the like, such as screen printing and curing or moulding. Then, the ball implantation process is performed, and the solder balls 252 are respectively implanted on the exposed second metal bolts 236 as an integral structure for external contacts. The material of the solder balls 252 includes tin-lead alloy. The above When the process is applied to mass production, a plurality of dual wafer structures can be formed on a conductive substrate at the same time, and finally the step of cutting and separating is performed. In addition, the present invention has other process options, such as the above-mentioned plating layer 21 is selected. If the plating process is not used, the photoresist layer can be used as the etching mask layer instead of the photoresist layer. However, the thickness of the final metal plug will be thinner. Please refer to Figure 8, which shows the dual wafer without plating. Structure. On both surfaces of the first metal plug 234a and the second metal plug 236a, the plating layer is not covered. Its thickness is the same as that of the conductive trace 238a. In the manufacturing process, I -----.--- f -γ ^ ------ ------- taste (please note the item back and then fill read this page) Ministry of Economic Affairs Intellectual Property Office workers consumer cooperatives printed 9
經濟部智慧財產局員工消費合作社印製 d 6 665 \ 5 I 7 ^ t V. ti o c / 0 Ο (ί B7 五、發明説明（8 ) 對應於第3圖的部分，第一金屬栓區204與第二金屬栓區 206的鍍層210均以光阻層2丨8取代。至於對應於第6圖 的部分1則直接對表面214進行蝕刻，直至暴露出絕緣材 料230,由於未有鍍層保護》晶片座232a、第一金屬栓234a、 第二金屬栓236a及導電跡線238a具有相同厚度。其餘製 程部分則與上述相同。 因此，本發明的雙晶片構裝結構中，二晶片分別貼 附於晶片座之二表面，二晶片之焊墊也分別與第一金屬栓 對應的一端以導線連接。而絕緣材料覆蓋於二表面，分別 包覆晶片、第一金屬栓、導線、導電跡線，及第二金屬栓 的一端，暴露出第二金屬栓之另一端。第二金屬栓暴露之 一端則植接銲球。 還需進一步說明的，上述製程中第二金屬栓的部分 係以環形配置爲例，然而爲提高構裝積集度，及高腳位數 元件的應用，第二金屬栓亦可才用陣列式（array)配置。請 參照第9圖，其繪示雙晶片構裝結構金屬栓之配置示意圖。 其中，晶片座232位於中央，作爲承載晶片；第一金屬栓 234位於晶片座232外圍，用以與晶片之焊墊連接；第二 金屬栓236則以陣列的方式配置於第一金屬栓234之外 圍，用以植接銲球；導電跡線238則分別連接對應之第一 金屬栓234與第二金屬栓236。 綜上所述，本發明之雙晶片構裝結構及製造方法至 少具有下列優點： 1.本發明之雙晶片構裝結構，將二晶片結合於一構裝 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐> 4 6 66 5 1 A7 ” W 5 I 73tw1'.doc/0 06 A / B7 五、發明説明） 中，並可採用陣列式接點配置，因此具有較高之積集度； 而利用金屬栓、導電跡線及銲球作爲對外之連接媒介，具 有較短之訊號路徑，提高構裝之效能。 2. 本發明之雙晶片構裝結構，係以蝕刻方式形成金屬 栓及導電跡線等1具有較小之間距（pitch)，可縮小整體構 裝體積。 3. 本發明之雙晶片構裝的製造方法，將承載器之製作 (包括晶片座、金屬栓與導電跡線之形成）與組裝製程（包括 晶片黏附、打導線、封膠等）整合，可以簡化製程，並節 省額外治具之花費。 雖然本發明已以一較佳實施例揭露如上，然其並非 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者爲準。 (讀先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家橾準（CNS ) A4规格（210X297公釐）Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs d 6 665 \ 5 I 7 ^ t V. ti oc / 0 Ο (ί B7 V. Description of the invention (8) Corresponding to the part in Figure 3, the first metal bolt area 204 The plating layer 210 and the second metal plug region 206 are replaced by the photoresist layer 2 and 8. As for the part 1 corresponding to FIG. 6, the surface 214 is directly etched until the insulating material 230 is exposed, because there is no plating protection. " The wafer holder 232a, the first metal peg 234a, the second metal peg 236a, and the conductive trace 238a have the same thickness. The remaining process parts are the same as the above. Therefore, in the dual-chip structure of the present invention, the two wafers are respectively attached to On the two surfaces of the wafer holder, the solder pads of the two wafers are also connected to the corresponding ends of the first metal pins by wires. The insulating material covers the two surfaces and covers the wafer, the first metal pins, wires, and conductive traces, and One end of the second metal bolt exposes the other end of the second metal bolt. The exposed end of the second metal bolt is planted with solder balls. It should be further explained that the part of the second metal bolt in the above process is configured in a ring shape as Example, however To improve the build-up density and the application of high-pin components, the second metal pin can also be configured in an array. Please refer to FIG. 9 for a schematic diagram of the configuration of the metal pin of the dual-chip structure. Among them, the wafer holder 232 is located at the center as a carrier wafer; the first metal pin 234 is located on the periphery of the wafer holder 232 for connection with the pad of the wafer; the second metal pin 236 is arranged in an array manner on the first metal pin 234 The outer periphery is used for planting solder balls; the conductive trace 238 connects the corresponding first metal bolt 234 and the second metal bolt 236 respectively. In summary, the dual-chip structure and manufacturing method of the present invention have at least the following Advantages: 1. The dual wafer structure of the present invention combines two wafers into one package (please read the precautions on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm > 4 6 66 5 1 A7 ”W 5 I 73tw1'.doc / 0 06 A / B7 V. Description of the invention), and can use the array contact configuration, so it has a high degree of accumulation; And use metal pins, conductive traces, and solder balls as The external connection medium has a shorter signal path to improve the efficiency of the structure. 2. The dual-chip structure of the present invention is formed by etching to form metal bolts and conductive traces. 1 has a small pitch. The overall fabrication volume can be reduced. 3. The manufacturing method of the dual-chip assembly of the present invention involves the fabrication of a carrier (including the formation of a wafer holder, metal pins and conductive traces) and the assembly process (including wafer adhesion, wire routing) , Sealant, etc.) integration, which can simplify the manufacturing process and save the cost of additional fixtures. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Anyone skilled in this art will not depart from it. Within the spirit and scope of the present invention, some modifications and retouching can be made. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application. (Read the precautions on the back before you fill out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is sized for China National Standards (CNS) A4 (210X297 mm)