TW444335B - Process for forming self-aligned multi-level interconnect structure - Google Patents

Abstract

The present invention provides a process for forming self-aligned multi-level interconnect structure, which comprises the steps of: (a) providing a semiconductor substrate; (b) forming a conductive layer on the semiconductor substrate; (c) forming a plug above the conductive layer to expose part area of the conductive layer; (d) removing part of the conductive layer so that the remained conductive layer is used as a first wire and the first wire is self-aligned with the plug; (e) covering a dielectric layer on the semiconductor substrate and plug, wherein the dielectric material has a low step coverage capability for forming voids in the dielectric layer between the first wires; (f) planarizing the dielectric layer to expose the top of the plug; and (g) forming a second conductive wire on the top of the plug. The present process is able to not only form the self-aligned multi-level interconnect structure, but also decrease the capacitance coupling effect between the first wires. Furthermore, it is able to block the conductive ingredient from entering the voids in the dielectric layer and thus prevent the multi-level interconnect structure from being damaged.

Description

4443 3 5 f2 · 'Explanation (l)' " This case is about a process for forming a multiple interconnect structure, especially a process for forming a self-aligned multiple interconnect structure. With the rapid development of the semiconductor industry, the accumulation degree of integrated circuits has gradually increased. When the surface of the wafer cannot provide enough area to make a large number of components, multiple interconnects must be used to connect the various components, that is, using a multilayer structure. Complete more complex designs and provide more complete functions on the same area of the chip. Of course, in order to reduce the size of the semiconductor device as much as possible, in addition to using a multilayer structure, reducing the distance between components is also a goal of the semiconductor industry to research and develop, so as to meet today's requirements for small size and high performance of semiconductor devices. With the generation of precision technology, the requirements for line width also range from micron to sub-micron, and even extend to the field of deep sub-micron. However, as the distance between components decreases, the capacitance-combining effect between adjacent wires brings problems. When the distance between wires is shorter, there is no doubt that the capacitive coupling effect will be greater. When the line width is less than 0.3 microns At that time, the capacitance of 9096 is from the capacitance between the wires, which is to a degree that cannot be ignored. In order to reduce the coupling effect between the wires, some people began to fill low-k materials between the wires and the wires. , Its dielectric constant is less than 3, preferably less than 2 'For example, adding tetraethylorthosiiane (TEOS) to reduce the dielectric constant to 3.3, this dielectric material has been applied to 0 In the 35 micron process, some people predict that the future dielectric materials will develop toward the use of polymers and aerogels. The above-mentioned method for reducing the capacitive coupling effect by using the research and development of a dielectric material belongs to the field of materials. Now a new process has been proposed. Even without using a new dielectric material, the capacitive coupling effect between the wires can be reduced.

Page 4443 3 5 I. Explanation of the invention (2) is to form an air gap in the dielectric material between the wires (JG Fleming and ER Osmun, " Use of Air Gap Structures to Lower Intralevel Capacitance ", DUMIC Conference, pl39-146, 1997), that is, part of the dielectric material is replaced by air 'because the dielectric constant of air is very low (about 1), it will undoubtedly greatly reduce the capacitive coupling effect between the wires. The structure of multiple interconnections is shown in the first figure. The semiconductor substrate 11 includes metal oxide semiconductor field effect transistor (MOSFET) elements (not shown), and the metal oxide half field effect of different layers The transistor elements are in ohmic contact with the wires 12 and 13 with a plug 14 connecting the wires 12 and 13 to communicate the metal-oxide-semiconductor half-field effect transistor elements in different layers. In addition, except for the specific Outside of the partial connection, each metal-oxide-semiconductor half-effect transistor element must be separated by a dielectric layer 15 to prevent short circuit or leakage. A dielectric 16 is shown in the dielectric layer 15 to reduce adjacent Capacitive coupling effect between wires 12. Although the addition of pores can reduce the capacitive coupling effect, there are hidden risks in the manufacturing process. Please refer to the second figure, which shows the general process steps of multiple interconnects. Please refer to the second figure (A). First, a conductive wire 12 is formed on a semiconductor substrate 11 including a metal-oxide-semiconductor field-effect transistor element. The material of the conductive wire 2 is mostly aluminum 'because the resistivity of aluminum is low' and the The adhesion between the silicon layers is good; then a dielectric layer 5 is deposited to isolate the different layers of gold-oxygen half field effect transistor elements. The material of the dielectric layer 15 is mostly silicon dioxide, and its dielectric constant is about 4, which can be A pore 16 is formed therebetween; then a photoresist layer 丨 7 is formed on the dielectric layer i 5. After pattern transfer (pattern) can be defined

4443 3 5 V. Description of the invention (3) Position of the interlayer window. Next, referring to the second figure (B), a portion of the dielectric layer 15 'is removed by anisotropic etching to form a dielectric window 18. Please refer to the second step (C). A conductive layer is deposited in the dielectric window 18 and the dielectric layer 15. The material is mostly town. Then #etch away the conductive layer above the dielectric layer 15 and leave only the dielectric layer. The conductive layer in the ®18 is formed as the plug 14 'and finally formed on the plug 14-the wire 13' becomes a multiple interconnect structure as shown in the first figure. The disadvantage of this process is that if the definition of the photoresist layer 17 is inaccurate, so that the etched interlayer window 18 is in communication with the aperture 16, the conductive material will inevitably enter the aperture 16 when the conductive layer is filled. The entire structure of multiple interconnects will be cracked, and short circuits and leakages will occur. In addition, 'the use of filling conductive materials in the interlayer window has another drawback—as the line width becomes thinner', it is not easy to completely fill the interlayer window. Insufficient step coverage capabilities will cause Holes appear in the plug. This will cause the reliability of the component during operation. Therefore, U.S. Patent No. 5, 6 63, 1 08 proposes to first form a wire and the plug above it, and then place a phase between the wire and the plug. Filling the dielectric layer 'can avoid the above problems, but this method still has alignment problems when generating wires and plugs. Due to the lack of conventional technology, the present invention has a spirit of perseverance and excellence in research. In order to improve the problem of excessive capacitive coupling effect between wires and the inability to effectively align in the conventional technology, the final research and development The process of forming a self-aligned multiple interconnect structure in the present case is expected to effectively solve the shortcomings in the conventional technology.

$ 6 pages 4443 35 I. Description of the invention (4) The process of the connection structure can form self-aligned plugs and wires to avoid short circuits or leakage caused by poor alignment. Another object of this case is to provide a process for forming a self-aligned multiple interconnect structure, which can effectively reduce the capacitive coupling effect between the wires. Another object of the present case is to provide a process for forming a self-aligned multiple interconnect structure. The obtained plug has a complete contact surface with the wire, reduces the contact resistance, and facilitates electrical conduction. According to the purpose of this case, 'to form a multiple interconnect structure, the manufacturing process includes the following steps: (a) providing a semiconductor substrate containing a metal-oxygen half field effect transistor element; (b) generating a first conductive layer over the semiconductor substrate Layer; (c) forming a plug post over the first conductive layer; (d) removing a portion of the first conductive line that is not covered by the plug post, and the remaining first conductive layer is the first conductive line, so A wire can be self-aligned with the plug post to form a dielectric layer over the semi-finished product obtained in the previous step; (f) planarize the dielectric layer to facilitate subsequent processes while exposing the top of the plug post; and (g ) A second wire is formed on the top of the plug post. According to the above conception, the plug post in step (c) is a tungsten plug, and its formation includes steps: (cl) forming a metal tungsten layer over the first conductive layer, and (c2) forming a first layer on the metal tungsten. A photoresist layer; (c3) using the first photoresist layer as a mask to etch a part of the metal tungsten layer not covered by the first photoresist layer, and the remaining metal tungsten layer is a tungsten plug; and (c4) Remove the first photoresist layer. According to the above concept, the formation of the first conductive line in step (d) includes the step. (Dl) forming a second photoresist layer on the plug post; (d2) using the second

4443 3 5

The photoresist layer is a first conductive wire that is masked, and a portion of the first conductive layer that is not covered by the second photoresist layer is etched is the first conductive line; and (d3) the second photoresist layer is removed. In addition, the second light formed in step (dl) must completely cover the plug pillar. According to the above conception, the planarization of the dielectric layer in step (f) includes the steps: (fi) forming a layer above the dielectric layer. A trench filling layer, forming an air gap between the first wires, and then partially flattening the dielectric layer; and (f2) etching the trench filling layer until the top of the plug pillar is exposed to achieve comprehensive planarization. According to the above concept, the formation of the second wire in step (g) includes the steps. (Gl) forming a second conductive layer over the dielectric layer; (g2) forming a third photoresist layer over the second conductive layer; g3) Use the third photoresist layer as a mask to etch a portion of the second conductive layer that is not covered by the third photoresist layer, and the remaining second conductive layer is the second wire; (g4) remove the third light Barrier layer. According to the above conception, the materials and forming methods of the layers are described as follows: The material of the conductive layer is preferably aluminum, aluminum-copper alloy or aluminum-copper-silicon alloy, which can be generated by magnetron DC sputtering method and has a thickness of about 5000 Angstroms. Between 丨 〇〇〇〇〇〇〇〇, when etching, the use of four gaseous silicon / gas, boron trie gas / boron tribromide / gas, or four gaseous carbon / gas and other mixed gases for reactive ion etching The material of the plug is preferably tungsten, which can be generated by chemical vapor deposition with a thickness of about 500 Angstroms to 100 Angstroms, and carbon tetrafluoride / oxygen and nitrogen trifluoride / oxygen are used for etching. Or hexadecane sulfur / oxygen mixed gas for reactive ion etching; the material of the dielectric layer is preferably silicon dioxide, silicon nitride, silicon oxynitride, phosphosilicate glass, or borophosphosilicate glass. Pressure chemical vapor deposition, low pressure chemical vapor deposition, or plasma enhanced chemical vapor deposition;

Page 8 4443 3 5 Description of the invention (6) The trench filling layer is a spin-on glass oxide layer or a high-density plasma oxide layer, and the money is engraved by the method of surname or chemical mechanical polishing. According to the above-mentioned concept, the material of the dielectric layer can make the dielectric material with a low step coverage ability, so as to form a void between adjacent first wires, and reduce the capacitive coupling effect between the wires. According to the above idea 'in addition to the main multilayer structure, the following auxiliary layers may be included: 1. Form a barrier layer between the semiconductor substrate and the aluminum-containing layer to avoid spikes' may be a titanium / nitride layer Or Qinhe alloy layer, if it is Qin / ambient Qin layer, then a metal titanium layer is formed by magnetron DC sputtering method, the thickness is between 100 angstroms and 5,000 angstroms, and then nitriding The reaction method or reactive DC sputtering method forms a titanium nitride layer on the metal titanium layer, and the thickness is between 500 angstroms and 100 angstroms; if it is a titanium tungsten alloy layer, a magnetron is used. Generated by DC sputtering. 2. Form an adhesive layer between the metal tungsten layer and the conductive layer to enhance the adhesion between the conductive layer and the metal tungsten layer. 'It can also be a titanium / titanium nitride layer or a titanium town alloy layer. The formation method is as the aforementioned barrier layer.' 3. A layer of engraved stop layer is formed above the plug post, which can be used as the end point of etching during planarization. '4. Form a reflective layer between the conductive layer and the photoresist layer to prevent the photoresist layer from affecting the accuracy of the exposure due to the gloss of the conductive layer during exposure. It can be a nitride layer. Spontaneous sputtering. This case can be understood in more detail through the following drawings and detailed description of the preferred embodiment:

Page 94443 3 5 V. Explanatory Notes (7) The first picture is a schematic diagram of a typical multi-connector structure; the second (A) ~ (C) is a conventional multi-connector structure. The schematic diagram of the main steps; and the third step (A) ~ (I) are schematic diagrams of the main steps for forming a multiple interconnect structure using the present invention. The main components in the figure are marked as follows: 2 > 1 1: Semiconductor substrate 3 ′ 4: Tungsten metal layer 3a 4 a 1 · Plug post 7, 8 '1 6:: Pore 9 _ · 14 :: Plug 17 18 丨: Via window 61 62 64: Adhesive layer 63 65 • Anti-reflective layer The invention was revealed-a self-forming process can reduce the capacitance between the wires and avoid the alignment problem in the conventional method. Please refer to the third figure. The third figure is a schematic diagram of the main steps of utilization. 10: conductive layer, 10a, 12, 13: Wire 15: Dielectric layer trench filling layer, 51, 52, 53, 54: Photoresist layer: Barrier layer: Etch stop layer Alignment effect of multiple interconnect structures, and its self-alignment Structure which led to the phenomenon of short circuit or leakage. To form a multiple interconnect structure according to the present invention, please first refer to the third figure (A). A conductive layer 3 is formed on a semiconductor substrate 2 containing a gold-oxygen half field effect transistor element (not shown on the cymbal). The thickness is approximately 5000 Angstroms to 10,000 Angstroms, this layer of conductive layer 3 will become a wire later. The material of conductive layer 3 is mostly aluminum. This is because aluminum has good conductivity and good adhesion to silicon dioxide, but because aluminum has electricity Migration

Page 10 1443 3 5 V. Explanation of the invention (8) (electromigration), so the use of copper or copper-silicon-containing aluminum alloy 'Conductive layer 3 is formed using magnetron DC sputter ing' The temperature is controlled between room temperature and 500 ° C. In addition, because silicon has a certain solid solubility for aluminum at about 400 ° C, in order to prevent silicon from entering the aluminum layer by diffusion, causing a spike (spike) phenomenon and a short circuit, it is necessary to firstly use the semiconductor substrate 2 (mostly A barrier layer 61 is formed between the silicon substrate) and the conductive layer 3. The material of the barrier layer 61 is mostly titanium / titanium nitride or titanium tungsten. First, a layer of metal is formed by magnetron DC sputtering method. The titanium layer has a thickness of about 100 Angstroms to 500 Angstroms. Next, the wafer can be placed in an environment containing nitrogen or ammonia, and the titanium metal can be nitrided to Ti11 by high temperature, or by reactive quenching. (Reactive sputtering) A layer of titanium nitride is deposited directly on the metal titanium layer, with a thickness of about 500 Angstroms to 100 Angstroms. As for the titanium tungsten alloy layer, it is generated by magnetron DC sputtering. Next, a plug is formed, and the material of the plug is mostly aluminum or tungsten, because tungsten's high melting point 'while the internal stress is not large' makes it the main plug material in the industry today. First, chemical vapor deposition (chemica 丨 va ρ οr deposition, CVD) was used, and the reaction gas was tungsten hexafluoride, which produced 5000 angstroms to loooo angstroms at 300 eC to 550 ° C and 1 to 100 torr. Of tungsten metal layer 4. At the same time, in order to increase the adhesion between tungsten and other metals, a glue layer 62 is first formed between the tungsten metal layer 4 and the conductive layer 3, and the adhesion layer is mostly a titanium / titanium nitride layer or a titanium tungsten alloy layer. Therefore, the formation method and conditions are the same as the foregoing barrier layer 6 1. After depositing a tungsten metal layer 4, a titanium nitride layer can be deposited as an etching step for subsequent steps.

M43 3 5 I V. Description of the invention (9) '' --- The formation method and conditions of the stop layer 63 are the same as above, and its use will be described later. Then, in order to define the pattern of the plug, a photoresist layer 51 'is square-shaped on the etch stop layer 63, and the pattern is transferred as shown in the third figure. Please refer to the third figure (B), using the photoresist layer 51 as a mask to etch the tungsten metal layer 4 ′ Before this, of course, it is necessary to remove a part of the etching stop layer 63 above the tungsten metal layer 4 to be etched. This is repeated. The tungsten metal layer 4 is etched using reactive ion etching (RIE). The reaction gas can be carbon tetrafluoride / oxygen, nitrogen trifluoride / oxygen, or sulfur hexafluoride / • oxygen. A mixed gas of fluoride and oxygen reacts with tungsten to form a hexafluoride crane to volatilize. The retained metal layer becomes the plug column 4 & and the photoresist layer 51 is removed. Refer to the second figure (C). After forming the plug post 4a, the next step is to form the lower wire. First, a photoresist layer 52 is formed above the plug post 4a. The light is defined according to the pattern of the wire to be formed. The resist layer 52, the photoresist layer usually covers the entire plug post 4a, and at the same time covers a small part of the lower conductive layer 3 'but as the line width is shortened' the definition of the photoresist layer is sometimes not so precise, so there are The photoresist layer 53 does not completely cover the plug post 4a. Then refer to the third figure (D) 'Etching the conductive layer 3 with the photoresist layers 52 and 53 as masks' Using a reactive ion etching method, the reaction gas can be four gaseous silicon / gas, three gaseous boron / gas The mixed gas of gaseous compounds (bromide), boron tribromide / gas, or tetracarbonated carbon / gas, and chlorine gas reacts with aluminum to form a three-gasification inscription, and then volatilizes. The photoresist layers 52 and 53 are removed. When the definition of the photoresist layer 53 is not accurate enough, at this time, the portion of the plug 4a that is not covered by the photoresist layer 53 is only the upper titanium nitride layer.

Page 12 4443 3 5 f Fifth, the description of the invention (ίο) Engraving the 'plug post 4a' will not be affected because the reaction gas used to etch aluminum and the town is not the same. It can be seen from the third figure (D) that the obtained plug post 4a has the largest contact area with the lead wire 3a, which can reduce the resistance of the contact surface, which is particularly beneficial to conduction. Moreover, the plug post 4a and the lead wire 3a are also self-aligned. The alignment method is formed without alignment problems. Please refer to the third figure (E) again, and then fill a dielectric layer 7 between the adjacent wires 3a and the plug posts 4a to isolate the upper and lower wires. There are many kinds of materials that can be used as the dielectric layer 7. There are known silicon dioxide, silicon nitride, oxynitride, phosphosilicate glass (PSG), and borophosphosil icate glass (BPSG), etc., and the formation method includes atmospheric pressure. Atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD) And so on. For example, low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition (400 ° C) can be used to generate the silicon dioxide layer; low-pressure chemical vapor deposition or plasma-enhanced chemical vapor can be used to generate the silicon nitride layer. Vapor deposition, such as when using low-pressure chemical vapor deposition, the temperature is about 70 0 ° C to 800 ° C, the pressure is about 0.1 Torr to 1 Torr, such as the use of plasma to strengthen chemical vapor deposition , The temperature can be lowered below 450 ° c; the silicon oxynitride layer can also be formed by low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. When using low pressure chemical vapor deposition, the temperature is higher than 8 5 0 t : Using plasma-enhanced chemical vapor deposition method, the temperature can be reduced to 4 5 0 t: below; the generated phosphosilicate glass layer can be used

Page 13 4443 3 5 V. Description of the invention (II) Atmospheric pressure chemical vapor deposition method or plasma enhanced chemical vapor deposition method. When atmospheric pressure chemical vapor deposition method is used, the temperature is controlled to about 400 t: about If the plasma enhanced chemical vapor deposition method is used, the reaction temperature is similar to the atmospheric pressure chemical vapor deposition method; the borophosphosilicate glass layer can be formed using the atmospheric chemical vapor deposition method or the plasma enhanced chemical vapor deposition method. Its temperature conditions are similar to the formation of a phosphate rock glass layer. In addition, when using dielectric materials, we must choose materials with low step coverage. That is, we hope that the poor filling will occur, so that most of the dielectric materials will be deposited on the surface 'and form pores 8 between adjacent wires 3a. The internal air can reduce the capacitive coupling effect between the wires 3a. The principle has been described above. Please refer to the third figure (F), which shows a planarization step. A dielectric layer 7 is filled with a gap (f iu) layer 9 in the groove. The material can be coated on glass (spin on glass (Sog) oxide (silicon dioxide), high density plasma (HDP) oxide. The spin-on glass-breaking method first spin-coated a liquid dielectric material on the wafer, such as lysate (Uicate) or siioxane, and uses the fluidity of the dielectric material * to fill the concave Pa. Then the solvent is removed by heat treatment to form a material similar to silicon dioxide; the high-density plasma method is a new type of chemical vapor deposition & line i. The trench filling layer 9 produced by this method is denser, especially when Seeing that it is getting smaller and smaller, the high-density plasma method can provide better step coverage. Then please refer to the third figure (G In order to achieve comprehensive flatness, avoid focusing problems when exposing the photoresist layer, and Affects the accuracy and resolution of the lithographic image, the dielectric material above the plug column must be

Page M 4443 3 5 V. Description of the invention (12) There are two methods for uniform removal, one is called etch back method, and the other is chemical mechanical polishing (CMP). The former is to remove the dielectric material above the plug posts 4a by using an etching method. This method will affect the flatness due to the spacing between the plug posts 4a; the latter is a more commonly used method in the industry today. The method achieves the purpose of flattening. At this time, 'the etch stop layer 6 3 formed in the previous step comes in handy'. Because of the difference in the plasma spectrum of titanium nitride and tungsten, it is easy to judge when the last name is carved or ground. The plug column 4a stops polishing once the polishing end point is detected, and then thoroughly cleans the remaining slurry on the wafer by brushing, spraying, and ultrasonic cleaning. After flattening, you can start to form the upper wire. Please refer to the third figure (H). The steps are the same as forming the lower wire 3 & The formation of the conductive layer 10 (aluminum, aluminum-copper alloy, or aluminum-copper-silicon alloy) and the anti-reflective layer 65, the adhesive layer 64, and the conductive layer 10 have been described in detail above, so they are not repeated here, and it is necessary to form a reflective Layer 65 'This is because the metallic luster of aluminum itself will affect the exposure of the photoresist layer above it, which will affect the accuracy of the lithography. Therefore, a photoreflection layer 65 is formed in the photoresist layer and its inscription: The material is mostly titanium nitride. The formation method is the same as the method of forming titanium nitride mentioned earlier. After the autumn, a photoresist layer 54 is formed according to a desired upper-layer wiring pattern. Finally please = the third picture ⑴, using the photoresist layer 54 as a mask, the last part of the conductive layer 10 is engraved, the remaining method is to use reactive milk can be four gas silicon / gas, three gas rot / gas , Two> stinking delete / qi, or four-qi / bu-broken / stem-stem preparation η · Emulsification% 1 / qi 4 gas (bromide) and gas

Page 15 4443 3 5 V. Description of the invention (〖3) ~~-The mixed gas' remaining conductive layer is the wire 10a, and then the photoresist layer is removed 'to this' to form a multiple interconnect structure This brings us to the complete structure of a self-aligned multiple interconnect. The advantages of the process disclosed in the present invention include the ability to generate self-aligned wire 2 plugs' so that the wire has the largest contact area between the plugs; in addition, a void is formed in the dielectric layer to reduce the capacitive coupling effect between the wires. Without causing short circuit or leakage due to the filling of conductive materials; further, first forming plug posts so that the trenches between the plug posts have a high aspect ratio, which makes it easier to form a dielectric layer with pores ; And the tungsten metal layer that will become a plug is deposited on the conductive layer without any etching step, so there is no need to clean the interface between the tungsten metal layer and the conductive layer. In contrast, the traditional method is to deposit tungsten metal In the etched via window, residues of the etch via window must be left in the via window. 'In order to avoid the reduction of the contact between the plug and the wire', an additional step of cleaning the via window is necessary. ' It can be seen that this process can also simplify the original process. To sum up, this case is characterized in that when forming multiple interconnects, the lower-layer wires, dielectric layers, plugs, and upper-layer wires are generated traditionally first by forming plugs, then by lower-layer wires, and then by dielectric layers. Generating upper-layer wires can not only simplify the original process, but also improve the structural defects of multiple interconnects, which is a process with great application value. In this case, anyone who is familiar with this skill can use any of the techniques to modify it, but it is not as good as the person who wants to protect the scope of the patent application.

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Claims (1)

4443 3 5 VI. Scope of patent application 1 · A process for forming self-aligned multiple meats & k ^ _ interconnected structure 'includes steps, (a) providing half of the guide substrate; (b) in A first conductive layer is formed over the semiconductor substrate. (C) A plug-pillar is formed over the first conductive layer, and a part of the first conductive layer is exposed; (d) the first conductive layer is removed A part of the first conductive line is formed, and a part of the semiconductor substrate is exposed, the first conductive line formed is self-aligned with the plug post; (e) a portion of the semiconductor substrate A dielectric layer is formed over the region and over the plug pillar; (f) planarizing the dielectric layer to expose the top of the plug pillar; and (S) forming a second over the top of the plug pillar Wires to complete the self-aligned multiple interconnect structure. 2 * The process for forming a self-aligned multiple interconnect structure as described in item 1 of the scope of the patent application, wherein the material of the first conductive layer is selected from the group consisting of aluminum, aluminum-copper alloy, and copper-copper stone alloy. one. 3 'The process of forming a self-aligned multiple interconnect structure as described in item 2 of the scope of the patent application, wherein the first conductive layer is formed by a magnetron DC sputtering method, and the thickness is between 5000 Angstroms and Between 10,000 Angstroms. 4. The process of forming a self-aligned multiple interconnect structure as described in item 2 of the patent application scope, wherein before the step (b), the process further includes a step (bl) between the semiconductor substrate and the first A barrier layer is formed between the conductive layers to avoid spikes. surface 4443 3 ο 6. Patent application scope 5. The process of forming a self-aligned multiple interconnect structure as described in item 4 of the patent application scope, wherein the barrier layer is a titanium / titanium nitride layer or a titanium tungsten alloy Floor. 6 * The process for forming a self-aligned multiple interconnect structure as described in item 5 of the scope of the patent application, wherein the formation of the titanium / titanium nitride layer includes the following steps: (bll) using magnetron DC sputtering method Forming a titanium metal layer on a semiconductor substrate, the thickness of which is between 100 angstroms and 500 angstroms; and (b 1 2) forming a nitrogen layer on the titanium metal layer by a nitriding reaction method or a reactive DC sputtering method The titanium layer has a thickness between 50 angstroms and 1,000 angstroms, and the formed double-layer structure forms the titanium / titanium nitride layer. 7. The process of forming a self-aligned multiple interconnect structure as described in item 1 of the scope of the patent application, wherein the plug post is a tungsten plug. 8. The process of forming a self-aligned multiple interconnect structure as described in item 7 of the scope of patent application, wherein in step (c), the formation of the ball plug comprises the following steps: (cl) the first conductive Forming a metal tungsten layer over the layer; (c2) forming a first photoresist layer 'over the metal tungsten layer and exposing a part of the metal tungsten layer; (c3) using the first photoresist layer as a mask, Etching a portion of the metal tungsten layer to form the tungsten plug; and (c4) removing the first photoresist layer. 9 · The process for forming a self-aligned multiple interconnected honeycomb structure as described in item 8 of the scope of the patent application, wherein the metal tungsten layer is formed by chemical vapor deposition, and the thickness is between 500 angstroms and 10 angstroms. 0 0 0 Angstroms. ^ Page 18 4443 3 5 VI. Scope of Patent Application 10 · The process of forming a self-aligned multiple interconnect structure as described in item 8 of the scope of patent application, before the step (Cl), the process further includes a step ( ell) forming an adhesive layer between the first conductive layer and the metal crane layer to enhance the adhesion between the first conductive layer and the metal tungsten layer β 11 formed as described in item 10 of the scope of the patent application Process for aligning multiple interconnect structures' wherein the adhesive layer is a titanium nitride layer or a titanium crane alloy layer. 12. The process for forming a self-aligned multiple interconnect structure as described in item 11 of the scope of the patent application, wherein the titanium nitride layer is formed by a reactive DC method. ‘13. The system for forming a self-aligned multiple internal structure as described in item χi of the scope of the patent application, wherein the titanium-tungsten alloy layer is formed by a magnetron DC sputtering method. 1 4 'The process of forming a self-aligned multi-structure as described in item 8 of the scope of the patent application', wherein the engraving of the metal tungsten layer is based on a reactive ion etching method, and the reactive ion etching gas system is made of carbon tetrafluoride. Selected from the group consisting of oxygen / oxygen, dinitrogen / oxygen, and sulfur hexafluoride / oxygen — chemical i 5. The process of forming a self-meat structure as described in the scope of the patent application, wherein step (d) is more The method includes the following steps: forming a second photoresist layer over the plug pillar (n) and exposing a part of the conductive layer; ♦ the first mis (d2) of the second photoresist The layer is a mask. The first domain is etched, and the remaining first conductive layer forms part of the first conductive region U3) to remove the second photoresist layer.夂 444335 P. Patent application scope " " " " ~ 16. The process of forming a self-aligned multiple interconnect structure as described in item 15 of the patent application scope, wherein the etching of the first conductive layer is performed by reaction The silver ion engraving method is used for this purpose. The reactive ion etching gas system is selected from the group consisting of silicon tetrachloride / gas, tri-gas decomposition / gas, tribromide greenhouse / gas, and carbon tetrachloride / gas. One. 17. The process of forming a self-aligned multiple interconnect structure as described in item 1 of the scope of patent application, wherein step (d) further includes the following steps: (d4) forming a third photoresist layer on the plug post And expose a part of the plug pillar and a part of the first conductive layer; (d5) using the third photoresist layer as a mask, etching a part of the first conductive layer; The first conductive layer forms the first wire; and (d6) removes the third photoresist layer. 18. Form a self-aligned multiple interconnect structure as described in item 1 of the scope of the patent application. The process 'wherein the material of the dielectric layer is self-silicon dioxide' silicon nitride, silicon oxynitride, phosphosilicate glass, and boron One of the groups selected by the phosphosilicate glass. '19 The process of forming a self-aligned multiple interconnect structure as described in item 18 of the scope of the patent application, wherein the formation of the dielectric layer is performed by a normal pressure chemical vapor deposition method, a low pressure chemical vapor deposition method, and One of the groups selected by the slurry enhanced chemical vapor deposition method was selected. 20 The process of forming a self-aligned multiple interconnected complex structure as described in item 18 of the scope of the application for patent, wherein the formation of the dielectric layer is made of a material with low step coverage capability to make the dielectric Layer on the first wire gap to reduce the capacitive coupling effect between the first wires. Page 20 4443 3 5 21 The process of forming a self-aligned multiple interconnect structure as described in item 1 of the scope of the patent application, wherein step (c) further includes a step of forming an etch stop layer over the plug post as the end of the etching process. determination. 2 2 · The process for forming a self-aligned multiple interconnect structure as described in item 21 of the patent application, wherein the etch stop layer is a titanium nitride layer. 2 3 * The process of forming a self-aligned multiple interconnect structure as described in item 21 of the scope of the patent application, wherein step (f) includes the following steps: (fl) forming a trench filling layer over the dielectric layer , Filling in the unevenness of the dielectric layer, and (f 2) removing part of the trench filling layer to the etch stop layer to expose the top of the plug pillar. 24 ‘The process for forming a self-aligned multiple interconnect structure as described in item 23 of the scope of the patent application, wherein the trench filling layer is a spin-coated glass oxide layer or a high-density plasma oxide layer. 25. The process for forming a self-aligned multiple interconnect structure as described in item 23 of the scope of patent application, wherein step (f2) is performed by an etch-back method or a chemical mechanical polishing method. 2 6 · The process of forming a self-aligned multiple interconnect structure as described in item 1 of the scope of the patent application, wherein step (g) includes the following steps: (gl) forming a dielectric layer over the planarized dielectric layer A second conductive layer; (g2) forming a fourth photoresist layer over the second conductive layer, and aligning the fourth photoresist layer with the plug post; (g3) using the fourth photoresist layer as Mask, and etch the second conductive part area, and the remaining second conductive layer is 4443 3 5 Factory 6. Shen ^ ------- (g4) Move 2 * The fourth photoresist layer. The process of forming self-aligned multiple interconnected gold as described in item 26 of the scope of the patent application, the material of the second conductive layer is selected from the group consisting of aluminum, aluminum-copper and 28'-face silicon alloy. Pick one. The line wording is a process for forming a self-aligned multiple interconnected shovel as described in item 27 of the scope of the patent application, wherein the formation of the second conductive layer is magnetron DC sputtering, and its thickness is between 500 and 500. Between Angstrom and 10,000 Angstroms. · As described in item 27 of the patent scope, a process of forming a self-aligned multiple interconnect $ structure, wherein before the step (gl), the process further includes a step / gll between the second conductive layer and the A “barrier layer” is formed between the plug posts to avoid spikes. 30 ′ The process of forming a self-aligned multiple interconnect structure as described in item 29 of the scope of the patent application, wherein the barrier layer is a titanium / titanium nitride layer or a titanium tungsten alloy layer. 31. The process for forming a self-aligned multiple interconnect structure as described in item 27 of the scope of patent application, wherein a step (g21) is further included in the fourth photoresist layer and the second before the step (g2). A reflective layer is formed between the conductive layers to avoid affecting the accuracy of the fourth photoresist layer exposure during lithography. 32. The process of forming a self-aligned multiple interconnect structure as described in item 31 of the scope of the patent application, wherein the anti-reflective layer is a titanium nitride layer. 3 3 · The process of forming a self-aligned multiple interconnect structure as described in item 32 of the scope of patent application, wherein the titanium nitride layer is formed by a nitriding reaction method or a reactive DC sputtering method. 3 4 * Form self-aligned multiple interconnects as described in item 1 of the patent application Page 22 443 3 5 VI. Scope of Patent Application Structure manufacturing process, transistor element. The semiconductor substrate is made of a plurality of metal-oxygen half-field-effect interconnect structures to form a multi-pass with low capacitance light-on effect. It includes the steps of: (a) providing a semiconductor substrate; (b) in A plurality of first wires are formed above the semiconducting substrate; (c) a plurality of plug posts corresponding to the first wires are formed above the plurality of first wires; (d) are filled between the plurality of first wires A dielectric material with a low step coverage ability forms a dielectric layer, and causes the dielectric layer to form a pore between the plurality of first wires to reduce the capacitance facet effect between the plurality of first wires, (e ) Planarizing the dielectric layer ′ to expose the top of the plug post; and (f) forming an alignment structure aligned with the helmet terminal above the top of the plurality of plug posts. Page 23