4-36992 五、發明說明（1) 種 本發明係有關一種積體電路製程，特別是有關於 用於記憶陣列之自我對準源極連線製造方法。 傳統記憶陣列係包括複數個排列之電晶體，形式係如 第1圖所示，隔離氧化層0X係用以隔離出主動區，而由複 晶矽等導電材料構成之字元線WL則跨於主動區卜， 此*外於 字元線WL兩侧之主動區上係透過離子摻雜步驟形成源極區 S和汲極區D ’其中’由於源極區S —般係電性連接 電壓如接地電壓，因此必須切斷隔離氧化層〇χ以保持各電 晶體之源極區S電性連接至源極電壓，因此，隔離氧化層… 0Χ之製作必須考量閘極字元線WL彼此間之間距C，其包^ 隔離氧化層0X在源極區8上之間距0及隔離氧化層〇χ'距^問極 字το線WL之距離a，使得源極接觸窗之大小在傳統技術中 亦必須保持較大之尺寸，不利集積度的提高。 之自I5進ί ί 3:之一目的，在於提供一種用於記憶陣列 、線製造方法，以避免上述問題的產生。 病對進ί ί i Γ的，本發明提供一種用於記憶陣列之自 赛、」彳’後製造方法，包括下列步驟。首先依序形成 導電層於基底上；然後形成-第-罩幕 ^ ^ 2 出部分第一導電層表面之數個第一開口；操 二絕緣層於此些第-開口内；形成第二導電層， 2具有露出部分第一罩幕層及相鄰第二絕緣層表面之第二 二：土ίΐ第二開口内之第一罩幕層以露出第-導電層； 出之第一導電層及第二導電層以形成一露出基 一 一開口’透過第三開口進行源極離子植入形成源極4-36992 V. Description of the invention (1) This invention relates to an integrated circuit manufacturing process, and particularly to a method for manufacturing self-aligned source wiring for a memory array. The traditional memory array system includes a plurality of arrayed transistors. The form is shown in Figure 1. The isolation oxide layer 0X is used to isolate the active area, and the word line WL made of conductive material such as polycrystalline silicon crosses The active region, the source region S and the drain region D are formed through the ion doping step on the active regions on both sides of the word line WL, where the source region S is generally electrically connected to the voltage such as Ground voltage, so the isolation oxide layer χ must be cut off to keep the source region S of each transistor electrically connected to the source voltage. Therefore, the production of the isolation oxide layer 0 × must consider the gate word line WL between each other. The distance C includes the distance a between the isolation oxide layer 0X on the source region 8 and the distance 0 between the isolation oxide layer 0x ′ and the distance WL between the pole word το line WL, so that the size of the source contact window is also in the conventional technology. It must be kept larger in size, which is not conducive to the improvement of the degree of accumulation. One of the goals of I5 is to provide a method for manufacturing memory arrays and lines to avoid the above problems. In the case of disease, the present invention provides a self-matching and post-manufacturing method for a memory array, which includes the following steps. Firstly, a conductive layer is sequentially formed on the substrate; then, a plurality of first openings on the surface of the first conductive layer of the -th-mask ^ 2 are formed; two insulating layers are formed in the first openings; and a second conductive layer is formed. Layer 2 has a second second layer that exposes part of the first cover layer and the surface of the adjacent second insulating layer: the first cover layer in the second opening to expose the first conductive layer; and the first conductive layer and The second conductive layer is formed with an exposed base and an opening, and the source ion is implanted through the third opening to form a source.
ΙΗ 第4頁 Δ36 9 92 五、發明說明（2) 區；於第三開口内形成第一絕緣間隔層. 源極區之第三導電層以填滿第三開口 ，丄^ '電性連接至 連線之製造，然後進行後續記憶陣列製=。我對準源極 為讓本發明之上述和其他目的、牿 顯易懂，下文特舉—較佳實施例，並配：所：m明 細說明如下： 口所附圖式’作詳 圖示之簡單說明： 第1圖係顯示傳統記憶陣列之上視圖。 第2A圖至第21圖係顯示本發明之—實施 準源極連線之製造流裎剖面圖。 自我對 第2G，圖至第21，圖係顯示本發明之另_實施例 我對準源極連線之部分製造流程剖面圖。 第3圖係顯示依據第2人圖至第21圖或第％， 剖面圖完成之用於記憶陣列之自我對準源極連線 符號說明： ^ 100〜半導體基底；120~氧化層；140〜複晶矽層；16〇〜 I化矽層；180〜氧化層；22 0〜絕緣間隔層；24〇〜複晶矽 一，26 0〜光阻層；260’ ~氧化層；28 0〜絕緣間隔層；WL〜字 元線；S〜源極區；d〜汲極區。 實施例： 一請參照第2 A圖至第2 I圖，其所繪示為本發明所提出之 :較佳實施例，其中用於記憶陣列之自我對準源極連線製 方法’包括下列步驟。 mΙΗ Page 4 Δ36 9 92 V. Description of the invention (2) region; a first insulating spacer layer is formed in the third opening. A third conductive layer in the source region fills the third opening, and is electrically connected to Connect the manufacturing, and then follow-up memory array system =. I aim at the source to make the above and other objects of the present invention obvious and easy to understand. The following is an example of the preferred embodiment, and is equipped with the following: The detailed description is as follows: Note: Figure 1 shows the top view of a traditional memory array. Figures 2A to 21 are sectional views showing the manufacturing flow of the implementation of the quasi-source connection of the present invention. Self-alignment 2G, Figures 21 to 21, the figure shows another _ embodiment of the present invention, a cross-sectional view of a part of the manufacturing process where the source line is aligned. Figure 3 shows the self-aligned source connection symbol descriptions for the memory array completed according to the second figure to the 21st or 21st percentile: ^ 100 ~ semiconductor substrate; 120 ~ oxide layer; 140 ~ Polycrystalline silicon layer; 160 ~ I silicon layer; 180 ~ oxide layer; 220 ~ insulating layer; 240 ~ polycrystalline silicon 260 ~ photoresist layer; 260 '~ oxide layer; 28 ~~ insulation Spacer layer; WL ~ word line; S ~ source region; d ~ drain region. Embodiment: First, please refer to FIG. 2A to FIG. 2I, which are shown in the present invention: a preferred embodiment, in which a self-aligned source connection method for a memory array includes the following step. m
IHI 第5頁 Γ Λ36992IHI Page 5 Γ Λ36992
五、發明說明（3) 首先依據第2Α圖，提供一半導體基底1〇〇 ’例如一ρ型 半導體材質之基底。 然後於基底1 0 0上依序形成一絕緣層1 2 0，例如是以敎 氧化法生長之氧化層、以及一導電層1 4 0，例如是以化學 氣相沈積製程沈積並摻入雜質之摻雜複晶矽層。 接著，形成一罩幕層160，其具有露出部分導電層14〇 表面之第一開口 1 6 2，例如，先以化學氣相沈積製程形成 一氮化矽層1 6 0，然後利用微影及蝕刻製程定義氮化妙 層’形成露出部分摻雜複晶矽層140表面之第一開〇162。 請參閱第2Β圖，填滿一絕緣層1 80於前述第一開α i 62 内，例如’先利用化學氣相沈積製裎全面沈積一氧化層 1 8 0並填滿第一開口丨6 2，然後實施一平坦化製裎，例如對 氧化層1 8 0進行回姓刻或化學機械研磨，露出氮化矽’ 之罩幕層160、160’。 貞 叫參閱第2C圖，形成一導電層2〇〇，其具有露出 氮化矽材質之罩幕層160,及相鄰絕緣層丨8〇表面之第二 =1 6 4例如先利用化學氣相沈積製程全面性沈積一薄 :t :2』0」「然後利用微影及蝕刻製程定義複晶矽層200， 形成露出氮化石夕材質之第-罩幕層_，及相 鄰氧化層180表面之第二開口164。 請參閱第2D圖 露出導電層140之部 1 8 0為蝕刻保護層， 1 6 4内之以氮化石夕為 去除第二開口164内之罩幕層160，以 分表面’例如以複晶矽層20 〇、氧化層 利1熱磷酸溶液濕蝕刻去除第二開口 材為之罩幕層16〇，’露出以摻雜複晶V. Description of the invention (3) First, according to FIG. 2A, a semiconductor substrate 100 ', such as a p-type semiconductor material substrate, is provided. Then, an insulating layer 120 is sequentially formed on the substrate 100, such as an oxide layer grown by a hafnium oxidation method, and a conductive layer 140 is deposited, for example, by a chemical vapor deposition process and doped with impurities. Doped polycrystalline silicon layer. Next, a mask layer 160 is formed, which has a first opening 16 2 that exposes part of the surface of the conductive layer 140. For example, a silicon nitride layer 160 is first formed by a chemical vapor deposition process, and then a lithography and The etching process defines the nitrided layer ′ to form a first opening 162 that exposes a part of the surface of the doped polycrystalline silicon layer 140. Referring to FIG. 2B, an insulating layer 1 80 is filled in the aforementioned first opening α i 62. For example, “the first step is to use chemical vapor deposition to deposit an oxide layer 1 8 0 and fill the first opening 丨 6 2 Then, a planarization process is performed, for example, the oxide layer 180 is etched back or chemical mechanically polished to expose the mask layers 160 and 160 'of silicon nitride. Referring to FIG. 2C, a conductive layer 200 is formed. The conductive layer 200 has a masking layer 160 exposing a silicon nitride material, and a second surface of the adjacent insulating layer 丨 80. For example, a chemical vapor phase is used first. The deposition process comprehensively deposits a thin layer: t: 2 "0", and then uses the lithography and etching processes to define the polycrystalline silicon layer 200 to form the first mask layer_ which exposes the material of the nitride stone, and the surface of the adjacent oxide layer 180. The second opening 164. Please refer to FIG. 2D. The exposed part of the conductive layer 140 is an etching protection layer, and the nitride layer is used to remove the mask layer 160 in the second opening 164. 'For example, the polycrystalline silicon layer 20, the oxide layer 1 hot phosphoric acid solution wet etching to remove the second opening material as the mask layer 16O,' exposed with doped polycrystalline
第6頁 436992 五、發明說明（4) 矽層為材質之導電層14〇之部分表面。 明參閱第2E圖’接著去除導電層2〇〇及開口内露出之 ，電層1 40以形成一露出基底】〇〇之第三開口〗66 ^例如以 氧化層1 8 0和氮化矽罩幕層】6 〇為蝕刻保護層，利用非等向 性蝕刻製程如乾蝕刻去除複晶矽導電層2〇〇和開口内之摻 雜複晶矽材質之導電層14〇，形成一露出部分基底1〇〇表面 之第三開口 1 66，接著透過第三開口 1 66進行源極離子植入 形成一^原極區s。 α參閱第2F圖’先於第三開口 i 66内形成一絕緣間隔 層220，然後形成一電性連接至源極區5之導電層^❶以填 ϊίίτ1σΛ66 °例"V先利用化學氣相沈積製程順應性 / 軋化層或氧化層/氮化矽層/氧化層，然後進行 回蝕刻形成一絕緣間隔層2 2 〇。 24二第先三利二^ fll Γ#40/ ^ ^ # ^ ^ ^ ^ ^ ^ Uf〇 和虱化矽材質之罩幕層16〇。 * 乳匕層180 線之製造，然後進行後續記憶陣^製^成我對準源極連 清參閱第2G圖，形成另—覃i ‘· 240。例如，&塗佈—光阻材料，，蓋導電層 圖案化光阻層為材質之罩幕層：霜’：後’留下以 絕緣層180和複晶矽材質之導電層24〇藉此覆盘氧化材質之 請參閱第2H圖，該步驟為 層180及光阻材料之罩幕層之絕緣 ^刊用非等向 43^992 五、發明說明（5) 14姓刻裟程如乾银刻方式依序去除氮化妙材質之罩幕層 ⑽及複晶石夕材質之導電層140以形成字元線WL:及 定形成汲極區之部分基底100的第四開口168，接著， 剩餘之圖案化光阻層2 6 〇。 ” 請參閱第21圖，透過此第四開口168進行汲極離子植 入形成-汲極區D ’並於第四開口168内之字元線叽側壁形 成-絕緣間隔層，例如先利用化學氣相沈積製程順應性沈 積-TEOS氧化層或氧化層/氣化石夕層/氧化層，然後進行回 蝕刻形成一絕緣間隔層2 8 0。 此外，請參閱第2G,至第21，圖，其顯示本發明之另_ 實施例，其中，相同編號代表相同元件，於此不再贅述。 首先，請參閱第2G，圖，本實施例形成另一罩幕層 2 6 0之方式，係選擇以熱氧化法於複晶矽材質之導電層 240表面生成一氧化材料之絕緣層26〇，。 請參閱第2H，圖，該步驟為選擇以前述氧化材料之絕 緣層1 80、26 0’為蝕刻保護層，利用非等向性蝕刻製程， 如乾蝕刻方式依序去除氮化矽材質之罩幕層16〇及複晶矽 材質之導電層140以形成字元線WL、及露出預定形成沒極 區之部分基底100的第四開口168 ’接著去除以熱氧化 成之絕緣層2 6 0 ’ 。 請參閱第2 I ’圖’透過此第四# 口 ！ 68進行没極離子植 入形成-汲極區D，並於第四開口168内之字元線叽側壁形 成一絕緣間隔I，先利用化學氣相沈積製程順應性沈積一 TEOS氧化層或氧化層/氮切層/氧化$，然後進行回敍刻Page 6 436992 V. Description of the invention (4) The silicon layer is part of the surface of the conductive layer 14 of the material. Refer to FIG. 2E for details. Then, the conductive layer 200 is removed and the opening is exposed, and the electrical layer 1 40 is formed to form an exposed substrate. The third opening is 66. For example, an oxide layer 180 and a silicon nitride mask are used. [Curtain layer] 6 is an etching protection layer. The non-isotropic etching process such as dry etching is used to remove the conductive polycrystalline silicon layer 200 and the conductive layer 14 doped with the polycrystalline silicon material in the opening to form an exposed part of the substrate. The third opening 1 66 on the 100 surface, and then performing source ion implantation through the third opening 1 66 to form a primary region s. α Refer to FIG. 2F. 'An insulating spacer layer 220 is formed in the third opening i 66 first, and then a conductive layer electrically connected to the source region 5 is formed to fill in ττ1σΛ66. Example " V first uses a chemical vapor phase The process compliance / rolled layer or oxide layer / silicon nitride layer / oxide layer is deposited and then etched back to form an insulating spacer layer 2 2 0. 24 2nd first benefit 3 ^ fll Γ # 40 / ^ ^ # ^ ^ ^ ^ ^ ^ Uf〇 and the cover layer of silicon material 16〇. * Manufacture of 180 lines of milk dagger layer, and then carry out subsequent memory array ^ system ^ I aligned the source connection. Refer to Figure 2G to form another-Qin i ‘· 240. For example, & coating-photoresist material, the conductive layer is patterned and the photoresist layer is used as the cover layer of the material: frost ': back' leaving the insulating layer 180 and the conductive layer 24 made of polycrystalline silicon. Please refer to Figure 2H for the coating material. This step is the insulation of the layer 180 and the cover layer of the photoresistive material. ^ Publication is non-isotropic 43 ^ 992 V. Description of the invention (5) 14 Surname process such as dry silver The mask layer ⑽ of the nitrided material and the conductive layer 140 of the polycrystalline stone are sequentially removed to form the word line WL: and the fourth opening 168 which defines a portion of the substrate 100 forming the drain region. Then, the remaining pattern Photoresist layer 26. Please refer to FIG. 21, through this fourth opening 168, a drain ion is implanted to form a drain region D ', and an insulating spacer is formed on a side wall of a zigzag line in the fourth opening 168. For example, a chemical gas is first used. Phase deposition process conformably deposits-TEOS oxide layer or oxide layer / gasification stone layer / oxide layer, and then etch back to form an insulating spacer layer 2 0. In addition, please refer to 2G, to 21, the figure, which shows Another embodiment of the present invention, in which the same number represents the same element, will not be repeated here. First, please refer to FIG. 2G, FIG. This embodiment forms another cover layer 2 60, which is selected by thermal The oxidation method generates an insulating layer 26 of an oxide material on the surface of the conductive layer 240 made of polycrystalline silicon. Please refer to FIG. 2H, this step is to select the insulating layer 1 80, 2 0 ′ of the foregoing oxide material for etching protection Layer, using an anisotropic etching process, such as a dry etching method to sequentially remove the silicon nitride mask layer 16 and the polycrystalline silicon conductive layer 140 to form word lines WL and expose the electrodeless region to be formed Part of the substrate 100's fourth opening 168 ' In order to remove the thermally oxidized insulating layer 2 6 0 ′, please refer to FIG. 2 I 'FIG.' Through this fourth # port! 68 to perform electrodeless ion implantation-drain region D, and in the fourth opening 168 A zigzag line 叽 side wall forms an insulating gap I. A TEOS oxide layer or an oxide layer / nitrogen cut layer / oxidation layer is first deposited in conformity with the chemical vapor deposition process, and then etched back
第8頁 436 ^ 92 五'發明說明（6) ' -- 形成一絕緣間隔層280。 傳圖’其顯示第21、21，圖之上視圖，以其與 化層ΟΧ二伴姓1圖比較，於第1圖中’由於必須切斷隔離氧 源極區s電性連接至源極電壓，因此，隔離 ?作必須考量閘極字元㈣彼此間之間距c， π二±5；二離氧化層0X在源極區S上之間距b及隔離氧化層0X ” J子元線WL之距離a ’亦即接觸窗之大小在傳統技術 :幻f保持較大之尺寸’不利集積度的提高…，第3 二2、*我對準源極S係利用上*複晶石夕材質之導電層24 0來 陪雜鬼接至源極電壓，因此，隔離氧化層0X可以直接用來 =源極區S而不必考量前述之製程容許度，亦即源極接 觸®之大小可以縮減。 Β ίί本發明已以較佳實施例揭露如上，然其並非用以 和範園^明丄任何熟習此技藝者，在不脫離本發明之精神 圍内’當可作更動與潤飾’目此本發明之保護範圍當 視後附之申請專利範圍所界定者為準。Page 8 436 ^ 92 Five 'Explanation of Invention (6)'-Forming an insulating spacer layer 280. "Transfer" shows the 21st, 21st, top view of the figure, and compares it with the 1st layer of the chemical layer 0x, and in the 1st figure, 'the oxygen source region s must be electrically connected to the source because the isolation oxygen source region s must be cut off Voltage, therefore, the isolation operation must take into account the distance between the gate characters ㈣ between each other, c, π two ± 5; the distance b between the oxide layer 0X on the source region S and the isolation oxide layer 0X ”J sub-element line WL The distance a ', that is, the size of the contact window is in the traditional technology: the size of the f is kept large, and the unfavorable accumulation is improved ... The conductive layer 240 is used to accompany the ghost to the source voltage. Therefore, the isolation oxide layer 0X can be directly used as the source region S without having to consider the aforementioned process tolerance, that is, the size of the source contact ® can be reduced. Β ί The present invention has been disclosed as above in a preferred embodiment, but it is not intended to be used by Fan Yuan ^ Ming 丄 anyone skilled in this art, and should not be altered and retouched without departing from the spirit of the present invention. The scope of protection shall be determined by the scope of the attached patent application.
第9頁Page 9