TW432334B - Virtual computer certification platform - Google Patents

Abstract

The certification platform is applied with clock-based simulation method, providing the certification environment for newly developed microprocessor chip, firmware and peripheral chip. The entire design of the certification platform employs an object-oriented design planning that simulates the provided function of actual personal computer on the computer workstation. The main body of the simulation system comprises four layers: (1) peripheral device, (2) chipset of motherboard, (3) bus interface command and protocol and (4) microprocessor. Among them, except the certification microprocessor actually implemented by high level hardware description language verilog, elements of the rest of three layers are designed with object-oriented programming in accordance with the interface command and protocol of actual simulated elements. The implementation of the three layers are done with the C++ programming language. The part of the certification platform implemented with C++ programming language can be easily integrated with the microprocessor model described by high level hardware description language, such as verilog, and the programming language interface (PLI) provided by verilog to form an environment for function certification and diagnostics through the inter-process communication (IPC) of UNIX. The certification platform is presented with an user-friendly window interface by motif of X-windows. The major purpose of certification platform consists of the following categories: (1) microprocessor chip is designed on three layers to form the function certification and diagnostic tool and environment for behavior model, RTL model and gate model; (2) the development and simulation tool for the operating system development and transplantation of the newly developed microprocessor and the low level firmware BIOS; (3) simulation and certification tool and environment for the newly developed computer peripheral chip.

Description

432334 V. Description of the invention (1) — This case is a virtual verification platform ', especially a virtual computer verification platform. For the research and development of technology related to the verification platform of virtual computer, before we proposed this simulation architecture, there was a virtual computer platform developed by South Korea to verify the Intel 80486 Aitani microprocessor. The concept and technology used in this platform lies in the Instruction-Based simulation method, which uses a single instruction cycle completion time to simulate and calculate the work events that peripheral devices should complete. The advantage of this simulation method is that the execution of simulated microprocessor instruction behavior is fast. The disadvantages are: (1) lack of verification of the correctness of the signals between the microprocessor and the surrounding protocols; (2) the microprocessor design on the platform needs to be designed in a behavioral model implemented in a similar C programming language (Behavi 〇r Model), which is far from the actual microcomputer chip circuit; (3) because the instruction cycle simulation method is used in the architecture, it is impossible to provide the microprocessor description description level (RTL Lev e 1), and the gate Level circuit description level (Gate Level) verification function; (4) its underlying architecture is not simulated with a single component function, causing difficulties in expanding the overall peripheral device of the system or changing the periphery to match the verification of different microprocessors; (5) unable to provide Peripheral device signal response and status to provide debugging capabilities for microprocessor chip circuits. The purpose of the present invention is to implement a software virtual computer verification platform to assist the design of microprocessors, the early development of system software and low-level control firmware, or the development of computer peripheral chips. The invention was first successfully applied to verify the Intel x86 compatible microprocessor microarchitecture and its subsequent development, and it also has the same important assistance for the development of other microprocessors.

V. Description of the invention (2) The development and transplantation of the new system of the microprocessor completed by the ri0g hardware description language. The development of the in-line system of the low-level moving body development such as the S system is more advanced: the advancement of the S system development cycle. '& Point can also provide an effective replacement verification environment for verifying newly developed computer peripheral chips embedded in this verification platform. In order to achieve the above purpose, the virtual computer verification platform proposed in this case includes: a virtual computer simulation system which is used to simulate a function, interface agreement and a timing of a computer motherboard and peripheral devices to provide: (a ) A microprocessor chip is designed for integration verification and debugging at three levels: a Behavior Mode register description mode (RTL Mode) and a gate mode (Gate Mode). (2) — System software and a firmware development, debugging and verification environment, (c) a computer peripheral chip simulation and verification environment and a set of online debugging assistance tools, which are electrically connected to the virtual computer simulation system for During the microprocessor simulation, the peripheral device content is modified in real time to assist the microprocessor in debugging. As described in the microprocessor design verification platform, the virtual computer simulation system may include: a special function that integrates a microprocessor chip and a virtual computer simulation system, and the special function provides a generalized general interface so that The microprocessor chip design implemented by a Veri log program can easily communicate the microprocessor interface signals through UNIX's inter-stroke communication (inter_pr〇cess

^ 1323 3 ^ ______ V. Description of the invention (3)

Communicat i on) mechanism, which is passed to the virtual computer peripheral chip simulation system executed on another trip; a shared sequential circuit embedded with a microprocessor chip, which is responsible for generating the virtual computer simulation system and the microprocessor chip Synchronize the timing between them, and collect the interface signals generated by each timing cycle of the microprocessor, and then send the positive and negative edges of each synchronization timing cycle to the virtual computer outside the microprocessor chip by using the special function. Simulate the system and wait for the dual purpose of synchronization and data transmission; ° 'A peripheral chip simulation subsystem that integrates each independent analog peripheral chip component. This peripheral chip simulation subsystem integrates each simulation in an object-oriented planning manner. Chip components to provide the peripheral control chipset functions, interface protocols and timing of the virtual computer simulation system;-integrate the peripheral device simulation subsystem of each independent simulation peripheral device component, this peripheral device simulation subsystem integrates each with an object-oriented planning Simulating device components to provide peripheral equipment of the virtual computer simulation system Function; and a bus command interpreter, the command interpreter is responsible for this bus interpret the command signal from the microprocessor chip agreements and requirements according to their transfer to the periphery of the wafer command requires analog subsystem. The verification platform of the microprocessor design as described, wherein the special function is vpm_call (). As mentioned in the verification platform of microprocessor design, the online debugging aids may include: a window operation interface, this window operation interface is matched with C ++ program—

Page 7 43 23 3 4 V. Description of the invention quot " X-ffindows, a Motif library, a Unix standard system service library and some Per] programming language, __Tci / Tk implementation, responsible for the virtual A display and an input / output operation interface of the computer verification platform as a whole; an editor that can not modify the memory content online in real time for real-time modification during the simulation period of the microprocessor chip; a display and online modification of the hard disk content in real time Editor for real-time modification of the contents of a hard disk simulation component at any time during the simulation period of the microprocessor chip; a set of low-level management tools for the hard disk, this low-level management tool for reading a virtual hard disk Hardware parameter table, low-level formatted hard disk function; a set of MS-DOS 5_0 compatible file system management tools This MS dos 5 · 0 compatible file system management tool can be used to run without an operating system On the virtual computer simulation system and the microprocessor chip, plan the hard disk of the virtual computer simulation system (par titi on & Labe 1 i ng), format the MS-DOS file (Format ting), file copying, file deletion, directory creation, directory deletion and other file system operations. This function helps the operating system device (Installati〇n) of the virtual computer simulation system, and the BIOS a Japanese film writing tool, This Bi0s chip writing tool is used to write a new BIOS image ROM image file into the simulation chip of the virtual computer simulation system, so that the new BI 〇§ will be executed on the virtual computer Simulation system and the microprocessor chip. The software virtual computer verification platform as described above, wherein the virtual computer simulation system and the microprocessor can be used as a system software in application

432334 Fifth, the invention description (5) (including operating systems, and B I os, etc.) development and debugging tools. The software virtual computer verification platform as described, wherein the virtual computer simulation system is completed in conjunction with C ++. The software virtual computer verification platform as described above, wherein the microprocessor is completed with Veri 10g. As described in the software virtual computer verification platform, the virtual computer simulation system and the microprocessor are applied as a verification environment for newly developed computer peripheral chips in the computer system. The software virtual computer verification platform as described, wherein the computer is a personal computer. This case can be understood in more depth through the following diagrams and detailed descriptions: Figure (1): Conceptual logical block diagram of the virtual computer verification platform in this case. Figure (II): The logical block diagram of the virtual computer verification platform in this case. Figure (C): The virtual computer verification platform in this case. Figure (IV). Virtual hard disk simulation components of the virtual computer verification platform in this case. Figure (5) · The virtual hard disk simulation component of the virtual computer verification platform in this case. Figure (6): Virtual memory simulation components of the virtual computer verification platform. Figure (7): The communication interface between the virtual computer and the Verilog simulator.

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The main drawing numbers in the diagram are as follows: 1 1: Virtual remote control Hi I WL% device 12 analog motherboard 13 operating system 14 workstation 15 1 rT hard drive component 16 physical monitor 1 7 keyboard peripheral components 21 bus interpreter Design model Ϊ Ϊ: Carry out inspection of each piece of flat table: The overall system planning system uses objects to guide the function of the physical component;; == a program object implementation to simulate the correct peripheral function ^ boundary check ^ number of orders Λ and State /, with a view to provide = each component is designed with object simulation, so that the programming community can easily modify, maintain and exchange various program objects to meet the needs of the simulation environment. '' The concept of system operation is shown in Figure (1): In this concept map, it mainly includes virtual peripherals 11, analog motherboard 12, Sun Solaris operating system 13, Sun workstation hardware 丨 4, physical hard disk components 15. Physical monitor 16 and keyboard peripheral elements 17 and the like, which present a rough overview of the operation of the simulation system of the virtual computer verification platform. The rightmost box in the figure represents a microprocessor 121. The microprocessor 121 is a behavior model microprocessor (Behavior Model) or a register state transition description model microprocessor completed in Verilog hardware description language. (RTL Model), or Gate Level Model microprocessor.

Page 10 4 3 23 3 4 V. Description of the invention (7) The middle expansion circle indicates that the module H system # € edge control chipset and bus interface 1 22 'It contains a personal computer chipset 1221, memory control Processor 1 2 22 and interrupt / data processor 1 223. Each component in this block 122 is composed of analog components implemented in C ++. The message communication between blocks 122 and 1 21 is based on the Message Passing (UNIX ipC) mechanism and Cadence provided by ϋΝχ

The PLI interface provided by Veri log is completed. These two parts also constitute the simulation part of the personal computer motherboard of this simulation system. The leftmost box in the figure represents the virtual peripheral device 11 of the simulation system in the verification platform, which includes the VPC peripheral ill, the ROM component 112, and the virtual component driver 113. This virtual device π simulates the possible functional actions and states possessed by a physical device, and timely drives the appropriate physical device (such as obtaining a keyboard scan code from a physical keyboard) with a UNIX System Service Call, and receives simulated simulations. Synchronized, occasional chat device information. The exchange of Λ information between this block 11 and the middle personal computer chipset block 221 is completed using the Message Passing mechanism of the UNIX system. Figure (2) shows the logic blocks of the simulation system in the virtual computer verification platform. In the figure, the bus interpreter 21 is the main component connecting the microprocessor 121 and the analog motherboard 12. This component is composed of two bus interface components, 纟 η 〇, and the two damaged components are respectively Yes: (1) Bus interface signal front-end conversion module implemented by Veri] _〇g hardware description language; (II) Bus interface signal back-end interpretation module implemented by C ++ programming language . The type of bus interface can be changed depending on the microprocessor

Page 11 4 3 2-V. Description of Invention (8). At present, this verification platform only has Socket 7 for selection. In the future, it can include more types of bus interface components. The virtual computer verification platform of the present invention adopts a clock-based simulation method. The implementation method of this method is described below. The analog system and the microprocessor chip circuit need to have a common reference timing. There are two ways to generate this timing. The first is that the simulation system of this virtual computer provides the microprocessor with the special timing function vpm_caU () developed by us as a reference timing. The first is to generate synchronous timing by the timing generator extended inside the microprocessor, and to notify the external simulation system through our vpm-ca 1 1 () function to achieve the function of synchronous simulation. In the simulation system of the virtual computer verification platform, the latter simulation method is adopted. The synchronous timing circuit (the circuit is the Socket-7 bus interface element of the simulation system) extended by the microprocessor is positive at each synchronous timing cycle. In the negative and positive margin periods, the simulation data and synchronization messages are sent to the virtual microprocessor simulation system. Any externally-triggered message data, including,, input and output (such as keyboard input), component-triggered events (such as hard disk number 'and / system management interrupt S M1) will be simulated by the analog element; The principle of transmitting positive and negative edges to each component of the τ micro-period in each synchronization cycle is set as a principle. The implementation is to simulate its physical chip movement and implement its objects in the C ++ programming language. level

43 23 ^ 4 V. Description of the invention (9) The subsystem communication interface developed by the platform is integrated with the entire simulation system. The component has the function of debugging and information data collection and display & verification of the microprocessor chip circuit itself and the interface agreement with a wealth of information, and the function of online modification of a single peripheral component asset = for the microprocessor chip circuit Debugging capabilities have a pretty good effect. Take the example of memory components. When we switch the execution mode of the error-prone microprocessor (the ability of real mode to protected mode in Intel x86 compatible microprocessors), we You can easily observe whether the form is normal between the conversion patterns from the system forms stored in the 己 memory body element. If there is a problem, we can try to temporarily change the system form record during the online execution period to help the microprocessor execute ahead. If there are other errors, the debug time of the microprocessor is as short as possible. . These debugging capabilities are especially helpful for the development of low-level software such as operating systems and β 丨 0s. _ In developing these system software, we can not only start system software development, transplantation, and provide rich system debugging information in system software development before the microprocessor physical chip is not yet completed. The concept of applying a virtual computer verification platform to develop system software is unique. The virtual computer verification platform has four main simulation technologies, namely the reference timing simulation method, the object-oriented simulation design method of independent chip component behavior simulation, and the combination of C ++ program components and Verilog program components: generalized communication interface functions : Vpni_call◦, and microprocessor simulation design. These four main analog technologies allow designers of peripheral chips to choose any high-level programming language such as C ++ / C or Veri og to implement their new

Page 13 4 3 23? &Quot;

Fifth, the invention description (ίο) and integrated into our virtual computer verification platform to verify the chip circuit simulation, to verify whether the new design can correctly control the surroundings and cooperate with microprocessors and other fields. This virtual computer verification platform uses X-Windows operation interface, and uses Mot if window component architecture to produce a three-dimensional, easy-to-operate window interface. The appearance of the operation interface applied to a microprocessor design verification is shown in Figure (3). The Power button in the upper left of the two figures is mainly used to start and close the microprocessor simulation system. Pressing the Power button normally will Generate a new process to start Cadence Verilog Simulator to program and execute the RTL Code (or Behavior Code, or Gate-Level Code) of the microprocessor, and start the virtual computer verification platform at the same time to simulate the components of the system Simulation ^, If you are performing a microprocessor behavior simulation, press the power button to turn off the simulation of the microprocessor and the simulation of each component in the simulation system. The function of the reset button in the upper right corner of the figure is equivalent to the function of the RESET key of a physical personal computer host. Pressing the Reset button will cause the virtual computer to send a reset status to the microprocessor and the simulation system of the virtual computer to notify each analog component and request each relevant analog component to handle the corresponding RE SET action. The knowledge arranged on the right side of figure (II) is used to control the simulation behavior of the microprocessor system in the simulation. The Sin button shown on the right side of the figure (3) can simulate the external interruption of the SMI of the host system, forcing the microprocessor to enter the system management mode. The Tools button shown on the right side of the figure (3) can also call many useful

Page 14 432334 V. Description of the invention (π) Auxiliary tools, such as low-level format of the virtual hard disk (Format), MS-DOS compatible FAT file system partition, Labeling, Format, and BIOS installation and other auxiliary tools . ^ Although this virtual computer verification platform was developed under the Solaris operating system and χ-Windows environment on Sun computer workstations, it is easy because the components have clear interfaces and do not use too many special system service calls related to the system. Transplant the source code of this virtual computer verification platform to other operating systems and hardware. And the IPC mechanism of UNIX Message Passing used by each part can be easily converted into the network protocol of the Socket interface, so that the virtual computer verification platform no longer needs to be executed on the same computer as Cadence veril () g Simulator. And they can work together through the Internet. Therefore, the technical features of this case are: 1. The simulation system is planned with an object-oriented design pattern. 2. The simulation method of reference timing (Clock-Based). 3. The actual simulation of each peripheral device and chip action. 4. The new Verification environment for peripheral chips; five, X_Windows operation interface; and six, high portability. The implementation of this case is as follows: (1) The communication function between the general C ++ / C program simulation component and the Verilog program simulation component Vpm_ca 〖l () vpm_call () The function itself is implemented in the high-level C programming language D This function use. \ ^ 1 ^ 1 (^? 1 ^ (? 1 'called 1 ^ 11111111 ^

Language interface) interface standard function cooperates with Vernog Simulator to extract the parameters of Veri log type and convert them into parametric type of c

Page 15 432334 V. Description of the invention (12), then format it to convert it into a binary standard string, and then use the system service call function of Message passing provided by the UNIX operating system to The waiting (B1 ocking) method is transmitted to the running C ++ personal computer simulation system and waits for a reply message from the personal computer simulation system. When the personal computer simulation system responds with the results of this communication message, the vpm_cal 1 () function needs to process the results into Verilog-type parameters, and then return the results to Verilog's Simulator. As shown in Figure (7), the leftmost oval block represents the execution of the device simulation subsystem of the virtual computer simulation system, and the middle oval block represents the execution of the chip simulation subsystem of the Veri log simulator. The box indicates the microprocessor code that will be read, interpreted, and executed by the Verilog simulator. When the virtual computer system is executed, the Veri 10g simulator will read in and resolve the program code of the execution processor. When the code is called, the Verilog simulator will call the vpm_cal 丨 〇 function we wrote, vpm_cal 1 ( ) Will take the necessary parameters, encapsulate it into a message, and then send the message to the UNIX operating system in a message-passing manner as shown by the dashed arrow in the middle of figure (7), and then send the message to the virtual computer waiting for the command The simulation system performs work (PrOcess). After receiving the command, the command interpreter of the virtual computer simulation system will send it to the relevant processing simulation component according to the command request. After the result is obtained, the result message will be sent to the UNIX operation as shown in the outer dashed line in Figure (7). The system then returns the vpm_call to the waiting result. —Call〇 After receiving the result, after processing the format conversion, hand it to the Veri log simulator to complete the whole process.

432334 V. Description of the invention (13) —- a work of vpm-c-all (). The work flow of vpm_caU () is shown in Figure (8). After the three parameter values are ready, vpm —call establishes the IPC port and exchanges information to obtain the reply parameters. (2) The timing-based simulation method adds an extended timing circuit to the analog circuit of the camera processor chip. This circuit is only responsible for two things: (1) generating a microcomputer and a virtual computer simulation. Timing cycle; (2) The microprocessor interface signal is fixedly sent at the positive and negative edges of each shared timing cycle, and synchronously waits for the response information of the virtual computer simulation system. The agreement to send interface signals on the positive and negative edges enables the pseudo-computer simulation system to be suitable for both the event-driven and the cycle-based microcomputer chip circuit design. (3) Simulation of peripheral components with independent C ++ program components Each component of the virtual computer simulation system uses a set of programs to accurately simulate the physical functions, command execution, interface agreement and time sequence of the component. By integrating the functions of these components, we can construct a system environment similar to a physical personal computer system. (4) The simulation system of the microprocessor simulation program, the peripheral chipset simulation program, and the peripheral simulation program is executed in parallel. The simulation system of the virtual computer verification platform adopts the multi-tasking method of multi-tasking systems such as UNIX. In the same way, the Veri log simulator was started to perform the simulation of the microprocessor. At the same time, we also launched the peripheral chipset simulation program of the virtual computer and the peripheral device simulation program of the virtual computer. Each of these three uses our design

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vpm —ca 丨 丨 () and UN 丨 X operating system provide message transfer function to achieve the ability of synchronization and information communication. The features and functions of this case are as follows: (0) This virtual computer verification platform has been implemented and used to verify the development of an X86 compatible microprocessor. In the microarchitecture, behavior mode, register description mode, and logic gate mode development In the process, it plays a lesser role. '' (2) This virtual computer verification platform has high portability, scalability, and organization. 1 'Market value of this case and the competitiveness of related products: The market value of this patent is hereby given. Competitiveness with other similar products is briefly described as follows: A. Description of products with similar functions: al. Microprocessor design verification market: In the microprocessor design verification market, there has not yet been a design with this patent. The software simulation verification platform has similar commercial suite software. In the microprocessor design verification, the verification method currently used by the industry 'is nothing more than the use of hardware simulation to develop or customize its own low-frequency motherboard.' Connected to the microprocessor hardware circuit simulator to deal with the microprocessor interface protocol and control signal problems. Or use a group of software workers To develop its own software simulation environment. A2 · System software and low-level control firmware development market: In the system software and low-level control firmware development market, the more successful products are compatible with the X86 series of Beacon Corporation. Series of embedded products

432334 Five 'invention (15) products, such as VisutalProbe x8 6 Simulator [2] and so on. The characteristic of this product is that it can be operated on Dos / Windows95 / WindowsNT, fast; j; not intended to operate at the command and bus level. a3. In terms of computer peripheral chip development and other markets: According to the data of the largest chipset maker in China, is there no market for auxiliary chipset design yet? re Silicon's verification tool. The current steps are: formulating or researching specifications (Speci f icat i on), making or obtaining chip set test vectors (Test Vectors), wafer fabrication (IC fabrication), making wafer evaluation boards (Eva lat ion board), Start the operating system on the chip evaluation board, execute the test program, try different combinations of microprocessors, memory and I / O, and then debug with tools such as logic analyzers. For these & chip vendors, they look forward to having design tools to provide: (a) pre-production evaluation to shorten the design cycle; (b) verification agreement (Protto); (c) adjustment of design Parameters (such as Buffer Size); (4) optimization; (5) performance evaluation. β · Market Value and Competitiveness: Low Cost and Low Price: In terms of microprocessor design, system software, and development of Ming control firmware, and computer peripheral chip development, other than the hardware simulation platform of this supplier Alternative choice.除 This patented two-body simulation platform has the absolute advantage of low price in addition to the accurate simulation of a moon dagger similar to a hardware simulation platform. G μ. ^ Operation and stable test environment: Compared with hardware simulation, it is more profitable. The software simulation platform developed by 乂 ΐί 利 has easier to handle and easy to handle uploading and downloading programs (unlike the hardware simulation platform,

432334 V. Description of the invention (16), such as re-flashing EEPROM or FLASH ROM, etc.), and the program can be modified online. Unnecessary errors, such as poor interface contact, can be ruled out by the software simulation platform, so that developers can focus more on real functions and timely testing. And when a system error causes a crash, its complete storage and execution of the message status of each component is helpful to the system's debugging, and it can easily reconstruct the environment that caused the system error at that time. _b3 'more ① The entire simulation environment 1 is the embedded system software development market. There are currently simulation platforms developed by companies such as Beacon. Products such as VisualPr0be χ86 SimuUtr developed by Beacon can provide embedded system software developers with simulations at the command and bus level. However, it can only support functional simulation and cannot provide a more accurate timing verification for the operator. "And 'this timing verification is often the most painful part of the industry. In addition, for the collection of peripheral information, VisualPróbe χ86 simulat〇r can only collect a limited portion 'such as memory content, etc.' For large and rigorous systems, it has its shortcomings. b4 · More accurate and adjustable system simulation: products such as xj6 Sjm ^ ulator use the whole system completely based on 匚 or € + +, etc .: Ϊ ί: ί: Therefore, the simulation program every time You have to follow the new system, and go to do ρ 胄 ^. In terms of microprocessors, new specifications of microprocessors have been developed. Operators need to rewrite microprocessors according to the newly acquired microprocessor specifications. T should: Tingqiu :: The result of this approach is a waste of time and labor, and microprocessing T = Accuracy is yet to be confirmed. The platform developed by this patent is: mmenfa :: body description language. This method can directly use microprocessors to produce micromechanical electromechanical%. The industry does not need to rewrite the analog part.

Page 20 432334 V. Description of the invention (17) b5. A wider application market, the virtual computer verification platform developed by this patent can be applied to microprocessor design, system software and low-level control firmware development, and computer peripheral chips Development and other markets, this is not possible with any existing computer design assistance software suite. The final conclusions are as follows: 1. Utilization fields in the industry The virtual personal verification platform in this case can provide three utilization fields in the industry: (1) Provide a verification platform for microprocessor design to assist the verification of micro-frame design. It can provide a complete system environment for its behavior mode, register description mode and logic gate mode, and it can be fully verified. (2) Provide a pre-development platform to assist in the development and debugging of new system software (including operating systems and BIOS, etc.). (3) Provide simulation and verification tools and environment for newly developed computer peripheral chips. 2. Problems to be solved The virtual computer verification platform in this case solves the following six main technical issues. (1) Reference timing simulation method. (2) An object-oriented simulation method for simulating the behavior of independent chip components. (3) The simulation environment of the microprocessor. (4) Combining C ++ program simulation components and VerU〇g program simulation components to communicate information and integrate to complete the simulation work. (5) Graphic operation interface of X-Wind〇Ws window.

Page 21 432334 V. Description of the invention (18) * (6) It is easy to add, delete and modify analog components to form a new analog system.

System D III. Problem-solving technology ^ The benchmark timing simulation system requires a common system timing. We use a timing generator extended inside the microprocessor to generate synchronous timing to inform the analog components of the simulation system. In addition, the object-oriented design mode is used to simulate each peripheral chip component with a single program object, such as ATA Controller chips, hard disks and other personal computer common peripheral devices and chip functions and protocols, and add storage and extraction debugging to each analog component Necessary information and dynamic recording of the status of newly developed microprocessors and peripherals. The microprocessor can be displayed in the platform in three modes: behavior mode, register description mode or logic gate mode. These three modes use high-level hardware description languages (such as Verilog) to build simulation systems. " In solving the problem of information communication and integration simulation between hardware analog components described in different programming languages, we use IPC (Inter-Process Communication) provided by UNI X ^ PLKProgramming Language Interface provided by Cadence Verilog; and developed the applicable The communication function vpm_call () used in the general protocol is to assist the integration of a microprocessor described in a high-level hardware description language (such as Verilog) with a peripheral analog component implemented in a high-level programming language. As for the X-Windows graphical user interface, we use the Motif window component architecture to create a three-dimensional, easy-to-operate window surface. The technology of using independent components to simulate individual solid components, and object guidance

Page 22 432334 V. Description of the invention (19) The way of planning, so that the overall simulation environment has a set of elements and communication interfaces. This approach makes our virtual computer simulation system easy to integrate with new analog components or remove components from the analog system. This case may be modified by any person skilled in the art, but none of them can be protected as attached to the scope of patent application.

Page 23 432334 V. Description of the Invention (20) References: [1] Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park and Chong-Min Kyung, " A C-Based RTL Design Verification Methodology for Complex Microprocessor ", 34th DAC, pp.83-88, 1998.

[2] Beacon Development Tools, Visual Probe x86 Simulator, Product Brief, 1998.

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Claims (1)

4 3 2334 6. Scope of patent application 1. One type (virtual..SIM multi-platform, including: a virtual computer simulation system, which is used to simulate a function, interface agreement and time of a computer motherboard and a peripheral device Sequence to provide: (1) a microprocessor chip design in a behavior mode (Behavior Mode), a register conversion description mode (RTL Mode) and a gate mode (Gate Mode) integration verification on three levels And debugging, (2) a system software and a firmware development, debugging and verification environment, (3) a computer peripheral chip simulation and verification environment, and a set of online debugging assistance tools, which are electrically connected to the Virtual computer simulation system 'is used for real-time modification of the peripheral equipment during the microprocessor simulation. Verify the content of the debugger to assist in debugging the microprocessor. 2. As described in item 1 of the scope of patent application; Taiwan 'where the virtual computer simulation system may include: a special function integrating a microprocessor chip and a virtual computer simulation system' This special function provides a generalized general interface In order to make the microprocessor chip design implemented with a Veri 10g program, the microprocessor interface signal can be easily transmitted through UNI X's Inter-Intercom Communication (Inter_Prcess C0mmun icat i on) mechanism To a virtual computer peripheral chip simulation system that executes on another itinerary; a shared timing circuit embedded with a W processor chip is embedded in the circuit; this circuit is responsible for generating the synchronous timing between the virtual computer simulation system and the microprocessor chip; and After collecting the interface signals generated by each timing cycle of the microprocessor, the positive and negative edges of each synchronous timing cycle are transmitted to the virtual computer simulation system outside the microprocessor chip with the special function, and wait for the result , Page 25 432334_ VI. Scope of Patent Application '---- To achieve the dual purpose of synchronization and data transmission; a peripheral chip simulation subsystem that integrates each independent analog peripheral chip component, and this peripheral chip simulation subsystem is object-oriented planning Integrate each analog chip component to provide the peripheral control chipset functions, interface protocols and timing of the virtual computer simulation system; ^ — Integrate each peripheral device simulation subsystem that independently simulates peripheral components, and this peripheral device simulation subsystem uses The object-oriented planning method integrates various simulation device components to provide peripheral device functions of the virtual computer simulation system. A bus command interpreter is responsible for interpreting protocol signal commands from the microprocessor chip. According to its requirements, it forwards the command request to the peripheral chip simulation subsystem. 3. Please refer to the prepared verification platform described in item 2 of the patent scope, where the special function is Yang ^ ㈡ 丨 丨 ^, Bu 4. The platform described in item χ of the scope of patent application, where the online debugging Auxiliary tools can be packaged ^ A window operation interface 'This window operation program is implemented with an X-Wmdows, a Motif library, a Unix standard system service library, and some Perl programming languages, a Tcl / Tk implementation A display and input-output interface of the virtual computer verification platform as a whole; an editor that displays and instantly modifies the memory content online for instant modification at any time during the simulation period of the microprocessor chip; Hard disk content editor, used to modify the contents of a hard disk simulation component at any time during the simulation period of the microprocessor chip 苐 Page 26 ^ 32334 6. Tools for patent application; A set of low-level management tools for hard disks. This low-level management tool for hard disks has the functions of reading out—virtual hard disk hardware parameter table and low-level formatted hard disks; A set of MS-DOS 5.0 compatible file system management tools. This MS-DOS 5.0 compatible file system management tool can be used to run on the virtual computer simulation system and microprocessor chip without operating system. File system operations such as planning and labeling, MS-DOS file formatting, file copying, file deletion, directory creation, directory deletion, etc. An operating system device (Ins tall a ti on) which is helpful for the virtual computer simulation system; and a BIOS chip writing tool, which is used to convert a ROM image file of a new BIOS program (ROM Image File) is written into the simulation chip of the virtual computer simulation system, so that the new M OS is executed on the virtual computer simulation system and the microprocessor chip. > 5. The pseudo-computer verification platform as described in item 1 of the scope of patent application, wherein the virtual computer simulation system and physical machine can be used as a system software (including operating system, BI 0S, etc.) Development and debugging tools. 6 units, 7 units, 8 As described in the scope of the patent application, the proposed computer verification system is the virtual computer simulation system, and the completer. The processor is cooked in Veri. As described in item 1 of the scope of patent application Ιϋϋ Page 27 432334 VI. Application scope Patent application, in which the virtual computer simulation system and the microprocessor are used as verification loops for newly developed computer peripheral chips in the computer system. territory. 9. The virtual computer verification platform as described in item 8 of the scope of the patent application, wherein the virtual computer simulation system is +. So, the successful person 10, and the pseudo computer verification platform as described in item 8 of the scope of the patent application, where the The microprocessor is based on Veri 1 0g 1 1 as described in item 1 of the scope of the patent application. The proposed computer verification platform is a personal computer. Page 28