TW410380B - Method of forming the gate oxide - Google Patents
Method of forming the gate oxide Download PDFInfo
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- TW410380B TW410380B TW88108723A TW88108723A TW410380B TW 410380 B TW410380 B TW 410380B TW 88108723 A TW88108723 A TW 88108723A TW 88108723 A TW88108723 A TW 88108723A TW 410380 B TW410380 B TW 410380B
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Description
410380 五 '發明說明(1)410380 Five 'Explanation of invention (1)
本發明是有關於半導體裝置(semiconductor device) 的製程,特別是有關於形成高品質金氧半電晶體 (metal-oxide semiconductor transistor ; MOS transistor)之閘極氧化層(gate oxide)的方法。The present invention relates to a semiconductor device manufacturing process, and more particularly, to a method for forming a gate oxide layer of a high-quality metal-oxide semiconductor transistor (MOS transistor).
閘極氧化層通常為’位於金氧半電晶體之閘極電極下 方之氧化層(例如S i 02層)。電晶體經過此閘極氧化層誘發 通道之電何’所以其必須為品質極佳的氧化層。因此,一 般常在高純度之乾燥氧化環境下,並且於85〇〜11〇〇。(:的溫 度將石夕晶圓(Si wafer)進行乾氧化(dry oxidati〇n)以形 成厚度30〜150埃的閘極氧化層, 有一種提昇閘極氧化層的方法被提出,例如矽晶圓在 熱氧化,執行乾氧化法之後,對於形成有熱氧化層之矽晶 圓施以氮氣(')/或是氬氣(Ar)等非活性氣體(inert gas) 之回火處理(annealing),以增進閘極氧化層完整性(gate oxj,integrity ; G0I)。通常,以崩潰電壓(Vbd)與崩潰 電容(Qvd)等參數作為閘極氧化層品質之指標。 然而,隨著積體電路之設計準測(design rule)持續The gate oxide layer is usually an oxide layer (such as the Si 02 layer) located below the gate electrode of the metal-oxide semiconductor transistor. The transistor passes through this gate oxide layer to induce the channel's electric charge ', so it must be an oxide layer of excellent quality. Therefore, it is usually in a high-purity dry oxidizing environment, and the temperature is between 85 and 1100. (: Temperature is used to dry oxidize Si wafer) to form a gate oxide layer with a thickness of 30 ~ 150 angstroms. A method for improving the gate oxide layer has been proposed, such as silicon crystal After thermal oxidation and dry oxidation, the silicon wafer on which the thermal oxidation layer is formed is subjected to an annealing process such as nitrogen (') or inert gas such as argon (Ar). To improve the integrity of the gate oxide (gate oxj, integrity; G0I). Generally, parameters such as breakdown voltage (Vbd) and breakdown capacitance (Qvd) are used as indicators of the quality of the gate oxide. However, with integrated circuits Design rule continues
L Ϊ ΐ鼓:必要提供電性特性更佳,Φ即具有良好閘極氧 化層元整性的熱氧化層。 層的Si於5审本發明的目的在於提供-種形成閘極氧化 保金氣丰雷曰2 昇閘極氧化層的完整性,進而確 保i乳牛電日日體兀件之可靠度。 法,提:-種形成閘極氧化層的方 我有主動&域之半導體基底,上述方法包括L Ϊ Drum: It is necessary to provide a thermal oxide layer with better electrical characteristics, ie, good gate oxide layer integrity. The purpose of the present invention is to provide a kind of gate oxide to ensure the integrity of the 2 liter gate oxide layer, and thus to ensure the reliability of the solar cow body. Method:-A method for forming a gate oxide layer. I have an active & semiconductor substrate. The above method includes
410380 ^_ 五、發明說明(2) ' ' --- 下列步騍’利用熱氧化法,在上述半導體基底之主動區域 形成一熱氧化層;以及對上述熱氧化層施以氫氣回火步一 鱗,以形成閘極氣化層。 再者’上述氳氣回火步驟之溫度為6〇〇〜11〇(rc,苴 又以600〜800 °C較佳。 並且,進行氫氣回火步驟之後或之前,更包括對上述 熱氧化層施以氮氣及/或氩氣等非活性氣體回火步驟。 上述非活性氣體回火處理的溫度介於6〇〇至11〇(rc之 再者’上述熱氧化法係在含有乾燥氧氣之環境下進 行。 圖式之簡單說明 第1〜3圖係顯示根據本發明較佳實施例形成金氧半電 晶體之閘極氧化層的製程剖面圖。 符號之說明 100〜半導體基底(單晶矽基底)。 FOX〜場氧化層。 AA〜主動區域。 102〜熱氧化層。 102a〜閘極氧化層。 實施例 〆以下利用第卜3圖之形成閘極氧化層的製程剖面圖, 以詳細地說明本發明之較佳實施例。410380 ^ _ V. Description of the invention (2) '--- The following steps (1) use a thermal oxidation method to form a thermal oxide layer on the active area of the semiconductor substrate; and apply hydrogen tempering to the thermal oxide layer (1). Scales to form a gate gasification layer. Furthermore, the temperature of the above-mentioned radon gas tempering step is 600-110 ° C, and radon is preferably 600-800 ° C. Furthermore, after or before the hydrogen tempering step, the thermal oxidation layer is further included. Tempering step of inert gas such as nitrogen and / or argon. The temperature of the above-mentioned inert gas tempering treatment is between 600 and 110 (the RC is further described above) The thermal oxidation method is in an environment containing dry oxygen The following is a brief description of the drawings. FIGS. 1 to 3 are cross-sectional views showing a process for forming a gate oxide layer of a metal-oxide semiconductor transistor according to a preferred embodiment of the present invention. Explanation of symbols 100 to semiconductor substrate (single-crystal silicon substrate) ). FOX ~ field oxide layer. AA ~ active area. 102 ~ thermal oxide layer. 102a ~ gate oxide layer. Example 〆 The following is a cross-sectional view of the process of forming the gate oxide layer using FIG. 3 to explain in detail A preferred embodiment of the present invention.
首先’請參照第1圖’第1圖顯示形成有場氡化物F〇XFirst, "please refer to Fig. 1". Fig. 1 shows that a field halide FOX is formed.
之半導體基底100剖面’上述場氧化物F〇X係在高溫下利用 濕氧化法(wet oxidation)所形成,其用以定義出主動區. 域A A。上述半導體基底1 〇 〇例如單晶矽基底。The cross section of the semiconductor substrate 100 'the above-mentioned field oxide FOX is formed at a high temperature using a wet oxidation method, which is used to define an active region. A A. The semiconductor substrate 100 is, for example, a single crystal silicon substrate.
接著’請參照第2圖,利用850〜1100 X:的溫度,在含 有乾燥氧氣的環境下進行氧化製程,以形成熱氧化層 102。然後,在6〇〇〜;n〇〇°c的溫度下進行20〜40秒鐘的氫氣 (Ha)回火處理步驟,上述氫氣回火步驟的溫度又以 600〜800 °C更佳D 最後’請參照第3圖,在6 0 0至11 〇 〇 °C的溫度下,進行 例如氮氣(Na)及/或氬氣(j\r)之非活性氣體之回火處理步 驟,以形成當作閘極氧化層丨〇2a之回火後熱氧化層。 後續依照傳統技術進行複晶矽層、絕緣層沈積、微 影、蝕刻、離子植入步驟,以完成金氧半電晶體元件的製 作。 上述實施例之回火處理係先施行氫氣回火處理,再施 行氮氣及/或氬氣回火處理,然而本發明不限於此。更換 氫氣回火處理以及氮氣及/或氬氣回火處理的順 可達到本發明的目的。 ~ 本發明特徵以及效果Next, referring to FIG. 2, an oxidation process is performed at a temperature of 850 to 1100 X: in an environment containing dry oxygen to form a thermal oxide layer 102. Then, the hydrogen (Ha) tempering treatment step is performed at a temperature of 600 to 600 ° C for 20 to 40 seconds, and the temperature of the hydrogen tempering step is preferably 600 to 800 ° C. Finally, D 'Please refer to FIG. 3, and perform a tempering treatment step of an inert gas such as nitrogen (Na) and / or argon (j \ r) at a temperature of 600 to 11000 ° C to form a current Used as the gate oxide layer 〇2a after tempering thermal oxidation layer. Subsequent steps of the polycrystalline silicon layer, the insulating layer deposition, the lithography, the etching, and the ion implantation are performed in accordance with the conventional technology to complete the fabrication of the metal-oxide semiconductor device. The tempering treatment in the above embodiment is performed with hydrogen and then with nitrogen and / or argon, but the present invention is not limited thereto. The purpose of the present invention can be achieved by replacing the hydrogen tempering treatment and the nitrogen and / or argon tempering treatment. ~ Features and effects of the present invention
本發明之特徵在於,以乾氧化法形成用來當作閘極氧 化層102之熱氧化層之後,增加一道氫氣回火處理步驟, 再施以非活性氣體回火處理。藉此,可更提高閘極氧化層 的品質,進而確保金氧半電晶體之可靠度。 雖然本發明已以較佳實施例揭露如上,然其並非用以The invention is characterized in that after the thermal oxidation layer used as the gate oxide layer 102 is formed by a dry oxidation method, a hydrogen tempering treatment step is added, and then an inert gas tempering treatment is performed. Thereby, the quality of the gate oxide layer can be further improved, and the reliability of the gold-oxygen semi-transistor can be ensured. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to
第6頁 _410380_ 五、發明說明(4) 限定本發明,任何熟習此項技藝者,在不脫離本發明之精 神和範圍内,當可作更動與潤飾,因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Page 6_410380_ V. Description of the invention (4) The invention is limited. Any person skilled in the art can make changes and retouches without departing from the spirit and scope of the invention. Therefore, the scope of protection of the invention should be considered after The attached application patent shall prevail.
第7頁Page 7
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TW88108723A TW410380B (en) | 1999-05-27 | 1999-05-27 | Method of forming the gate oxide |
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TW88108723A TW410380B (en) | 1999-05-27 | 1999-05-27 | Method of forming the gate oxide |
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