TW398137B - The discrimination circuit between receiving signals and its method - Google Patents

Abstract

This invention is the discrimination circuit used for receiving signals and its method. This circuit is composed of a detector to detect the peak value signal depending upon the correlation between the receiving signal and reference signal. It also contains the generator to generate the discriminating signal. While the peak value is detected in the predetermined period, high resolution signal is indicated. If the peak value signal is not detected in the period, it will indicate these receiving signals as analog broadcasting signal. Therefore, whether the selected channel-receiving signal is high resolution digital signal or an analog broadcast signal can be automatically determined. This invention could prevent the receiver from wrong operation.

Description

V. Description of the Invention α) ____ [Background of the Invention]-"Field of Invention", the present invention is related to receiving and determining whether the receiving signal is # t, and more particularly about a kind of method. The relevant technical description of the resolution signal or the broadcast signal is "close to the United States, P containing ^ C-Η» " ATV system of the Grand Alliance TV transmission system As advanced television. The Advanced Television System Committee (A; fc; traditional analog system (GA-, or GA-VSB) uses the historical remnant band (VSB) modulation method, the coefficient is transmitted Method "/ By the way, even though HDTV broadcasting has begun, traditional NTSC still needs to coexist. The receiver must have a structure that can receive both the radio broadcast and the ntsc τν broadcast. That is, because the same channel in different regions may be One of NTSC τν broadcasting or HDTV broadcasting is necessary for this structure to be able to receive two types of broadcasting. In summary, the simultaneous broadcasting receiver that receives HDTV signals and NTSC TV signals includes a tuner, HDTV signal processor and NTSC TV signal processor and display 'These processors are respectively SHDTV signal and NTSC τν signal. Therefore,' to be able to use a single display of the terminal to display HDTV signals or one of NTSC TV signals' must determine the currently connected The signal is an HDTV signal or an NTSC TV signal. It also needs a circuit to determine the currently selected signal in order to display the channel selected by the user in the receiver that receives the HDTV signal. Investigate HDTV Signal

Page 4 5. Description of Invention (2) Or NTSC TV signal. "Summary of the Invention" d One of the objects of the present invention is to provide a circuit for determining whether the received signal is a high-resolution digital signal or an analog broadcast signal. In order to achieve the first purpose, 'a detector for identifying a circuit between received signals', a peak signal is detected based on the correlation between the received signal and the reference signal. If a peak signal is detected within a predetermined period, a generator indicates that the received signal is a high-resolution signal with a predetermined digital signal format, and if a peak signal is not detected within a predetermined period, the generator indicates that the received signal is analogous Broadcast signal: In order to achieve the second purpose, a method is provided to identify the received signal as a digital, high-resolution signal or analog broadcast signal, including the following steps: According to the difference between the received signal and the reference signal Correlation level 'detects a peak signal; and generates a discrimination signal to indicate that the received signal is an analog broadcast signal when a peak signal is not generated within a predetermined period. [Brief Description of the Drawings] By describing the preferred embodiments of the present invention in detail with the accompanying drawings, the above-mentioned objects and advantages of the present invention can be more clearly understood. Among them: Figure 1 is a block diagram showing the simultaneous application of HD / NTSC of the present invention. Broadcast receiver; 'Detailed block diagram of Figure 2' shows the channel decoder and jid / NTSC discriminating circuit in Figure 2; Figure 3 depicts the format of the residual sideband (VSB) round frame, and,

Page 5 V. Description of the invention (3) Figure 4 is the format of the field sync signal sequence of the field sync field in Figure 3. "Comparison of component numbers and names in the drawings" 10 2 ... Tuner 10 4 ..... • Buffer / Demultiplexer 106 .. •••• NTSC IF Amplifier 10 8 ... ... NTSC processor 110 ... digital converter (ADC)

114 116 118 12 0 12 2 12 4 12 6 12 8 13 0 1 3 2 13 4

13 8 14 0 14 2 HD IF amplifier second ADC channel decoder transmission decoder video decoder display processor DAC / mixer display DFPLL circuit matching filter NTSC rejection filter symbol clock restorer signal detector equalization Decoder decoder (TC Μ) decoder (FEC)

V. Description of the invention (4) 2 0 0 -... Η D / NTSC discrimination circuit 2 0 2 · · · '· ·. Signal generator 2 0 4. · · "'% Peak Detector 2 0 8 · · · · · · Decimal Counting Device 2 1 0 · · ·' '% — Decision Circuit 2 1 2 · · · · * · m-number generator 2 1 4 · · · * * · 6 3 PN Correlator 2 1 6 * · · ''%% Peak Detector 2 1 8 · · · · · · Decimal Counter 2 2 0 · · · ''%% Decision circuit 2 2 2 ······ Generator [Description of the preferred embodiment] The following will describe the discrimination between different types of received signals according to the present invention, the circuit and the method thereof with reference to the following drawings. In the first figure, the tuner 102 receives the HDTV signal and the NTSC TV signal at the same time. In the buffer / demultiplexer 104, the HDTV signal or NTSC TV signal provided by the tuner 丄 02 is temporarily stored in the buffer, demultiplexed by the demultiplexer, and provided to the NTSC intermediate frequency ( IF) amplifier 〇 and HD IF amplifier 1 1 2. The NTSC IF amplifier 106 amplifies the NTSC IF signal from the retarder / demultiplexer 14. The NTSC processor 108 demodulates the amplified NTSC IF signal into a baseband signal. _Analog to Digital Converter (ADC) 丄 1 ^

V. Description of the invention (5)-;-Solution, ^ analog NTSC signal is converted into digital data and provided to the first input 'port of the display processor 1 2 2. The IF amplifier 1 1 2 amplifies the signal from the buffer / demultiplexer 1 0 = 'IF. The second ADC 1 1 4 converts the amplified HD IF signal into bit data. The frequency decoder 1 ~ 6 demodulates the HD 2 signal converted into digital data into a baseband signal, and self-demodulates the data recovery area of the baseband signal = synchronization signal and symbol clock, and synchronizes the recovered section Signals and symbols are provided to the HD / NTSC discrimination circuit 2000. The demodulated signal has a packet type. Therefore, the transport decoder 8 analyzes the transmission packet header from the transmission packet and distinguishes the transmission packet into a video stream (st ream) and an audio stream according to the analyzed packet identification (PID). Video decoder 1 2 0 Decodes the video data from the video stream to HD / NTSC identification circuit 2 0 0 Uses the segment synchronization signal and symbol clock from the channel decoder 1 16 to determine that the received signal is an HDTV signal Or NTSC TV signal, and provide identification signal HD / NTSC. The display processor 1 2 2 selects one of the NTSC TV signal from the first ADC 1 1 0 or the HDTV signal from the video decoder 1 2 according to the identification signal HD / NTSC. The selected signal or a signal suitable for display Processing, and providing the processed signal to a digital. Analog converter (DAC) / mixer 1 2 4. The DAC / mixer 1 2 4 converts the data processed by the display processor 1 2 2 into an analog image signal, and generates an on screen display (0SD) signal, such as caption information, in accordance with HD / NTSC Identification signal provided by the circuit 2 0 0

V. Description of the invention (6) The channel is an HDTV channel or an NTSC TV channel. The generated OSD signal is mixed with an analog video signal, and the mixed signal is displayed through the display 1 2 6. The subtitle information can be a graphic (OSG) signal on the screen. Here, omitting this part from the buffer / demultiplexer 104 to the first ADC 110 of the simultaneous broadcast receiver shown in FIG. 1 can form a receiver structure that only receives HDTV signals. FIG. 2 is a detailed block diagram of the frequency decoder 1 16 and the discrimination circuit 2 0 shown in FIG. 1. In the second figure, the digital decoder phase-locked loop (DFPLL) circuit of the channel decoder 1.16 1 2 8 uses the second ADC to provide the index (pi l0t) signal contained in the tributary material to restore the carrier, and The recovered carrier is demodulated into a baseband signal. The matched filter 1 3 0 controls the symbol rate of the data provided by the DFPLL circuit 1 2 8 to divide and remove the signal distortion and sampling deviation of the demodulated baseband signal. That is, the matched filter 1 3 0 controls the symbol rate 2fs of the data provided by DFPIT Snow Government: =. Circuit The NTSC rejection filter 1 3 2 removes the NTSC TV signal component contained in the HDTV signal provided by the matched filter 130, because the ntsc signal will cause interference when coexisting in the HDTV channel.

The symbol clock recovery pirate 1 3 4 responds to the output of the matched filter 1 3 〇 and the section synchronization signal from the section synchronization signal detector i 3 6 to recover the symbol clock, and the frequency is twice as high as the symbol clock. A sampling clock with a frequency of 2fs is applied to the second ADC 114 in the i-th figure. The symbol clock fs provided by the symbol clock restorer 1 3 4 is provided to other blocks for processing digital signals not shown in the figure, and provided to the matched filter 13 and HD / NTSC.

Page 9 V. Description of the invention (7) Identification circuit 2 0 0. The segment sync signal detector 1 36 detects the segment sync signal in the output of the matched filter 1 30. That is, the segment sync signal detector 丄 3 6 input is provided by the matching filter 1 3 〇 and is controlled to have a symbol rate & the data 'takes = the correlation value in units of four symbols, accumulated in the area The segment is the obtained correlation value in units, and a segment synchronization signal is generated at the position where the largest cumulative correlation value is detected in each data segment. The correlation value accumulated for each sector has a maximum value during the four sector synchronization symbol area. The equalizer 1 3 8 updates and equalizes the filter coefficients of the equalizer using the known additions in the field synchronization section to remove multipath distortion through the transmission channel, trellis modulation (TrelHs_c. ded m〇dulati ON) jTCMj decoders 1, 4 〇 the output of the equalizer 丄 38 to grid decoding. Month] To the error correction (f 0rward err0rc〇rrect) (FEC) decoder ^ 4 2 to remove the interleaved scanning of the data decoded by the grid, the error correction decoding and randomization of the data removed from the interleaved scanning, and provide Data to the transmission decoder 1 1 8 shown in Figure 1. The 5th pseudo number (pN) correlator 2 of the HD / NTSC discrimination circuit 2 provided by the present invention—the input port 2 is connected to the output port of the matched filter 1 3 ◦. The correlator 2 0 4-the output port of the reference signal generator 2 0 2. Port number generator for the second round of the correlator 214? 19. The first reference of the inverse master is the first input port of the peak detector 206.

1 1PN m

Η

Page 10 V. Description of the invention (8) The output of the correlator 2 04 is the second input of the spring 2 06, bee. The first reference value is input to the detector in sequence and connected to β q DM 4 B. The first input port of the peak detection 2 1 6 is connected to the 63 PN correlator 214 and the φ grid is inserted into the detector. Chu 216 ^ A reference value is deleted e) tf 5 | 〇n 〇. One round into the port. First Reliable (conf i derc) Ϊ 测 = Detector 1 3 clock connected to the first peak detector 206 璋 Connected to the segment sync signal Enable to detect the counter 218 璋 Connect U to the symbol clock restorer The output of " 4. The output port of the counter 2 ^^ is connected to the output port of the second decision circuit 2 2 0. The signal generator 2 2 2 can be composed of a multiplier or an AND gate. The generator 2 2 2 The first and second input and input ports are connected to the output ports of the first and second decision circuits 2 1 0 and 2 2 0, respectively. The output port of the generator 2 2 2 is connected to the display processor 1 2 2 and the DAC. Each control port of the mixer / mixer 1 24. The operation of the HD / NTSC discrimination circuit 2 00 will be described with reference to Figs. 3 and 4. According to Fig. 2, the HDTV signal provided by the matched filter 130 is, That is, the VSB data is input to each of the 5 x 1 pN correlators 2 0 4 and 6 3 p ° N phase ° related to the first input VS. Here, the VSB data frame is shown by the two diagrams shown in Figure 3. Places are composed of 1 field synchronization area and 3 12 data sectors, and each data sector is composed of 4 symbol sector synchronization signals and 8 9 0 < d data symbols, add segment synchronization signal to the 8-level digital data stream in the field sync segment and the front end of each data segment, eat & ^ & + the same

Page 11 V. Description of the invention (9) The step signal has a consistent pattern, of which 4 symbols have the signal levels of "+ 5, -5, _ 5 and + 5", and other data in the data section are randomly It consists of 8 signal levels (± 1, ± 3, ± 5, and ± 7). The field sync signal sequence FIELD SYNC # 1 and FIELD SYNC # 2 showing the beginning of the field are added to the field sync segment. The field sync segment is the first segment of each field, that is, 'as the fourth As shown in the figure, the field sync segment is composed of 8 3 2 symbols, and the segment sync signal is located at the first 4 symbols '5 1 1 virtual number (5 1 1PN) is located next to 5 1 1 symbols' 3 5 3 PN is located next to 1 8 9 symbols. The additional information is located at the remaining 1 2 8 symbols, where '11 11PN is a predetermined signal sequence represented by + 5 and a 5-bit level, so it is used in a signal processing block using a known sequence such as equalization, In the second 6 3 PN of the three 6 3PNs, each field alternately reverses the phase. The field synchronization signal sequence with the format shown in Figure 4 and showing the beginning of the field is added to the first of each field. The sequence of the 'field synchronization signals' in each plaque segment has always been consistent. The first reference signal generator 2 0 2 generates a virtual random number, and the length of a reference signal is 5 1 1 (— 5 1 1PN reference signal), that is, the first reference signal generator 2 0 2 is partial and repeated. Generates the same field sync signal sequence as shown in Figure 3 with a 5 1 ipN signal, and the second reference signal generator 2 1 2 generates a virtual random number, where the length of a reference signal is 6 3 (— 6 3 PN reference Signal), that is, the second reference signal generator 212 partially and repeatedly generates the same 6 3 PN signal as the field sync signal sequence number contains. In the present invention, the first reference signal generator 2 0 2 and the second reference The signal generators 2 丄 2 are set separately for explanation

Page 12

5. Description of the invention (10). 2, 5 1 1 PN reference signal and 6 3 M reference signal can be generated by a single reference signal generator. ^ No.-Reference signal generator 202 and second reference signal generator: 51 丄 'test signal 6㈣ The reference signal is supplied to 5 1 1 PN correlator 2 0 4 and 6 3 PN correlation 2 1 4 The second input 槔. Therefore, the 5 1 1 PN correlator 2 〇 4 obtains the correlation value of 5 1 1 PN by using the correlation value between the 5 sigma 2VSB data and the 5 1 1PN reference signal. The device 2 0 6 detects whether the 5 1 1 PN correlator 2 ◦ The 5 1 PN correlation value provided by 4 is greater than the first—reference value, and is it? A peak signal 'detects the -peak signal in each field.

The data disc 62 obtains the correlation value of 63pn by accumulating the correlation value of the VSB test room in units of 6 3 symbols. The first peak detector 2 1 6 detects 6 3 PN correlator 2 and 4 provides, 3 PN correlation value. Whether it is greater than the second reference value REF2 and provide a second peak signal. The second peak signal is detected alternately two or three times in each picture field. This is because the phase of the second 6 3PN of 'three 6 3PN in each picture field alternates. Inverted. At this moment, the peak value is displayed at the place where the 5 PN and 6 3PN signals are placed in the field sync signal sequence, and the value of "" 〇" is located at the non-field sync signal sequence. "Here" is a simplified hardware.丄 pN correlator and 6 3 PN correlator 2 1 2 can detect 6 3 PN reference signal and 6 3 PN reference signal and 5 丄 reference signal, respectively. Correlation value of PN and 5PN1 correlation value of PN

Page 13 V. Invention description (11) 6 The sector synchronization signal is provided to confirm the reliability of the peak value detected by the first peak detector 2 06. In the case of HDTV signals, whenever the sector When the synchronization signal is generated 3 1 3 times, the first peak detector 2 0 6 provides the first peak signal. Therefore, when the first peak detector 2 0 6 detects the first peak signal, the first reliable counter 2 0 8 receives The first peak signal is used as the enabling signal and the segment sync signal generated by the segment sync signal detector 1 36 is calculated. When the first peak detector 2 0 6 provides the first peak signal, the first reliable counter 2 0 8 Calculate 3 1 3 segment synchronization signals and provide logic " high " signal to the first decision circuit 21 °. ° The first guilty counter 218 confirms the reliability of the peak detected by the second peak detector 216 'in HDTV In the signal situation, as shown in FIG. 4, the first peak signal / regulator 2 1 6 provides two second peak signals in each field about the first one of the three consecutive 6 3PNs and the second six 3 3PN. Therefore, the second reliable counter 2 1 8 receives the second peak detector The first first peak signal of 2 2 6 is used as the enable signal to calculate the 1 2 6 symbol clocks generated by the symbol clock restorer 1 3 4 and provide logic when the next second peak value signal is output. " The high " signal reaches the second decision circuit 2 2 0, where the first symbol of the 63 PN and the third symbol of the 63 Pn are separated by 126 symbols. The first and second decision circuits 2 1 0 and 2 2 0 judge the first and second and nine t numbers! 1 2 ◦ The 8 and 2 1 8 logic I " shang '' signals provided continuously for a predetermined number of times are determined as HDT V signals and provide logic, high first and second: fixed signals. That is, the first and second decision circuits 2 丄 0 and; detect the outputs of the first and second reliable counters 208 and 218 for a fixed period. ;

5. Description of the invention (12) The signal determines whether there is periodicity, and decides whether the output signal is HDTV signal or NTSC TV signal; in the case of HDTV signal, there is continuous periodicity. The multiplier of the discrimination signal generator 2 2 2 multiplies the output of the first decision circuit 2 1 0 by the output of the second decision circuit 2 2 0 and provides a discrimination signal rib / NTSC. That is, when the first and second decision circuits 21 and 22 are both detected, the discrimination signal generator 2 2 2 provides a logic " South " discrimination signal to display the output signal system. HDTV signal, when any one of the two power stations 10 and 220 does not detect the periodicity, it provides a logic "low" identification signal to show that the output signal is an NTSC τν signal. In Figure 2, the discrimination circuit has two channels for reliability. However, one channel can be used, and the present invention can be applied to a receiver to receive a digital terrestrial wave signal to be broadcast. It can also be applied to a broadcast receiver at the same time to receive NTSC τν signals and HDTV signal, that is, in the HDTV receiver, the user selects that the selected channel is HDTV, or the channel of NTSC channel, which is displayed according to hd / nts (: identification signal with subtitle information. In the present invention In the NTSC n signal ysB modulation method, the signals are described as examples of analog broadcast method signals and examples of noble resolution signals, and standard resolution (sd) signals can be incorporated into the south resolution signals. As mentioned above, According to the present invention, the wrong operation of the receiver can be prevented, and the received signal according to the 5 channel selection f can be a high-resolution signal or an analog broadcast signal, thereby meeting the needs of consumers.

Page 15

Claims (1)

Case number 87120555 6. Application patent scope 1. A receiving signal discrimination circuit between receivers, including: a detection device, a detection peak generating device, and a value signal, the South Resolution Signaling Received Patent Range Gate, It is used to turn off the degree, and the value detector _., 〇 Patent range is tested to receive a high degree. The signal range of the patent range No. 5 1 1 When the peak level is measured in the virtual close degree, it is displayed 2. If the phase peak signal is applied between phases 3. If the application is related to the gate inspection 4. If the application, test signal sequence _5. If you apply for testing equipment, generate the signal based on the phase between the received signal and the reference signal; and generate the identification signal to check and display that the received signal has a predetermined digital signal within a predetermined period, and it is not detected during the predetermined period. Peak signal German. The detection device in item 1 includes: obtaining the resolution signal and the reference signal. Providing a correlation value; and providing a discrimination circuit between the two received signals when the correlation value is greater than the reference value, wherein the sign bit of the phase resolution signal The receiving signal discriminating circuit between the element and the reference signal is one item, and the parameter is the same as the number of field synchronization (PN) of the VSB signal field. , The discrimination circuit between the received signals in item 4 of the patent scope, wherein the device generates the identification signal when it is placed in a picture field to continuously provide a peak signal for a predetermined number of times. “The received signal is displayed at a high resolution. 1 item identification circuit between received signals, in which the signal sequence of the reference signal is the same as the VSB signal field sync signal sequence_ 画 _1 I 871202201.ptc Page 17 2000.02. 18.017 Case number 87120555 6. Patent application scope 1. A receiving signal discrimination circuit between receivers, including: a detection device, a detection peak generating device, and a South Resolution indication when a signal is valued The received range of patents is used to close the degree, and the value detector _., 〇 The range of patents is tested to a high degree of reception. The signal range of the patent range No. 5 1 1 When the peak level is measured in the virtual close degree, it is displayed 2. If the phase peak signal is applied between phases 3. If the application is related to the gate inspection 4. If the application, test signal sequence _5. If you apply for testing equipment, generate the signal based on the phase between the received signal and the reference signal; and generate the identification signal to check and display that the received signal has a predetermined digital signal within a predetermined period, and it is not detected during the predetermined period. Peak signal German. The detection device in item 1 includes: obtaining the resolution signal and the reference signal. Providing a correlation value; and providing a discrimination circuit between the two received signals when the correlation value is greater than the reference value, wherein the sign bit of the phase resolution signal The receiving signal discriminating circuit between the element and the reference signal is one item, and the parameter is the same as the number of field synchronization (PN) of the VSB signal field. , The discrimination circuit between the received signals in item 4 of the patent scope, wherein the device generates the identification signal when it is placed in a picture field to continuously provide a peak signal for a predetermined number of times. “The received signal is displayed at a high resolution. 1 item identification circuit between received signals, in which the signal sequence of the reference signal is the same as the VSB signal field sync signal sequence_ 画 _1 I 871202201.ptc page 17 2000.02. 18.017 _ case number 87120555_ year month revision _ 6, the scope of the patent application 6 3 PN 〇7. For example, the circuit for receiving signals between the scope of patent application No. 6 identification circuit, where the detection device to When the predetermined symbol distance provides a peak signal, and when the detection device continuously provides a predetermined number of peaks generated by the predetermined symbol distance during a field, the generating device generates an identification signal to show that the received signal is a high-resolution signal. 8. For example, the circuit for identifying signals between received signals in the scope of patent application, wherein the detection device includes: a first correlator for obtaining a correlation between the received high-resolution signal and the first reference signal, and providing a first correlation Value; a second correlator to obtain the correlation between the received high-resolution signal and the second reference signal and provide a second correlation value; a first peak detector to be used when the first correlation value is greater than the first reference A second peak signal when the second correlation value is greater than a second reference value; and a second peak detector. 9. For example, the circuit for receiving signal discrimination in item 8 of the scope of patent application, wherein the first and second correlators respectively obtain the correlation between the sign bit of the high-resolution signal and the first and second reference signals, and provide the first First and second correlation values. 10. For example, the eighth winter inter-signal discrimination circuit of the patent application, wherein the signal sequence of the first reference signal is the same as the 5 Π PN signal, and the signal sequence of the second reference signal is the same as the 63 PN signal. 11 If the circuit for receiving signal discrimination between item 8 of the patent application scope, 871202201.ptc Page 18, 2000.02.18.018 _Case No. 87120555_Year Month and Amendment_ Sixth, the scope of patent application. The generating device includes: a first period detector for detecting the period of the first peak signal; a second period detector To detect the period of the second peak signal; and a logic circuit to generate a discrimination signal to display that when the first and second period detectors detect the period, the received signal is a high-resolution signal, and When any one of the first and second period detectors does not detect a period, it shows that the received signal is an analog broadcast signal. 1 2 According to the discrimination circuit between received signals according to item 8 of the scope of patent application, the generating device includes: a first reliable counter for calculating a sector synchronization signal, and providing a first peak signal when a first peak signal is detected during a field; A detection signal; a second reliable counter for calculating the symbol clock, and providing a second detection signal when the second peak signal is detected at a predetermined symbol distance; a first decision circuit for continuously providing a predetermined number of times When the first detection signal is generated, a first determination signal of an active state is generated; and a second determination circuit is configured to generate a second determination of the active state when the second detection signal is continuously provided for a predetermined number of times. A signal; and a logic circuit for generating an identification signal to indicate that the received signal is a high-resolution signal when both the first and second decision signals are in an active state, and in either of the first and second decision signals When it is not active, the received signal is an analog broadcast signal. 1 3 As described in the patent application scope of the receiving signal discrimination circuit, which is connected 871202201.ptc page 19 2000. 02. 18. 019 _ case number 87120555_ year month day__ VI. The patent application scope receiver is a simultaneous broadcast receiver, including: a tuner, used to receive a predetermined digital format High-resolution signals and receiving analogues. Broadcast signals; ·. The first signal processor is used to demodulate the tune-resolution signals provided by the tuner into the baseband signals, and detect the synchronization signals and Symbol clock; 'a second signal processor to demodulate the analog broadcast signal provided by the tuner into a baseband signal; and a display to select the output signal of the first signal processor or the second signal based on the discrimination signal Any one of the output signals of the processor, and processes the selected output signal into a signal suitable for display. 14. The receiving signal discrimination circuit according to item 1 of the scope of patent application, wherein the receiver is a high-resolution receiver, and includes: a tuner for receiving a high-resolution signal with a predetermined digit 9-channel decoder for The received high-resolution signal is demodulated into a baseband signal, and the demodulated signal is detected to synchronize the signal clock; a display processor is used to caption data based on the identification signal. Shows whether the channel selected by the user is a high-resolution TV channel or an analog broadcast TV channel. 15 — A method for identifying a received signal as a high-resolution signal in a digital format or an analog broadcast signal, including the following steps: a. Detecting a detection signal based on the correlation between the received signal and the reference signal; as well as 871202201.ptc Page 20, 2000.02. 18. 020 Case No. 87120555 Amendment Date: Patent Application Scope b. Generate an identification signal to show that when the detection signal is generated within a predetermined period, the received signal is a high-resolution signal, and When no detection signal is generated during the predetermined period, the received signal is an analog broadcast signal. 16. The method according to item 15 of the scope of patent application, wherein step a includes the following steps: a 1 provides the correlation value by obtaining the correlation between the received high-resolution signal and the reference signal; and a 2 when the correlation value When it is greater than the reference value, a detection signal is provided. 17 The method according to item 16 of the scope of patent application, wherein the correlation between the sign bit of the received high-resolution signal and the reference signal is detected in step a. 1 8 The signal of the reference signal in scope 1 of the patent application The sequence is the same as 51 1PN in the same field of the VSB signal field. 19. The method according to item 18 of the scope of patent application, wherein the identification signal generated in step b is used to display the received signal as a high-resolution signal when a predetermined number of detection signals are continuously provided during a field in step A. 20 The method according to item 15 of the scope of patent application, wherein the signal sequence of the reference signal is the same as the 63PN of the VSB signal field sync signal sequence. I 2 1 The method according to item 20 of the scope of patent application, wherein the identification signal is generated in step A so that when the detection signal is generated with a predetermined symbol distance, and a predetermined number of predetermined times are provided during one of the fields in step a. When the detection signal is generated by the symbol distance, it shows that the received signal is a high-resolution signal 0 871202201.ptc Page 21 2000. 02. 18. 021