經濟部中央樣準局員工消費合作社印11 SI9842 A7 _B7_ 五、發明説明（/ ) 本發明有關對稱式多處理器系統，尤其有關此種 系統內之插斷處理。 本發明有關之背景技術請參閱下列之文件。 第 1 文件：Multiprocessor Specification，Version 1.1 , 4/11/1994 第 2 文件：Multiprocessor Specification，Version 1.4 , July, 1995 多處理器系統的架構有許多不同的變化選擇。依 據英代爾於1994年所公布的MPS 1.1版對稱式多處 理器規格書，其MP架構之插斷（Interrupt)控制處理 單元可如第一圖（A)所示。此插斷控制器10具有一可 程式插斷控制電路（PIC) 102、轉換器電路（Router) 104 及一輸出/入進階可程式入插斷控制電路（10 APIC)106，可程式插斷控制電路（PIC)102負責接受 由ISA(或EISA)系統匯流排來的IRQ0〜IRQ15插斷 信號及由PCI匯流排來的INTA#〜INTD#插斷信號。 當此MP系統以具有二個（含）以上的處理器12、 14的情形下，如第一圖（A)所示，並進入多處理器系 統環境下運作時PIC 102是不動作的，且是由I/O .APIC 106負責安排插斷優先次序，並藉由APIC匯流 排16與處理器12內的當地（1〇^丨）八卩1(：122、處理器 14內的當地APIC 142溝通。 轉換器104是一個映射暫存器（mapping register，或稱 re-direction table)，負責將由 PCI 匯 流排來的插斷（INTA#〜INTD#)映射成ISA的某一插 本紙张尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (請先閲讀背面之注意事項再填寫本頁) —裝 訂 319842 A7 B7 經濟部中央標準局貝工消費合作杜印製 五、發明説明（叉） 斷（IRQO〜IRQ15)，如此可使PCI插斷信號由作業系 統（0S)看起來爲ISA插斷信號，作業系統即可不管其 是否爲PCI的插斷。於系統開機階段時，由BIOS依 據系統內PCI裝置的情形對轉換器104進行程式化 (program)，以決定其實際映射方式。 支援MPS 1.1之多處理器架構也可以只安排一 個處理器，而成爲一單處理器系統，如第一圖（B)所 示。此時，I/O APIC 106是不動作的，而是由PCI 102 及轉換器1〇4共同負責安排插斷優先次序，並發出插 斷請求（INTR)給處理器12。由以上所述可知，支援 MPS 1.1版規格之硬體架構中，其插斷控制器1〇是 一個積體（Integrated)電路，其內包含可程式插斷控 制電路102、轉換器電路104及輸出/入進階可程式 入插斷控制電路106。 除了其他基本功能，一個多處理器系統內的 BIOS須負責將系統規劃（configuration)訊息傳送給 作業系統（0S)，此規劃訊息包含有關所有的處理器、 以及系統內之多重處理元件（components)。在MP多 處理器系統的架構下，是由BIOS內一個規劃表 (configuration table)貯存這些規劃訊息，其詳細說明 可參考上述二文件中的第四章。作業系統收到這些規 劃訊息後會程式化I/O APIC 106以便決定由 ISA(EISA)或PCI匯流排來的插斷如何處理。 在規劃表中與本案有關的爲一個輸出/入插斷分 配（I/O Interrupt Assignment)的項目（entry)。此一項 ------；-----^ I 裝-- (諳先閱讀背面之注意事項再填寫本頁) 卜訂 本紙張尺度適用中國國家標準（（：1^)六4現格（210乂297公釐) 319842 A? __ B7 五、發明説明（今） 目供告知作業系統那一插斷源（source)連接至每一個 I/O APIC的插斷輸入端。如第一表所示，爲此項目 的格式。其中，"來源匯流排識別編號（ID)"供識別插 斷信號的來源匯流排，而"來源匯流排IRQ·，則供識別 該來源匯流排中的那一個插斷信號。P0定義I/O APIC的輸入信號極性，若爲00代表其與匯流排規格 相同，若爲11則爲低準位動作（active low)，若爲01 則爲尚準位動作（active high)。EL定義I/O APIC的 輸入信號觸發模式.(trigger mode)，若爲00代表其與 匯流排規格相同，若爲11則爲準位觸發（level trigger)，若爲〇 1則爲信號緣觸發（edge trigger)。 n ^^^1 ! 1 _ m (請先閱讀背面之注意事項再填寫本頁) 第一表 目標I/O APIC之 輸入端 (INTIN#) 目標I/O APIC之 識別編號(Π)) 來源匯流排 IRQ 來源匯流排識 別編號(ID) I/O插斷旗標 插斷形態 項目形態 3 保留 EL P0 31 20 18 15 8 7 0 訂 經濟部中央標準局員工消費合作杜印製 對一支援MPS 1.1規格的多處理器系統而言，如 第一圖（A)(B)所示，因轉換器104與I/O APIC 106是 在一個積體電路10內，所以作業系統不須花額外的 功夫去處理由PCI匯流排來的插斷信號（INTA#〜 INTO#)。 舉一例，吾人可在輸出/入插斷分配項目中提供 3 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X 297公釐） 經濟部中央樣準局負工消費合作社印繁 A7 B7 五、發明説明（詧） 下列一組値（十六進位）Printed by the Central Consumer Council of the Ministry of Economic Affairs 11 SI9842 A7 _B7_ V. Description of the invention (/) The present invention relates to a symmetrical multiprocessor system, especially to the interruption processing in such a system. For the background technology related to the present invention, please refer to the following documents. The first file: Multiprocessor Specification, Version 1.1, 4/11/1994 The second file: Multiprocessor Specification, Version 1.4, July, 1995 There are many different options for the architecture of multiprocessor systems. According to the MPS 1.1 version of the symmetric multiprocessor specification published by Indell in 1994, the interrupt control processing unit of the MP architecture can be shown in the first figure (A). The interrupt controller 10 has a programmable interrupt control circuit (PIC) 102, a converter circuit (Router) 104, and an output / input advanced programmable interrupt control circuit (10 APIC) 106, which is programmable interrupt The control circuit (PIC) 102 is responsible for receiving IRQ0 ~ IRQ15 interrupt signals from the ISA (or EISA) system bus and INTA # ~ INTD # interrupt signals from the PCI bus. When the MP system has two or more processors 12, 14, as shown in the first figure (A), and enters the multi-processor system environment, the PIC 102 does not operate, and It is the I / O. APIC 106 that is responsible for arranging the interruption priority, and by the APIC bus 16 and the local (10 ^^) 8 (1) in the processor 12 (122, the local APIC 142 in the processor 14 Communication. The converter 104 is a mapping register (or re-direction table), which is responsible for mapping the interruption (INTA # ~ INTD #) from the PCI bus to a certain paper size of the ISA. China National Standard (CNS) Λ4 specification (210X 297mm) (Please read the precautions on the back before filling in this page) —binding 319842 A7 B7 Central Bureau of Economic Affairs, Ministry of Economic Affairs, Beige Consumer Cooperation Du Printed V. Invention description (fork ) Interrupt (IRQO ~ IRQ15), so that the PCI interrupt signal can be seen by the operating system (0S) as the ISA interrupt signal, the operating system can regardless of whether it is PCI interrupt. During the system startup phase, the BIOS Perform the converter 104 according to the situation of the PCI device in the system Program to determine the actual mapping method. The multi-processor architecture that supports MPS 1.1 can also arrange only one processor and become a single-processor system, as shown in the first figure (B). At this time, The I / O APIC 106 does not operate, but the PCI 102 and the converter 104 are jointly responsible for arranging the interruption priority order, and issuing an interruption request (INTR) to the processor 12. As can be seen from the above, MPS is supported In the 1.1 version of the hardware architecture, the plug-in controller 10 is an integrated circuit, which includes a programmable interrupt control circuit 102, a converter circuit 104, and an advanced input / output programmable insert Break control circuit 106. In addition to other basic functions, the BIOS in a multiprocessor system must be responsible for sending system configuration (configuration) messages to the operating system (OS). This planning message contains information about all processors and multiple Processing components (components). Under the architecture of the MP multi-processor system, a BIOS configuration table (configuration table) to store these planning information, the detailed description can refer to the above two documents Chapter 4. After receiving these planning messages, the operating system will program I / O APIC 106 to decide how to handle the interruption from ISA (EISA) or PCI bus. In the planning table, it is an output / input Interrupt assignment (I / O Interrupt Assignment) item (entry). This item ------; ----- ^ I installed-- (know the precautions on the back and then fill out this page) The standard of the paper for the book is applicable to the Chinese national standard (（： 1 ^) 六 4 Present grid (210 mm 297 mm) 319842 A? __ B7 V. Description of the invention (present) The purpose is to inform the operating system which plug source is connected to the plug input of each I / O APIC. A table shows the format of this project. Among them, " source bus identification number (ID) " is used to identify the source bus of the interrupt signal, and " source bus IRQ · is used to identify the source bus The interrupt signal in the row. P0 defines the input signal polarity of the I / O APIC. If it is 00, it is the same as the bus bar specification. If it is 11, it is active low, if it is 01, it is Active high. EL defines the input signal trigger mode of I / O APIC. (Trigger mode), if it is 00, it is the same as the bus bar specification, if it is 11, it is the level trigger. If it is 〇1, it is the signal edge trigger (edge trigger). N ^^^ 1! 1 _ m (please read the precautions on the back before filling this page) Table 1 Input terminal of target I / O APIC (INTIN #) Identification number of target I / O APIC (Π)) Source bus IRQ Source bus identification number (ID) I / O interrupt flag flag interrupt shape item Form 3 Reserved EL P0 31 20 18 15 8 7 0 Ordered by the Ministry of Economic Affairs, Central Standards Bureau, Employee Consumption Cooperation Du Printed For a multiprocessor system that supports MPS 1.1 specifications, as shown in the first figure (A) (B) Because the converter 104 and the I / O APIC 106 are in an integrated circuit 10, the operating system does not need to spend extra effort to process the interrupt signal (INTA # ~ INTO #) from the PCI bus. As an example, we can provide 3 paper standards in the I / O distribution allocation project for the Chinese National Standard Falcon (CNS) A4 specification (210X 297 mm). The Central Sample Bureau of the Ministry of Economic Affairs, Negative Consumers Cooperative, Indochina A7 B7 V 3. Description of invention (詧) The following set of values (hexadecimal)
03 00 00 00 01 0B 02 0B 其中03代表項目形態（entry type)， 〇〇代表插斷形態（interrupt type), 〇〇 代表插斷旗標（I/O Interrupt flag)中的 ΡΟ，EL 及4個保留位元， 〇〇代表插斷旗標（I/O Interrupt flag)中的其他保 留位元， 〇1代表來源匯流排識別編號（Source Bus ID)， 〇B代表來源匯流排IRQ(Source Bus Aq)， 02代表目標I/O APIC識別編號（DESTINATION I/O APIC ID), 〇B 代表目標 I/O APIC 輸入端（DESTINATION I/O APIC INTIN#);依上述規劃値，作業系統將I〇 APIC 1〇6之插斷輸入的第十一（0B HEX)根輸入信號定爲 來自IS A匯流排的IRQ 11 (〇B HEX)。此時的IRQ 11 的極性被定義爲與ISA規格相同（PO = 00)，且觸發模 式係被定義爲信號緣觸發（EL = 00)。此第十一（0B HEX) 根輸入插斷信號實際上是源自於PC_I匯流排上的 INTx#，此PCI插斷信號進入插斷控制器10後，由轉 換器104映射成IRQ 11，而成IO APIC 106的第11 個信號輸入。至於信號來自哪一個匯流排，實際上僅 是供作業系統作參考，而不對IO APIC 106產生實質 影響。真正影響IO APIC 106動作的是信號連接輸入 端的位置、信號極性以及觸發模式。 4 本紙依尺度適用中囷國家標华（CNS)A4規格（210x297公麓） (請先閲讀背面之注意事項再填寫本頁) —裝03 00 00 00 01 0B 02 0B where 03 represents the item type (entry type), 〇〇 represents the interruption type (interrupt type), 〇〇 represents the interruption flag (I / O Interrupt flag) (PO, EL and 4 Reserved bits, 〇〇 represents the other reserved bits in the I / O Interrupt flag, 〇1 represents the source bus identification number (Source Bus ID), 〇B represents the source bus IRQ (Source Bus Aq), 02 represents the target I / O APIC ID (DESTINATION I / O APIC ID), 〇B represents the target I / O APIC input (DESTINATION I / O APIC INTIN #); according to the above planning values, the operating system will The eleventh (OB HEX) input signal of the interrupt input of APIC 106 is set to IRQ 11 (OB HEX) from the IS A bus. In this case, the polarity of IRQ 11 is defined to be the same as the ISA specification (PO = 00), and the trigger mode is defined as signal edge trigger (EL = 00). The eleventh (0B HEX) root input interrupt signal is actually derived from INTx # on the PC_I bus. After the PCI interrupt signal enters the interrupt controller 10, it is mapped to IRQ 11 by the converter 104, and The 11th signal input of IO APIC 106. As for which bus the signal comes from, it is actually only for the reference of the operating system, and does not have a substantial impact on the IO APIC 106. What really affects the action of IO APIC 106 is the position of the signal connection input, the signal polarity, and the trigger mode. 4 This paper is applicable to the China National Standard (CNS) A4 specification (210x297 ft) according to the standard (please read the precautions on the back before filling in this page)-install
eT 3i9842 經濟、部中央榡準局員工消f合作社印製 Α7 Β7 五、發明説明（5 ) 英代爾公司於1 995年公佈了 MPS 1.4版對稱式 多處理器規格書，其架構爲MPS 1.1版的延伸。如第 二圖（A)所示。此架構下可具有一相當於8259A的插 斷控制器20、一 I/O APIC 22、一第一處理器24、 一第二處理器26 〇其中插斷控制器20與I/O APIC 22 分別爲兩顆積體電路《 PIC20與IOAPIC22分別獨 立的優點爲在多處理器運轉模式下，來自於PCI匯流 排類的插斷信號可不佔用IRQO-IRQ16的資源（因不 經ROUTER 204)，如此整個系統可更有效運用非常 i 有限的IRQ資源。插斷控制器20由ISA(或EISA)匯 流排輸入插斷信號（IRQ0〜IRQ 15)及由PCI匯流排輸 入插斷信號（INTA#〜INTD#)。另外，I/O APIC 22 由ISA(或EISA)匯流排輸入插斷信號（IRQ0〜IRQ15) 及由PCI匯流排輸入插斷信號（INTA#〜INTD#)。 在對稱I/O模態下（請參考上述第二文件的第三 章），並於進入多處理器系統環境下運作時，插斷控 制器20大部分情況下是不動作的。插斷控制器20內 又包含PIC電路202及轉換器204。I/OAPIC22藉 APIC匯流排28與處理器24的當地APIC 242及處理 器26的當地APIC 262溝通。 參考第二圖（B)，在單處理器模態下，I/O APIC 22是不動作的，而由插斷控制器20負責輸入由 ISA(EISA)匯流排來的插斷信號及由PCI匯流排來的 插斷信號，並依優先順序，發出插斷要求INTR信號 給處理器24，請求提供協助。 5 本紙張尺度適月中國國家標隼（CNS ) A4規格（210X297公釐）eT 3i9842 Printed Α7 Β7 by the Ministry of Economic Affairs, Central Bureau of Economics and Social Welfare Co., Ltd. 5. Description of the invention (5) Indell Corporation published the MPS 1.4 version of the symmetric multiprocessor specification in 1995, and its architecture is MPS 1.1 The extension of the edition. As shown in the second figure (A). Under this architecture, there can be an interrupt controller 20 equivalent to 8259A, an I / O APIC 22, a first processor 24, and a second processor 26. The interrupt controller 20 and the I / O APIC 22 are respectively The two integrated circuits "PIC20 and IOAPIC22 are independent. The advantage is that in multi-processor operation mode, the interrupt signal from the PCI bus type can not occupy the resources of IRQO-IRQ16 (because without ROUTER 204), so the whole The system can more effectively use very limited IRQ resources. The interrupt controller 20 inputs the interrupt signal (IRQ0 to IRQ 15) from the ISA (or EISA) bus and the interrupt signal (INTA # to INTD #) from the PCI bus. In addition, I / O APIC 22 receives the interrupt signal (IRQ0 ~ IRQ15) from the ISA (or EISA) bus and the interrupt signal (INTA # ~ INTD #) from the PCI bus. In the symmetric I / O mode (please refer to Chapter 3 of the second document above) and when operating in a multiprocessor system environment, the interrupt controller 20 is mostly inoperative. The interrupt controller 20 further includes a PIC circuit 202 and a converter 204. The I / OAPIC 22 communicates with the local APIC 242 of the processor 24 and the local APIC 262 of the processor 26 via the APIC bus 28. Referring to the second figure (B), in the uniprocessor mode, the I / O APIC 22 is inactive, and the interrupt controller 20 is responsible for inputting the interrupt signal from the ISA (EISA) bus and the PCI The interrupt signal from the bus, and in accordance with the priority order, sends an interrupt request INTR signal to the processor 24 to request assistance. 5 The size of this paper is suitable for China National Standard Falcon (CNS) A4 specification (210X297mm)
Mt,----1--^--'—装-- (請先閲讀背面之注意事項再填寫本頁) 訂 A7 B7 五、發明説明（6 ) 如圖一所述之硬體架構亦符合MPS 1.4規格，不 同點在MPS1.1規格無法詳盡描述圖二的硬體架構^ 在一支援MPS 1.4的硬體架構下，插斷控制器20與 I/OAPIC22可爲兩顆1C，且於對稱模態下插斷控制 器20不動作。依據MPS 1.4的規格，在規劃表中之 輸出/入插斷分配的項目中，必須爲PCI匯流排產生 的插斷信號（INTA#〜INTD#)有所描述，如此作業系 統才會知道如何程式化I/O APIC 22內的轉向表 (redirection table)，使 I/O APIC 22 處理 PCI 匯流排 4 來的插斷。 參閱第二文件的附錄D-3，針對PCI裝置的插 斷，第一表中的來源匯流排IRQ欄位的規格如第二表 所示。 (請先閲讀背面之注意事項再填寫本頁) 丨裝 訂， 第二表 欄位 偏移offset (bytes: bits) 長度 (位元） 說明 來源匯流排 IRQ 5:0 2 0x0 對應 INTA#，0x1 對應 INIB# 0x2 對應 INTC#，0x3 對應 INTO# 來源匯流排 IRQ 5:2 5 產生插斷的PCI裝置編號 保® 5:7 1 給未來使用 經濟部中央標準局—工消費合作社印製 因此，吾人若在輸出/入插斷分配項目中提供下 列一組値（十六進位） 03 00 0F 00 00 30 02 10 其中03代表項目形態（entry type), A7 B7 經濟'部中央橾準局負工消費合作社印製 五、發明説明（7) 〇〇代表插斷形態（interrupt type)， OF 代表插斷旗標（I/O Interrupt flag)中的 PO，EL 及4個保留位元， 00代表插斷旗標（I/O Interrupt flag)中的其他保留位元， 、 〇〇代表來源匯流排識別編號（Source Bus ID)， 30代表來源匯流排IRQ(Sour*ce Bus IRQ), 02代表目標I/O APIC識別編號（DESTINATION I/O APIC ID), 10 代表目標 I/O APIC 輸入端（DESTINATION I/O APIC INTIN#)，其中 0 F (Hex) = 0000 111 1 (Binary)，' 因 此 PO=ll、EL=11，來源匯流排 IRQ 値 30(Hex)=0 01 100 00(Binary)，因此前兩個位元00對應INTA#， 接著五個位元01100 (=12 (decimal))代表產生插斷的 PCI裝置編號爲12;依上述規劃値一隻原MPS 1.4規 格的作業系統將I/O APIC 22插斷輸入的第十六（10 HEX)根輸入信號定爲來自PCJ_匯流排上裝置編號爲 12的PCI裝置之插斷信號（INTA#)。而根據MP_5 1.4 規格所準備的作業系統接獲此一項自値後，因而能得 知第二圖（A)的架構，而成功的啓動（Boot)多處理器 系統，並程式化（program)I/0 APIC 22內旳轉向表 (redirection table)，以利用 I/O APIC 22 處理 PCI 匯 流排來的插斷。 反之，若以舊版支援MPS 1.1的作業系統運作依 MPS 1.4規格架構的硬體時，因無法了解03 00 0F 00 7 (請先閲讀背面之注意事項再填寫本頁) 」丨 裝 *6T·. 本紙張尺度適用中國國家標準（CMS ) Α4規格（210Χ 297公釐） 經濟部中央標準局員工消費合作杜印製 A 7 B7 五、發明説明（8 ) 00 30 02 10的插斷分配所代表之意義，該系統就無 法啓動運作以處理PCI匯流排來的插斷（INTx#)。 基於某些原因，有一些使用者於使用依MPS 1.4 規格架構的硬體時，卻有需求以支援MPS 1.1規格的 作業系統來運作。 而本發明即在提供一方法來解決此一問題。 亦即，於對稱式多處理器系統中，藉用本發明， 可以一支援MPS 1.1規格的作業系統來運作支援MPS 1.4的硬體架構，且能夠處理例如由PCI裝置來的插 斷。 ^ 圖示簡要說明： 第一圖揭露依MPS1.1規格所發展的系統架構。 第二圖揭露依MPS1.4規格所發展的系統架構。 本發明之作法是以PCI匯流排插斷的信號規格 重新描述ISA匯流排中的某一個插斷，例如IRQ11， 藉此將此一 PCI裝置的插斷模擬爲IRQ 11插斷》 詳言之，吾人可在輸出/入插斷分配項目中提供 下列一組値（十六進位） 03 00 OF 00 01 0B 02 10 其中03代表項目形態（entry type)， 00代表插斷形態（interrupt type)， OF 代表插斷旗標（l/o Interrupt flag)中的 PO, EL 及4個保留位元， 本紙浪尺度適用中國國家標隼（CNS ) A4現格（210X297公釐） M..------：—* ~裝-- (請先閲讀背面之注意事項再填寫本頁) irMt, ---- 1-^ --'— install-- (please read the precautions on the back before filling in this page) Order A7 B7 5. Invention description (6) The hardware architecture as shown in Figure 1 is also Complies with the MPS 1.4 specification, the difference is that the hardware architecture of Figure 2 cannot be described in detail in the MPS1.1 specification ^ Under a hardware architecture that supports MPS 1.4, the interrupt controller 20 and I / OAPIC22 can be two 1C, and In the symmetric mode, the interrupt controller 20 does not operate. According to the specifications of MPS 1.4, in the project of I / O interruption allocation in the planning table, the interruption signal (INTA # ~ INTD #) generated by the PCI bus must be described so that the operating system will know how to program Redirection table in I / O APIC 22 to enable I / O APIC 22 to handle interruption from PCI bus 4. Refer to Appendix D-3 of the second document. For the interruption of PCI devices, the specifications of the source bus IRQ field in the first table are shown in the second table. (Please read the precautions on the back before filling this page) 丨 Binding, the second table column offset (bytes: bits) length (bits) Description Source bus IRQ 5: 0 2 0x0 corresponds to INTA #, 0x1 corresponds to INIB # 0x2 corresponds to INTC #, 0x3 corresponds to INTO # Source bus IRQ 5: 2 5 Generate interrupted PCI device number Bao 5: 7 1 For future use Printed by the Central Bureau of Standards of the Ministry of Economic Affairs-Industrial and Consumer Cooperatives Provide the following set of values (hexadecimal) in the input / output interruption allocation project 03 00 0F 00 00 30 02 10 where 03 represents the project type (entry type), A7 B7 Ministry of Economics, Central Bureau of Preparatory Bureau of Unemployment Consumer Cooperative Printing 5. Description of the invention (7) 〇〇 represents the interruption type (interrupt type), OF represents the interruption flag (I / O Interrupt flag) PO, EL and 4 reserved bits, 00 represents the interruption flag Other reserved bits in the I / O Interrupt flag,, 〇〇 represents the source bus identification number (Source Bus ID), 30 represents the source bus IRQ (Sour * ce Bus IRQ), 02 represents the target I / O APIC identification number (DESTINATION I / O APIC ID), 10 represents the target I / O APIC input terminal (DESTINATION I / O APIC INTIN #), where 0 F (Hex) = 0000 111 1 (Binary), so PO = ll, EL = 11, source bus IRQ value 30 (Hex) = 0 01 100 00 (Binary), so the first two bits 00 correspond to INTA #, then the five bits 01100 (= 12 (decimal)) represent the PCI device number 12 that generated the interruption; according to the above plan, an original The operating system of the MPS 1.4 specification defines the sixteenth (10 HEX) root input signal of the I / O APIC 22 interrupt input as the interrupt signal (INTA #) from the PCI device with device number 12 on the PCJ_ bus. After the operating system prepared according to the MP_5 1.4 specification receives this value, it can know the structure of the second figure (A), and successfully boot (Boot) the multiprocessor system and program it. I / 0 APIC 22 includes a redirection table to use I / O APIC 22 to handle interruptions from the PCI bus. Conversely, if you are using an old operating system that supports MPS 1.1 to operate hardware that is based on the MPS 1.4 specification, you will not be able to understand 03 00 0F 00 7 (please read the precautions on the back before filling out this page) ”丨 Install * 6T · . This paper scale is applicable to the Chinese National Standard (CMS) Α4 specification (210Χ 297 mm) Du 7 printed by the consumer consumption cooperation of the Central Standards Bureau of the Ministry of Economic Affairs A 7 B7 V. Description of invention (8) 00 30 02 10 The significance of this is that the system cannot start operation to handle interruption from the PCI bus (INTx #). For some reasons, some users need to support the MPS 1.1 operating system when using hardware based on the MPS 1.4 specification. The present invention provides a method to solve this problem. That is, in a symmetric multi-processor system, by using the present invention, an operating system supporting the MPS 1.1 specification can operate a hardware architecture supporting MPS 1.4, and can handle interrupts such as PCI devices. ^ Brief description of the diagram: The first diagram reveals the system architecture developed according to the MPS 1.1 specification. The second figure reveals the system architecture developed according to the MPS1.4 specification. The method of the present invention uses the signal specification of PCI bus interruption to redefine a certain interruption in the ISA bus, such as IRQ11, thereby simulating the interruption of this PCI device as IRQ 11 interruption We can provide the following set of values (hexadecimal) in the I / O interrupt allocation project 03 00 OF 00 01 0B 02 10 where 03 represents the entry type and 00 represents the interrupt type, OF Represents the PO, EL and 4 reserved bits in the l / o Interrupt flag. This paper wave scale is applicable to the Chinese National Standard Falcon (CNS) A4 (210X297mm) M ..---- -： — * ~ 装-(Please read the precautions on the back before filling this page) ir
A 3x9842 A7 B7 經濟部中央標準局負工消費合作社印製 五、發明説明（？） 00代表插斷旗標（I/O Interrupt fiag)中的其他保 留位元， 01代表來源匯流排識別編號（Source Bus ID)， 0B代表來源匯流排IRQ(Source Bus IRQ), 02代表目標I/O APIC識別編號（DESTINATION I/O APIC ID), 10 代表目標 I/O APIC 輸入端（DESTINATIONI/O APIC INTIN#)，其中 0 F (Hex) = 00001 1 1 l(Binary)，因 此PO=ll 、 EL=11 ，來源匯流排（ISA) IRQ値 0B(Hex)=ll (decimal);依上述規劃値MPS 1.1作業系 統可將I/O APIC 22插斷輸入的第十六根（10 HEX)的 輸入信號定爲來自ISA匯流排之插斷信號IRQ 11(0B HEX)，但此時之第十六根（10 HEX)的輸入信號的極 性被定義爲低準位動作（ρ〇=ιι)，且觸發模式係被定 義爲準位觸發（EL=11)，此一 IRQ 11之信號定義與ISA 插斷之規格不同、但卻與PCI插斷之規格相同。 如此，在依MPS1.4規格所建置的新硬體架構 下，以支援MPS 1.1規格的舊作業系統蓮作時，作業 系統讀到03 00 0F 00 01 0B 02 10的插斷分配時，依 照此一規劃値，程式化（program) I/O APIC 22內的轉 向表（redirection table)，就能夠在此支援MPS l.i的 舊作業系統下處理依MPS1.4規格所建置的硬體架構 下之PCI匯流排的插斷INTx#。 於實際硬體架構中，INTA#、INTB#、 INTC#、 INTD#均分另(J接至IO APIC 22的不同輸人端 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ------^--* -裝-- (請先閱讀背面之注意事項再填寫本頁) rir ^ 經濟部中央標準局員工消費合作社印製 A7 B7五、發明説明（R ) (如第16-19腳），依PCI裝置所插置PCI槽（SLOT)位 置的不同，會使用道不同的INTx#，所以前插斷分配 表須由BIOS依實際硬體配置進行動態的安排。 也就是說，於本發明一種對稱式多處理器系統中 之PCI插斷處理方法中，此系統包含一輸出/入可程 式插斷控制積體電路（I/O APIC)及一插斷控制器積體 電路，該輸出/入可程式插斷控制積體電路具有多個 插斷輸入端分別接收來自ISA匯流排的插斷（IRQ)、 PCI匯流排的插斷（INTx#)，該多個插斷輸入端中的 某一預定輸入信號爲PCI匯流排的INTx#插斷信號， 且此INTx#插斷信號被系統中之某一 PCI裝置佔用。 本發明方法之特徵在於：將該預定輸入信號定爲ISA 匯流排中之一插斷信號，而該預定輸入信號之極性被 定義爲PCI規格，該預定輸入信號之觸發模式被定義 爲PCI規格。 其中該預定輸入信號來自多個插斷輸入端中的 第十六根（10 HEX)插斷輸入腳。或者，該預定輸入信 號來自多個插斷輸入端中的第十七根（Π HEX)插斷 輸入腳。或者，該預定輸入信號來自多個插斷輸入端 中的第十八根（12 HEX)插斷輸入腳。或者，該預定輸 入信號來自多個插斷輸入端中的第十九根（Π H^X) 插斷輸入腳。 而其中，該ISA匯流排插斷信號爲IRQ 11(0Β HEX) 〇該預定輸入信號之極性爲低準位動作’且其 觸發模式爲準位觸發。 (請先閱讀背面之注意事項再填寫本頁) —裝 訂A 3x9842 A7 B7 Printed by the National Bureau of Standards of the Ministry of Economic Affairs of the Negative Consumers Cooperative V. Invention description (?) 00 represents other reserved bits in the I / O Interrupt fiag, 01 represents the source bus identification number ( Source Bus ID), 0B represents the source bus IRQ (Source Bus IRQ), 02 represents the target I / O APIC identification number (DESTINATION I / O APIC ID), 10 represents the target I / O APIC input terminal (DESTINATIONI / O APIC INTIN #), Where 0 F (Hex) = 00001 1 1 l (Binary), so PO = ll, EL = 11, source bus (ISA) IRQ value 0B (Hex) = ll (decimal); according to the above plan value MPS 1.1 The operating system can set the input signal of the sixteenth root (10 HEX) of the I / O APIC 22 plug input as the interrupt signal IRQ 11 (0B HEX) from the ISA bus, but the sixteenth root at this time (10 HEX) The polarity of the input signal is defined as a low level action (ρ〇 = ιι), and the trigger mode is defined as a level trigger (EL = 11), this IRQ 11 signal definition is interrupted with ISA The specifications are different, but they are the same as the PCI interrupt specifications. In this way, under the new hardware architecture built according to the MPS 1.4 specification, when the old operating system supporting MPS 1.1 specification is used for operation, the operating system reads the interrupt assignment of 03 00 0F 00 01 0B 02 10 according to This planning value, the redirection table in the program I / O APIC 22, can handle the hardware architecture built according to the MPS1.4 specification under the old operating system that supports MPS li INTx # of the PCI bus. In the actual hardware architecture, INTA #, INTB #, INTC #, INTD # are equally divided (J is connected to different input terminals of IO APIC 22 9) This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 Ali) ------ ^-* -installed-- (Please read the precautions on the back before filling in this page) rir ^ Printed A7 B7 by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of Invention (R) (For example, pins 16-19), different INTx # will be used according to the location of the PCI slot (SLOT) inserted in the PCI device, so the front plug-out allocation table must be dynamically arranged by the BIOS according to the actual hardware configuration That is to say, in the PCI interrupt processing method in a symmetric multiprocessor system of the present invention, the system includes an output / input programmable interrupt control integrated circuit (I / O APIC) and an interrupt control Integrated circuit, the output / input programmable interrupt control integrated circuit has multiple interrupt input terminals to receive interruption (IRQ) from ISA bus and interruption (INTx #) from PCI bus, respectively. A predetermined input signal in the interrupt input terminal is the INTx # interrupt signal of the PCI bus, and the INTx # is interrupted The number is occupied by a PCI device in the system. The method of the present invention is characterized in that the predetermined input signal is defined as one of the ISA bus interrupt signals, and the polarity of the predetermined input signal is defined as the PCI specification. The trigger mode of the input signal is defined as the PCI specification. The predetermined input signal comes from the sixteenth (10 HEX) plug-in input pin among multiple plug-in input terminals. Alternatively, the predetermined input signal comes from multiple plug-in input The seventeenth (Π HEX) plug-in input pin in the terminal. Or, the predetermined input signal comes from the eighteenth (12 HEX) plug-in input pin in the multiple plug-in input terminals. Or, the predetermined input signal The nineteenth (Π H ^ X) plug-in input pin from multiple plug-in input terminals. Among them, the ISA bus plug-in signal is IRQ 11 (0Β HEX). The polarity of the predetermined input signal is low Level action 'and its trigger mode is level trigger. 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-LT 10 本紙沬尺度適用中國國家標準（CNS ) Α4規格（2】0X297公釐）-LT 10 The size of this paper is applicable to China National Standard (CNS) Α4 specification (2) 0X297mm