312848 0599twf.doc/Jessica/002 ____B7 五、發明説明（1 ) 發明背景與發明領域 本發明係有關於積體電路裝置，特別是有關於具有 以金屬氧化半導體（MOS)輸出電晶體爲靜電崩潰防止 電路的半導體裝置。 祖顧技術之描述 熟知的一種低耗電量、高積集化的半導體裝置-互 補型MOS積集電路(CMOS-IC)，其是在同一種半導體 基底中’同時形成P通道MOS電晶體與N通道MOS電晶 體，而兩MOS電晶體的汲極（drain)有共通的導線， 其可實現上述低耗電量與高積集化的目的。 在MOS電晶體中，連接輸出線的一邊稱爲汲極，而 連接電源VPD或接地線Vss的一邊稱爲源極(source)，,亦 即載子（carrier)的供給端稱源極，而輸出端稱爲汲極， 然而，所有MOS電晶體可變的源/汲極將被指出。 近年來，隨著高速化、高積集化的要求，淺雜質擴 散層、縮小尺寸的元件等因素，道種CMOS積體電路 中，輸出電晶體被靜電破壞已成爲問題。所以，一般習 知MOS利用相同導電型的當作輸出電晶體，並以並列方 式連接著，其中閘極保持’關閉’狀態，而構成靜電崩潰 .保護電路。因只使用輸出電晶體無法確保抗突波(Surge) 電壓的作用，於是加上保護電晶體，則突波被分流至輸 出電晶體與保護電晶體以確保抗靜電破壞之能力。 但是，在半導體裝置的PN接面之阻抗，通常對抗逆 方向的靜電突波（以下稱逆方向靜電突波）比起對抗順方 _ 4 本紙張尺度逋用中國國家標準（CNS) A4规格（210X297公釐） 312848 A7 0599twf. doc/Jessica/002 __ B7_ 五、發明説明（）） 向的靜電突波(以下稱順方向靜電突波）的能力還差。所 以，在的習知技術中，附加保護電晶體，亦是爲了確保 對抗逆方向靜電突波的能力。 請參照第12圖舉例說明，其詳述MOS型電晶體對 逆方向靜電突波的特性圖。在第12圖中，a代表用以作 爲高電壓用途的製程所製成的MOS電晶體之ID-VD特性 曲線圖，而b代表用以作爲一般用途的製程所製成的 MOS電晶體之ID-VD特性曲線圖。這種特性特別是顯示 崩潰電壓（breakdown voltage)附近。 由第12圖可了解，不管是用於一般或高電壓，在 MOS電晶體的汲極與基底(或井區）之間所構成的pn接面 處，施加逆向偏壓（reverse bias)，當該逆向偏壓超越 源極-汲極間崩潰電壓BVsd的某一點時，則引起急遽的 降伏現象（avalanche phenoriaenon)，使汲極電流開 始流通，然後，隨著逆向偏壓的增加，而進入負性抵抗. 區（negative resistance region)在〔此區當汲極電壓 下降時汲極電流增加〕，之後，進入定電壓區 (constant voltage region)，其顯示當汲極電壓發生 微小變化時，汲極電流將有急遽的變化。 因此，從第12圖可了解，在MOS電晶體中，使逆 '向靜電突波電流開始流動的電壓稱爲操作開始電壓 (operation starting voltage)，此成爲前述源-汲極 區的崩潰電壓BVsd，另外，MOS電晶體靜電崩潰的發 生也導因於突波電流焦耳發熱（joule heating)〔由汲 本紙張尺度適用中國國家榇準（CNS ) A4规格（210X297公釐） A7 0599twf.doc/Jessica/002 五、發明説明（彡） 極電流與保持電壓所產生的〕，焦耳發熱愈大則靜電崩 潰愈嚴重。 保持電壓是如第12圖所顯示定電壓區的汲極電壓 Vhb與Vha。此處的保持電壓，一般都與上述的源-汲極 崩潰電壓BVsd成正比關係，使用爲了供源-汲極區高崩 潰電壓的製程所製造的MOS電晶體有高的保持電壓，換 言之，在MOS電晶體有較高的開始電壓（逆向突波電流 開始流動的電壓），則電壓崩潰變得容易。 因此，如上述習知之構成，只有輸出電晶體與保護 電晶體組合這一點不同，其餘皆相同，所以兩種電晶體 對抗靜電突波發揮相同的功效，亦即輸出電晶體與保護 電晶體對抗逆向靜電突波發揮相同的功效，如果逆向靜 電突波若不超越輸出電晶體的源-汲極區崩潰電壓BVsd 很多，則保護電晶體不會開始動作。因爲輸出電晶體在 動作時，若存在電壓崩潰，則會引起輸出電晶體靜電崩 潰。. 經濟部中央樣準局員工消費合作社印製 避免上述問題的方法之一如'：設法使得輸出電晶體 與保護電晶體的保持電壓變爲不同，然而，爲了達成上 述目的，製造方法必須改變，所以可能會衍生出複雜與 繁冗製程的缺點。 在半導體裝置中使用習知技術，利用與輸出電晶體 相同結構的保護電晶體與輸出電晶體並列連接，若是以 淺接合的輸出電晶體對抗，或是對抗施予高崩潰電壓 時，增加保護電晶體的佔有面積是難以避免的，其會導 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 312卿 0599twf, doc/Jessica/002 A7 B7 經濟部中央標準局員工消費合作社印— 五、發明説明（Y) 致晶片(chip)價提高的問題。 更特別的是，如上述的裝置，保護 積需要擴大的程度，盡可能如輸出電晶體接合面積所減 少的程度，亦即，如因淺接合所減少的程度，另一點， 保護電晶體必須維持夠大的接合面積，以對抗具有高崩 潰電壓的製程之保持電壓。 本發明槪述 所以本發明主要的目的是提供一種半導體元件，其 具有可當作靜電崩潰防止電路的的開關（switch)元 件，而可對抗當逆靜電突波電壓低於輸出電晶體源-汲極 崩潰電壓，以達到突波對輸出電晶體的影響最小而防止 輸出電晶體的電壓崩潰。 . 本發明另一目的是提供一種半導體裝置，其所具之 電壓突波防止電路與輸出電晶體同時完成，而不需改變 該半導體裝置的製程，其中電壓崩潰防止電路具有比習 知的電壓崩潰防止電路還大的阻抗以對抗靜電突波。 本發明另一目的是提供一種半導體裝置，其使用 MOS電晶體或是雙載子電晶體當作保護電晶體，藉此， 減少保護電晶體所佔的面積，並獲得較大阻抗的保護電 晶體以對抗靜電突波。 本發明尙有一目的是提供一種半導體裝置，其可應 用於利用MOS電晶體爲輸出電晶體之各種宇導體裝置。 本發明還有另一目的是提供一種半導體裝置，可應 用於具有第一導電型與第二導電型的兩個輸出電晶體以 晶體的接合面 (#先鬩讀背面之注意事項再填寫本頁) f 裝_ 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 0599twf.doc/Jessica/002 A7 B7 五、發明説明（夕） 並列方式連接著，因此得到一阻値提高以對抗崩潰電壓 的保護電晶體。 根據上述目的，本發明提供一種半導體裝置，其具 有第一導電型主動MOS輸出電晶體，其源極/汲極區其 中一端被連接於該半導體裝置之輸出端子（output terminal)，並且具有保護輸出電晶體受靜電崩潰破壞 之設計，其中靜電崩潰保護的設計意謂著利用第二導電 型半導體開關電晶體並列連接於輸出電晶體，而其中一 端連接於輸出端子。 如上述的結構，在本半導體裝置的輸出端子處，發 生對輸出電晶體的靜電突波時，當靜電突波電壓比輸出 電晶體的崩潰電壓低時，則第二導電型的半導體開關元 件會動作。因此，由於逆方向靜電突波所產生對輸出電 晶體的不利影響比習知減輕了。 經濟部中央標準局員工消費合作社印策 同時，在製造半導體裝置時，因爲從電路的構成可 知，第二導電型的半導體開關元件，可依照一般製程被 形於基底的任何一個位置，所以'事實上，第二導電型 的半導體開關元件的製造，包含於半導體裝置形成的製 造流程中。 因此，形成第二導電型的半導體開關元件，不需外 加任何特別的流程即可完成，上述本發明的優點與目的 將藉由一配合圖式之較佳實施例的詳述後，而更加突 顯。 圖式之簡單說明= 本紙張尺度適用中國國家標準（CNS ) A4規格（210X25)7公釐） 312848 A? 0599twf.doc/JesS1ca/002 β? 五、發明説明（b ) 第1圖係第1實施例說明圖，輸出電晶體是使用PMOS 的說明圖； 第2圖係第1實施例另一種說明圖，輸出電晶體是使 用NMOS的說明圖； 第3圖係第2實施例說明圖，輸出電晶體是使用PMOS 的說明圖； 第4圖係第2實施例另一種說明圖，輸出電晶體是使 用NMOS的說明圖；312848 0599twf.doc / Jessica / 002 ____B7 V. Description of the invention (1) Background and field of the invention The present invention relates to an integrated circuit device, in particular to the use of a metal oxide semiconductor (MOS) output transistor to prevent electrostatic breakdown Circuit semiconductor device. Zu Gu's description is well known as a low power consumption, high integration semiconductor device-complementary MOS integrated circuit (CMOS-IC), which is formed in the same semiconductor substrate 'P channel MOS transistor and N-channel MOS transistors, and the drains of the two MOS transistors have common wires, which can achieve the above-mentioned purposes of low power consumption and high accumulation. In MOS transistors, the side connected to the output line is called the drain, and the side connected to the power supply VPD or the ground line Vss is called the source, that is, the supply end of the carrier is called the source, and The output is called the drain, however, all variable source / drain of MOS transistors will be indicated. In recent years, with the demand for higher speed and higher integration, shallow impurity diffusion layers, and reduced-size devices, etc., in such CMOS integrated circuits, it has become a problem that the output transistor is destroyed by static electricity. Therefore, it is generally known that MOS uses the same conductivity type as the output transistor and is connected in parallel, in which the gate remains in the "closed" state, which constitutes an electrostatic breakdown protection circuit. Because only the output transistor can not ensure the anti-surge voltage, so the protection transistor is added, the surge is shunted to the output transistor and the protection transistor to ensure the ability of anti-static damage. However, the impedance of the PN junction of the semiconductor device is generally against the electrostatic surge in the reverse direction (hereinafter referred to as the electrostatic surge in the reverse direction) compared to the anti-shun square_ 4 This paper standard uses the Chinese National Standard (CNS) A4 specification ( 210X297 mm) 312848 A7 0599twf. Doc / Jessica / 002 __ B7_ 5. Description of the invention ()) The ability of the electrostatic surge (hereinafter referred to as the forward electrostatic surge) is still poor. Therefore, in the conventional technology, the additional protection of the transistor is also to ensure the ability to resist reverse electrostatic surges. Please refer to Figure 12 for an example, which details the characteristics of MOS transistors against electrostatic surge in the reverse direction. In the twelfth figure, a represents the ID-VD characteristic curve of the MOS transistor made by the process for high voltage use, and b represents the ID of the MOS transistor made by the process for general use -VD characteristic curve graph. This characteristic especially shows the vicinity of the breakdown voltage. It can be understood from Figure 12 that, regardless of whether it is used for general or high voltage, a reverse bias is applied at the pn junction formed between the drain of the MOS transistor and the substrate (or well), when When the reverse bias voltage exceeds a certain point of the breakdown voltage BVsd between the source and the drain, it causes a rapid avalanche phenomenon (avalanche phenoriaenon), so that the drain current begins to flow, and then, as the reverse bias voltage increases, it enters a negative Sexual resistance region (negative resistance region) in [this region when the drain voltage drops when the drain current increases], then enter the constant voltage region (constant voltage region), which shows that when the drain voltage changes slightly, the drain The current will change abruptly. Therefore, as can be understood from FIG. 12, in the MOS transistor, the voltage at which the reverse electrostatic surge current starts to flow is called the operation starting voltage (operation starting voltage), which becomes the breakdown voltage BVsd of the aforementioned source-drain region In addition, the occurrence of electrostatic collapse of MOS transistors is also due to the surge current joule heating (from the size of the paper to the Chinese National Standard (CNS) A4 specification (210X297 mm) A7 0599twf.doc / Jessica / 002 5. Description of the invention (彡) caused by the polar current and the holding voltage], the greater the Joule heating, the more serious the static electricity collapse. The holding voltage is the drain voltages Vhb and Vha in the constant voltage region as shown in FIG. The holding voltage here is generally proportional to the above source-drain breakdown voltage BVsd. The MOS transistors manufactured for the process with high breakdown voltage in the source-drain region have a high holding voltage. In other words, MOS transistors have a higher starting voltage (the voltage at which the reverse surge current begins to flow), so the voltage collapse becomes easier. Therefore, as the above-mentioned conventional structure, only the combination of the output transistor and the protection transistor is different, and the rest are the same, so the two transistors have the same effect against electrostatic surge, that is, the output transistor and the protection transistor are against reverse The electrostatic surge has the same effect. If the reverse electrostatic surge does not exceed the source-drain breakdown voltage BVsd of the output transistor, the protection transistor will not start to operate. Because when the output transistor is operating, if there is a voltage collapse, it will cause the electrostatic collapse of the output transistor. . One of the ways to avoid the above problems is printed by the Central Consumer Council of the Ministry of Economic Affairs and Employees ’Cooperatives:“ Try to make the holding voltage of the output transistor and the protection transistor different. However, in order to achieve the above purpose, the manufacturing method must be changed. Therefore, the shortcomings of complex and tedious processes may arise. Using conventional technology in semiconductor devices, using the same structure of the output transistor as the output transistor to connect the output transistor in parallel, if the output transistor with shallow junction is against, or against high breakdown voltage, increase the protection circuit The occupied area of the crystal is inevitable, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 312 Qing 0599twf, doc / Jessica / 002 A7 B7 Employee Consumer Cooperative Printed by the Central Bureau of Standards of the Ministry of Economy— 5. Description of the invention (Y) The problem of increasing the price of chips. More specifically, as in the above-mentioned device, the protection product needs to be expanded as much as possible to the extent that the output transistor junction area is reduced, that is, if it is reduced due to shallow junction, another point, the protection transistor must be maintained The bonding area is large enough to resist the holding voltage of the process with high breakdown voltage. The present invention aims to provide a semiconductor element having a switch element that can be used as an electrostatic breakdown prevention circuit, which can resist when the reverse electrostatic surge voltage is lower than the output transistor source Pole collapse voltage to minimize the impact of the surge on the output transistor and prevent the voltage collapse of the output transistor. Another object of the present invention is to provide a semiconductor device with a voltage surge prevention circuit and an output transistor that are completed simultaneously without changing the manufacturing process of the semiconductor device, wherein the voltage collapse prevention circuit has a voltage collapse than conventional Prevent the circuit from having a large impedance to counter static surges. Another object of the present invention is to provide a semiconductor device that uses a MOS transistor or a two-carrier transistor as a protection transistor, thereby reducing the area occupied by the protection transistor and obtaining a protection transistor with a larger impedance To counter static surges. It is an object of the present invention to provide a semiconductor device which can be applied to various types of space conductor devices using MOS transistors as output transistors. Another object of the present invention is to provide a semiconductor device, which can be applied to two output transistors having a first conductivity type and a second conductivity type as the junction surface of the crystal ) f pack _ The size of the bound paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) 0599twf.doc / Jessica / 002 A7 B7 V. The description of the invention (Xi) is connected in parallel, so it has a resistance increase. Protection transistor against breakdown voltage. According to the above object, the present invention provides a semiconductor device having a first conductivity type active MOS output transistor, one end of a source / drain region is connected to an output terminal of the semiconductor device, and has a protection output The design that the transistor is destroyed by static electricity collapse. The design of the static electricity collapse protection means that the second conductive semiconductor switching transistor is connected in parallel to the output transistor, and one end is connected to the output terminal. As described above, when an electrostatic surge on the output transistor occurs at the output terminal of the semiconductor device, when the electrostatic surge voltage is lower than the breakdown voltage of the output transistor, the second conductivity type semiconductor switching element will action. Therefore, the adverse effect on the output transistor due to the reverse electrostatic surge is less than the conventional one. At the same time, the Ministry of Economic Affairs, Central Bureau of Standards, Employee and Consumer Cooperative printed the policy. At the same time, when manufacturing semiconductor devices, it can be seen from the circuit configuration that the second conductivity type semiconductor switching element can be formed at any position on the substrate according to the general process, Above, the manufacturing of the second conductivity type semiconductor switching element is included in the manufacturing process of semiconductor device formation. Therefore, the formation of the second conductivity type semiconductor switching element can be completed without any additional process. The above-mentioned advantages and objectives of the present invention will be more prominent after the detailed description of a preferred embodiment in accordance with the drawings . Brief description of the diagram = This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X25) 7 mm) 312848 A? 0599twf.doc / JesS1ca / 002 β? V. Description of the invention (b) Picture 1 The illustration of the embodiment, the output transistor is an explanatory diagram using PMOS; Figure 2 is another illustration of the first embodiment, the output transistor is an illustration of using NMOS; Figure 3 is the illustration of the second embodiment, output The transistor is an explanatory diagram using PMOS; Figure 4 is another explanatory diagram of the second embodiment, and the output transistor is an explanatory diagram using NMOS;
第5圖係第3實施例說明圖，使用一個輸出電晶體的 說明圖； N 第6圖係第3實施例另一種說明圖，使用複數個輸出 電晶體的說明圖； 第7圖係第4實施例說明圖； 第8圖係說明第4實施例的操作； 第9圖係第5實施例說明圖，保護電晶體是使用 MOS電晶體的說明圖； 第10圖係第5實施例另一種說明圖、保護電晶體是 使用雙載子電晶體的說明圖； 第11圖係本發明之應用例之說明圖； 第12圖係課題的說明圖；以及 第13圖係第1實施例之補充說明圖。 發明實施例 以下，請參照各圖式，其詳述本發明若干實施例的 重點，而且藉由這些實施例的說明本發明的特徵與優點 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 312848 A7 0 599twf.d〇c/JeSslca/002_B7 _ 五、發明説明（^/ ) 可以更加突顯。 現在請參閱各圖式，其說明本發明的實施例，在下 一個實施例中，其是假設半導體是P型矽基底。 1.第一實施例. 第1圖係提供第一實施例說明用，其包括第一導電 型電晶體11以作爲輸出電晶體用，與第二導電型電晶體 13，以作爲保護電晶體用，其中第一導電型電晶體11是 PMOS，而第二導電型電晶體13，則是NMOS。 將第一導電型電晶體U的汲極lid連接於做爲半導 體裝置輸出端子的輸出墊15，而其源極Us與N井連接 於第一電源供應線VDD，其閘極lid被連接於既定的信 號線（圖未顯示），以達到保護第一導電型電晶體11免於 受靜電突波的破壞。 1 同時，第二導電型電晶體13是用以當作一開關裝 置，其汲極13d連接於輸出墊15，而其源極13s連接於第 一電源供應線VDD，而閘極13g連接於正常操作時使第 二導電型電晶體13保護關閉狀態的第二電源供應線 Vss。而基底連接於第二電源供應線vss。因此’第一導 電型電晶體11與第二導電型電晶體13被設置於輸出墊15 與第一電源供應線Vdd之間，而並列形式連接著。 此第1實施例的半導體裝置’因靜電突波從輸出墊 15進入。請參照第I3圖以做說明。在第13圖之中’（；表 示逆方向，而d則表示順方向的汲極電流對汲極電壓 (ID-VD)之特性曲線圖。 10 本紙張尺度逋用中國國家標率（CNS ) A4规格（2丨0><2.97公釐） 312848 0599twf. doc/Jessica/〇〇2 A7 ---- 87__ 五、發明説明（g ) 此第1實施例的半導體裝置之中，成爲保護對象的 電晶體是第一導電型電晶體11，當負靜電突波被施加於 輸出墊I5時’第〜導電型電晶體^，從VDD來的逆方向 靜電突波是可見的。 在輸出墊15施加負靜電突波，則第一導電型電晶體 11的操作起始電壓，相當於如第U圖所示的源極_汲極 間之朋潰電壓(以下記成BVsd” 因此’若不提供第二導電型電晶體13，亦即NMOS 電晶體’以當作保護電晶體，則當靜電突波在超過 BVsd的某一點電壓時，會產生突波電流’從第一導電 型電晶體Η的汲極11 d往源極11s流通。 因爲靜電突波，在第二導電型電晶體13的汲極1.3d 與基底之間的PN接合處，變成順方向進行，所以靜電崩 潰保護電路的操作起始電壓，相當於第二導竃型電晶體 I3之中PN接合處所謂的平帶電壓（flat band voltage)(以下記成Vf)。若基底是採用矽基底，而不管 具有何種濃度的雜質時，則Vf若大約爲〇_6V。因此靜電 突波超過Vf的某—點電壓，會產生突波電流，而自第二 導電型電晶體13的汲極i3d與基底間流通後往源極13S。 而且此時，因爲Vf<BVsd，所以突波電流邊乎都進 入第二導電型電晶體13，所以，逆方向靜電突波流往第 一導電型電晶體11所造成的不退影響，遠比習知_減 緩。另外，依據第13圖所顯示的，當不提供第二導電型 電晶體I3，亦即NMOS電晶體，作爲保護電晶體時，第 11 本紙張从逍用中國國家棣準（CNS ) A4絲（210X297公釐） 0599twf.doc/Jessica/002 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（7 ) 一導電型電晶體11的保持電壓是Vi，而電流是、，在本 發明中，L相等的電流流經第二導電型電晶體13，所得 到的汲極電壓，以來表示。而保持電壓與汲極電壓的 關係是ν2<ν,。 相等電流流過的時候，所發生的焦耳發熟現象（汲 極電壓及電流的累積），於第二導電型電晶體13的一端 較小，而於第一導電型電晶體11的一端則較大，意即是 假設第一導電型電晶體11與第二導電型電晶體丨3具有相 同面積’遭受相同的焦耳發熱造成的破壞時，第二導電 型電晶體I3比起第一導電型電晶體11 ’可'以用較小的面 積，而具有較高的阻抗以對抗靜電突波的破壞。 根據以上的說明，此第一實施例的半導體裝置之 中’當做保護電晶體的是使用與輸出電晶體相反導電型 的MOS電晶體，所以，保護電晶體對於逆方向的靜電突 波對輸出電晶體破壞之操作起始電壓爲，因爲平帶電壓 Vf與習知的操作起始電壓BVsd比較，Vf<BVsd，所 .以’對於逆方向的靜電突波，保護電晶體比起輸出電晶 體較早動作，在操作中的汲極所承受的電壓比起習知同 一種導電型保護電晶體的保持電壓還低，因此，減少因 突波電流而產生的焦耳發熱現象，而獲致較高的阻値以 抵抗電壓崩潰。 而且’在第一實施例當中，可使用習知的CMOS-IC製造過程，不需要增加製造步驟，只需要改變圖案 (Pattern)設計，就可得到想要的效果。而且’關於保護 ctf先閣讀背面之注^^項再填寫本頁) f 裝— m HI- mi in 訂 本紙張尺度適用中國國家操準（CNs ) A4規格（210X297公釐） 312848 a 7 〇599twf.doc/Jessica/002 ____ 五、發明説明（|(?) 電晶體的佔有面積減少之功效，在以下的實驗結果可得 到驗證。使作爲輸出電晶體的第一導電型電晶體π的閘 極保持約40^，而且，使作爲保護電晶體的第二導電型 電晶體13的閘極保持約80；^。實施在美國軍事標準 3015.7號(厘11^丁〇-3 015.7)己被規格化的靜電破壞試 驗標準，其測得的崩潰電壓是1700V。. 同時，利用習知技術當做比較例，意即使用兩個 PMOS電晶體而構成輸出及保護兩電晶體,兩電晶體的閘 極總長度約300_，一樣實施MIL-STD-3015.7已被規 格化的靜電破壞試驗，而測得崩潰電壓只有1400V。. 用以上的結果可知，若依據本發明，雖減少保護電 晶體的佔有面積，但比起習知的裝置比起來，可獲致較 高的阻値。 另外，若輸出電晶體是NMOS電晶體，而其保護電 晶體爲PMOS電晶體時，如第2圖所示的電路構造，當然 也可適甩本發明。特別是，第二導電型電晶體11，亦 即，NMOS電晶體成爲被保護的電晶體，其汲極lid連 接於用以輸出的半導裝置的輸出端子（輸出墊15)，將此 源極11s與基底連接於第二電源供應線Vss，其閘極llg 連接於既定的信號線(圖未顯示）。 同時，第一導電型電晶體I3，亦即PMOS電晶體， 作爲保護電晶體，其汲極l3d連接於輸出墊15，而其源 極13s連接於第二電源供應線Vss，將通常動作時保持“ off”狀態之PMOS電晶體1 3之閘極13g與N井連接於第一 i3 本紙張尺度逋用中國國家橾準（CNS ) Μ規格（210X297公釐） A7 經濟部中央標準局貝工消费合作社印装 0599twf.doc/Jessica/002 D / 五、發明説明（Π ) 電源供應線VDD，其中第一電源供應線vDD的電位 (potential)使正常操作時第一導電型電晶體13保持關 閉。 2.第二實施例 請參照第1圖，第1圖係提供本發明第二實施例說明 用，其包括PMOS電晶體11以作爲輸出電晶體用’與一 NPN型雙載子電晶體17.，以作爲保護電晶體或一開關元 件用，其中PMOS電晶體11、輸入墊I5等其他構成元件 的連接關係，與第一實施例相同。 同時，NPN電晶體17當做保護電晶體，其射極l7e 連接於輸出墊15，其集極17c連接於第一電源供應線 VDD，基極17b連接於第二電源供應線Vss ’此處第二電 源供應線Vss的電位，爲使正常操作時NPN型雙載子電 晶體17保持關閉狀態之電位。因此，PMOS型電晶體11 與NPN型雙載子電晶體Π被設置於輸出墊15與第一電源 供應線VDD之間，而並列形式連接著。 在第2實施例的半導體裝置中，若將此輸出墊15當 作負極（negative pole) ’而靜電突波被施加於此’因 爲靜電突波在NPN電晶體17的射極-基極之間的PN接 合處，以順向方流通，所以當該靜電突波超越Vf的某一 點時，在NPN電晶體17的射極-基極之間’則會產生基 極電流會流通。 而且，基極電流流通後，NPN電晶體17會“開”，而 在射極17e—集極17c之間，會產生集極電流。 (ir先閱讀背面之注意事項再填寫本頁) f 装. 訂 本紙張尺度逋用中國國家梯準（CNS ) A4规格（210X297公釐） A7 B7 0599twf.doc/Jessica/002 五、發明説明（p) 因爲對一般NPN電晶體而言，集極電流大於基極電 流的數倍至數10倍，所以最後靜電突波幾乎都成爲集極 電流，也就是說，流往PMOS電晶體11的源極113而被 吸收。也就是說，平帶電壓Vf小於操作起始電壓 BVsd，所以，突波電流幾乎都進入NPN電晶體17，而 不流進PMOS電晶體11。 根據以上的說明，該第2實施例的半導體裝置之 中，是以與輸出電晶體相反導電型的半導體層構成具务寸 極與集極之雙載子電晶體做爲保護電晶體，所以與逆向 靜電突波對應之操作起始電壓爲Vf。 因爲與習知技術的操作起始電壓BVsd比較’ Vf<BVsd，故對於外施之逆方向靜電突波，保護電晶體 會比輸出電晶體還早動作。'且動作中的保持電壓比習知 同一導電型保護電晶體還低。此結果使得因突波電流產 生靜電破壞發生所伴隨的焦耳發熱現象可以減低’並獲 致較高的阻抗，以對抗電壓崩潰。 而且在此第2實施例中，將雙載子電晶體用來保護 電路，所以不需要閘極電極，因此，也不需要供給閘極 電位，故比起第1實施例，可以更縮小保護電晶體的佔 有面積。 另外，如第4圖所示，將NMOS電晶體當作輸出電 晶體，而以PNP電晶體當作保護電晶體也是可行的。也 就是說，成爲保護的對象NMOS電晶體11 ’其汲極lid 連接於做爲半導體裝置之輸出端子的輸出墊I5，其源極 15 尽紙張尺度適用中國國家標率（CNS ) A4a格（210X297公釐） 先 闖 意 事 項 i 經濟部中央棣準局員工消費合作杜印製 經濟部中央橾準局貝工消費合作社印製 312848 0599twf.doc/Jessica/0 02 五、發明説明（p) 11s以及基底連接於第二電源供應線Vss ’而其閘極llg 連接於既定的信號線（圖未顯示)。 同時，PNP電晶體17當做保護電晶體，其射極 17e、集極17c、基極17b分別連接於輸出墊I5、第二電 源供應線vss、第一電源供應線VDD ’此處第一電源供應 線VDD的電位，爲使正常操作時PNP型雙載子電晶體17 保持關閉狀態之電位。 3.第三實施例： 請參照第5圖，其繪示本發明較佳之第三實施例之 用導體元件。其說明在並列連接著的輸出電晶體11與第 二導電型的的開關元件中，設置一抑制流往輸出電晶體 11的靜電突波電流之分流爲目的之電阻元件19。 . 輸出電晶體Π的汲極1 id連接於介於保護電晶體13 的汲極13d與輸出墊15之間的連接點P1，電阻元件19位 位於其間。 在保護電晶體13的汲極Hd與輸出電晶體的汲極 lid之間加入電阻元件19 ’則會抑制由輸出墊15施加的 靜電突波，流往輸出電晶體11的電流量，而往保護電晶 體13流入的電流量會提高。 因此與第一、第二實施例比起來，本第三實施例提 高了保護電路體對於輸出電晶體的保護效果。 而且，本實施例對於做爲保護對象的輸出電晶體的 面積很小時特別有效。若電阻元件19的電阻越大，則效 果也越大。所以可以使用電阻率高的井蓝當電阻’而不 (ir先閲讀背面之注意事項再填寫本頁)Figure 5 is an explanatory diagram of the third embodiment, using one output transistor; N Figure 6 is another explanatory diagram of the third embodiment, using a plurality of output transistors; Figure 7 is the fourth Figure 8 illustrates the operation of the fourth embodiment; Figure 9 illustrates the fifth embodiment; Figure 9 illustrates the use of MOS transistors; Figure 10 illustrates another example of the fifth embodiment. The explanatory diagram and the protective transistor are explanatory diagrams using a double carrier transistor; FIG. 11 is an explanatory diagram of an application example of the present invention; FIG. 12 is an explanatory diagram of a subject; and FIG. 13 is a supplement to the first embodiment Illustrating. In the following, please refer to the drawings, which describe in detail the key points of several embodiments of the present invention, and illustrate the features and advantages of the present invention through these embodiments. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 Mm) 312848 A7 0 599twf.d〇c / JeSslca / 002_B7 _ Fifth, the invention description (^ /) can be more prominent. Referring now to the drawings, which illustrate an embodiment of the present invention, in the next embodiment, it is assumed that the semiconductor is a P-type silicon substrate. 1. First embodiment. Figure 1 provides a description of the first embodiment, which includes a first conductivity type transistor 11 as an output transistor, and a second conductivity type transistor 13 as a protection transistor , Where the first conductivity type transistor 11 is PMOS, and the second conductivity type transistor 13 is NMOS. The drain lid of the first conductivity type transistor U is connected to the output pad 15 as the output terminal of the semiconductor device, and its source Us and N well are connected to the first power supply line VDD, and its gate lid is connected to a predetermined Signal line (not shown) to protect the first conductivity type transistor 11 from electrostatic surge. 1 At the same time, the second conductivity type transistor 13 is used as a switching device, its drain 13d is connected to the output pad 15, and its source 13s is connected to the first power supply line VDD, and the gate 13g is connected to the normal During operation, the second conductive type transistor 13 protects the off-state second power supply line Vss. The substrate is connected to the second power supply line vss. Therefore, the 'first conductivity type transistor 11 and the second conductivity type transistor 13 are disposed between the output pad 15 and the first power supply line Vdd, and are connected in parallel. The semiconductor device of the first embodiment enters the output pad 15 due to electrostatic surge. Please refer to Figure I3 for explanation. In Figure 13 '(; indicates the reverse direction, and d indicates the characteristic curve of the drain current to drain voltage (ID-VD) in the forward direction. 10 The paper scale uses the Chinese National Standard Rate (CNS) A4 specification (2 丨 0> < 2.97mm) 312848 0599twf. Doc / Jessica / 〇〇2 A7 ---- 87__ V. Description of the invention (g) This semiconductor device of the first embodiment is subject to protection The transistor is the first conductivity type transistor 11, when a negative electrostatic surge is applied to the output pad I5 ~ the first conductivity type transistor ^, the reverse direction electrostatic surge from VDD is visible. In the output pad 15 When a negative electrostatic surge is applied, the operating starting voltage of the first conductivity type transistor 11 is equivalent to the source-drain potential breakdown voltage shown in Figure U (hereinafter referred to as BVsd). Therefore, if not provided The second conductivity type transistor 13, that is, the NMOS transistor 'is used as a protection transistor. When the electrostatic surge exceeds a certain voltage of BVsd, a surge current will be generated from the first conductivity type transistor Η The drain 11 d flows to the source 11 s. Due to the electrostatic surge, the drain 1 of the second conductivity type transistor 13 .3d The PN junction between the substrate and the substrate becomes forward, so the starting voltage of the electrostatic breakdown protection circuit is equivalent to the so-called flat band voltage (flat band voltage) of the PN junction in the second conductive transistor I3 voltage) (hereinafter referred to as Vf). If the substrate is a silicon substrate, regardless of the concentration of impurities, if Vf is about 0_6V. Therefore, the electrostatic surge exceeds a certain point of Vf voltage, will produce a sudden The wave current flows from the drain electrode i3d of the second conductivity type transistor 13 and the substrate to the source electrode 13S. And at this time, because of Vf < BVsd, the surge current almost enters the second conductivity type transistor 13 Therefore, the non-regressive effect caused by the reverse direction electrostatic surge flowing to the first conductivity type transistor 11 is much slower than the conventional _. In addition, according to the display in FIG. 13, when the second conductivity type transistor is not provided I3, also known as NMOS transistor, as the protection transistor, the eleventh paper is used from the Chinese National Standard (CNS) A4 wire (210X297 mm) 0599twf.doc / Jessica / 002 A7 B7 Employee of the Central Standards Bureau of the Ministry of Economy Printed by consumer cooperatives 7) The holding voltage of one conductive type transistor 11 is Vi, and the current is, in the present invention, the current equal to L flows through the second conductive type transistor 13, and the resulting drain voltage is expressed and maintained. The relationship between voltage and drain voltage is ν2 < ν ,. When equal current flows, the Joule ripening phenomenon (accumulation of drain voltage and current) occurs at one end of the second conductivity type transistor 13, The one end of the first conductivity type transistor 11 is larger, which means that it is assumed that the first conductivity type transistor 11 and the second conductivity type transistor have the same area and suffer damage caused by the same Joule heating. The two-conductivity-type transistor I3 can use a smaller area than the first-conductivity-type transistor 11 and has a higher impedance to resist the destruction of electrostatic surges. According to the above description, in the semiconductor device of this first embodiment, the MOS transistor of the opposite conductivity type to the output transistor is used as the protection transistor. Therefore, the protection transistor The operation starting voltage of crystal destruction is that, because the flat band voltage Vf is compared with the conventional operation starting voltage BVsd, Vf < BVsd. Therefore, for the electrostatic surge in the reverse direction, the protection transistor is better Early operation, the voltage that the drain in operation is subjected to is lower than the holding voltage of the conventional conductive transistor of the same conductivity type, therefore, the Joule heating phenomenon caused by the surge current is reduced, and a higher resistance is obtained To resist voltage collapse. Moreover, in the first embodiment, the conventional CMOS-IC manufacturing process can be used, without adding manufacturing steps, and only by changing the pattern design, the desired effect can be obtained. And 'About the protection of ctf first read the note on the back ^^ and then fill out this page) f Pack — m HI- mi in The size of the printed paper is applicable to the Chinese National Standards (CNs) A4 specifications (210X297 mm) 312848 a 7 〇 599twf.doc / Jessica / 002 ____ 5. Description of the invention (| (?) The effect of reducing the occupied area of the transistor can be verified in the following experimental results. The gate of the first conductivity type transistor π as the output transistor The electrode is kept at about 40 ^, and the gate electrode of the second conductivity type transistor 13 as the protective transistor is kept at about 80; ^. Implemented in the US military standard No. 3015.7 (Cent 11 ^ Ding 〇-3 015.7) has been standardized The standard of the electrostatic breakdown test is 1700V. At the same time, the conventional technology is used as a comparative example, which means that two PMOS transistors are used to form the output and protect the two transistors and the gates of the two transistors. The total length is about 300 mm, and the static breakdown test that has been standardized by MIL-STD-3015.7 is also implemented, and the measured breakdown voltage is only 1400V. From the above results, it can be seen that, according to the present invention, although the occupied area of the protection transistor is reduced But compared to the conventional In comparison, a higher resistance can be achieved. In addition, if the output transistor is an NMOS transistor and the protection transistor is a PMOS transistor, the circuit structure shown in Figure 2 can of course be adapted to the cost. In particular, the second conductivity type transistor 11, that is, the NMOS transistor becomes a protected transistor, and its drain lid is connected to the output terminal (output pad 15) of the semiconductor device for output. The source electrode 11s and the substrate are connected to the second power supply line Vss, and the gate electrode 11g is connected to a predetermined signal line (not shown). At the same time, the first conductivity type transistor I3, that is, the PMOS transistor, serves as a protection transistor , Its drain 13d is connected to the output pad 15, and its source 13s is connected to the second power supply line Vss, the gate 13g of the PMOS transistor 13 that is kept in the "off" state during normal operation and the N well are connected to the first 1. The size of this paper uses the Chinese National Standard (CNS) M specifications (210X297 mm). A7 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 0599twf.doc / Jessica / 002 D / V. Description of the invention (Π) Supply line VDD, where the first power supply line The potential of the vDD keeps the first conductivity type transistor 13 off during normal operation. 2. For the second embodiment, please refer to FIG. 1, which provides a description of the second embodiment of the present invention, which includes PMOS The crystal 11 is used as an output transistor and an NPN type double carrier transistor 17. It is used as a protection transistor or a switching element. The connection relationship between the PMOS transistor 11, the input pad I5 and other constituent elements, and The first embodiment is the same. At the same time, the NPN transistor 17 is used as a protection transistor, its emitter 17e is connected to the output pad 15, its collector 17c is connected to the first power supply line VDD, and its base 17b is connected to the second power supply line Vss. The potential of the power supply line Vss is a potential that keeps the NPN bipolar transistor 17 in the off state during normal operation. Therefore, the PMOS type transistor 11 and the NPN type double carrier transistor Π are provided between the output pad 15 and the first power supply line VDD, and are connected in parallel. In the semiconductor device of the second embodiment, if the output pad 15 is regarded as a negative pole 'and an electrostatic surge is applied thereto' because the electrostatic surge is between the emitter and base of the NPN transistor 17 The PN junction of the terminal flows in the forward direction, so when the electrostatic surge exceeds a certain point of Vf, a base current will flow between the emitter and base of the NPN transistor 17. Furthermore, after the base current flows, the NPN transistor 17 will be "on", and a collector current will be generated between the emitter 17e and the collector 17c. (ir read the precautions on the back and then fill out this page) f Pack. The size of the paper is in accordance with China National Standard (CNS) A4 specification (210X297mm) A7 B7 0599twf.doc / Jessica / 002 5. Description of invention ( p) Because for general NPN transistors, the collector current is several to ten times greater than the base current, so in the end, the electrostatic surge almost becomes the collector current, that is, the source of the PMOS transistor 11 The pole 113 is absorbed. That is, the flat band voltage Vf is smaller than the operation start voltage BVsd, so almost all the surge current enters the NPN transistor 17, but does not flow into the PMOS transistor 11. According to the above description, in the semiconductor device of the second embodiment, the semiconductor layer of the opposite conductivity type to the output transistor constitutes a bipolar transistor with a current electrode and a collector as the protection transistor, so The operation starting voltage corresponding to the reverse electrostatic surge is Vf. Since the operation start voltage BVsd of the conventional technique is compared with Vf < BVsd, the protection transistor will act earlier than the output transistor for the applied reverse electrostatic surge. 'And the holding voltage during operation is lower than that of the conventional protection transistor of the same conductivity type. As a result, the Joule heating phenomenon caused by the electrostatic destruction caused by the surge current can be reduced and a higher impedance can be achieved to prevent voltage collapse. Moreover, in this second embodiment, the bipolar transistor is used to protect the circuit, so the gate electrode is not needed, and therefore, the gate potential is not required to be supplied, so the protection circuit can be further reduced compared to the first embodiment. The occupied area of the crystal. In addition, as shown in Figure 4, it is also feasible to use NMOS transistors as output transistors and PNP transistors as protection transistors. That is to say, the NMOS transistor 11 ′ that is the object of protection has its drain lid connected to the output pad I5 that is the output terminal of the semiconductor device, and its source 15 conforms to the Chinese standard rate (CNS) A4a grid (210X297) Mm) First of all, I ’m interested in the matter. I Consumer spending cooperation of the Ministry of Economic Affairs, Central Bureau of Precinct Printing, printed by the Ministry of Economic Affairs, Central Bureau of Preservation, Beigong Consumer Cooperative. 312848 0599twf.doc / Jessica / 0 02 V. Invention description (p) 11s and The substrate is connected to the second power supply line Vss' and its gate 11g is connected to a predetermined signal line (not shown). At the same time, the PNP transistor 17 is used as a protection transistor, and its emitter 17e, collector 17c, and base 17b are respectively connected to the output pad I5, the second power supply line vss, and the first power supply line VDD. Here, the first power supply The potential of the line VDD is a potential that keeps the PNP bipolar transistor 17 in the off state during normal operation. 3. Third Embodiment: Please refer to FIG. 5, which illustrates a conductor element used in the third preferred embodiment of the present invention. In the description, the output transistor 11 and the second conductivity type switching element connected in parallel are provided with a resistance element 19 for the purpose of suppressing the shunt of the electrostatic surge current flowing to the output transistor 11. The drain 1 id of the output transistor Π is connected to the connection point P1 between the drain 13d of the protection transistor 13 and the output pad 15 with the resistive element 19 located therebetween. Adding a resistance element 19 'between the drain Hd of the protection transistor 13 and the drain lid of the output transistor will suppress the electrostatic surge applied by the output pad 15 and the amount of current flowing to the output transistor 11 will be protected The amount of current flowing into the transistor 13 will increase. Therefore, compared with the first and second embodiments, the third embodiment improves the protection effect of the protection circuit body on the output transistor. Moreover, this embodiment is particularly effective when the area of the output transistor to be protected is small. The greater the resistance of the resistance element 19, the greater the effect. So you can use the well blue high-resistivity resistor instead of (ir read the notes on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公藿） A7 0599twf,doc/Jessica/002 五、發明説明（%) 會有因配置電阻而使保護電路占有面積增大方面的缺點 (dermerit).。 另外，電阻元件19的應用，也可以適用於以雙載子 電晶體作爲保護電晶體用途之時機(如第3圖所示）。 而且，當複數個輸出電晶體以並列形式連接於輸出 墊15時（如第6圖所繪示），將電阻元件19置於不影響 輸出電晶體Π爲保護對象的以外的輸電晶體的位置是合 適的。 請參照第6圖，輸出墊15與第一輸出電晶體 (PMOS電晶體）11，以及第二輸出電晶體（NMOS電 晶體）21以並列的方式連接著。所以，電阻元件19被設 置於第一以及第二電晶體11、21各別汲極的接點？2之上 的第1輸出電晶體的另一側。 在第6圖的例子中，電阻元件19被設置於第一輸出 電晶體的源極Us與第一電源供應線VDD之間。也可以將 電阻元件設置於第一輸出電晶體11的汲極lid與連接點 P2之間。 4.第四實施例： 接著，請參閱第7 (A)與7 (B)圖，沿續第四實 施例之後，其說明在半導體裝置中，具備抑制因靜電突 波電流所引起的發熱現象之功能。 . 當使用雙載子電晶體當作保護電晶體（如上述第二 實施例），設計集極接合面積會考慮因靜電突波電流所引 起影響而盡可能使接面合積寬廣。 ___._ 17 本紙張尺度適用中國國家標準（CMS ) A4規格（210X297公釐） 05 99twf. doc/Jcssica/002 Λ/ __^_B7 _ 五、發明説明（β ) ,This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 commonweed) A7 0599twf, doc / Jessica / 002 V. Description of the invention (%) There will be shortcomings in the area of the protection circuit increased due to the configuration of the resistance ) .. In addition, the application of the resistance element 19 can also be applied to the timing of using the two-carrier transistor as a protection transistor (as shown in Fig. 3). Moreover, when a plurality of output transistors are connected in parallel to the output pad 15 (as shown in FIG. 6), the resistance element 19 is placed at a position other than the transmission transistor that does not affect the output transistor Π as the protection object is suitable. Referring to FIG. 6, the output pad 15 is connected to the first output transistor (PMOS transistor) 11 and the second output transistor (NMOS transistor) 21 in parallel. Therefore, the resistance element 19 is provided at the contact of the respective drains of the first and second transistors 11, 21? 2 on the other side of the first output transistor. In the example of Fig. 6, the resistance element 19 is provided between the source Us of the first output transistor and the first power supply line VDD. The resistance element may be provided between the drain lid of the first output transistor 11 and the connection point P2. 4. Fourth Embodiment: Next, please refer to FIGS. 7 (A) and 7 (B). Following the fourth embodiment, it is explained that the semiconductor device is equipped with suppression of heat generation caused by electrostatic surge current. Function. When using a two-transistor transistor as a protection transistor (as in the second embodiment above), the collector junction area is designed to take into account the impact of electrostatic surge currents to make the junction area as wide as possible. ___._ 17 This paper scale is applicable to the Chinese National Standard (CMS) A4 specification (210X297 mm) 05 99twf. Doc / Jcssica / 002 Λ / __ ^ _ B7 _ V. Description of the invention (β),
因此，第四實施例是沿用第二實施例已說明的NPN 電晶體17之寬廣（lateral)型的NPN電晶體，其詳述如 下〇 於是，請參照第7圖(A)與(B)。（A)是部分平面圖而 (B)是(A)圖I - I線之斷面圖。 首先，在P型矽基底31形成N型雜質擴散區33，而 將其當做射極，然後，形成將N型雜質擴散區33環繞的 P型雜質擴散區35，而用以當做歐姆接觸（ohmic contact)，並且在區域35周圍形成用以當做集極的N型 雜質擴散區37，且在第7(A)、（B)圖的編號39則是 場氧化物。 在電晶體17之中’而集極-基極接合界面是NM慘 質擴散區37的內側邊界37a，而射極-基極接合界面則 是N型雜質擴散區的內側邊界33a。因集極-基極接合 處，有充分寬的接合面積，故因靜電突波引起的發熱現 象會儘可能減少。 集極接合面積的設計，取決於半導體裝置理論之計 算或經驗値。 在第四實施例之中，在各雜質擴散區皆以金屬作電 性連接，例如鋁A1導電層穿過接觸孔（contact holes) 以作連接，最後由連接外部用的銲墊(bonding pad)往 外拉出。 在PMOS電晶體11中，對於負逆方向的靜電突波， 其受到NPN電晶體17之射極-基極之間的PN接合處成 本紙張又度適用中國國家標準（CNS) A4规格（210><297公釐〉 A7 0 5 99twf.doc/Jessica/0 02 五、發明説明（A ) 爲順方向而得到保護，其對於靜電突波的操作起始電壓 .是 Vf。 同樣地，在NPN電晶體中，當靜電突波超過Vf 時’則基極電流會向NPN電晶體流通，而爲基極電流數 倍至數十倍的集極電流也會流通。 請參照第8圖，其顯示當靜電突波電壓爲Vx時， NPN電晶體17的各節點(node)的電位狀態圖式，靜電突 波Vx幾乎都流入集極-基極之間的接合界面。此意味著 當集極電流流通時，集極-基極之間的電位差遠大於射 極-基極之間的電位差，並且意味著在集極一基極接合 之處，因電流與電壓的累積而產生焦耳發熱比較多。 因此，在第四實施例中，考慮上述的焦耳發熱現 象，而將集極-基極接合面積增加，所以集極-基極接 合處所發生較大的焦耳發熱量可以擴散至整個接合面 積，使得單位面積平均的發熱量可以減低，所以得到較 大的阻抗以抑制靜電突波的破壞。· 而且，在第四實施例中，特別採用圓形的雙載子電 晶體爲保護電晶體以減少其佔有面積，而儘可能地製造 出加強電阻以對抗靜電崩潰之半導體裝置。 ' 而且此例說明了採用橫向型（lateral)雙載子電晶 體作爲保護電晶體，其在集極接合面積考慮了因靜電突 波產生的發熱現象，而採用縱型（longitudinal)的雙 載子電晶體當成保護電晶體當然也可以適用。 5.第五實施例： 本紙張尺度適用中國國家榡準（CNS ) A4规格（210X297公嫠） A7 0599twf. doc/Jessica/002 五、發明説明（丨) 接著，請參照第9 (A)、（B)圖，其顯示本發明第 五實施例之示意圖，其藉由下列兩例，說明靜電崩潰對 於半導裝置的導電金屬之影響。 5 -1例 第五實施例之一的例子中，採用與輸出電晶體相反導 電型的MOS電晶體作爲保護電晶體時，.考慮連接於半導 體裝置的輸出端子的另一端（閘極的一側）的源-汲極區 域，其連接於導線金屬距離，其可使得因爲靜電突波電 流之焦耳發熱現象所產生的導線金屬的擴散現象降低° 第9圖（A)顯示與第1圖相同的半導體裝置電路國’而 第9圖(B)顯示當作保護電晶體的NMOS電晶體13，其在 於矽基底的實際配置圖。在第9圖(B)之中，源極13s表 示源-汲極之中，連接於半導體裝置的輸出墊15的另一 端，X表示連接點13x與源極13s之距離，而VDD導線至 源-汲極區之中的閘極13g的一側的距離，其必須考慮不 受靜電突波電流之發熱現象所導致的導電金屬擴散之影 響。 通常，在半導體裝置的設計中，X的大小取決於理 論之計算或經驗値。所以，此距離X大於距離y (介於連 接點l3y與汲極13d之間，且位於Vss導線至源-汲極之 中的閘極13g的一側有關），鄰接於接觸孔的導電金屬 會因焦耳發熱現象而熔融，進而向基底擴散，當熔融金 屬的擴散超越PN接合界面時則會造成靜電崩潰破壞。 請參第9圖(B)的MOS電晶體，S、D各別代表pN接 20 本紙張尺度適用中國國家樣準（CNS) A4规格（210χ·297公釐） 312848 A7 Ο 5 99 twf. doc/Jessie a/002 _ 157 五、發明説明（G) 合界面，S是閘極鄰接的源極13s界面，而D則是閘極另 一側鄰接的汲極13d界面。 而當突波電流往NMOS電晶體13的源極-汲極之間 流通時，如第8圖所說明的理由，源極一基底間接合界 面的發熱量比起汲極-基底間的接合界面還多。. 因此，從源極13s與導線金屬之連接位置13x至閘極 電極之間的距離，亦即將源極-基底間接合界面的距離 X增加，使熔融物質從發熱源避開，所以在金屬導線熔 融時，熔融的金屬擴散而超過接合界面之前，較大的突 波電流必然流通，由於上述兩因素，可得到較高的阻 値，而促進靜電突波崩潰防止的能力。 在本實施例（5-1)中，作爲保護電晶體所使用M0S 電晶體，其可減少保護電晶體佔有面積的增加，而製造 出抗靜電破壞效果優異的半導體裝置。 5-2 例： 請參照第10圖(A)與(B)，其顯示本發明第五實施例的 第二例，第10圖（A)是上述的橫向型NPN電晶體的平面 圖。（B)則是第1〇圖（a)Q部分的放大圖。 當使用雙載子電晶體作爲保護電晶體時，須使集極與 被連接的金屬導線的連接位置到集極接合面的距離，幾 乎不受靜電突波電流所引起的發熱之金屬導線擴散之影 響所需的適合距雛。 請參照第10 (B)圖，距離川爲從介於當作集極N型 雜質擴散區3 7與金屬導線（圖未顯示）之間的連接點3 7x _ 21 本紙張適用中國國家襟率《CNS ) A4規格（2Η)χ297公釐） A7 059 9twf.doc/Jessica/002 五、發明説明（f?) 到集極接面37a，必須考慮其幾乎不受靜電突波電流所 引起的發熱之金屬導線的擴散影響的距離。 相同地，距離、以是取決於半導體裝置設計之理論計 算或經驗値。而此距離L/從介於當作射極N型雜質擴散 區33與金屬導線（圖未顯示）之間的連接點33x到射極接 面33a的距離L2還大。 鄰接於連接點的導線金屬會被焦耳發熱而熔融，然後 往基底擴散，接著當熔融金屬通過接面之界面時，靜電 崩潰將會發生，會造成不可回復的故障亦即是造成破 壞。 再者，以第8圖以雙載子電晶體爲保護電晶體爲例， 在其集極-基極接合界面因突波電流引起的發熱量比起 來射極-基極接合界面還多。 因此，將介於集極鄰接的接觸孔與集極-基極接合界 面之間的距離增加，而使可熔融物質從發熱處隔開，所 以在金屬導線熔融時，熔融的金屬擴散而超過接合界面 之前，較大的突波電流必然流通，由於上述兩因素，可 得到較高的阻値，而促進靜電突波崩潰防止的能力。 經濟部中央標準局員工消費合作社印製 在本實施例（5-2)中，作爲保護電晶體所使用雙載子 電晶體，其可減少保護電晶體佔有面積的增加，而製造 出抗靜電破壞效果優異的半導體裝置。 本發明較佳實施例的半導體裝置的應用例請參照第11 圖。 本發明可以適用於各種具備以第一導電型的MOS電晶 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） 112848 0599twf.doc/Jessica/002 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明) '體作爲輸出電晶體的半導體裝置。 請參照第11圖，其顯示其中1個應用例，即是用於半 導體記憶裝置中的動態隨機存取記憶體DRAM(dynamiC random access memory)的適用例。在DRAM40中，具 有由複數個記憶體單元(memory cell)41 a組成的記憶體 陣列（memory array)41，內部電路區43、輸出電路區 45。本發明省略說明記憶體陣列41、內部電路區43的關 係。 輸出電路45由PMOS電晶體及NMOS電晶體的兩個輸 出電晶體11組成，而其中一輸出電晶體由連接於作爲保 護電晶體的NMOS電晶體之PMOS電晶體構成的，而另 一個輸出電晶體則是由連接於作爲保護電晶體的PMOS 電晶體之NMOS電晶體所構成，其二者如上述本發明的 既定關係來連接。 若依據本適用例，保護電晶體的占有面積不會增加， 且製造流程也不需變更，其可使本發明所應用的DRAM 比習知具更佳的抗靜電破壞能力。若根據本發明的半導 體裝置，其具有第一導電型而源極-汲極區的一方連接 於輸出墊的MOS型輸出電晶體，形成靜電保護電路（保 護電晶體）是可能的，其將第二導電型的開關元件連接 一端於輸出墊，保護電晶體與輸出電晶體形成並列連接 關係，並且其閘極（或基底）連接於可以使保護電晶體 保持於正常操作時爲’關閉’的狀態的電位。 由本半導體裝置的輸出端子，往輸出電晶體施加逆方 23 (會先閎讀背面之注意事項再填寫本頁) f 裝· 本紙張尺度適_用中國國家標隼（CNS〉A4規格（210X297公釐） 經濟部中央揉準局員工消費合作杜印製 31^848 A7 0599twf.doc/Jessica/002 扣 五 '發明説明（2| ) 向靜電突波，並且當靜電突波電壓低於輸出電晶體的崩 潰電壓時，第二導電型的半導體開關元件會動作。所 以，逆方向靜電突波對於輸出電晶體的影響比習知還 小。 而且，本發明另一優點爲，當使用較低的操作電壓， 半導體開關元件的佔有面積可以儘可能地減小，且因爲 本半導體開關元件，使用原本的半導體裝置的製程就可 製造出來，所以保護電晶體的佔有面積不會增加，且製 造流程不需變更就可提供因提高阻抗而比習知抗靜電突 波破壞能力更佳的半導體裝置。. 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍內，當可作些許之更動與潤飾，因此本發明 之保護範圔當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）Therefore, the fourth embodiment is to follow the NPN transistor 17 of the lateral type described in the second embodiment. The detailed description is as follows. Therefore, please refer to FIGS. 7 (A) and (B). (A) is a partial plan view and (B) is a cross-sectional view taken along line I-I of (A). First, an N-type impurity diffusion region 33 is formed on the P-type silicon substrate 31 and used as an emitter. Then, a P-type impurity diffusion region 35 surrounded by the N-type impurity diffusion region 33 is formed and used as an ohmic contact (ohmic contact) contact), and an N-type impurity diffusion region 37 serving as a collector is formed around the region 35, and the number 39 in FIGS. 7 (A) and (B) is a field oxide. In the transistor 17, the collector-base junction interface is the inner boundary 37a of the NM heavy diffusion region 37, and the emitter-base junction interface is the inner boundary 33a of the N-type impurity diffusion region. Since the collector-base junction has a sufficiently wide junction area, the phenomenon of heat generation due to electrostatic surges is reduced as much as possible. The design of the collector junction area depends on the theoretical calculation or empirical value of the semiconductor device. In the fourth embodiment, metal is used for electrical connection in each impurity diffusion region, for example, an aluminum A1 conductive layer passes through contact holes for connection, and finally a bonding pad for external connection is used. Pull it out. In the PMOS transistor 11, for the negative and negative electrostatic surge, it is subjected to the PN junction between the emitter and base of the NPN transistor 17 and the cost is again applicable to the Chinese National Standard (CNS) A4 specification (210 > < 297 mm> A7 0 5 99twf.doc / Jessica / 0 02 V. Description of invention (A) is protected in the forward direction, and its operating starting voltage for electrostatic surge is Vf. Similarly, in NPN In the transistor, when the electrostatic surge exceeds Vf, the base current will flow to the NPN transistor, and the collector current, which is several to several tens of times of the base current, will also flow. Please refer to Figure 8 for the display When the electrostatic surge voltage is Vx, the potential state pattern of each node of the NPN transistor 17 and the electrostatic surge Vx almost flow into the junction interface between the collector and the base. This means that when the collector current When circulating, the potential difference between the collector and the base is much larger than the potential difference between the emitter and the base, and it means that at the junction of the collector and the base, there is more Joule heating due to the accumulation of current and voltage. Therefore, in the fourth embodiment, considering the Joule heating phenomenon described above, and The collector-base junction area is increased, so the larger Joule heat generated at the collector-base junction can be diffused to the entire junction area, so that the average heat generation per unit area can be reduced, so a large impedance is obtained to suppress The destruction of electrostatic surges. Moreover, in the fourth embodiment, a circular double-carrier transistor is particularly used to protect the transistor to reduce its occupied area, and a semiconductor with a strengthened resistance to resist electrostatic collapse is manufactured as much as possible ”And this example illustrates the use of lateral dual carrier transistors as protective transistors, which considers the phenomenon of heat generation due to electrostatic surges in the collector junction area, and the use of longitudinal (longitudinal) double Carrier transistors can also be used as protective transistors. 5. Fifth embodiment: This paper size is applicable to China National Standard (CNS) A4 specification (210X297 public daughter) A7 0599twf. Doc / Jessica / 002 V. Description of the invention (丨) Next, please refer to Figure 9 (A), (B), which shows a schematic diagram of the fifth embodiment of the present invention, which uses the following two examples to illustrate the static breakdown The influence of the conductive metal of the semiconductor device. 5-1 Example In the example of the fifth embodiment, when a MOS transistor of the opposite conductivity type to the output transistor is used as the protection transistor, consider connecting to the output terminal of the semiconductor device The source-drain region at the other end (the side of the gate), which is connected to the wire metal distance, can reduce the diffusion phenomenon of the wire metal due to the Joule heating phenomenon of electrostatic surge current ° Figure 9 ( A) shows the same semiconductor device circuit country as in FIG. 1 and FIG. 9 (B) shows the NMOS transistor 13 as a protection transistor, which is actually arranged on the silicon substrate. In FIG. 9 (B), the source 13s represents the source-drain, which is connected to the other end of the output pad 15 of the semiconductor device, X represents the distance between the connection point 13x and the source 13s, and the VDD wire to the source -The distance on the side of the gate electrode 13g in the drain region must be considered not to be affected by the diffusion of the conductive metal caused by the heating phenomenon of the electrostatic surge current. Generally, in the design of semiconductor devices, the size of X depends on theoretical calculations or empirical values. Therefore, this distance X is greater than the distance y (between the connection point 13y and the drain 13d, and located on the side of the gate 13g from the Vss wire to the source-drain), the conductive metal adjacent to the contact hole will Due to the Joule heating phenomenon, it melts and then diffuses to the substrate. When the diffusion of the molten metal exceeds the PN junction interface, it will cause electrostatic collapse and damage. Please refer to the MOS transistor in Figure 9 (B), S and D stand for pN and 20 respectively. The paper size is applicable to China National Standards (CNS) A4 (210χ · 297mm) 312848 A7 Ο 5 99 twf. Doc / Jessie a / 002 _ 157 V. Description of invention (G) Joint interface, S is the source 13s interface adjacent to the gate, and D is the drain 13d interface adjacent to the other side of the gate. When the surge current flows between the source and the drain of the NMOS transistor 13, for the reason explained in FIG. 8, the heat generation of the junction interface between the source and the substrate is higher than that between the drain and the substrate. There are more. Therefore, the distance from the connection position 13x of the source electrode 13s to the wire metal to the gate electrode, that is, the distance X between the source-substrate junction interface is increased, so that the molten material is avoided from the heat source, so the metal wire When melting, before the molten metal diffuses beyond the junction interface, a large surge current must flow. Due to the above two factors, a higher resistance value can be obtained, and the ability to prevent electrostatic surge collapse is promoted. In the present embodiment (5-1), the MOS transistor used as the protection transistor can reduce the increase in the area occupied by the protection transistor, and produce a semiconductor device excellent in antistatic destruction effect. 5-2 Example: Please refer to FIGS. 10 (A) and (B), which shows a second example of the fifth embodiment of the present invention. FIG. 10 (A) is a plan view of the above-mentioned lateral NPN transistor. (B) is an enlarged view of part Q of Fig. 10 (a). When using a double carrier transistor as a protective transistor, the distance between the connection position of the collector and the connected metal wire to the junction surface of the collector must hardly be diffused by the metal wire that is heated by the static surge current Affect the required distance from the young. Please refer to Figure 10 (B), the distance is from the connection point between the N-type impurity diffusion region 3 7 as the collector and the metal wire (not shown) 3 7x _ 21 "CNS) A4 specification (2Η) x 297 mm) A7 059 9twf.doc / Jessica / 002 5. Description of the invention (f?) To the collector junction 37a, it must be considered that it is hardly heated by the static surge current The distance affected by the diffusion of the metal wire. Similarly, the distance depends on the theoretical calculation or empirical value of the semiconductor device design. And this distance L / distance L2 from the connection point 33x between the emitter N-type impurity diffusion region 33 and the metal wire (not shown) to the emitter junction 33a is also large. The wire metal adjacent to the connection point will be heated and melted by Joule heating, and then diffuse to the substrate. Then when the molten metal passes through the interface of the junction, electrostatic collapse will occur, causing irreversible failure, that is, damage. Furthermore, taking the two-carrier transistor as a protective transistor in Fig. 8 as an example, the heat generated by the surge current at the collector-base junction interface is more than the emitter-base junction interface. Therefore, the distance between the contact hole adjacent to the collector and the collector-base junction interface is increased to separate the meltable substance from the heat-generating place, so when the metal wire is melted, the molten metal diffuses beyond the junction Before the interface, a larger surge current must flow, and due to the above two factors, a higher resistance value can be obtained, and the ability to prevent electrostatic surge collapse is promoted. Printed by the employee consumer cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs in this embodiment (5-2), the double carrier transistor used as the protection transistor can reduce the increase in the area occupied by the protection transistor and produce anti-static damage A semiconductor device with excellent effects. Refer to FIG. 11 for an application example of the semiconductor device of the preferred embodiment of the present invention. The invention can be applied to a variety of papers with the first conductivity type MOS transistors. The paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 112848 0599twf.doc / Jessica / 002 A7 B7 Employee consumption of the Central Bureau of Standards of the Ministry of Economic Affairs Printed by the cooperative. V. Description of the invention) 'As a semiconductor device that outputs transistors. Please refer to Fig. 11, which shows one application example, that is, an application example of a dynamic random access memory (DRAM) used in a semiconductor memory device. The DRAM 40 has a memory array 41 composed of a plurality of memory cells 41 a, an internal circuit area 43, and an output circuit area 45. In the present invention, the relationship between the memory array 41 and the internal circuit area 43 is omitted. The output circuit 45 is composed of two output transistors 11 of PMOS transistor and NMOS transistor, and one of the output transistors is composed of a PMOS transistor connected to the NMOS transistor as a protection transistor, and the other output transistor It is composed of an NMOS transistor connected to a PMOS transistor as a protection transistor, and the two are connected as the above-mentioned predetermined relationship of the present invention. According to this application example, the occupied area of the protection transistor will not increase, and the manufacturing process does not need to be changed, which can make the DRAM used in the present invention have better anti-static destruction ability than the conventional ones. If the semiconductor device according to the present invention has the first conductivity type and one of the source-drain regions is connected to the MOS type output transistor of the output pad, it is possible to form an electrostatic protection circuit (protection transistor). The two-conductivity type switching element connects one end to the output pad, the protection transistor and the output transistor form a parallel connection relationship, and the gate (or substrate) is connected to a state where the protection transistor can be kept in the 'off' state during normal operation The potential. From the output terminal of this semiconductor device, apply the reverse 23 to the output transistor (you will read the precautions on the back and then fill out this page) f pack · This paper size is suitable _ China National Standard Falcon (CNS> A4 specification (210X297 company %) Employee consumer cooperation of the Central Ministry of Economic Affairs of the Ministry of Economic Affairs, Du Duan 31 ^ 848 A7 0599twf.doc / Jessica / 002 buckle five 'invention description (2 |) to the electrostatic surge, and when the electrostatic surge voltage is lower than the output transistor At the breakdown voltage of the second type, the semiconductor switch element of the second conductivity type will operate. Therefore, the effect of the reverse electrostatic surge on the output transistor is smaller than that of the conventional one. Moreover, another advantage of the present invention is that when lower operation is used Voltage, the occupied area of the semiconductor switching element can be reduced as much as possible, and because the semiconductor switching element can be manufactured using the original semiconductor device manufacturing process, the occupied area of the protection transistor will not increase, and the manufacturing process does not need The change can provide a semiconductor device that is better than conventional anti-static surge destruction due to increased impedance. Although the present invention has been disclosed in a preferred embodiment such as However, it is not intended to limit the present invention. Anyone who is familiar with this skill can make some changes and modifications within the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be regarded as an attached patent application. The scope is defined as the standard. This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm)