TW214588B - - Google Patents

Description

214588 Λ 6 IJ6 Central Ministry of Economics # quasi-bureau A industrial and consumer cooperatives printed 5. Description of the invention (3) The present invention is an information processing device, which includes a 㑩 only external memory unit, the unit has a Program processor. In particular, it is a portable external memory unit with a programming memory to store programs to be executed on the main processing system. Main processing rules such as TV entertainment rules. Some designs are like using a programmable removal processor to improve the main system's high-speed rendering processing capability. Programmable processors, including hardware, are used to convert from one-tiled pixel-based format to character-based format. The image of this application is the same as the application number-, _ 相 _, its name > used in an external memory system with a programmable processor for a long-term game system (Agent No. 1248 -2). And the name v related to the application number is used in the graphics processor with enhanced memory control circuit of Yiqian TV game system (Agent No. 1248-5). The conventional TV game instrument has an 8-bit processor and a sub-system related to display processing, which are implemented on a TV game control board. A typical way is to use 8-bit to 8-bit matrix pre-stored characters on the cassette, and use this pre-stored yuyuan's various programmable combinations to create a screen display, thus generating a drawing. This type of conventional technology, electric tour musical instrument system, has the ability to move the entire display background and multiple moving targets controlled by the player. This kind of conventional technical system must operate on every tilt frame for moving objects composed of polygons, such as turning and redrawing, etc., and are unable to actually implement this TV amusement function. Conventional technology 8-bit processor, related to this system of display processing, can not perform, for example, effectively turn three degrees (please read back to the precautions #fill this page) Install-line-this Paper scales are used in the National Standards (CNS) Ή specification (210x297 g *) 3 81. 6. 10,000 sheets (Η) 214588 Λ 6 η 6 V. Description of the invention (4) Space polygonal base target, or appropriate proportion For this kind of rotating target, to produce 3-D special effects. The present invention recognizes that precise drawing needs to be updated on a screen-by-pixel-by-pixel basis, and that complex mathematics is performed on a real-time basis. This type of conventional technology is based on character-based video games, and cannot perform such work. Conventional technology 8-bit TV game instruments cannot effectively perform other image processing techniques. This technique requires a pixel-by-pixel basis to quickly update the picture. For example, this rule cannot be effectively mapped to a target to a display polygon, and the polygon is another display target (hereinafter referred to as the w pattern (please read the back to the note first # 塡 写 此 页) Ministry of Economy The use of the printing of the quasi-authorized shellfish consumer cooperatives is more basic and accurate. After the picture is drawn, the yuan needs to be matched. The back of the yuan 3-shows that the need is the same as the one born. This is a necessary example. The 16-shaped mat is a colored mask. Take * 1 to apply, and try to change the frame to a 7C real device before the success of this picture. Nu. The speed of the dense color base may allow this to change the picture. The effect of the music is wonderful. Yuan painted high noodles. It is painful to have the noodles in the game, and the more dense words are first on the back. Shi Biyi ’s desire for a device to be a pre-approved device is actually framed.霈 JH: You can swim in your eyes, you can enjoy it, you can see it in the basic group, you can see it, and you can see it, jg humanoid empty drawing system, depending on the edge of the appliance. In the meter, such as an electric device, set Yuan Le Qile J ', and issue a multi-three-piece device with a music label position game, tour W. For machine music, the position can be viewed as a small M element. Youtong 1 6 Acupuncture and visual acupuncture electricity standard / intercontinental contraction / position according to the position of the music electric shift technology and the real big Η0〇 yuan electricity here. You Yuan and Zhixian side turn big and do n’t put ¥ know the position. The position of Xi ’s multi-rotation is to retrain 16 for the analysis of electric 16 movements. The application of the above-mentioned method is a comprehensive solution. This shift is very effective and complete and ex reform. Unconventional multi-base up-conversion, U-shape painting, wide-screen surface, special features, twiddles, better spooling, better flatness frame machine, fully packed, ordered-line-this paper scale side use a «家 楳Bi (CNS) T4 specification (210X297 male dragon) 4 81.6. ΙΟ, ΟΟΟίΚΙΙ) 214588 Λ 6 | {6 Printed by the Central Economic Bureau of the Ministry of Economic Affairs KX Consumer Industry Co., Ltd. 5. Description of the invention (5) The edge of the polygon, and The target of this polygon base is a proper pixel-on-pixel · basis. This kind of work, like performing on a tilted pixel-to-pixel basis, consumes a lot of processing time. In the conventional technology, the movable game instrument cassette is modified to improve the compactness of the game instrument, which uses an existing processor to address a larger programming address space, which is larger than the host microprocessor allows. The number of closed address lines. For example, this conventional technology 8-bit system uses a game instrument cassette containing a multi-memory controller crystal H to perform bank switching and other added functions with the crystal H. However, the wafers associated with the 100-megabyte packet switching cannot perform high-speed graphics processing on TV entertainment systems. The present invention solves the above-mentioned problems of the conventional technology, and utilizes to provide a slap unique and fully programmable sap graph processor, whose image is designed in a removable external memory unit, and is connected to a main information processing system . In the embodiment described here, a shovel video game system implemented by the present invention includes a master video game system and a video game instrument cassette, which contains the picture microprocessor. The picture processor and TV musical instrument system contains many unique and excellent features. The following is a summary. According to the present invention, a special graphics drawing processor can be plugged in and connected to a mastermind. For maximum processing speed, the graphics processor can also be operated parallel to the main computer. In one embodiment, the game instrument cassette where the key map processor is located also includes a ROM (ROM) and a RAM (RAM). The graphics co-processor of the present invention is tailored to its own needs and to be charged from the master (please read back and forth at the first time # 蜞 write this page) This paper standard uses the Chinese National Standard (CNS) specifications (210x297 Long) 81. 6. 10,000¾ (11) °! 45 δ8 Λ 6 IJ6 Employee's consumption cooperation of the Central Bureau of Economic Development of the Ministry of Economic Affairs. Printed five. Description of invention (6) Memory pus change during brain data capture. The processor can simultaneously execute the program with the main brain to allow high-speed processing, prior to the conventional musical instrument system can not be achieved. The picture-co-processor of the present invention is like a three-bus structure connection operation implemented on a game instrument cassette, which allows the effective use of RAM and ROM cassettes and uses the best main processor cassette The ability of both processors to effectively use this memory device. The fully user-programmable co-processor of the present invention, including a unique instruction set, allows high-speed processing. The instruction set can be effectively implemented in relation to 3-D drawing arithmetic and calculations, including, for example, the execution of special instructions using special hard-wired characters, which are used to draw individual pixels on the display of characters from the main TV game console. The instruction set includes unique pixel-based instructions, from the programmer's point of view, such as the use of allowing the addressing of "Qi Cai" pixels to create a tilt, "virtual" bit mapping even if the main rule is a character base. The pixel data and picture processor converts the meta-data. This format is typically used by main character-based 16-bit machines. So, for example, although programmers use a unique w PLOT 〃 instruction to read pixels in a day, when two pieces of data are read into RAM, the data is converted into a slap character base format, which enables the 16-bit host to use. Special-purpose pixel map hardware executes this instruction to effectively allow the implementation of high-speed 3-D key keys. The hardware-in-plane hardware is instantly converted from pixel coordinate addressing to character mapping to addressing, and this main principle of addressing can be used naturally. The best way is that the processor uses the specified X and Y coordinates to write a program, this coordinate is defined on the display surface every pixel position. (Please read the back and the precautions # fill in this page first) Pack. Thread · This paper size is used as a family tree iMCNS) T4 specification (210X297 mm) 6 81.6. 10,000ft (11) 214588 Λ 6 η 6 5 2. Description of the invention (7) Therefore, the execution of the drawing operation is based on the pixels designated by the programmers, and is printed in cooperation with the employees of the Ministry of Economic Affairs, Bureau of Biography. Cheng Xiangbiao's operation instructions included in the Ming Fang show that it can be driven by a seat holder. It is a good package tool. It can be used in the system's most powerful management diagram. Yuandi allows a harmonious use-the opportunity of the block is everywhere. It is a precedent of an X-style body, which has a total of block-like look. The detailed drawing of the single drawing of RA, so that the beginning of the drawing box is more like a merging, and it is a block. Kaki's example is more suitable for shadows, and the prime address says that the image of the square device is small in size. One instrumental instrument, one practical operation, one-way into a detailed description of the single-piece instrument, the tour guide and the good tour series, the same as the Υ, the example is the most important one, the most difficult place is not the same as the painting, the rule is easy to apply. The unification and drawing rules, the main species X and the Yuan Shi Rong Shi Yuan, the front art element image in each color are more clear, the main picture is shown in the common eye, and the image is changed to the color of M0, which will be released. The public office indicated that the rendition should be fixed. All the 0 materials and pictures are determined by this system, as shown in this document. It is shown in Fig. 44A. The first step is to show that it is very clear. 0 Licheng Reunion Kuaiyuan is the predecessor of the next system, the system of the system and the system of Aoyu «Yu. The diagram in this article is composed of 1 2 3 and strip 4. 5 Preface < 07 Hard, let ’s choose a 10% rationale. Picture pseudo Η internal diagram Η picture follow the picture after the picture shows the replacement of the best example of the block of the original expression of the main block of the master, the master's work (please read the precautions Sun Xu first Write this page) This paper is used in the national standard (CNS) f 4 specifications (2 丨 0X297 g; it) 7 81.6.! 0,000 * 〇 [) 214538 Λ 6 η 6 Ministry of Economics Bureau of Standards and Ordnance Consumer Cooperation Du Printing 5. Description of the invention (8) The plaque 8A is a block garden that displays the input multiples received by the drawing controller and the output signals generated by the drawing controller. Fig. 8 is a color matrix element of the pixel picture function circuit in the color matrix. FIG. 8C is a more detailed block diagram of the RAM controller shown in FIG. 4A, which is related to the timing, control, and data signals of the pixel drawing circuit. _ 9 A as shown in plaque 9 is related to the timing, control and data signals of the RAM controller. Fig. 10 is a circuit diagram illustrating the arbitration pass shown in Fig. 9. Letter 11 is the resynchronization circuit diagram of the embodiment of the picture coprocessor of the present invention. Plaque 12 is a timing signal description of the resynchronization circuit shown in FIG. 11. Yuan 13 shows a more detailed block of the RAM controller of the painting coprocessor of the present invention. FIG. 14 is a block diagram of a fast controller of a picture garden coprocessor according to an embodiment of the present invention. Circle 15A shows a block diagram showing the instruction decoding related circuit of the graphics coprocessor of the present invention. 15B is like a timing signal, demonstrating the operation of the forward-looking logic in U15A. U16 and 17 pseudo-blocks show the register control logic of the graphics coprocessor according to an embodiment of the present invention. Fig. 18 is a drawing coprocessor for the production of tilted polygons according to the first embodiment (please read the back-end notes # 塡 写 this page) This paper uses the standard of China B Η 楳 楳 (CNS) T4 (210X297); «:) 81. 6. 10,000 sheets (Η) Printed by the Ordnance Industry Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy 214538 V. Description of the invention (9)-The sequence of operation example flow. Figures 19, 20, and 21 show examples of how you can create polygonal base kneading to illustrate the scale and rotation characteristics of dimensions according to an embodiment of the present invention. Too invention; > Musk dwelling hide california note description is as follows: According to this embodiment, the present invention painting garden co-processor interacts with Yi Ren 16 Ren Yuanxiao video game system. This system is like the Super Nintendo Entertainment System (Super NES) sold by Nintendo of America. This Super Nintendo Entertainment System is described in part in US Application No. 07 / 651,265, Image w Image Processing Device, and its application date is April 10, 1991. And the application on August 26, 1991, application number 07 / 749,530, whose name a directly records billions of access devices and external storage devices ". These applications are here for reference. It is understood that the present invention is not limited to the application of Super HES, and it can be applied to other video games or other non-television games and information processing devices. For ease of reference, the graphics processor according to an embodiment of the present invention will hereinafter be referred to as " Mario chip ". The Malio chips described in the current preferred embodiment are packaged in a TV play cassette. It should be understood that the Maliu chip in the present invention does not have to be in the same cassette as the programming memory, as long as it is connected to an extract memory and the main processing unit when in use. Figure 1 is a preferred example of a storage device according to the present invention. An example of a music player cartridge / external record of 100 million. The playing instrument cassette includes a printed circuit board (not shown), on which all the circle 1〆 components are mounted. The cassette includes a row of connectors 1 and it is placed on the embedded end of the printed circuit board. Original paper 5 *: standard use in a clear standard (CNS) T4 specification (210x297 public address) 81.6. 10,000¾ (II) (Please read the back and the precautions # fill in this page first) Pack. Line-214588 Λ 6 15 6 Employee's consumer cooperation of the Central Bureau of Economic Development of the Ministry of Economic Affairs, du printed fifth, invention description table) used in Fu round signal and Main control panel from Super nes. The connector of this column Mildew 1 is accommodated by a mating connector and placed on the Super NES main control board. According to the embodiment of the present invention, the Mali Ou crystal piece (drawing common processor) 2 is provided on the playing instrument cassette, like a piece of 100 to 128-legged Jiu Road crystal piece. Maru Ou Jing H receives many control, address and data signals from the main processing system (such as Super NES). For example, the Maruio chip 2, receives a 21MHz clock signal input from the main processing system via pin P112, and a system time signal input via the PU7-tilt 21MHz (or another predetermined frequency). The input of the remote system clock signal enables, for example, to provide a Malyn processor, to use the main CPU to store the memory timing information of the memory, and to provide the timing operation of the clock signal in the Malyn chip. , Maruio chip 2 also includes a tiltable external clock signal input when sickle (pin 11〇), mesh Maruio chip to an external quartz 4, to drive Maruio CPU, for example, in a tilt It is higher than the frequency clock signal of 21MHZ received from the main system. The main CPU address input (HA) is connected from the main processing (for example, Super NES CPU / Graphic Processing Unit PPU) address bus to the Mullah Crystal H2 via pin P37 to pin P62. Similarly, from the main system data input (Ηβ), the main CPU data bus V is coupled to the Malo chip 2 via pins P65-P72. In addition, the Mali wafer 2 receives a reset signal via pin P119 and a pin P118, and the read and write control signals via pins P104 and P105 receive an update signal RFSH from the main CPU. The Mali chip generates an interrupt request signal IRQ, and erbium combines this signal 1 to the Super NES via pin P120. Receive other control signals from the Super NES, such as a tilted ROMS E £ signal via pin 106, such as used to start a main program i ~ y (please read the notes before you fill in the wooden page) It is accessed with the Chinese Standard (CNS) T4 specification (210x297 male: «:) 10 81. 6. 10,000 sheets (II) 214588 V. Invention description 1 (1) type R0M10. In addition, the cassette also includes a value confirmation processor 3, which exchanges data with a super NES confirmation processor on the input I, output 0, and reset R lines. The confirmation processor 3 and the safety system used for confirming the playing instrument cassette can also refer to US Patent No. 4,799,635. The Maro chip is compatible with KAM6 and 8 傜 RAK address bus (RAM A), with RAM address pins P74-P91, and RAM data bus (RAM D) and data pins P93-1 00. Some RAMs can be dynamic memory devices. The control part uses row and column address strobe signals (R AS, CAS), which are connected via pins P90 and P91. Use one or more Yong RAMs instead of dynamic RAMs, and pins P90 and P91 are used to connect address signals to their different RAMs, without using row and column address pulse signals. The write enable control signal VE is properly meshed to RAM 6 to 8 via pin 107. Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs (please read the back-to-date precautions and add wooden pages). Use the main CPU to generate read and write control signals (R, W), and pass the 105 is connected to Maru Ou Jing H. By monitoring these read and write signal lines, Malioux chips can determine the nature of the memory access operations that this Super NES CPU attempts to perform. Similarly, from the main system almost all addresses and controls, use the Malio chip supervision to track the trajectory of the main CPU. The ROM and RAM address signals received by the Maru chip are supervised and passed to the appropriate memory device. In this regard, the ROM address is pinned to pins R2 and P26 via the ROM address bus, and is connected to the program R0M10, and the RAM address is pinned to RAM 6 and 9 via pins P74 to P91. Input data from the ROM and RAM of the main CPU, through the ROM data bus and the pins P28-P35, and through the pins P93 to P100 to properly combine to R0H10, Ma Liu »chip can be used to receive a call In addition to the above-mentioned ROM and RAM, the different denominator devices are not. For example, we are planning to use the paper standard in China. A B Jiatbi (CNS) TM specification (2 丨 0x297 male dragon) 11 81. 6. 10,000¾ (H) 214588 Λ 6 Β 6 CX Engineering of the Central Bureau of the Ministry of Economic Affairs Consumer Cooperation Du Printing 5. Description of the invention (1 2) Make Ma Lijing M used in the TV game system with only CD ROM. For example, in Figure 1, a shovel CD ROM (not shown) replaces R0M10 and is used to store character data, program instructions, images, graphics, and audio data. A traditional CD head (also not shown) is suitable for connecting to the Maliou chip 2, receiving billions of addresses from the address bus P2-P26, used to access data from the data bus P28-P35 and // Or instructions. The detailed operations and specific instructions of CD reading and CDR0M storage system are well known to professionals in the industry. Using the advantages of CD ROM storage, it greatly reduces the cost of storing data per byte. The data storage cost may be 100 to 1,000 percent less than the storage cost of semiconductor ROM. However, unfortunately, the CD ROM records 100 million access / readout time, even slower than the semiconductor R 〇 Μ. Ma Liujun Jing H uses a three-bus structure, which allows data to use at least three-tilt bus in parallel. In this regard, as shown in Figure 1, the music instrument cassette, Maruio chip 2 is integrated into a ROM bus (including ROM data line, ROM address line and control line), a RAM bus (including RAM Address lines, data lines, and control lines) and a tilt main processor bus (including main address, data, and control lines). The Maliou wafer structure allows parallel pipeline (Pip ^ ined) operation to occur to obtain the best output capacity. In this regard, the Mario chip reads a byte of data from the ROM, and when processing other data, still writes the data to the RAM to allow 3-D phase drawing to be performed efficiently. As explained further below, the 2CD part of the Maremer wafer uses a 16-bit structure and is still designed to interface with the 8-bit R0M10 and RAM 6, 8-crystal H. The internal registers of all internal data buses are 16 bits, read from R0M10, and write 12 copies of 5JL standard paper to use Chinese National Standard (CNS) T4 specifications (210X297 male dragon) 81. 6. 10,000 sheets ( II) (please read the precautions first and fill in this page) A 6 η 6 Printed by the Central Bureau of Standards of the Ministry of Economic Affairs κχIndustry and Consumer Cooperatives V. Invention Instructions (13) into RAM6, 8, Buffer ", and typical The ground does not slow down the program execution speed. / Similarly, Maru Ou Jing M2 can also access instructions and suspect data from the CD ROM. And write the information into RAM6, 8 and use it for post-embedding DMA to send the image RAM into the main processor, such as Super NES Graphics Processing Unit (PPU). Professionals in this industry will appreciate it, such as the conversion of the programmable data coordinates of the Maliou chip 2 from the CD ROM directly to the PPU's image RAM. Omit storage and access operations through RAM. The extremely fast processing speed of the Maliou chip 2 allows CD ROM storage to be practically used in ring applications, although CD ROM requires long read access times. Before storing the CD and ROM, the image and sound are compressed using the data compression technology of Futong. Data compression and post-original technology are common knowledge for those in the industry. After accessing the compressed data from the CD ROM, Ma Jingxin H2 uses a traditional data recovery algorithm to recover the data, which takes less time than what can be done with a traditional graphics processor. Because it is operated with a dysprosium 21MHZ clock signal, the Maliou chip 2 completes the recovery and transfers the data to the RAM 6 and 8 within a predetermined time period. Therefore, the typical CD ROM access period can greatly access the image and sound Information (compressed form). However, the effect of this relatively long access time is reduced because the actual access time for each data byte is greatly reduced after data recovery using the Malychip 2. When performing recovery using the Maruchip 2, the main graphics processor, such as the super HES PPU, can perform other processing tasks. Of course, if the speed does not need to be tested for another application, then Ma Jing Ou Jing H 2 can access uncompressed data from the CD ROM. (Please read the notes on the back of the page to write a wooden page by Sun Yan) The standard of the S family standard (CNS) (210X297 g; «:) 13 81. 6. 10,000¾ (II) 214588 Λ 6 Β 6 Printed by CX Industrial and Consumer Cooperation, Central Bureau of Economics and Development, Ministry of Economic Affairs. V. Description of Invention d 4) When using static RAM, the cassette may also include a spare battery. A spare backup battery 12 is connected to a conventional backup battery circuit 14 via a tilt resistor R, providing a static RAM and a static RAM chip selection signal RAMCS. A spare backup RAM (RSRAM), if the power supply is lost Can provide a material storage function. In addition, the network is connected to the RAM address bus, and the resistor 16 can be optionally set. During normal operation, the Mario chip address lines are output to RAM 6 and 8. However, during reset and power-on operations, the use of the address line as an input line generates a bow high or low signal depending on whether it is connected to a pre-determined high voltage VCC or ground. In this way, a slap ^ 1 〃 or " 〇〃 is properly read into a stuffed internal Marie Ou Jing H register. After resetting, depending on the different settings of these resistors, Maruio can determine (during program execution), for example, the clock rate of the multiplexer, to the RAM access time of the Maruio chip, use The clock signal rate of other operations in Maruio etc. Through these options, the settings of the register can be set up, and the Mullah chip can be used in many different types of billion-meter memory devices without modifying the design of any Mullah chip. For example, if a dysprosium dynamic RAM setting is detected, the multiple is updated to an appropriate number of times. In addition, the selection setting is used to control the speed, for example, the operation of the processor multiplexer circuit, and allows the use of the lutet processor to execute other instructions at a faster rate to execute certain multiplication instructions. Therefore, with the start of a delayed multiplication execution, the remaining instructions can be executed at a faster clock signal rate (for example, the processor may be set at the clock signal 30MHZ, so selecting the setting will effectively cause the multiplication instruction to execute at 15HHZ). Figure 2 is a block diagram of the main TV game instrument system of a pseudo-embodiment. Its 14 paper standards are used in the B National Standard (CNS) T4 specification (2 丨 0x297mm) 81. 6. 10,000 sheets (II) ( Please read the back-end notes first. Xun writes a wooden page) Λ 6 1 (6 214588 V. Description of invention ί 5) (please read the back-end notes #fill in this page) in the example game instrument card _ 如 圈 1 The designer. _2, for example, the Super NES sold by Nintendo on behalf of the United States. However, the application or rules of the month 1 in the Super NES as shown in H2 #. The Super NES includes a 16-bit main CPU in its control panel 20. For example, it may be a 65 8 16 compatible computer. The CPU22 is meshed to a 1 RAM32, for example, it may include 128 {(byte storage. CPU22 meshed to a ramen-shaped processing unit (PPϋ) 24, in turn cadmium is merged into a stuffed image RAM 30, which may Including, for example, the remaining words. During the vertical or horizontal extinction interval, the CPU 22 accesses the image RAM 30 via the PPU 24, except during the active line scan period, when the PPU 24 accesses the color image RAM. _ Like RAM30, it generates an image to be displayed on the user's video 36. The CPU is also networked to a slap sound processing unit APU26, which is integrated into a working RAM 28. The APU may contain a commercial audio chip, Generate sounds that are related to the TV game program. This program is stored in the R0M10 of the game instrument cassette. The CPU can only access the work RAM28 through the APU26. The PPU24 and APU26 are integrated into the user's home through the RF converter unit 34 TV 36. Printed by the Ministry of Economic Affairs, Pyongyang Precinct, β Industrial Consumer Cooperative

In the image RAM30 of the Super NES, it is necessary to load the appropriate character data stored in the card program R0M11. (The cassette does not only store game programs, but also uses character data during game play). Any moving objects, such as ghost information, or display of back gathering information • It must be placed in the image RAM30 before use. The program R0M10 access uses the main address and data bus of the CPU 22, and is connected to the edge connector 1 of the printed circuit board as shown in the garden 1 via a crane matching connector 18. The PPU24 is connected to the game instrument cartridge and shares the main CPU data and address bus and connector 23, so it provides a way to use it for PPU. This paper standard is easy to use a Β 家 楳 准 (CNS) Τ4 specifications (210X297 male dragon) 15 81. 6. 10,000 sheets (H) Λ6 _____ Π_6 _____ V. Description of the invention (16) (please read the back and the precautions #fill in the soldier) data and control signals to the cassette. The APU26 shares the main CPU bus and the Feiyin sleep bus 27, which are connected to the game cartridge. The CPU22 address space is mapped to, so the program R0M10 is at the starting position 0, and is typically divided into 32-bit segment program ROMs. About half of the CPU address space is used. At the top of each 32K-bit segment of the CPU address space, the address work RAM32 and various different registers are typically used. The formula ROM10 is typically 4 megabytes. The CPU22 used in the Super NES can address the dysprosium program R0M10. On the S-side, Ma Liutan M 2 only includes a slap 16-bit program counter, and therefore includes a group register, used to select 32K bytes in the program R0M10. In this embodiment, the Mario chip only has a 24-bit space mapped to the Super NES memory. It contains the R0M10 starting address at $ 0 0: 8 0 01 and the starting address of the RAM chip 6,8 on the cartridge is $ 70:00 0. Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Because R0M10 and RAM6 and 8 on the cassette are separated from the bus, so ® chip can access them in parallel. And RAM6,8 has fast access & ROM, and the design of Ma Liuxi Jing also uses this execution advantage. Ma H does not access any memory in the Super NES, that is, does not access the work # RAM 32 or PPU video RAM 30. If you want to process data or draw a bitmap of Maruou chips, the M S material is included in the RAM chips 6, 8 of the Maru Cartridge. Therefore, any variables that are common to any NES CPU program and Maru Oujing M program must be placed in the Oka RAM RAM H6,8. The δ pre-remaining data required for any Malyu chip program can be in R0H1I, and any variables will be in RAM6,8. Ο Any variables required for the Super NES program are not included in the cassette RAM6, 8 sheets of paper for easy use 8 B Family Standard (CNS) A 4 specifications (2) 0χ297; (¢) 81.6. 10,000 »(B) 16 Printed by the Central Standard of the Ministry of Economic Affairs and printed by the A-Consumer Cooperative Society 21458ο λ 6 ____ Π_6__ V. Description of the invention (17). In terms of resources, RAM6 and 8 are located at the higher addresses in the memory space. It is best to place the cassette RAM6, 8 on the basis of priority. Any non-essential variables should be stored in Super HES internal RAM32. Bits written by Maruyang Crystal H are mapped to Maru, Cali 6,6,8, and will be executed under the control of Super NES · Fu will be sent to the image RAM30 of the PPU. Yuan Ying until the ring frame is completely shot. Suppose the CPU 22 of the Super NES accesses all the internal RAM in the Super NES control board when the Maruchip does not appear. The Maruio chip does not access the slag RAM, so all data sent between the Maruio R0M / RAM chip and the internal Super HES must be initiated using the CPU 22 itself. For data transmission, the program of CPU22 can be used, or the entire block of data can be moved by DMA transmission. The Maliou Cassette and RAM6,8 are generally used by all game programmers. The CPU 22 has only a controller, so that the CPU can temporarily access the cassette or the RAM chip. Under the condition that the power is turned on or reset, the Maru chip is turned off, and the CPU 22 is completely accessed by the cartridge ROM and Rik chip. To enable Ma Litan to execute a crane program in Crystal H • Must make the CPU22 program give up its access to the ROM or RAM Crystal H, preferably both. And wait for the chip to complete its assigned work, or another way, CPU22 can copy some program code to the internal work RAM32, and execute it there. The MaLiXi chip only has multiple registers, and can be read or read by the side program of the Super NES CPU. From Yingzhi to CPU22, there are 100 million brewing Yingzhi, and its starting address is $ 00: 3000. As shown in _2, the Super NES generates and receives different control signals. When the Super NES CPU22 needs to access the program R0M10, it generates a control times (please read the precautions first and then write the wooden pages on the wall) Binding · Order_ Line-This paper standard is used in "« 家 «准 (CHS ) f 4 specifications (2) 0 × 297 male dragon) 17 81. 6. 10,000 sheets (ί () Λ 6 Π 6 214588 V. Description of the invention β 8) ROHSEP. If you want to start a new update, the Super NES will generate a

L (please read the notes beforehand # 塡 write this page) Update the signal RFSH. The Emirates Euclidean chip completes an operation, which transmits an interrupt signal IRQ on the interrupt request line, as it is related to the super HES CPU. In addition, the CPU 22 generates read and write signals. From the timing channel circuit 21 in the control board 20, general timing signals are generated. A power-on / reset signal is also generated in the main control board 20, and the pot is coupled to the playing instrument cassette. Super HES also includes a confirmation processing device 25, which pseudo-exchanges the data at input I and output 0. And according to the above-mentioned US Patent 4,799,635, the R wire and a confirmation processing device 3 are reset on the television game instrument. In the processing device 25 shown in U.S. Patent 4,799,635, the CPU 22 is kept in a reset state until confirmation is established. Printed by the Ministry of Economic Affairs, Central Bureau of Precision Industry, A Industrial and Consumer Cooperatives, the block diagram of the Super HES TV game shown in Figure 2 has been described here in general. Further details about the Super NES include PPU24, which can be found in US Application No. 07 / 651,265, whose name is' " Image Processing Device ", and its application date is April 10, 1991. This application is here for reference. . How to transfer information between the Super NES and the game instrument cassette can be found in US Application No. 07 / 749,530, date of application on August 26, 1991. The name, the image processing system and the external storage device are used directly. E-body access device 〃, and the United States application No. 07/7 93,7 35, the application date on November 19, 1991, its name a embedded graphic display device and the use of external storage unit " here. These claims are here for reference. For some applications, the inventor has recognized that more information needs to be transmitted during the vertical extinction period than the main processing DMA circuit can actually transmit. Therefore, the 51 standard of this paper is used in a B family standard (CNS) T4 specification (210x297 male dragon) 18 81.  6. 丨 0,000 sheets (H) 21. 4588 Λ 6 Μ 6 Printed by the Ministry of Economic Affairs, Central Bureau of Labor and Development, β-Work Consumer Cooperation Co., Ltd. V. Description of Invention {9) The extended vertical extinction time that may be expected. It may even cause the graphic size to be reduced slightly. With this method, the biggest advantages are the processing speed and the update rate of graphics. A perspective view of the example mechanical design of Yuan 3 Jie, a play instrument cassette case 19, which is used to house a Malio chip and other cassette structures as shown in FIG. Similarly, the circle 3 is a perspective view of a slap example housing used in a TV game console 20, and the hardware of the super HES TV game shown in Figure 2. For the mechanical design of this TV game instrument control board 20 and the corresponding movable game instrument cassette 19, please refer to US Application No. 07/748, 938, application date August 2, 1991, name, TV games ", this application is here for reference. FIGS. 4A and 4B are block diagrams of the Maliou crystal H2 as shown in FIG. 1. First, focus on the various busbars in Figures 4A and 4B. Command bus IHSTI? An 8-bit bus, which matches the command code to a variety of different modules. The X, Y, and Z buses are 16-bit data buses. The ΗΑ bus is a 24-bit main address bus. In the current best embodiment, it is used to address the super NES address bus. The HD bus is an 8-bit main bus, which is used to integrate into the Super NES data bus. The PC bus is a healthy 16-bit bus, which integrates the output of the Mateo chip programming counter (for example, in the general register block 76 register R15), to a variety of different components. The ROMA bus is a 20-bit ROM address bus. The ROM D bus is an 8-bit ROM data bus j. The RAM A bus is a biased RAM address bus. The RAMD-IN bus is an 8-bit RAM bus data bus. And RAMD-0UT is one (please read the notes beforehand Sun Kan writes this page) Installation-line-this paper 51 scale happy use a B home standard (CNS) 4 specifications (210x297; ¢) 19 81. 6.  10,000 »(II) Λ 6 Π 6 3i4588 V. Description of invention 6 〇) 8-bit RAM write data bus. / Ma Liuhe chip and Super NES share cassette RAM6,8, this RAM is used as the main mechanism for transmitting data between Ma Liuhe and Super NES. Super HES accesses the Maruio chip via the address and data bus HA and HD. The Maliou chip register 76 is accessed via the Super HES via the Super NES address bus HAA. Super HES accesses the chip program R0M10 and RAM6, 8 via the Maliou chip 2. The ROM controller 104 and the RAM controller 88 receive the memory access signal generated by the Super NES, and start the individual ROM and RAM memory access. Illustrated by the embodiment, the Maruchip 2 uses a RAM selection signal RAMCS to verify that the Super NES is currently addressing this RAM. The X, Y, and Z busbars shown in swollen 4A and 4B, and the internal Maruchip data bus. The X and Y busbars are source data busbars, and the Z data busbars are straightforward busbars. These buses carry 16-bit parallel data. When executing the command, the Maliou chip 2 puts the source of the data of one command on the X and / or Y bus, and puts the destination data on the Z bus. For example, when executing a command, add the contents of the two-shovel scratchpad and put the result in the third scratchpad. The arithmetic and logic unit (AUU50, receives the contents of the two source registers via the X and Y buses. And the result is merged into the Z bus (secondly supplied to a value-in-waiting register in block 76). Using the instruction decoding circuit 60 on the Maruio chip 2, the control signal obtained from the decoding of an instruction opcode is fused to the ALU50 to start an ADD operation. From the explanation of the circle 1, the Maruio crystal H pot Combined to Yihuo R〇H Exchange (please read the notes on the back of this page for the first time Sun Zengyan) Installation and line A 4 specifications (210x297 g; «:) 20 81.  6. 】 0,000 sheets ⑻ A 6 B 6 S145B8 Fifth, invention description fel) (please read the precautions first * write a wooden page) bus, a RAM bus, and a super NES main bus, all can be parallel Communication. Supervised by Malijun Chip 2, controlled by the main Super NES bus transmission, address and data multiples • to determine which tilt operation the main system is performing. The cassette ROM bus and cassette RAM bus are accessed in parallel, depending on the Super NES operation in progress at any known time. In the traditional Super NES TV game instrument cartridge, the main CPU address and data line are linearly coupled to RAM and ROM. Therefore, RAM and ROM cannot be accessed in parallel. According to an aspect of the present invention, the Marachip 2 is as shown in Figure 1, and separates the ROM bus and the RAM bus from the Super NES bus. The Maliou Chip 2 supervises the signals transmitted on the Super HES bus. And it is decided which signal needs to be networked to the ROM chip and RAM chip, and the ROM and RAM bus are separated after the second event, because this bus is not time-separated. Using separate ROM and RAM busses, the CF chip 2 can simultaneously write from ROM to RAM. In this way, Maruio crystal H can be effectively used for straight ROM chips, so the access time of the chip is significantly slower than the RAM access time, and there is no need to wait for the completion of RAM access before storing the RAM. Printed by A-Consumer Cooperative Society, Ministry of Economic Affairs, Ministry of Economic Affairs. In Figure 4A, as mentioned above, the Maliou chip 2 is fully programmable and includes an ALU50. All arithmetic functions performed by ALU50 are within the Ma Jingjing wafer, except that the multiplication is performed by operating multiplier 64, and the circle-shaped hard mannequin is used to process certain pixel circle-shaped operations. Receiving an appropriate control signal from the instruction decoder 60, the ALU 50 performs addition, subtraction, mutual exclusion, shift, and other operations. As shown in Figure 4A, the ALU50 receives information about the operation from the X and Y bus. At the beginning of this operation, it uses a control signal received from the command decoder. And the result of the meshing operation goes to the z bus. The size of the paper is used in the national standard (CNS) T4 specification (210x297 male dragon) 81.  6.  10,000 sheets (Π) 2 1% Λ 6 It 6 Printed by GX Industrial and Consumer Cooperation of the Central Bureau of Economic Development of the Ministry of Economic Affairs. 5. Description of the invention) Figure 6 will further illustrate A LU. In addition, the Maliou chip 2 includes special-purpose hardware to enable 3-D special effects and other drawing group operations to be effectively performed, so Xiaoshiyou musical instruments that use these functions can be actually built. Mali's chip 2 includes hard picture 52, which helps to convert the address from the pixel block in real time, and converts the characters used by the Super NES to the address. The advantage is that writing a program on the Maruio chip can use the commands Χ, Υ purlin to define the position of each pixel on the display screen. Therefore, performing the plaque operation is based on the pixels specified by a euro programmer, and the diurnal hardware 52 can immediately convert the specified pixels into character data in an appropriate format. Then, the character data is mapped to the desired location and used for display on the Super NES image 30, as shown in Group 2. In this way, Maru Oujing H programmers only use the super HES video RAM30 as a single bit, but in fact it is a character. The hard skull 52 responds to various commands related to different painting groups to allow the programmable selection of the X and Υ coordinates on the display screen, as well as the predetermined color for a specific pixel, and the pixels that are drawn to each other, so , Χ and Υ coordinate conversion is simplified to an address defined by a character, the form of this element definition is used to drive the super HES image RAM30. Painted Hard Brew 52 has a phase gate data gate, which allows pixel data to be buffered before writing to the cassette RAM to minimize RAM data changes. After the X and Y block data are converted and buffered in the hard drawing 52, the character definition data is sent to the cassette RAM. The map hardware is installed by tilting the PL0TX register 56 and PL0TY register 58 (please read back and take care first ^ Sun fills in the wooden page).  Line-This paper uses the Chinese National Standard (CNS) Grade 4 (210x297 mm) 22 81.  6.  10,000¾ (II) Λ 6 116 V. Description of invention $ 3) Don't receive X, Υ coordinate data. In the presently preferred embodiment, the PL0TX and PLOTY registers are not separate registers (as shown in 麧 4A), but the general register of the Manet sigh chip (that is, as shown in 銸 4B, in the register The registers R1 and R2 in block 76). The drawing hard sickle 52 also receives pixel color information via a partial color register 54. As explained below, the color of each pixel is stored in a matrix of 8X8 registers, in which each lanthanum pixel color specification occupies one column of matrix. The painting country hard man 52 handles the address and data of Yuyuan related to X and Y and the color input to the character RAM6,8. The character address is forwarded to the RAM controller 88 via the output line 53 and to a RAM address bus RAMA. Yuyuan data goes through round 55, multiplexer 93 and RAM data bus RA (D-out, to character RAM. Drawing hard waist 52 allows dysprosium to be addressed to pixels within the character, so the programmer provides one Partial " virtual " bit mapping to the display system. When keeping compatible with the super HES Yuyuan format., And virtual " bit mapping to remain in the cassette RAM Sent to Super NES Video RAM30, you use, for example, an eDMA® way in the above application No. 07/7 49,530. The prestige hard pus 52 allows individual pixel control of the speed of departure • Therefore some 3-D drawing effects include rotation The size and size changes become practical. Because the pixels are converted into character format, the painting garden hard smoke 52 is also received from a cassette RAM6, 8 via the RAMD-in data latch 82 and the input line 83 to receive the current pixel Information of other pixels in Zhoupu of X and Y. Using the previous pixel data taken from RAM6 and 8, and temporarily stored in the RAM data gate, the number of writes to RAM is the smallest. As shown in Figure 4A, the RAM data gate R80, 84 and 86, the relative color data received by Yi Di Cheng Chong; this image (Please read the notes on the back of this page to write this page by Sun Nan). _ Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, printed by the Migong Consumer Cooperative Co., Ltd., and used in the middle of the family. Standard (CNS) Ή specifications (2 丨 0x297 ; ¢) 23 81.  6. 】 0,000 sheets (II) Λ 6 Β 6, '4538 ;; i ·-V. Invention briefing 4) Multi-bit planes that have been stored in the cassette RAM, to provide the hard-copy 52 data / RAM The data latch 80 network is connected to the Super NES bus, so Super HES can read the content of the data latch. The RAM data latches 80, 82, 84 and 86 are controlled by the RAM controller 88. RAM data latches 84 and 86 operate from RAM6. 8 Receive the data, and combine the data from RAM6,8 to the destination Z bus, use a slap loaded into the register box 76 to pre-determine the register. In addition, the controller 88 is a latch 90, like a buffer RAM address. The address stored in the latch 90, like the RAM controller 88 via the RAM A bus, is used to address RAM6. 8. The RAM controller can also use the Super NES to access through the address bus HA. The plaque is hard. 5 2 It also responds to a READPIXEL command. Like reading this pixel color information, the content of the register R1 is used to define a horizontal position, and The content of the register R2 defines a value vertical position, and the result is placed in a value register of the register block 76 via the destination Z bus and the output line 87 in the register block 76. The PLOT hardware 52 will be described in further detail with FIGS. 7, 8A and 8B. The parallel pipeline buffer register 62 and an ALU controller instruction decoder 62 are coupled to the instruction bus INSTR, and operate to generate a control signal 〇CTL (using the output of this chip), the flap should be placed in Commands on the command bus start the operation. The Maruio chip 2 is like a parallel pipeline evacuation processor. When it is executing the current command, it grabs the command to be executed at the next tilt. The parallel pipeline register 2 stores the next instruction to be executed, and therefore, if possible, allows execution of the instruction during the encounter period. Commands placed on the command bus, use the program counter stored in a dump register 24 (please read the notes before filling in this page) install _ line Consumer cooperation du printed the paper standard Xiao B used in the national B standard (CNS) T4 specification (210X297 public; «:) 81 _ 6.  10,000 photos (II) Printed by the Employee Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs 4 to 8 Λ 6 __ [i_6_ V. Invention description 5)) Addressable content, this register is shown in the register block shown in Figure 4B, for example The register R15〇 in 76 uses the Maru Ou chip 2 to execute instructions, perhaps obtained from the program R0M10 shown in Figure 1, or Maru Ou internal fast RAM94, or from the cassette RAM6. 8. If the execution program is taken out of R0H10, the ROM controller 104 (as shown in FIG. 4B) will grab the instruction and place it on the Marshall chip instruction bus INSTR. If the program instruction is stored in the fast RAM 94, this instruction is directly output from the fast RAM 94 via the fast RAM output bus 95 and placed on the command bus. The main CPU, that is, the Super NES, is the part of the program R0M10 that is planned to be configured and used in the program instructions of the Ma Li Jing Jing H. The super HES program instructs the Ma Yanxi chip to perform a predetermined function, and provides the address of Ma Yuoujing Η at R0M10, using the code to access the Ma Yanxi Η. The parallel pipeline register 62, which fetches the instruction before a slap of the instruction is executed, provides the instruction phase information of the instruction decoder 60, so that the decoder can predict what will happen during the execution of the program, so it is allowed to look forward To deal with it. The block 60 decodes and controls the control circuit to generate control signals for instructing the ALU 50, the picture hardware 52, the fast control 68, etc., to perform the operation indicated by the execution instruction. The Maruchip also includes a tilt high-speed parallel multiplier 64, which is separated from the ALU50. In response to the predetermined command, the multiplier 64 operates to multiply the number of 2-tilt 8-bits received from the X and Y buss, and loads the 16-bit result to the destination Z bus. If it is possible to perform this multiplication calculation within an encounter period. The number of rounds up to the multiplier 64 may have a sign or no sign (please read the back-to-back notes # 塡 写 this page) This paper standard is used in a 81 home standard (CNS) Τ4 specification (210x297 : «:) 25 81.  6.  10,000 copies (II) 214588 Λ 6 Η 6 Printed by the Beigong Consumer Cooperative of the Central Bureau of Economics, Ministry of Economic Affairs V. Description of Invention). The multiplier can also perform long multiplication lotus calculations, in which the 16-bit number of two dysprosiums is multiplied to produce a 32-bit result. The multiplier 64 also includes a phase-part partial multiplication register 66, which stores part of the multiplication plot during multiplication. The slave command decoder 60 uses a β control signal to enable the multiplier 64 when decoding to a tilt multiplication method. Multiplier 64 will execute a 16-bit multiply long multiply instruction.  Enforcement within the minimum 4 times of the dysprosium. The format of the long multiplication instruction: R4 (lower word group), DREG (higher word group " Sreg ^ Re. Execute this instruction, like using the content of register R6 to multiply the source register, and store a Yu 32 The bit result is in the register R4 / DREG (lower / higher). The multiplication has a sign, then set the zero and signal flag on the 32-bit result. Perform the lotus calculation according to the following 6 tilt steps: Step 1 : Multiply R4 [0… 15] = SREG [0… 7] SR6 [0 ... 7] without sign. Step 2: X has 〆sign 〇R4 [.... 15] = R4 [0… 15] +2 56 * SREG [8… 15] * R6 [0… 7]. Ignore the higher 8 bits of the product, but retain from the carry of addition. Step 3: X has a sign. R5 [0… 15] = CY + U6 [8… 15] s SREG [0… + 256; sign extension. Step «4: X has no sign. Y has positive and negative signs. R4 [0… 15] = R4 [0… 15] + 256 * SREG [0 ... 7] * R6 [8 ... 15]. Ignore the more distant 8 bits of the multiplying Zhen, but retain the carry from the addition. Step »5: Y has a sign. R5 [0… 15] = R5 [0… 15] + CY + SREG [0… 7] * R6 [8… 15]) + 256; sign extension. Step »6: X. Y has a sign. R5 [0… 15] = R5 [0… 15] + RY [8… 15] * R6 [8- 15] 〇 (please read the precautions beforehand Sun Ye Qiaomu page) The paper size is not in use Η Family B (CNS) f 4 specifications (210x297 male dragon) 26 81.  6.  ] 0,000 sheets (H) 214588 Λ 6 Η 6 Printed by the Beigong Consumer Cooperation Department of the Central Bureau of Standardization of the Ministry of Education V. Description of the invention) The multiplier 64 used in this embodiment has, among others, digital computer arithmetic Instructions. With reference to circle 4B, the fast controller 48 (shown in further detail in circle 14), allowing a program owner to effectively start loading into the fast RAM 94 for some programs that are expected to execute at high speed. This type of, fast # is typically used to execute a small program Xunchen, like often happens when the picture is processed. The Maliou chip instruction set includes a '" CAWE々 instruction. Any command CM after the CACHE command is carried to the fast RAM until the fast RAM is full. When the CACHE instruction is executed, the current program counter state is loaded into the fast base register 70. Therefore, the contents of the fast base register define the starting position where this fast will be started. Most instructions are executed in one cycle. From relatively low external memory, such as R0M10, or RAM6, 8 instructions, they are fetched before they are executed. This will take an extra 6 cycles. To increase the execution speed of the program, the fast RAM94 in the Malikin crystal itself should be used. The fast RAM94 can be used to quickly record 100 million bytes for a 512-byte instruction. Compared to the average program size, the former is relatively small. Therefore, programmers must decide how to properly use Quicknote 94. Any program Xunchen can quickly record the size of the memory in 512 bytes, and it can be executed at full speed, that is, the capture and execution are in the same period. Because of the separate bus, when executing the code of internal fast memory 94, both ROM and RAM can be accessed at the same time. The fast RAM94 should be used to rotate a sprite $ (Sprite), using a Xunchen executed in the fast memory 94. When it performs rotation and large size (please read the precautions before filling in the wooden page), this paper uses the Chinese National Standard (CNS) T4 specifications (210X297) *. 81.  6.  10,000 sheets (II) 27 Λ 6 B 6 Printed by the Employee Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention? 8) When calculating small changes, the color of each pixel will be read from R0M10. It uses the PLOT instruction (described below) to write pixels to RAM6, 8. All happens in parallel, the slowest operation will make it slow down quickly. The slowest operation is often the ROM data capture, which is the designed Maliu chip, which uses buffer access in ROM and RAM. When compared to the relatively slow execution of R0M10, the execution speed of a program in fast RAM94 is 6 times faster. But first it must be loaded from the ROM into the flash memory 94. Performing this work is like starting with any Xun Chen who wants to receive a quick memory, and placing a command or two. Only the first 512 bytes of Xun Hun are retrieved from the address of the CACHE instruction and placed into a quick memory. When the first repeating code is executed, the program comes from R0M10 and is copied to the fast RAM in 16 bytes. All further iterations will be repeated from the fast RAM94, not the R0M10. The CACHE instruction is used in front of any repeated program loop. Only Xingjing's post-mine repeats benefit from the rapid record of billions of dollars. If the program loop is larger than 512 bytes and exceeds the fast memory 94, it will still work correctly. Only the first tooth 512 bytes is executed from the fast memory 94, but the rest is still executed from R0M10 . This may increase some speeds, but it is not ideal. In the preferred embodiment there is a fast sample bit register 72, like a part of the fast controller 68, which is used to identify the location of the memory that has been loaded into the fast RAM 94. The fast identification bit allows Maru Oujing H to quickly decide whether to obtain executable program instructions from the faster fast RAM, rather than from the program R0M10. Use the fast controller 68 or the super NES to converge via the super HES address (please read the backing notes # 塡 写 木 页) This paper is used in the 8B home sample standard (CNS) f4 specification (2) 0X297 male dragon ) 28 8K6.  10,000 sheets (10 214588 Λ 6 η 6 V. Description of the invention β 9) Row HA passes through the multiplexer 96 to access the fast RAM. The fast controller 68 is integrated into the program counter bus PC to load into the fast base register 70, and executes the check operation of the fast memory address exceeding the range. Similar to the parallel readout that can be done from R0M10, the Maruio chip also provides a way to write to RAM6, 8 in parallel. Whenever the Malioux register writes to RAM 6, 8, it will start, for example, to write the RAM to a separate RAM in the RAM controller 88 to perform the billion-element change. This typically takes 6 cycles, and when it does so, it will not delay the processor. If the programmer avoids another dysprosium RAM change at this time. For example, other processing is faster in interleaving intervals between each store instruction. Only in this way can the RAM write circuit have time to do its job. If the two writes are used in a row, when the first one is writing, the second tilt will extend the processor. For example (the instructions used from the instruction set will be described below) (please read the back and forth notes first # 蜞 写 木 页) The Ministry of Economic Affairs, Ministry of Economic Affairs, Central Bureau of Labor and Welfare printed the FROM R8; Store R8 to (R13) SH (R13) SM (R14) Store R0 to (R14) TO R1 FROM R2 ADD R3 execute: r 1 = r 2 + r 3 TO R4 FROM R5 ADD R6; execute: r 4 = r 5 + r 6 The size of the paper is based on the Zhongming S family standard (CNS) T4 specification (210X297 g) 29 81.  6.  10,000 sheets (11) Λ G η 6 214588 V. Description of invention (30) (please read the precautions on the back before filling in the wooden page) Note that the two-dump storage instructions are too close to each other. The second slap will require a period of 6 values because the RAM bus is busy trying to complete the first store command. A better way to write a program. If there are other useful codes separated between the two pseudo-save instructions, a faster execution speed can be achieved. For example: FROM R8; Store R8 to (R 13) SM (R1 3) TO R 1 FROM R2 ADD R3 f execute: r 1 = r 2 + r3 TO R4 FROM R5 ADD R6 execute r 4 = Γ 5 + r 6 SM (R 1 4) Execute R0 to (R 14) In this way, several more instructions are executed in parallel at the same time, the result of the instruction is written to RAM, and then the second storage instruction is executed after a few cycles. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs The following instruction set, including a quick instruction, is used to write back a dump register to the last RAM address. This allows > large amounts of data processing, using the values loaded from RAH, to do some processing on it, and then quickly save it back. As shown in Fig. 4B, —Mei immediate data latch 74 meshes to the command bus. The data latch 74 allows the command to provide the source of the data itself, so this command does not require a command source register. Immediately report the round out of the latch 74 to the destination bus Z. Sequentially speaking, one of the registers 76 is predetermined. The paper is pre-determined. The paper size is 30. The Chinese standard (CNS) A 4 specification (210X297 gram) is used. 214588 Λ 6 Η 6 Ministry of Economic Affairs Central Standards Bureau Printed by the consumer cooperative V. Description of the invention (3 ^ register. The instruction decoding circuit 60 decodes a data command immediately, and initiates the appropriate operation to send to the register. As shown in FIG. 4B, GETB temporarily The memory 98 is used to connect the above display / slow read operation. In this regard, if a relatively low access time ROM is widely used, conventional microprocessors typically have to wait until a data capture is completed, regardless of when a ROM. Using the following delay / buffer capture mechanism, other operations can also be performed when the data capture is completed. According to this mechanism, if the register R14 in the register block 76 is accessed or modified in any way , Automatically start the ROM or RAM grab, and its address is identified by the content of R14. As shown in circle 4B, the scratchpad R14 is incorporated into the ROM control control 104. The scratchpad is modified in any way at any time R14 content, ROM controller 104 For initial ROM access. The result of accessing the ROM is loaded into the GET B register 98 via the multiplexer 102. It is coupled to the ROM data bus ROM D. The following command identification allows the access to be balanced at GET B The information of the register 98. This information is loaded into the destination bus Z through the multiplexer 100, and then enters a dump register at the register block 76. In this way, if the data fetched from the ROM, you It is known how many pre-determined processing cycles it needs. So it can be fetched without waiting and performing other operations. Mario chips can execute, for example, irrelevant codes, after such data fetching has started. The GET B register is also used to store the information retrieved from R0M6, 8 through the multiplexer 102, as shown in FIG. 4B. The register block 76 has a total of 16-bit 16-bit registers (R0 ~ R15). The registers R0 ~ R13 are general purpose registers (although some registers are used for special purposes, as explained below). As mentioned above, the register R14 is used as a standard for reading Chinese paper (CNS) A 4 specifications (210X297 official history) 3 1 (please read the precautions before writing this page) Line · 214588 Λ 6 η 6 Printed by the Ministry of Economic Affairs, Central Bureau of Economic Development, Beigongxiaot Cooperative V. Description of Invention (3 2) The indicator of 100 million units, and, when modified, starting from ROM (or RAM) Reading period. The read bytes are stored in a temporary buffer plaque (GET B register 98), like later access using a dump GET L or GET Η command. The register R 15 is the program number It refers to the beginning of the next instruction to be fetched. The register R0 is a general purpose register, which is typically used as an accumulator. For most single encounter period commands, it also presets the source and destination registers. If, for example, it is desired to add the contents of R0 and R4 together, it only needs to indicate the R 4 register. The Rll, R12 and R13 registers are used to execute a value loop instruction. The R13 register stores the top address where the loop will be executed, and the R12 register stores the number of times the loop will be executed. If the content of register R12 is non-zero, then the instruction at the address specified in the contents of R13 is loaded into the program counter (R15) and executed. After the completion of the loop, the returned address is stored in the register R 1 1. The register control logic 78 is coupled to the register block 76, and controls access to the general registers R0 to R15. According to the format of the held instruction to be executed, the instruction decoding logic 60 converts the instruction 1 or the multiple registers R0 to R15. Scratchpad Control logic 78 specifies scratchpads. These scratchpads will require the user to execute the next instruction. The register control logic 78 is suitable as the output of the register to the X and Y bus. In addition, as shown in FIG. 4B, the appropriate temporary registers R0 to R15 receive information from the Z bus under the control of the temporary register control 78. The ROM controller 104 receives the address from the super NES address bus ΗΑ, (please read the precautions on the back before writing this page). Binding · Order-line.  The size of this paper is printed in China National Standard (CNS) Grade 4 (210X297H) 32 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 9,14588_Lii V. Description of the invention (3 3) or the Maruio chip will access this bit site. The ROM controller 104 is described in detail in the next step as shown in FIG. 13%. The information accessed from R0M10 is loaded into the fast RAM 94 for fast instruction execution. The ROM and RAM controllers 104, 108 only have bus cutting units, which cut access attempts between the Super NES and Marie Oujing. As will be further explained below, the Maruio chip also uses a status register (ie, in the register block 76 or in RAM6, 8), which can be accessed using the Super NES CPU, and the storage flag is used for identification Status conditions, such as zero flag samples, carry flags, plus and minus flags, overflow flags, a G0 " flag sample (when 1 indicates that the Maru chip is in progress, and 0 indicates that the Maru chip is stopped); one Dump the ROM byte to grab the flag in progress (indicating that the scratchpad R14 has been accessed). A variety of different mode indicator flags, including a ACT1 flag and an ACT2 flag; the immediate low byte and the high byte flag of the residence; the source of the flag indication and the current register, which has been a > with 〃 ago Set instruction and an interrupt flag setting 1. The Maliou wafer represents a square circle in the form of 4A and 4B. It uses Super NES to turn on or turn off the Mali wafer multiple times in one second to perform work. At the beginning, when the Super NES is turned on, the game program stored in R0M10 starts. It should be noted that before using the Super NES and Maruio chip processor game program to execute, first check the game instrument cassette. As in the embodiment, this confirmation occurs like using the start to put the Super NES CPU in a reset state, and confirming that the processor executes a confirmation program that is related to the game cartridge and the Super NES main control board. This is based on the US Patent 4,799,635. (Please read the notes beforehand, Sun fills in the wooden page) The BB family standard (CNS) A 4 specifications (210x297 g *) in the ifc scale of this paper (210x297 g *) 33 A 6 η 6 o- ^ A ^ Bo_ V. Description of the invention ¢ 4) From the beginning, the image of the Maruyang wafer is in the closed state. At the end of the day, the / Super NES has unlimited access to the game instrument cassette program ROM and game instrument cassette RAM. When the Super NES needs to use the Maruio chip processing capability to perform graphics operations or mathematical calculations, the Super NES stores the appropriate data for the Maruio chip processing in the cassette RAM (or pre-determined Maruio register) ); And in the Malichao chip program counter, load the address where the Malyu program will be executed. The data is processed using Mario chips, which may be pre-determined X, Y coordinate data of the target. The target rotates and zooms in or out. Maru Ou Jing can execute programs that implement algorithms to manipulate the foreground and background of different numbers of moving targets. Use Malo chip speed to enhance the hardware and software to get this operation can be performed at a very high speed. The use of Maricao chips to process ghosts can greatly expand the overall capabilities of TV game systems. For example, the Super NES restricts the display of 128 ghosts per frame, but with the Mario chip, hundreds of ghost displays can be achieved, as well as rotation, for example. When the Maliou chip completes the functions required by the Super NES. Execute a STOP instruction. And an interrupt signal is generated, and it is input to the Super NES to instruct Maru Ou Jing H to complete its operation, and sequentially instruct it to prepare to perform the next dysprosium work. You can also use the Maruio chip to perform small tasks, such as a high-speed multiplying task, or use it to draw a full-screen ghost S. In this work, the super NES is freely processed in parallel with the Maruio chip. If the super NES is far away from the RAM or ROM bus, when the bus is used. If the Super NES gives the Maruio chip, control the RAM and ROM bus on the musical instrument cassette (please read the precautions on the back before filling in the wooden page). Install the-line.  The Ministry of Economic Affairs, Central Bureau of Standards, Beigong Consumer Co., Ltd. cooperated in the printing of this paper. The Chinese National Standard (CNS) A4 specifications (210x297 g; «) 34 Λ 6 η 6 V. Invention description g5) (Please read the back first And the precautions need to be filled in 3), then Super NES can execute its working RAM32 standard program, as shown in Figure 2. Therefore, the output of the whole German system is increased, and a slap Super NES program to be executed is copied into its work RAM by copying from the ROM. At the same time, a program is executed using Maru Ping Jing M. The flowchart shown in _5 represents the operation sequence of the main CPU (for example, Super NES CPU) to execute the I " execute Ma 琍 歃 # program, like used to start the Ma yu chip, grab from the required address of the ROM And execute the code. The routine represented in Figure 5 will typically be executed by the Super NES CPU. When the routine is copied from the program R0M1O to its work RAM32 as shown in circle 2, at any time, when asked to perform a bow operation At this time, the main CPU executes this routine. As shown in block 1 2 5, when executing w to execute the Maru " main C Ρ ϋ routine, the initial operation is performed, including saving the super NES register. During the initial step, the routine is copied from the program R0M10 to the main CPU work RAM32. As shown in block 127, the R0M10 code group stores the code to be executed and is loaded into a chip memory. In addition, the actual address in the code group is stored in the Maruio chip screen base register, as shown in block 129. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy. Thereafter, as shown in block 131, the I / O input / output wedge is set on the Maruio chip to identify whether the 4, 16, or 256 color mode is used. This mode is similar to the color wedge operation of the main CPU. In addition, the mode setting is used to define the height of the number of characters displayed on the screen. The mode bit system is set to control the ROM and RAM bus to the Maru chip. Separately, the control of ROM and RAM bus can be selected, so set the Mali Ou to a bow mode, that is, it accesses the ROM bus, the RAM bus uses the Chinese standard (CNS) A4 specifications for the paper size. (210x297 公 35 Λ 6 Π 6-V. Description of the invention (36) (Please read the precautions before filling in the wooden ") or both. Therefore, if it is the setting of 〃 chess-type owner of Α 玛 琍 欧For ROM and RAM, the main CPU cannot read or write from or to the ROM or RAM. It should be noted that when the Maliou chip is using the program ROM bus, if the main CPU attempts to access the program ROM, there is a mechanism to make the matrix The Yeou chip returns the fake address to the Super NES. Jump to this address and keep the Super NES occupied until the Maru chip no longer accesses the cartridge ROM bus. As shown in block 133, The counter is loaded with a storage address, and after this address stores the first value instruction to be executed by the Machiou routine, the Machiou Jing H starts operating. Then, the main CPU waits for the slave Machiou chip (block 1 3 5 ) Comes a number interruption number. When the flute receives the one-tilt interruption signal, it informs the super NES Maru The chip has finished its operation and has stopped (block 137). If this interrupt signal is not received, the main CPU »waits for an interrupt (block 135). The Super NES may be in parallel with the Malmio chip during this time Executing the code, using the RAM32 fan circle to execute it, as shown in Figure 2. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy Box 76) to determine whether the Maruio chip " GO 〃 flag has been set, this flag indicates that the Maruio chip is in operation (137). In addition, the Maruio chip H status register setting A dysprosium interrupt flag is used to indicate the interrupt signal received by the main CPU. The Maruio chip is the source of the interrupt signal. Therefore, after the main CPUU35) receives a bow interrupt signal, test the appropriate Maruio state temporary storage To determine whether the Malyu chip is the source of interruption (relative to, for example, an interrupt signal for a vertical extinction interval). If the Maruio chip has been stopped (137), then the ROM and RAM Maruio owner mode bits are used in this paper standard to use the Chinese National Standard (CNS) A 4 specifications (210x297 gong) 36 Λ 6 η 6 Economy Printed by the Ministry of Central Standards Bureau Employee Consumer Cooperative V. Invention Instructions (3 7) Eliminated. And Super HES has full access to ROM and RAM. Super HES leaves the routine (141) and returns to the place where its program entered before the execution of the Mahalo routine. Ο When the CPU22 game instrument program converted the Malyu chip to the wedge of the ROM Malyu owner. It must stop accessing the ROM voluntarily. Whenever the CPU 22 needs to access the ROM for the same reason, it can only open and close the ROM Ma Jingou owner mode. The Malio chip will automatically stop when it needs to access this R0H next time until it returns to the ROM Malio owner mode. If it is executed from the internal fast RAM, it may not be necessary to stick to it. If the Maru chip is used in ROM in Maru Owner mode, it is very important that the CPU22 game instrument program does not even read anything from the ROM. For example, since it is extinguished vertically, it causes an NMI, and then the CPU 22 automatically stops attempts to fetch its interrupt vector from the ROM. It is undesirable, because CPU22 has clearly told Maru Oujing that it will stay away from the ROM, and a partial interruption has occurred, and then fetched from the ROM. In this situation, accessing a value ROM from the CPU 22, although in the Martial Owner's chess style, will allow the Maru chip to assume that this is an interrupt vector requirement. During the next capture of the interrupt vector in the ROM Marie Owner mode, the Marie chip will reconfigure the interrupt vector and enter the Super NES internal working RAM32 at the bottom of the stacked plaque. For example, if the normal interrupt direction is $ 00: FFEC, then it will generate a value jump to the position $ 00: 〇l〇c. Similarly, all interrupt vectors from $ 00: ffex will cause the CPU 22 to jump to the phase of $ 00: olox. The technology prevents the CPU22 from accessing the R0M10 when they should not, and transfers it to the onboard Super NES RAM32. Note (please read the notes on the back # fill in this page) to install.  line.  This paper uses the Chinese Standard (CNS) A4 specification (210x297 male dragon) 37 Λ 6 Η 6 5. Invention Description (3 8) Meaning, the RAM-based interrupt vector needs to include a jump or jump to the interrupt manager , That is, the actual code is stored, not just the vector address. When the Malyu chip is not in the Malyu owner mode, the normal ROM interrupt vector is used. It is best to refer to these locations to maintain the same address when the RAM-based interrupt vector goes to the same location. Refers to the Samaru chip instruction set, which provides an effective way to program high-speed zuanyuan and other processing algorithms. The following is a brief description of some instructions, and some registers used by different instructions. A detailed list of instructions in the instruction set is also included. The instruction is an 8-bit instruction, and is typically executed at the head clock signal. When, the instruction is modified by an 8-bit preamble. The Maruio chip instruction set includes a Temporary register override rule that allows programmers to specify destination and source registers before any instruction. If this "forced" prefix is provided, the instruction will only operate on the stacker. Therefore, the instruction set is variable-length instruction set and has countless combinations. There are certain basic instructions that are a head byte, which can be executed in one cycle. By providing pre-commands, a programmer can extend the functions of the commands. A command can be 8, 16, or 24 bits, depending on the programmer's wishes. The Malio processor uses instruction to start high speed, fast on-board RAM program execution, and delay / buffer I / O to memory. Through the use of a single-cycle pixel drawing instruction, the drawing process can be efficiently performed. The initial operation introduced by this instruction uses the above-mentioned pixel drawing hardware. Before the Zabeimaliu instruction set, when executing the instructions, the processor settings (please read the precautions on the back #fill in the wooden page) to install and order.  Line-Printed on the paper standard Xiaobei Standard (CNS) Grade 4 (210X297); ¢ 38 A 6 Η 6 4⑽_ V. Description of Invention $ 9) or deposit Take a variety of different records to the scratchpad. As explained below. First of all. Identify and store temporary: The next bit of the 16th bit is the same, the device retains the temporary state of the state. 16 016 The device stores and erases I. Stores the temporary flag and temporarily tilts the flag every state Flag state

Z 2

C 3

S

V

Flag flag to sample label flag 15 Flag bit negative R [Zero into positive overflow XO standard into (please read the precautions on the back before filling in the wooden page) 5 sample flag ο]] Line 15 into the chip into the crystal 14 euro ]) Jing Zhiweiwei stop installation-6 Γ take the group position Η ο R line, si advance in the main line. 7 Retention is set for the status of the state. 1 class instruction refers to the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. The printing of NI chip-level crystal super eye to Yehema cadmium indicates that the signal is in this state, and the number of cells produced is broken ^ in 0 flags " in Go positive% * flake crystal, European stop ♦ VV Value 1 and its predecessor, this command means that 0 indicates that the group fetches the index, grabs the 50-bit data element, and the ET level is 5G into the silk 5. The Μ Bϋρτφ flag $ D is set here. * Take S ^ ^ Check l Clear S ^ ^ ¾ Liqi cubic Mi Mi ESRO to ⑨ one, super one over -7 use 彳 彳 j to carry out 丨 in the ability) o are not stored transient state 0 Units with higher unit aw unit a wo group tm higher β Use a better unit II element master or m · * · Handle Η Crystal Ou Liban use the tentative flag state to set 0 unit position 8 Yu Qi's style is undefined and the order is determined before the decision. The paper size is used in front of the Chinese standard (CNS) A4 specification (210x297 mm) 39 04⑽ Printed by the Beigong Consumer Cooperative Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs. System V. Instruction compilation). Bit chess 8 a 1 11 transformation (ADD-> ADC, S II B-& SBC, etc.) 9 a 1 t 2 transformation (ADD-> ADD #, SUB- > SUB #, etc.) 10 i 1 Lidi bit low (before ih) 11 ih Lim bit high (low byte is balanced until hi quasi) 12 b SR eg & DR eg Both settings, use WIT Η setting Ο 13-Reserved 14 -Retain the 15 rg interrupt flag in the ACT1 mode identified above, an ADD instruction will be compiled into a bow ADD with carry. And a SUBTRACT instruction will be compiled into SUBTRACT with carry. A crane command ACT1 starts the wedge. The ACT2 instruction modifies the compilation of the ADD instruction to become ADD with immediate data, and modify SUBTRACT to become SUBTRACT with immediate data. ** immediately " the data is in bytes immediately after the command. It should be noted that the instruction ACT3 will set the positioning elements 8 and 9 to a logical level. The setting of bits 10 and 11 depends on whether the immediate data is immediate high byte or immediate low byte. Bit 12 of the status register defines a w 6〃 mode, in which a pre-command, WITH 〃 is used to set the source and destination registers. Bit 15 of the status register stores the Mario interrupt signal, which is set after Mario stops execution. This paper uses the Chinese National Standards (CNS) Grade 4 (210X297 g *) 40 (please read the precautions before reading, Qiaomu ") Λ 6 Η 6 Beicong Consumption, Central Standards Bureau, Ministry of Economic Affairs Printed by the cooperative. 5. Description of the invention) The Malio chip includes many registers, except for the above-mentioned status registers. As mentioned above, the Maruio chip includes 16 16-bit wide registers, as illustrated in register block 76 of FIGS. 4A and 4B. Most of these registers are general purpose registers and can be stored in data or addresses. However, register R15 is always used as a program counter. Typically, the register has two purposes, used to communicate with the main CPU, and used to control the execution of programs. In addition, the functions of the other registers used in the Maruchip are described in the following table. Special register function rO Preset DReg and SReg r 1 X coordinate of PLOT instruction r 2 Y coordinate of PLOT instruction r 3 None r4 LMULT instruction result of low byte r 5 None r6 Yu group multiplication is used in FRM0LT and LM0LT instruction r7 Used in the source of the MEREG instruction 1 r8 Used in the source of the MERGE instruction 2 r 9 No r 1 0 No rll Used in the connection register of the subroutine call r 1 2 The count of the LOOP instruction r 1 3 The address of the LOOP instruction jump r 14 ROM address, when correcting the readout from the ROM (please read the precautions on the back before filling in the wooden page) Install-• ^ _ Line (210X297 male dragon) 41 A 6 η 6

21.45BB

5. Description of the invention 4 2) r 1 5 Other registers 8-bit PCBAK 8-bit R0MBAK 8-bit RAMBAK 16-bit SCB 8-bit ΟΡ 8-bit SCS (please read the precautions before filling in the wooden Page) Start byte program counter program code group register program data ROM group register, 64K group program data ROM group register, 641 (group screen screen base bit plane code number screen screen row size selection : 256, 320, 512, 1024, 1280 (screen 16 & 20 U element high, in 2, 4 & 8 bit plane) The Malio chip also includes a color chess CM0DE register. In this register 4 One bit, as used in this embodiment, creates special effects as described below. By setting a bit change in a CM0DE register, these effects are created, based on whether 16 or 2 5 6 color resolution mode is set. For example, the following description: Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economics. The following is the CM0DE register bit C MODE bit drawing color 0 bit (NOT transparency bit) in the 16 color mode: if bit 0 = 1, and the selected color nibble = 0, then do not draw raw m 〇 256 color mode and bit 3 = 0: 42 This paper standard uses the Chinese National Standard (CNS) A 4 specifications (210x297 male dragon) Λ 6 Η 6 214588 V. Description of invention 43) If bit 0 = 1 , And the color byte = 0, the garden is not drawn. . In 258 color mode and bit 3 = 1: If bit 0 = 1, and the lower nibble of color = 0, no picture is drawn. Ν.Β. Transparent 0Ν = 0 Transparent 0FF = 1 Only use transparency OFF, fill a plaque with 0 (used to remove screen) CM0DE bit 1 Dithering bit Dithering in 16 color mode. (High / low nibble gives 2 colors) If (xpos XOR ypos AND 1) = 0, then select low nibble If (xpos XOR AND 1) = 1, select high nibble. If transparency is on and the selected color nibble is zero, no picture is drawn. In 258 color mode, jitter has no effect. CM0DE bit 2 The upper half bit color bit is in 16 color mode or 256 color mode, and CM0DE bit 3 is set. When this bit is set, the COLOUR command sets the lower half bit of the color register to the source The high nibble of the tuple. (Use uncompressed 16 colors to store ghosts, when the upper nibble is another ghost). If the lower nibble of the color register is zero, the picture is not displayed and transparency is turned on. (Please read the precautions on the back before filling in the wooden page) Installation-Line-Printed by the Central Bureau of Standards of the Ministry of Economic Affairs, Beigong Consumer Cooperative, this paper size is used in the middle of the home standard (CNS) A 4 specifications (210x297 male dragon) A 6 B 6 214588 V. Description of invention) CMODE bit 3 The complex bit has only 256 color modes. When this bit is set, the upper half of the color is locked. And the COLOR command only changes the low nibble. The transparency is calculated only from the low nibble. In the normal 256 color mode, if it is on, the transparency is calculated from all bits. ; 16 color mode examples

ibtr ο, $ CO (please read the precautions on the back before filling in the wooden page) colour ibtro, 0000 set the color $ CO; set 0 to install. Codeibtro, $ 97 colour plot ibtro, $ 30 colour plot color drawing garden $ 线 _ ibtro,% 0 0 0 1 No drawing, when the color is $ 0 transparency is open and the lower nibble = 0) Set bit 1 cmodeibtro, $ 4 0 co 1 ur This paper size is common China National Standards (CNS) A 4 specifications (210X297 g *) 44 214588 Λ 6 Β 6 V. Description of invention (45) plot Circle color $ 0 (transparency blue) STOP; 16 color mode, bit 2 setting example ibtr ο, $ C 0 colour; setting color $ C0; 256 color mode, bit 3 setting example ibtr ο, $ CO colour ibtrocodeibtro colour plot ibtro colour plot% 1000 47 $ 50 (please read the precautions on the back before filling in the wooden page ) Set color $ CO Set bit 3 Paint color $ C7 Printed ibtrocodeibtro colour P ο 1 t% 100 1 60 on paper size Use Chinese National Standard (CNS) A4 specifications (210x297; ¢) When the color is $ C0, do not draw the garden (transparency on and low nibble 0) set bit 3 and bit 1 to draw_color $ C0 (Transparency open) 45 Λ 6 Π 6 V. Description of the STOP; 256 color chess style, setting bit 3 and bit 2 example (please read the precautions on the back and fill in the wood) installation. Threading · Ministry of Economic Affairs Printed ibtr ο, $ C 0 colour ibtro, ^ 110 0 codeibtro, $ 7 4 colour plot ibtro, $ 0 3 colour plot ibt ro, ^ 1101 c η ode ibt ro, $ 08 colour plot stop If there is no other specification, set the color $ CO Set bit 3 and bit 2 group color $ C7 When the color is $ C0, do not draw (transparency on and low nibble = 0) set bit 3 , Bit 2 and Bit 1 drawing color $ C0 (transparency on) The multi-chip European chip register has special functions as shown in the table above. The dummy system must be set to the register R0, as a temporary register This paper uses the Chinese Standard (CNS) A4 specifications (210X297 公 #) 46 Beigong Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Printed This paper standard uses the Chinese National Standard (CNS) A 4 specifications (210X297 public 4588_nj_ V. Invention description 4 7) or the source register according to a pending instruction. The R0 register is also used as an ALU stacker. The multiply instruction, as described above, returns a 32-bit result. The lowest 16 bits are stored in register R4. The register R6 is used for phase-by-value fractional multiplication instruction (FRMULT) and a long multiplication instruction (LMULT). The registers R7 and R8 are used to execute the MERGE instruction. The Japanese command makes two pre-determined registers (ie, registers R7, R8) to be combined with each other to form a ghost podcast / data. The coordinate data is used for addressing a slap ROM table, which is mapped to a pre-decided Youxiong to a pre-decided polygon. This instruction is to help effectively perform the texture mapping operation. The two registers in the combined part are used to define the color address of the next pixel. The pixel is included in the spirit and mapped to a polygon. Use registers R11 to R13 to control subroutine execution. The register R11 serves as a link register for subroutine calls, and stores the contents of the program counter plus 1. The content of register R11 defines the address that must be accessed after completion of the process. Use register R12 to store a value count to define the number of cycles to be executed. The address of Xun Chen is stored in register R13. As described above, whenever the contents of the register R14 are modified, a byte is read from the stored address in the register R14 of the R0M10. In this way, a delay or slow balance READ operation is implemented, corresponding to the GET byte command identified below. Refer to a of the above table for other registers to be executed in the program ROM. The location of the program will be addressed using a 24 bit address. The lowest 16 bits of this position are found in the program counter. The highest bit definition program group is stored in a program 4 7 (please read the precautions before writing wooden pages) **? Τ- Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 4588_π_6 V. Description of the invention 4 8) Type code group (PC group) register. The ROM group register (ROMBANK) stores the highest bit, which is used to allow the address data stored in R0M10 to be stored, and is appended to the 16-bit ROM address stored in the register R14. Similarly, the RAM group register (RAMBANK) stores more distant address bits, and is used to allow the Ma Liuou Jing H processor to access program data in RAM. The contents of the RAM and ROM group registers, which are related to the Malyo chip ROM and RAM access instructions, are used to effectively extend the address range of the Malyo processor. The screen picture base register (SCB) is used to store the address to which the virtual bit of the target is mapped. This target can be created, and rotated, enlarged and reduced. When the one-pitch PLOT pixel instruction is executed, the screen picture base register SCB, which is stored at the RAM address, is accessed and written with information. The register NBP you use to store the number of bit planes. Typically, the indication uses 2, 4 or 8 planes. In addition, use an on-screen screen row size register SCS to specify the information to be mapped to the virtual bits, and the information system is represented by the number of characters included in the row. The Mario crystal instruction set listed below, the command abbreviation character ((nenonic), and related to decoding the function performed by the relevant instruction. First, a short note explains some of the functions of a relative instruction. When the Malyu When the chip completes its operation, it executes the stop command and sets the '" GO " flag to zero, generating any interrupt signal to the main CPU. The CACHE command operates to define a part of the program ROM, which is copied into the Maru chip Fast RAM, and execute from there. When the CACHE instruction is executed, the contents of the program counter are loaded into the fast base register, and the following instructions (please read the precautions on the back before browning the wood page) install &line; this For paper size, please use the Chinese Standard (CNS) A4 specification (210X297 male dragon) 48 Λ 6 η 6 214588 V. Description of the invention (4 9) The quick logo is reset. (Please read the precautions before you go hard " Wooden Pages> Maruio chip includes a series of delayed jump instructions, which are executed as instructions in the following table after the jump. The address where the jump occurs is relative to the content of the program counter. The instruction set is based on the following table There are a variety of different delay jumps. The Maliou chip contains multiple '" front " instructions, that is, to / with / from. The creation of these front-end instructions implies a back-wrapping instruction for data distribution. For example v TO " Pre-set destination register (DREG), used for the next command. " FROM 〃pre-set source register (SReg), used for the next command. w WITH 〃pre-set both. Most commands have a second source register here. If SReg and DReg are not set with pre-commands, they will be preset to R0. After each command, SReg and DReg are set to R0. If DReg is set to R15, the program counter causes the next value command to store its content in R15, and then starts a value cycle delay jump. The Ministry of Economic Affairs Central Standards Bureau Beigong Consumer Cooperative printed other pre-commands to set the status of high byte The flag of the memory to change the operation of the following instructions. All non-preceding instructions clear the status byte of the high byte. The following example shows how to modify the instructions after the pre-order instructions. 1 to r 4; r4 = r * 0 direction Right shift 1 1 sr from r 4; r * 0 = r4 shift right 1 1 sr; r0 = r4 shift right 1 alt 1 _ This paper scale uses the Chinese National Standard (CNS) T4 specification (210X297); ": ) 4 9 Printed by the Beigongxiao F Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Λ 6 Η 6 5. Description of invention 〇) from r 6 to r 5 add r 7; r5 = r * 6 + r7 + carry alt 1 with r 3 add r 3; r * 3 = r3 + r3 + carry (6502 rol) If 'flag, correct' is set in the status register ^ TO 〃 instruction is treated as a MOVE 〃 instruction. The TO command specifies the information to be moved to the register, and the F r ο B command information source. The STW instruction stores a specific word in a buffer plaque. It does not wait, until a save operation is completed before executing the following instructions. In this way, the use of one-degree RAM is slower than the processor, and do not unnecessarily slow down the processor. The execution of the LOOP instruction reduces the contents of the general register R12. If the content of R12 is not zero, then jump to the address specified by R13.

Altl, Alt2 and Alt3 are pre-instructions, which are set in the above-mentioned flag of the status register, so that the execution instructions are translated in different ways, as shown in the following table. The PLOT command recognizes the coordinates of the X and Y screens that will be drawn. And draw the color specified by the COLOR command relative to the screen position on the X and Y coordinates (as shown in the registers R1 and R2). The PLOT pixel instruction includes the automatic addition of R1 content, like assisting in drawing horizontal lines at high speed, and is free from including a partial additional instruction. Set the Altl flag, and then compile the PLOT command, which is a READ command (please read the precautions on the back and then write the wooden page). Installation · Line · This paper standard uses the Chinese National Standard (CNS) A 4 specifications (210x297 Mm) 50 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Λ 6 Η 6 5. Description of Invention 61) PIXEL Directive (RPIX). By executing the read pixel command RPIX, the color of the pixel at the position of the special #screen screen is read out, and it can also be used to remove unnecessary pixel information from the hard manta. / Read pixel command RPIX, which mainly uses circle hard bones to read out from the character matrix in reverse to determine the color of one specific pixel specified by the command. The COLOR instruction is provided to the color hardware, and uses the contents of a specific source register to define the color of the next pixel. * The C MODE " command sets the color mode, which can be used to produce different waiting effects, as demonstrated in the example above. For example, use the CM0DE instruction to generate a dithering effect, and change the color at another pixel to produce a gradient effect. The CM0DE command can be used to control transparency, so a ghost is displayed first and then the day is displayed in the background. The decision of transparency is based on the setting of a single-color chess-like flag, as shown in the example above. The instruction set also includes a decimal positive and negative multiplication, which is used to calculate the rotation polygon to determine the gradient or slope of the displayed target. Add instruction, if it is used in phase register R14, it will start reading from ROM. The GETC instruction will access the byte from the ROM and load it into the human color register. The following table specifies a Maryo chip instruction set according to an embodiment of the present invention. The creation of these instructions has been discussed above. (Please read the precautions on the back before filling in the wooden page). Packing and threading. The paper is used in the middle Η Η home sample standard (CNS) A 4 specifications (210X297 mm) 51 Λ 6 Π 6 5. Invention description R2) The six-level 籣 character of 楏 今 Hayabusa is $ 〇〇 $ 01 $ 02

STOP NOP CACHE $ 03

LSR 04

ROL $ 0 5 η η BRA sbyt $ Ο 6 η η BGE sbyte Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics $ Ο 7 η η BLT sbyte Stop Maru Ou Jing H, and produce 658 1 6 IRQ, g = 0 1 cycle no operation to set fast substrate to PC and reset fast flag. (Only if the PC is not equal to the current rapid base) If the rapid base Orl5, then the rapid base = r 1 5, reset the rapid flag. Logic shifts to the right, DReg = DReg LSR 1 〇 Carry to the left and turn from DReg = SReg R0L1 must be relatively extended hydroxy jump rl5 = rl5 + sign byte offset if greater than or equal to, then the relative delay jump, if ( s X 0 R v) = 1, then r 1 5 = rl5 + sign byte shift. If less, then the relative delay jump, if (s XOR v) = 0, then r5 = rl! + Sign cadmium shift. (Please read the precautions on the back before filling in the wooden page). Installed.-Line · Private paper standard for small use in S Η family standard (CNS) A 4 specifications (210x297 male dragon) _52_ 66 ΛΗ V. Invention description 5 3) $ 0 8 η η BNE sbyt Jumping to 0-delayed phase is equivalent to false $ 0 9 η n BEQ sbyt $ 0 a η n BPL sbyte 0 Delayed ΪΕΜ + pair 15 pairs monthly Γ Mmura-I Feng. Then 1 shift then shift · lirn, sugar, etc. The group phase is 0, the positive element is not z = the bit is, such as the bit is like a jump, such as a jump, a false jump, a false jump, a false negative

Z is negative, positive + (please read the notes on the back before writing this page)

S is negative and positive + $ Ob n BMI sbyte 0 The extended negative pair of phase shifts is the element such as jump and false jump if false Γ then Γ negative and positive + $ 0 c η n BCC sbyt Central Bureau of Economics Ministry of Economic Affairs Printed by the cooperative in the US $ 0 d η n BCS sbyt The paper size is based on the Chinese standard (CNS) A4 specification (210x297 g *). In addition to the removal of the standard deviation flag, the jump group bit jumps into the late position. Delayed false C shifts the component bit if it is false TT negative and positive phase ΰ Beiding set the sample flag to jump into the delay such as delayed false negative and positive + shifts 0 component if the bit

C 53 V. Description of invention Lu 4) $ 0 e η n BVC sbyte $ 0 f η n BVS sbyte $ 1 0-$ If TO r 0 ··· r 1 5 ifb ： $ 20-$ 2f MOVE WITH rO-r 15 $ 30- $ 3b STW (rn) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs if a 1 t 1: STB (rn) This paper is not used in China B National Standard (CNS) Grade 4 (210x297 g *) _Π6_ If the overflow is removed, then the relative delay jump If v = 0, then rl5 = rl5 + sign and byte shift If the overflow is set, then the relative delay jump If v = l, then rl5 = rl5 + positive and negative Number byte fistula migration (front) set DReg to rn (the destination register is used for the next value op) DR eg = r η rn = SReg (no flag setting) (front) set DReg and SReg to r η DR eg = r η SR eg = rnb = l store SReg RAM at the rn address [rn] = SReg [low character group / high buffer] [normally the tuple is at the number of addresses] remaining at the rn address Low-byte SReg RAM [rn] = SReg.l [Byte Buffer] _5 ^ d (Please read the precautions on the back before writing the wooden page) Λ 6 B 6

5. Description of the invention (5 5) $ 3c: LOOP $ 3d ALT1 $ 3e ACT2 $ 3f ACT3 $ 40 ~ $ 4b LDW (rn) if a 1 t 1: Printed by LDB (rn) Beigong Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs $ 4c

The PLOT private paper scale uses the Chinese Η Family Standard (CNS) A 4 specification (210X297 g; ":") minus r 12, and if rl2 < > 0, the delay jumps to the address at r * 1 3. 12 = rl2-l If rl2 < > 0, then rl5 = rl3 (TO / WITH / FROM ignored) (front) set altl flag alf 1 = 1 (front) set a 112 flag a 11 2 = 1 (Front) Set the altl and a 1 t2 flags a 1 t 1 = 1 a 1 t2 = 1 Load from the rn address into DReg, DReg = RAM [rn] (character group high / low wait) (normal Local byte even address) Loaded into DReg from the address at rn, (unsigned byte) DR eg. H = 0 DReg. L = RAM [rn] [byte wait] at r 1, r2 (x. g) draw pixels and add r 1 (HBrl and r2 will not be checked on the screen, and will be drawn anywhere in RAM)-^-(Please read the precautions on the back before filling in the wood Ϊ ) Install-,? τ- -line · f of .4 dip 8 Λ 6 Η 6 V. Description of the invention (56) if a 1t1:

RP IX $ 4d

SWAP $ 4e

COLOUR if a 1 t 1:

CMODE $ 50 ~ $ 5f ADD r 0. R 1 5 if a 1 11 ί

ADC if a 1 t2:

ADD

if a 111 + a1t2 ADC $ 60 ~ $ 6F SUB r0. r 1 5 it a 111:

Printed by the SBC Ministry of Economic Affairs Central Standards Bureau Beigongxiao F Cooperative if a 1 t2:

SUB

if a 1 11 + a 1 t2 CMP $ 70

MERGE plot (rl, r2), rl = rl + l read the color of the pixel at rl, r2 (x, y) DReg = point (rl, r2) swap bytes DReg.h = SReg. 1 DReg.l = SReg.h Set PLOT color, circle color = SR eg DReg = N0T SReg Set PLOT color, picture garden color = SReg DReg = SReg + rn DReg = SReg + rn + c DReg = SReg + ttn DReg = SReg + turn n + c DReg = SReg-rn DReg = SReg-rn-c DReg = SReg- # n SReg-rn (zero flag, plus-minus flag, carry flag, overflow flag) Combining the upper bits of r7 and r8 is DR eg (please read the precautions on the back before filling in the wooden pages) The paper standard is the Chinese National Standard (CNS) T4 specification (210x297 g; ¢) Οϋ A & BB_Π6_ V. Description of invention (5 7) DReg.h = r7 .h, DR eg. 1 = r 8 h Printed by Beigong Consumer Cooperative of Central Bureau of Economic Development, Ministry of Economic Affairs

$ 71 ~ $ 7f AND rl. Rl5 if a 111: B IC if a 1t2: AND if a 111 + a1t2 B IC $ 80 ~ $ 8f MULT rO. R 15 if a 1 11: UMULT if a 1 t2: MULT if The a 1 11 + a 1 t2 UMULT flag has the following result settings: s = bl5 OR b7 v = bl4 OR b6 OR sc = bl3 OR b5 OR vz = bl2 OR b4 OR c DReg = SReg AND rn DReg = SReg AMD NOT rn DReg = SReg AND tfn DReg = SReg AND NOT # n DReg = SReg * Rn (with sign 8 x 8 bits) DRegzSRegiSRn (without sign 8 x 8 bits) DReg = SReg:!: Lfn (W IE M. Sfe 8 x 8 digits) DRegzSRegUn (8 x 8 digits without sign) (please read the notes on the back before writing the wood S) The paper size is free to use the Chinese Standard (CNS) f 4 specifications (210X297 Gonglong) 5 7 214588 Λ 6 Η 6 V. Description of the invention (5 8) + Six-level _ 简 字 譃 功 m $ 90

SBK 9 1-$ 94 L INK1-4 $ 95

SEX $ 96

ASR if a 1 11: D I V2 97

Printed by ROR Employee Consumer Cooperative of Central Bureau of Standards $ 98-$ 9d if a 1 11: JMP r8 -r 1 3

L JMP

Save SReg and return to the last one using the RAM address link to return the address to r 1 1 rll = rl5 + l ·. · 4 Sign to extend the low byte to the character group DReg. [Bl5-bl7] = SReg. [B7] DReg . l = SReg. 1 Arithmetic shift to the right DReg = SReg ASR 1 Divide by 2 low-order bits DReg = SReg ASR 1 If DReg = l, then DReg = 0 carry flag stack rotates to the right DReg = DReg ROR 1 Jump to rl3 address , Rl5 = rn (delayed jump) long jump to r η address, (R 0 Μ group from SReg) and reset the fast memory rl5 = rn (delayed jump) rationale I? Π U 如 斷 左 盟 盟 = SR (Please read the precautions before filling in the wooden pages) Binding-This paper is printed on the Chinese Standard (CNS) A4 specifications (210x297); ":) 58 Printed by Beigongxiaof Cooperative, Central Bureau of Standards, Ministry of Economic Affairs system

214588 V. Description of the invention < 59) $ 9e LOB $ 9f FMU LT Λ 6 B 6 (please read the back and pay attention to item I before writing the wooden page). Install. Line.

if a 1 11: LMULT $ a 0-$ af η η IBT r 0-r 1 5, sbyte if a 111: LMS r0-r 1 5, byte if a 1t2: SMS rO-r 15. byte low byte DR eg. h = Ο DReg. l = SReg. 1 Fraction has sign multiplication, DReg = (SReg * r6) .hw (sign 16 * 16 bit multiplication), c = (SReg) ir6) .bl5 long sign Multiplication, DReg = (SReg ^ rB) .hw (sign 16 * 16 bit multiplication) r4 = (SReg * r6). Lw c = (SReg) * r6) .bl5 loading r * n with signal extension bit Group rn = immediate byte (sign extension extends from the absolute shift byte address to load r η rn = RAM [byte < C1] (word data) stores r η to the absolute shift bit Group address RAM [Bytes < Cl] = rn (character data) This paper uses the Chinese B standard (CNS) A 4 specifications (210x297 g) 59 21.4588 Λ 6 Η 6 Central Bureau of Standards Printed by Beigong Consumer Cooperative V. Description of Invention (gQ) $ b0- $ bf FROM r0-rl5 (Reset) Set 'S R eg = r η SR eg = rnifb: MOVES SR eg = rn (zero flag, positive and negative signs Flag overflow flag (sign low byte $ cO H IB high byte , DReg.h = 0 DReg. L = SReg. 1 $ c 1-$ cf OR rl-rl5 DReg = SReg OR Rn if. A 1 11: XOR DReg = SReg XOR Rn if a 1 t 2: OR DReg = SReg OR »n if a 1 11 + a 1 t 2 XOR DReg = SReg Xor # n $ d 0-$ de INC rO-r 1 4 Increase rn rn = rn 11 (ignore TO / WITH / FROM) $ df GETC from ROM Buffer gets bytes to P COT color if a 1 t 2: RAO RAM data set register = SReg if a 1 11 + a 1 t 2 ROMB RAM data set register = SReg $ e 0-$ ee DEC r〇-rl4 minus rn, rn = rn-l (TO / W ITH / FROM is ignored) $ ef G ETB Obtain unsigned bytes from the ROM buffer to DReg DReg = ROM buffer bytes, zero Extend (please read the precautions on the back before filling in the wooden fi) to install. '1T_ line. This paper scale uses the Chinese standard (CNS) A 4 specifications (210x297 male dragon) 60 214588 Λ 6 η 6

5. Description of the invention (βΐ) if a 111: GETBH

if a 1t2: GETBL

if a 111 + a1t2 GETBS Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs $ f 0-$ ffnnnn IWT r 0-r15, Yu group ifa 1 11: LM r 0-r 1 5, the word group is from the ROM suspect area Obtained DReg high byte DR eg = R 0 Μ buffer plaque byte, and low mixed DReg = (SReg & $ FF) + (byte < C8) (using W ITH) buffer plaque from ROM Get the low byte sent to DReg DReg = R0M buffer byte, and high mix (use W ITH) to get the sign byte from the ROM buffer and send it to DReg DReg = R0M buffer byte, the sign is extended to load Immediate block to rn rn = Immediate block (buffering) Load from absolute block address r * n rn = RAM [Yu group address] (Yu group data) Store rn to absolute block address if a 1 t2 : SM rO-r 15, Yu group Figures 6 to 17 show the block details of the further detailed components of Figures 4A and 4B. If you want to show the unique features of this invention alone, for those who are familiar with the circuits that are familiar to professionals in this industry, if you confuse this unique feature, you will not use the Chinese standard (CNS) A in the paper below 4 Specifications (210X297 male dragon) (Please read the precautions before writing the wooden page) 214588 __Be _ Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of Invention 2) for display. * As shown in Figure 6, an example arithmetic and editing unit in the ALU unit 50. The ALU50 is shown in circle 4A and circle 6 for connection to the X, Y and Z busbars. Therefore, the Maruchip chips are generally registered from the scratchpad to the ALU. ALU50 uses a 16-bit adder / subtractor 152 to perform addition and subtraction functions. ALU50 also includes Fu Tong's " AND Λ logic 18 channels 154, * 01 ^ all edited roads 156, and ', mutually exclusive edited roads 158. The ALU also includes a Fourier shift function circuit in which any carry flag bit is moved to the most distant bit position. And the result is connected to an input end of the multiplexer 164 via line 160. In addition, the ALU50 performs the operation of swapping bytes, so that the lowest byte and the most byte on the bus can also be exchanged. And the result is on line 162 to multiplexer 164. The X and Y busbars merge into Xiaolu 152, 154, 156 and 158, as shown in Park 6. Output from adder / subtractor 152, circuits 154, 156, 158, shift register, and swap function, etc., up to 16 bits, 6 rounds into one, and result " multiplexer 164 . Depending on the decoded result, the appropriate result image is output to the destination bus Z. The adder / subtractor 152, in addition to receiving 16 bits from the X bus, also receives the forward information on the X bus, or the information of the command itself, depending on the input of the command decoder to the multiplexer 150. In addition, ALU50 includes a crane CPU flag generation 霣 路 166. CPU Flag «Road 168 generates zero-bit, plus-minus, and carry signals, and is used to load at least one flag register in the 霣 路 166. Set the CPU flag sample from the command decoding circuit 60, the carry flag generated by this S-channel decoding command is enabled, zero (please read the precautions on the back and then write the wooden page hard) This paper standard uses Chinese National Standard (CNS) A4 specifications (210X297 mm) 62 214588 Λ 6 η 6 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Invention Description 6 3) Flag enable, positive and negative flag enable and overflow flag-like letter signals. The flag setting depends on the phase condition determined by the use of the adder / de-energizer 152. The flag is also set based on the content (or result) of the bus Z that is intended to be passed to the flag circuit 166. Use flags, for example, to trigger a conditional jump based on a wide range of conditions. Figure 7, 8Α and 8Β image garden 4Α circle picture circuit (52, 54, 56, and 58) further description. The circuit executes the PLOT command. This command obtains a specific X and Y block and draws a healthy pixel on the screen frame. The color of this pixel is specified by the content of the color register 54 loaded by the COLOR command. It should be noted that the Super NES uses a 㑩 character to map to the display screen. Day map The operation of the hard bones converts the address data of the pixel block to become the data from the Yuyuan map to the address data. The Super NES character is defined in the bit plane. Characters can be 2, 4 or 8 bit planes, used to define 4, 16 or 256 colors. Each byte defined by Yuyuan includes the characters of a row of pixels in a slap bit plane, and defines the pixels from left to right, high bit to low bit. For a filling 256 color wedge operation, 8 RAM locations need to be updated. The pixel circle hardware includes a local buffer mechanism, which includes a color matrix 206, whose storage will be displayed as all bits of a particular byte, because all these bits will eventually need to be updated. A slap bit plane counter 28 is coupled to the color matrix 208. The pixel coordinates are loaded from the X and Y busbars into the drawing circle X and drawing circle Y registers 202, 204. In the current embodiment, the general registers R1 and R2 are used as shown in Figure 7 _X temporary (please read the notes before filling in the wooden page) Standard (CNS) 4 specifications (210X297 mm) 63 M4588 Λ 6 15 6 Printed by Beigongxiao F Cooperative, Central Bureau of Standards, Ministry of Economic Affairs V. Invention Description (g4) Memory 202 and Temporary Memory 204. The X and Y erases of some register pixels are as specified by the PLOT command. The picture registers X and Y registers 202, 204 are combined into full and half adders, which are based on the character address calculation circuit, and output from the address to a value position tube shift circuit 214, which is sequentially combined to A picture address register 216 and a value comparator 218 are provided. The three least significant bit networks of the drawing X register are combined into a demultiplexer 212, which is sequentially combined into a tilted undetermined register 210. As shown in _8 Ran, the circle controller 200 receives a signal indicating that a PLOT picture (PLOT) or READ pixel command has been decoded, and other control multiples as described below. As much as possible, the controller 200 generates the control signal for the engraving group and uses it in the following manner. As shown above, the drawing control circuit 200 generates control signals for use in the pixel picture hardware 52. As shown in FIG. 8A, the pixel control circuit 200 receives the round from the undetermined register 210, and this output is coupled to the pixel control circuit 200 via the AND gate 201. If all 8 bits of the bit pending register 210 are set, the pixel is notified to control the set 200, skip a read cycle, and write the information in the color matrix 206 to RAM. The pixel control circuit 200 also responds to the PLOT command to start its operation. The pixel control logic 200 also responds to the READ pixel command PRIX to start the exact same operation, except that the new information is not written to the color matrix 206 and is used for output to RAM. As mentioned above, if you know the color of a pending pixel on the screen, you can execute this READ pixel command, and it can also be used to clear the current information on the color matrix. The controller 200 also receives a RAM complete control signal RAMD0NE, which is installed with (please read the precautions on the back before writing wooden pages) ..?! _ Line. This paper scale is free to use the Chinese B Family Standard (CNS) A 4 Specifications (210x297 male dragon) 64 21.4588 Λ 6 η 6 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of Invention 15) Instructed that the RAM access has been completed. The RAM completion signal, as described above, is also added with a bit plane set counter 208 to identify a spare bit plane in the color matrix 206. The circle controller 200 receives the PLEQ signal from the address comparator 218, which indicates that an address has already been matched, and there is no need to write the content of the color matrix 206 to the RAH, so it indicates that the current color matrix content update should be continued. The drawing controller 200 receives the screen picture mode SCR and MD control signals and informs the drawing garden controller 200 how many bytes to read and write. The drawing control circuit 200 generates a dump control signal DUMP, referring to FIGS. 7 and 8B, which causes the content of the color matrix 206 to be buffered in its second buffer section. In addition, the controller 200 generates a clear bit register signal CLRPND and a manned bit register control signal LDPND, and integrates this signal to the bit pending register 210. In addition, the controller 200 is related to the LDPfX and BPR control signals of the color matrix elements, as illustrated in FIG. 8B. The command decoder is used to decode the PLOT command, and the PLOT signal is input to the day drawing controller 200, and the generation of the indefinite signal LDPHD is initially loaded. The prerequisite is that it is as hard as possible. The LDPND signal is closed into the bit-instant register 210, enabling the loading of data from the demultiplexer 212 into the bit-instant register 210. CLRPND is generated to clear the pending signal, »it should be in RAM. The RAM completion signal RAMD0NE indicates that undetermined data has been written to RAM. After that, this bit-unscheduled register is vacated for use in the next "Pixel Day Map Information". The timing chart displays the image of various signals received by the drawing controller 200. Various address and data signals as shown in FIG. 8C, other phase control signals, and the drawing controller generate output control signals. As an example (please read the precautions on the back before filling in the wood 3). The paper is used in the middle Η Η family standard (CNS) «F4 specification (210X297 male dragon) 65 214588 Λ 6 Η 6 Ministry of Economic Affairs Central Standards Bureau shellfish Printed by the consumer cooperative 5. Description of invention § 6) Address value, data value, etc., are for illustrative purposes only. The following is the operation of drawing hard hard 52. When the diurnal controller 200 decides that the hard snake 52 is not busy. As shown in circle 4A, the contents of the color register 54 are loaded into the horizontal row of the 8 × 8 color matrix 206. Load the color matrix 200 with columns, and read with rows. The contents of the color register 54 are updated using a COLOR command. The color register 54 is a tilt register, and the color data is loaded into the color matrix through any subsequent PLOT command. In the vertical position of the color matrix 206, the bits of its color register are loaded, you decide by storing the three least significant bits in the picture X register 202. Therefore, the three lowest bits of the drawing address define a row of bits, and the bit color matrix 206 is updated. The undetermined bit register 210 is used to record specific bits of the Yuyuan segment of the screen image to be updated. The register 210 includes a 16-bit register flag, which indicates the bit to be written to the part of the screen. It is desirable to load the undetermined register 210 into a signal LDPND, and use the group controller 210 to generate a signal CLRPND to clear it. If a post mine drawing command will be executed, the screen will be updated to the same plaque. Repeating operations for a known bit, while adding color data to one pixel at a time, is loaded into the 8X8 color matrix 206. Then, through the drawing address stored in the lowest bit of the drawing X register 202, 9-slap bits are set to the in-place register 210. A specific bit is coupled to the shovel 3 to 8 demultiplexer 212 of the X register 202, and is loaded into the bit undetermined register 210. If the update pixel is more than 8 pixels, or if it occupies a different vertical position, the data written to the matrix 2 0 6 needs to be read out (please read the notes on the back # 埙 写 木 页) Printed with the Chinese 漳 楳 quasi (CNS) A 4 specifications (210x297 male dragons) 66 214588 Λ 6 η 6 Printed by the Central Standards Bureau of the Ministry of Economic Affairs KKXC Consumer Co., Ltd. 5. Description of invention b 7) RAM6 (or 8). After that, the spatial color matrix 206 receives the new color data until it receives a dumping command and writes it to the RAM9. The current content of the color matrix 206 is slowly balanced in the pixel plotter, that is, in the color matrix Within 206. When the data from the color matrix 2 06 is written to RAM 6 or 8, the address conversion calculation is performed, using the logic gate shown in FIG. 7 and the full and half bit adder circuit to convert the X and Y blocks into a RAM bit. site. The actual address calculation in this example is explained below. This calculation will vary depending on whether the user is in 4, 16 or 256 color mode. Calculate with 256 color mode as an example. The 256 color characters have 16 tilt bytes of 4 squares, each defining a pair of bit planes, for a total of 64 bytes. One bit is mapped to the structure, and it is used at every position on the screen area of the desired screen, and a unique character is placed. When drawing on the Super NES, it is best to arrange characters in columns. For example: (128 pixels high screen image) Character number 0 1 6 3 2 ...... 1 1 7 3 3 ...... 2 1 8 2 4 ...... • · · • ♦ ♦ 1 5 3 1 4 7 ...... Super HES is not limited to 256 yuan, so the bitmap to size is mainly limited by the memory and DMA transfer time. The Maliou wafer can draw circles, for example, 6 7 sheets of paper with Chinese Pujia Standard (CNS) Grade 4 specifications (210x297 mm) (please read the notes on the back of the book written by Sun Xun). * 1T_ line · Λ 6 I? 6 0 214588 V. Description of the invention (68> 128 and 160 pixels off the screen. The maximum screen size is 32 characters or 2 56 pixels. The following algorithm example shows how to use the column structure arrangement Bits are mapped to to control the pixel picture. First, calculate the bow pixel mask from the lowest three bits of the X coordinate for all bit planes. Pixel number masking% 10000000 01000000 (Please read 1, back first Please pay attention to this page and then fill out this page.) Pack · 7% 00000001 Next, use the Y coordinate of the lower 3 digits to remove, calculate the following shift, give the characters below, and then multiply the size of the characters. Screen color The size of Yuyuan is calculated in bytes 4 16 lines_ 16 lines. 16 32 Printed 256 6 4 by the Ministry of Economic Affairs of the Central Standards Bureau staff elimination cooperative. Secondly, remove the lower 3 bits of the X coordinate and calculate the top of the character row The offset. The column size is the number of column characters multiplied by the yuan Small. Normal column size Character height 16 20 4 256 bytes 320 bytes color 16 512 bytes 640 This paper standard is used in the national standard B (CNS) A 4 specifications (210X297 male dragon) 68 214588 Λ 6 \\ 6 V. Description of the invention (6 § The lower 3 bits of the Y block sample of 256 1024 bytes and 1280 bytes are printed by the Peking Gongxiao Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs to give the byte under the character bias Shift all the cadmium shift and add the current bit mapping finger to 9 m. The pixel holds the address of the octet of the octet plane. After the bit plane is pseudo-selectable 1 octet »Then 15 Bytes finally use pixel masking to set or clear pixel bits. 0 Set or clear 9 bits in each bit plane so that the color number is in the state of the bit 0. This number is stored in the color m according to the needs of the pixel. The example of the memory 54 0 code is displayed on the 4-bit plane using the 65816 code, which is displayed as a musical instrument Most of this routine is a table-driven register A, X and Y are 16-bit Se t C ο 1 0 U Γ «Get color and double Id a C 〇1 0 U Γ as 1 ata X • Set color mask 9 Used for bit plane and 1 Id am as k 1 tab X St amask 1 9 Set color mask »Used for plane 2 and 3 1 da η as k2 tab, > F stamas k2 Γ ts Use the Chinese National Standard (CHS) A 4 specifications (210X297 public address) (please read the precautions on the back and then leave this page) to install. Order _ line · Λ 6 Η 6 (please read the precautions on the back before writing) This page) 314588 V. Description of the invention (7Q)

Plot; Get horizontal and vertical coordinates; Double both and move to Y and X registers

Ida pi o t x 1 a s 1 a t a y »Y is the X coordinate * 2 Ida pl o t y 1 a s 1 a tax • X is the Y coordinate * 2; get the meal shift

Ida pyoftab, x; plus the start of the column offset c 1 c ade poxftab, y; plus double the buffer index (selected bit mapping to) c 1 c adc drawaap Printed by the Ministry of Economic Affairs Central Bureau of Industry and Commerce Cooperative Society Tax; x is the offset from the bitmap to the base to maintain the required pixel block; y is the X coordinate of the pixel * 2; do bit plane 0 and 1 lda.l bitmapbase, X; get the pixel held by the block and pbittabn, y; masking the old pixel color sta pnask. The paper size is universal Chinese B Family Standard (CNS) A 4 specifications (210x297) 214538 Λ 6η 6 V. Invention description (7 ρ

Ida η ask 1; mask color and and P bi 11 ab, y; pixel masking together ora P ask; connect with other pixels sta. 1 bitnapbase, X; save in place and map to Beigong Xiaot Cooperative of Ministry of Economic Affairs Central Standards Bureau Print; do bit planes 2 and 3, 1 da. 1 bit house apbase + 16, x and pbittabn, ysta pnask Ida mask 2 and pbittab, y ora pnask sta. 1 bit haze apbase + 16, xrts; pixel bit Masked pair of 256-word table P bi 11 abrept; nuffl-col dv $ 8080, $ 4040, $ 2020 · $ 1010, $ 0808, $ 0 40 4, $ 0 20 2, $ 0101 endr; the above table has reverse Word group P bi 11 ab η rept 32; num-col dw $ 7f77f,-$ 40 40,-$ 2 020,-$ 1010,-$ 808 · $ 404,-$ 20 2,-$ 101 71 Happy Use B Η Family Standard (CNS) A 4 specifications (210X297 public address) (please read the precautions on the back before writing wooden pages) ^ 14588 Λ 6 Η 6 V. Description of invention (7 2) endr; use in Plane 0 & 1 column masking (Ο to 15 columns) ask 1 tabdv $ 000 0, $ OOf f, $ ff 00, $ ffff, $ 00 00, $ OOf f, $ ff 00, $ ffffdv $ 00 00, $ 00 ff, $ ffff, $ OOf f, $ OOf f, $ ff 00, $ ffff; used for plane 2 & 3 column masking (0 to 15 (Column) i & ask2tab dv $ 0000, $ 0 000, $ 0000, $ 0000, $ OOf f, $ OOf f, $ OOf f, $ OOf fdv $ ff 00, $ ff 00, $ ff 00, $ ffff, $ ffff, $ ffff, $ ffff, $ ffffc ο 1-sizeequ Nu ber -char -Γ 0 ws * & * N uber-bit -planes (16) (4); Offset to the beginning of the character list py 〇 ftabte is p = 0 (please read the precautions on the back before writing this page) install < _ line-rept 32 printed by the Ministry of Economic Affairs, Central Bureau of Economics and Trade Cooperatives; number of character rows dv te Swollen p, te ^ p, te hire p, tebp, tenp, tenp, te ancestor pte 臛 p te.p = te.p + col-size endr; cadmium is removed from the list. The paper size is free to use the Chinese H family standard (CNS ) A 4 specifications (210x297 mm) 72 214588 Λ 6η 6 Printed by Beigongxiaot Cooperative, Central Bureau of Economics, Ministry of Economic Affairs V. Description of invention (7 3) ptoftab te ancestor p = 0 rep 16; the number of character rows dvte dirty p dtf te li p + 2 dw teap + 4 dw teap + 6 dw te hurricane p + 8 dvtebp + 1 0 dw tenp + 12 dw teap + 14 teap = temp + 32 endr Return to circle 7 for more details. On the screen, the X and Y coordinates define the position to be imaged. It is loaded with PLOT X and Y registers 202 and 204, (the register may be in (R1 and R2 registers in register block 76). The lowest three bits of the gold circle address are loaded into the PLOT X register 202, which is defined as a bit in a single bit plane byte group, and is written or specified by the X and Y coordinates. The contents of the stacker R0 are loaded into the columns of the color matrix 206, which is selected using the lowest bit of the X register 202. If the drawing X register 202 is 0, the highest bit of the pixel defined by 8 bits will be updated. If the plaque X register 202 is 0, the 3 to 8 solution multiplexer 212 will set the lowest bit, and the register 210 in the undetermined bit will become "Edit (please read the notes on the back before filling this page ) Binding · Order _ line. This paper standard is common to China National Standards (CNS) A 4 specifications (210X297 male dragon) 73 V. Description of the invention (7 4) RAM controller 88 uses the undetermined register 210 to indicate There is no need to write out the space from the RAM, because the bit position of the unregistered register 2 10 does not need to be corrected. The undetermined bit register 210 is used as a pixel masking buffer to prevent overwriting of new data from RAM if the new data is not what is expected. To perform this method, as shown in FIG. 7, the cityscape of the undetermined register 210 is synthesized and input to the color matrix circuit 206. If the BIT-PENDING register 210 is zero, the on-screen pixel address of the pixel is calculated and loaded into a painting address register 216 at the same time, and the pixel position in the byte is set the same as in the BIT- The bit of the PENDING register 210. If the BIT-PENDING register 210 is non-zero, the BUSY flag is set. If the newly calculated address is equal to the content of the PLOT-ADDR register 216, the new pixel bit position is set in the BIT-PENDING register 210, and the BOSY flag is reset. If the new address is different from the content of the PL0T-ADDR register, take the following steps: Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before writing this page) Step 1: If BIT -PENDING register 210 contains FFH, then go directly to step 3. Step 2: From RAM in PLOT-ADDR + scr. Base byte, enter the first batch of temporary data buffer, PLOT-BUFF. Step 3: If the data buffer bits are masked with the BIT-PEND register 210, then all the lines equal to the 0th row of the PLOT-COLOR register display, go directly to step 5. The specifications of the SS standard (CNS) T4 (210X297mm) for this paper standard for easy use 7 4 Λ 6 Π 6

2145SB 5. Description of the invention (7 5) Step 4: Write line 0 of the PLOT-COLOR register display, and enter all the bits that enable the PLOT-BUFF using the BIT-PENDING register. Write data-buff back to the RAM of PL0T-ADDR. Step 5: Do the same operation (PL0T-ADDR + 1), line 0 on the display with the PLOT-COLOR register. Step 6: If it is 8 or 256 color mode, do the same operation in (PL0T-ADDR + 16), and the second row of the PLOT-COLOR register display. Continue until all color bits are updated. (Please read the precautions on the back before writing this page) Printed picture X and picture Υ20 20, 240 printed by the Beigongxiaot Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs * Use the full addition represented in Figure 7 The structure of the full and half adders FA and Η A $ represented by the adder and the half adder and the phase logic path has been simplified as shown in the block of country 7 EBI country 〇 as follows t = Ss Address SC r-base + 2 wear y [0… 2] + (y [3 “• 7] =» 16 + ((X [3… 7] 窣 4) & & sc Γ ** ht) ^ char -S i Z e The middle term is • y 7 y 6 y 5 y 4 y 3 X 7 X 6 X 5 X 4 X 3 0 0 X 7 X 6 X 5 X 4 X 3 〇0 〇〇 P χ9 P x 8 P x7 PX 6 PX 5 PX 4 PX 3 PX 2 PX 1 P x0 therefore produces a 1-bit partial result PX [0… 9] • Use 9 such as 6-value full adder and 4 half-adder. The result is a bow 12 X 3 Mode multiplexer, using the value of C ha r-si ze to control the result of the part to be shifted t, then wedging into the correct accuracy for the selected screen image. This combination y is lower bit y [0… 2] f forms a 1 6-bit silver outfit · Order_ Line-This paper scale uses the Chinese National Standard (CNS) A 4 specifications (210x297 male dragon) 7 5 Λ 6 η 6 214588 5. Description of the invention) Screen address. To be completed The address calculation is added to the screen-base value scr [9… 22], which allows the screen image to be placed on the margin of lk. Then, the address is matched to a 2-position barrel shifter 214, using 1 or 2 Or 4 is multiplied by the address information round, depending on whether you choose 4, 16, or 256 color resolution. The output of the shift circuit 214 is coupled to a drawing address register 216, and the register is used as a RAM address buffer for storage. After executing the circle drawing command, this address needs to be buffered. The contents of registers R1 and R2, that is, drawing X and drawing Y, may change. The address comparator 218 compares the new address determined from the output of the shift circuit 214 by drawing a hard frame and the old address stored in the circular address register 216. If the address is different, this address needs to be written out to RAM. The address comparator 218 generates a control multiplier PLEQ [all network integrated into the map controller 200], if the picture address stored in the address register 216 is equal to the output of the shift circuit 214. Returning to the color matrix 206, as described above, the color matrix 206 is read out in columns. A dysprosium bit plane counter 208 is meshed to the color matrix 206 and defines the column readout. The bit plane counter 208 is coupled to the RAM controller and completes a RAM operation. The RAM controller 88 generates a tilt signal to increment the bit plane counter 208. The color matrix 2 0 6 includes elements of one of the matrix moments as shown in Figure 8B. A total of 64 such elements are in the matrix elements of the 8X8 matrix 206. When the picture_command is decoded, the controller 200 meshes the command control signal L D P I X to the latch 2 2 0, so that the color data C0L can be loaded from the color register 54 to the latch. Use the control paper size to use the Chinese National Standard (CNS) T4 specifications (210X297 male dragons) (please read the precautions to be filled out by Sun to fill in this page). Order_ _ Ministry of Economic Affairs Cooperative printed 81.4.0,000 sheets (H) 76. Ministry of Economic Affairs, Central Bureau of Industry and Commerce A. Co., Ltd. 5. Du Du Printing 5. Description of Invention 7 (7) The controller 200 generates a control signal DUMP, which is indicated in the color matrix The first level in 206 is buffered, and the data needs to be output to the screen. Once the DUMP signal is generated, the data stored in the latch 200 is coupled to the gate circuit 226 and the latch 228. When the DUMP signal is actively closed to the gate circuit 226, the gate circuit network is fed to the latch 228. At the same time, the disabling gate 224 sequentially prevents the reverse output of the latch 228 that keeps the previously stored data from being sloppy. When the data read from the RAM is filled into the data gap, the control signal BPR provides a zero input to the gate 222, and the LDRAM signal will be in a zero state. In these cases, the data input from the RAMP will enter the latch 228 via the gate circuit 226. The latch 228 data can then be read out via this RAM controller 88 to the RAM data bus, as indicated by circle 7. Combining other such elements, the pixel data indicated by the X, Y pixel identification is converted into character data compatible with the Super NES character format. As shown in circle 9, the RAM controller 88 generates different control signals related to the RAM of the game cartridge. Super NES, Maru Ou Jing H internal drawing hardware 52, and the data captured by the Maru Chan chip program, the common cassette RAM. The RAM controller 88 ensures that the appropriate address is sent to the RAM address bus at the appropriate time. The appropriate arbitration logic 310 controls, as shown in FIG. The RAM controller 88, including the multiplexer 304, is used for multiplexing input from the RAM data pin through the RAM D data bus and between the command bus and the command bus. The selection of the command bus or RAM data bus is pseudo-responsive to the signal received from the command decoder 60, and the appropriate RAM output is placed on the destination Z bus. The RAM controller 88 also includes a 16-bit data register 300, such as a security (please read the back-end notes first # 塡 write this page) if this paper is used in the standard 8 «家 楳 quasi-up 5)? 4 Specification (2) 0 father 297 male dragon) y 7 81. 4. 10,000 sheets (H) 214588 Λ 6 Β6 Printed by the Beigongxiao F Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Invention description (78) Store and write to RAM data It is under the control of the signal received from the instruction decoder 60 from the 16-bit X bus or the 16-bit Y bus. The data loaded into the data register 300 is divided into a low byte, and a tilt high byte, and meshed to the RAM data pin via the multiplexer 302, the multiplexer responds to receiving a value signal from the command decoder 60 , Output low or high byte. The RAM controller 88 also includes a 20-bit address multiplexer 308. The multiplexer 308 should respond to a control signal received from the arbitration circuit 310 to select a value address input, in which the arbitration circuit is derived from the code confirmation PACK, the data confirmation DACK, or the painting group confirmation PACK signal. Generated by circuit 310. The address signal from the Super NES address bus HA is received by the multiplexer 308 and is networked to the RAM address bus via the mega-signal timing signal generator 312, no matter when the owner of Mario Europea "; When the status bits are set to zero. The arbitration circuit 310 notifies the status of the owner of the chip RAM RAM, and the signal RAN of the arbitration circuit 310 is networked. The arbitration circuit also receives a RAM update control signal RFSH. The RAN and RFSH signals are '' or '' logic together to form a w pause signal as shown in Figure 10. The address multiplexer 308 also receives a tilt address input from the 16-bit multiplexer register 306. The multiplexer register 306 receives the contents of the Y bus, or the contents of the command bus, depending on a selection signal generated by the command decoder 60. The multiplexer 308 also receives the output of the data set register 314 as a tilt address input together with the contents of the program counter PC, as shown in FIG. The output of the screen day surface group register 316 is used to form the highest bit input to the drawing address of the multiplexer 308, and the input from the day road of FIG. 7 becomes the lower bit. Screen picture group register 316 and data group register 314, from the main data ^-(please read the precautions before writing this page) Standard (CNS) A 4 specifications (210X297 praise)

2I45BB Λ 6 Η 6 Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (79) The bus HD loads data and can be accessed by the main CPU. These registers, as shown in Figure 9, do not need to be implemented in the RAM controller 88 itself, but rather its content network is integrated into the RAM controller. The data set register 314 may be, for example, as described below in the ROM controller 104, and the screen scratchpad may, for example, be implemented in the graphics hardware 52. The multiplexer 308 input signal is selected as follows. If the code confirmation signal CACK is generated, the code group and the program counter PC are selected. If the data confirmation signal DACK is generated, then select the data group and add the multiplexer register input. If the Pkuto confirmation signal PACK appears, select the map address. Finally, if no CACK, DACK, or PACK appears, select the main (also, SNES) address input. The 20-bit address output of the multiplexer 308 is coupled to the chronograph signal generator 312, and these address signals are meshed with the RAM 6 and 8 at the appropriate time. The billion-volume timing signal generator 312 receives the round-off from the Gray counter of the arbitration block 310. The mega signal timing signal generator 312 decodes the output from the Gray counter and generates the output signal for the address RAMs 6 and 8 via the RAM address bus RAMA as shown in MN1. In another way, the timing signal generator 312 will generate control signals for accessing RAM 6, 8 including row address strobe RAS, column address strobe CAS, and write enable WE signal, as shown in Figure 1. . The semaphore timing signal generator 312 generates a slap DONE signal, like returning to the arbitration logic 310, to indicate the completion of the RAM cycle. The chronograph number generator 3 1 2 of Yiming also generates a data latch signal D A T L A T which latches data from the external RAM into the data latch of the RAM controller 88 (not shown). From RAM data and then, for example, RAMD-IN, Strontium to Ma via RAM data bus-This paper is used in the standard Η Η home standard (CNS) A 4 specifications (210X297 public goods) (please read the notes on the back first (Fill in this page again) Installation · Line · 214588 66 Printed by Employee Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs V. Description of Invention 6 Ο) Yeou Chip Circuit. The RAMA address signal output from the timing signal generator 312 is netted to any static RAM on the game cartridge. If the dynamic RAM is used on the playing machine cassette, the control signals CES, RAS and WE are generated. The structure of Emma Ou Jing H generates the static or dynamic RAM signals as appropriate, as indicated by the optional resistor settings described above. As shown in Xinjiang 9A, the exemplary timing signal generated by the timing signal generator 312 and other related signals are used. The data values and example addresses as described are for illustrative purposes only. Figure 8C shows the RAM DONE signal. The arbitration logic 310 is used in part to control the generation of RAM access signals at appropriate times. As shown in FIG. 10, the arbitration pass 310 receives the input of the billion-element access signal in response to the signal CACHE request CACHERQ, the data request DAT, RQ, and the graph request PLTRQ. Each of these input signals is temporarily stored in the latch 32, 327, 329. If the Imaho command is executed outside the range of RAM or ROM, the program starts with the reception of a fast request signal CACHERQ, which is used in the front and back of Figure 10 to confirm that the executing instruction does not leave the fast RAM range , And need to be executed outside the scope of RAM or ROM. Therefore, the CACHERQ signal is requested quickly, indicating that the instruction cannot be executed outside the flash memory 94. The data request signal DATARQ is generated as a result of the RAM access required to decode a command (for example, load byte, load byte command). In addition, the arbitration pass 310 receives a drawing request signal PLTRQ, and uses the drawing controller 200 to respond to the generator of the decoding of a drawing command. Arbitration logic 310 can only be enabled (as shown, using a status register The pause mode bit is in the state of w), which is being implemented by Dima Liou Jing Jing (please read the precautions before filling in this page). Install · Order 'Line · This paper standard uses the Chinese standard (CNS) ) A4 specifications (210X297 official history) 80 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 314 588 Λ (j _ Β 6 _____ Fifth, the description of the invention (8 1), and when the owner of the Maliou is set 〇 / In the quick request '35 # $ Seeking, and the painting garden request signal, after the latch 32, 327 and 329, CRQ, DRQ and PRQ signals are generated. 331, 333 and 335, from other gates @ 非 逆Output, receive some multiples, and establish the order of preference for these signals. In this regard, the fast request signal has the highest preference $, the data request the second highest preference, and the drawing requires the signal to have the lowest preference. The fast request signal specification Become the highest priority because it instructs Qiyuan to execute fast Shorthand the instruction outside the range of 100 million and it painfully accesses this instruction from RAM. Operate the brake circuit 3 3 3 and 3 3 5 to ensure that a lower pros and cons is not required. Latches 3 39 and 341 are not set, if a higher pros and cons It is required to set its other latch. Only when the system is not in the pause mode 1, the latch 337, 339, 341 can be set, because the temporary chess signal turns to each gate 331, 333, 335. The chess signal is suspended It will be set to a low logic level state, when the Malyu owner, also has free access to the RAM. The chieftain confirms that the latches 337, 339 and 341 are already in * 1 " Middle), if the pause is set to * 丨 ", the latches 337, 339, and 341 cannot be set. Gates 33, 333, and 335 create RAM access first. If the latch 337 setting is requested quickly, data confirmation will not be set Latch 3 3 9. If the quick or data request latch setting, it is not set. Confirm the latch 3 4 1. The latch 337 uses the quick request signal setting, immediately generates a quick 11 recognition signal CACK, and immediately uses as shown in Figure 10 Logic circuit builds available fast 94 (or RAM) . Generate data confirmation multiple DACK and drawing request confirmation signal PACK to confirm the data request and drawing request signal. If the logic circuit shown in the figure determines that the RAM is not busy. (Please read the notes on the back * fill in this page) Packed. This paper is used in the “Bai Family” quasi (CNS) A 4 specifications (210 father, 297 male) 81 214588 Λ 6 Η 6 Printed by the Beigongxiaot Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of invention (β 2) The non-inverted outputs of the latches 3 3 7, 3 3 9 and 3 4 1 are meshed to the gate circuit 343, like resetting the Gray counter 3 45 through the NOR gate 344 in sequence, generating timing signals for RAM access . Professionals in the industry know that Gray counters are counters that change only one output bit at a time, and can be conveniently used to control RAM access time. The completion signal generated by the timing signal generator 312 is received by the NOR gate 344, and the latches 337, 339, 341. The completion signal indicates completion of a RAM session. When the completion signal is generated, the arbitration logic 310 is triggered to remove the appropriate latch to remove the requirement of the latch. The completion signal is also networked to the original circuit, that is, the fast controller 68 or the drawing controller 52, indicating that the RAM access has been completed. According to another alternative embodiment of the invention. The Maliou chip uses a dual clock signal system. Therefore, the Maliou chip processor does not need to be driven by the same clock signal as the above RAM controller circuit. The RAM controller 88 may, for example, be driven by a 21 MHz clock signal received from the Super NES, and use other variable frequency clock signals to drive the Majestic OH processor. In this way, the Maliu chip processor will not be limited to the operation of the 21 MHz clock signal rate. According to the Marauer chip of this embodiment, a non-synchronized mechanical control circuit may be used, as shown in FIG. 11, for performing a clock resynchronization dual clock signal interface function. The circuit in Figure 11 is used in the interface with the Majino chip processor, if it is implemented with a clock signal system that is different from the operation of the memory controller. As shown in Figure 11, the resynchronization circuit receives an input clock signal. The paper standard uses the Chinese Standard (CNS) A4 specification (210X297) 8 2 (Please read the precautions on the back before filling this page ) Binding · Binding _ Line. 214588 λγ, ___ Η 6_ V. Description of the Invention 3) DIN, this signal is not synchronized with the tilt signal CK. The resynchronization circuit generates a bow signal from DIN. This IDN is synchronized with CK, regardless of whether the DIN frequency is higher or lower than the clock signal rate CK. In the embodiment shown in FIG. 12, in response to the signal DIN, the circuit shown in FIG. 11 is shown. Transition from state 010, 110, 100, 101, 111 and return to the initial state 010. The _11 resynchronization circuit is used to receive dual clock signals at any interface, such as ROM controller 104 and RAM controller 88. As shown in Figure 11, the circuit is embarrassed by the input signal DIN, so swap from space or reset state "010" to form the state a 110 ", as the latch A is set by using F. Just resynchronize the clock signal C1 (slow, maybe it is already true, then use the gate E to reset the latch B to form the state w 1 0 0 〃. When the clock signal goes high again, set the latch C to use the gate A to form the state> 1 0 1 〃. The Ministry of Economic Affairs, Central Bureau of Standardization, Beigong Xiaozhi cooperated to print the latch C from the circuit, as shown in Q of Figure 11. When the input signal goes low again, latch B is again set to form the state using gate C ~ ' 1 1 1 〃 After reaching the state "111", the clock signal CK goes low again, and then the gate G is used to reset the latch A to form the state 011. After that, the clock signal CK goes high again, and the gate is used to reset the latch C , Return to the idle state of the state machine. Circle 13 is a further detailed diagram of the ROM controller 104 of FIG. 4B. The ROM controller 104 includes a fast manned device 400, which controls the manned storage in the ROM 10 and the cassette RAM, Currently executing program instructions into the Maruio chip fast RAM94. Manned to fast RAM94 instructions are grouped in 16-byte groups. When a slap jump instruction is encountered, in the middle of the 16-byte segment, a full 16-bit The tuple section needs to be filled with bent ore, Before. Fast loading circuit 81. 6. 10,000 sheets (H) The original size of the paper is 5 Chinese standard (CNS) T4 specifications (210x297 g: ¢) 83 Λ 6 Η 6 214588 V. Description of the invention (84) 400 , Including a 2-bit state machine, like Xin Ying should decode the jump instruction, so ensure that the remaining bytes of the 16-byte fast segment are loaded into the fast RAM94. The first state of the fast loading logic state machine is unheard of Status, it will be true if the program is executed outside the scope of the fast memory, or if the program data has been loaded into the fast memory. The second status indicates that it will occur simultaneously from the cartridge ROM or RAM , Load the fast memory and execute the program. Use the decoding of the jump instruction to trigger the third state, which is still valid until all the bytes of the 16-byte fast segment have been loaded. The fourth state encounters when executed During a jump, the jump to the inaccurate phase is at the address of a lanthanum fast 16-byte boundary. In this case, the fast memory "enters, from the beginning of the boundary, to the part of the program jump 16 The relevant address of the bit segment. Fast as shown in circle 4B The controller 68 generates a fast signal and inputs it to the fast loader 400. It also indicates that the requested instruction does not appear in the fast RAM 94. Therefore, the instruction needs to be fetched from the ROM. The code group signal identification will be accessed The highest three bits of the address. And indicates whether the program ROM or RAH will be accessed. The fast loader 400 also includes a counter (not shown), which maintains the lowest bit corresponding to the program counter PC during program execution The count of the element. This counter is loaded into the PC input via the fast loader 400. The fast load circuit 400 of the ROC controller 104 also receives the wait and execution control signal. It instructs the Maliou processor to remain in the waiting state for any reason, and the Maliou chip is in the "executing" mode. Under this environment, the fast loading circuit 400 generates a code grabbing control multiple, as shown in FIG. 13 meshed to the H0R gate 408, and then coupled to the clear input of the ROM timing counter 406. When the fast loading circuit 40 0 generates a code grab signal, (please read the precautions on the back before writing this page). Install and line. This paper is printed by the Cooperative Society of the Central Standards Bureau of the Ministry of Economic Affairs. China National Standards (CNS) A 4 specifications (210X297) 84 214538 Λ β Π 6 Printed by the KX Engineering Consumer Price Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ V. Description of Invention 8 (5) in the ROM controller 104 Logic circuit, start a shovel code capture that is higher than the data capture pros and cons, at this time and the code capture start precedes the data capture Ί '!. The arbitration circuit cooperates with the priority operation, as shown in Fig. Ο, and may be used to enable the generated signal, which is given a higher priority than the data grabber. When the clear signal is removed from the ROM timing counter 406, a head counting period is started. The ROM timing counter 406 is used to generate the ROMDYDY timing signal, which pseudo-indicates that ROM data is available at the ROM data pin, and its signal is output from the gate circuit 410. This ROM data preparation signal R0MRDY is pinned to the resynchronization circuit 402, which may, for example, include the resynchronization circuit shown in FIG. After the processor clock signal is synchronized, a signal ROM DCK is generated to reset the latch 404, and a data capture signal is generated to indicate a value data capture, which uses the trigger triggered by the access of the register R14, thus obtaining EN- R14 signal. When the ROM timing counter 406 reaches a predetermined count, a data capture signal is generated to ensure that the data is available at the ROM data pin. The ROM controller shown in Group 13 generates an ROM address output from the multiplexer 414, and selects address information from one of the following inputs. The code register 412 is loaded from the Super NES data bus to define the ROM program group that will be executed by the Malyo program code. The program group register 42 provides 8 bits of a 23-bit ROM address to the multiplexer 414. The lower bits of the ROM address are pseudo-obtained from the contents of the program counter PC. When data is written to the fast RAM, the fast load 400 is used to generate the lower 4 bits from the fast load signal. Regardless of when the scratchpad R14 is accessed, an additional multiplexer 414 address input is generated from the content of the Malacca general scratchpad R14. (Please read the back and the precautions in the first place. #The script book is used in the paper standard. A national standard (CNS) 4 standard (210x297 mm) 81. 6.〗 0,000 sheets (H) 85 A 6 Β6 5 、 Instructions for invention (8) 6 (Please read the precautions on the back before filling in this page) The data capture latch 404 obtained by the access of the register R14 generates a data capture signal, which is used for a control input to make The multiplexer 414 selects its R14 round-robin. (And loads the contents of the data group register 416 from the super data bus HD). The data group register 416, which contains the higher bits of the data group, you are related to A slap R14 capture operation. In addition, the data capture multiple I »is latched to the latch 4 0 8, and the count of the initial R 0 M timing counter 406 is sequentially generated through the gate 410 to generate a ROM preparation signal R0MRDY. When the R0MRDY signal, the data from the ROM data bus ROM D [7… 0] is available. The address multiplexer 414 also receives a ROM address from the super NES address bus HA. The super NES bit will be selected The address bus depends on the state of the signal * ROM ", and is integrated into the multiplexer 414 control wheel. W ROM 〃 control signal , Instructs the Maru ROM controller, the Super NES has the control of the ROM address bus. After decoding a jump-and-kick instruction, the address multiplexer 414 feeds the program counter, plus the counter generated in the fast loader 400 The lower 4 bits of the number. While allowing the fast segment to be loaded into the remaining 16 bytes, this manned data is printed before being decoded by the Employee Consumer Cooperative of the Ministry of Economic Affairs Central Standards Bureau. , From R0H data R 0 MD to Mario ’s destination bus Z. The data capture signal is generated by the latch 404 and the R0MRDY signal generated by the count 406 when using the ROM. The pot is closed to the gate 418 to enable the ROM buffer 420 Loading. From the ROM data bus R0MD [7 ··· 0], ROM data is loaded into the ROM buffer 4 2 0. / The multiplexer 422 plaque decodes the command code to select an input. 86 The size of this paper is based on China National Sample (CNS) Grade 4 (210X297). 2l ^ 588 Λ 6 It 6 Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of Invention i) 87%. (For example, GET B uses the access to the scratchpad R14 to trigger automatic data capture). If the code grabbing operation is decoded, the ROM controller 104 will mesh the command to the command bus of the Mario chip as shown in FIG. 15A. If a MGET B command is decoded, the bytes stored in the register 402 are placed on the Z bus. Some GET B command operations include data on the X bus, like input to the multiplexer 422 via phase matching, as shown in FIG. 13. Then, the data that fits into the destination Z bus is loaded into one of the Malyu general registers 76. The fast controller as shown in circle 14 is described in further detail. The quick controller 68 includes an identification latch 506. The flag 506 includes, for example, 64 to remove the latch to indicate whether the instruction is stored in the flash RAM 94 (when implemented in the flash controller, for illustration purposes only). The 64 flags per mark of the latch 506 are relative to the 16-bit information stored in the flash RAM 94. The instructions are loaded with fast RAM94, while the instructions are executed from R0H or RAM. When a jump instruction is executed, as described above, the RAM 94 carries the remaining bytes of the 16-byte segment via the fast manned device 400, which is related to the ROH controller 104 shown in FIG. Until these remaining bytes are loaded, when loading the flag flag latch 506, it cannot flag the entire 16-byte segment. Describing the gate circuit 510, when the program counter counts from 0 to 15, the 14-bit subtractor 502 outputs a signal outside the range (which is like an inversion), and when the ROM controller outputs its ROM data preparation signal R0MRDY When a byte is ready to be output), the gate circuit 510 sets the identification latch 506, and the address of its location uses the demultiplexer 504. / (Please read the precautions to be filled out on this page by Sun Qiuqian first) This paper is used in the standard β B Family Standard (CNS) TM specification (210X297) * 81. 7. 20,000 sheets (II) 87 Λ 6 II 6 V. Description of the Invention 8 Orders) When decoding a fast dump command, an overseas Chinese control letter is generated at the bus 501 (please read the note on the back of Ercheng to write this page) number to instruct to remember Delu 94 from the fast RAM There are post-execution instructions. The control signal on the bus 501 is erbium coupled to the fast base register 500 to load input, and 13 higher bits of the program counter PC are loaded into the fast base register 500. At the same time, as shown in FIG. 14, the door latch 506 is cleared. The output of the fast * bottom register 500 and the higher bits of the program counter (for example, bits 3-15) are combined to the subtractor 502 to determine whether to input from the address of the program counter PC, within the fast RAM94 range . The output of the subtractor 502, for example, its lower 6 bits, such as the higher bit of the fast RAM address, these three lower address bits are combined from the program counter PC. The self-subtractor 502 generates a out-of-range signal from a binary carry signal, and generates an out-of-range signal 0 / RANGE, which is inverted. When the signal outside the inversion range is high, the setting of one of the lanthanum latches of the latch array 506 is started. The latch setting will depend on the output of the fast address from the subtractor 502 via the demultiplexer 504, and will be compared to a 16-byte segment in the fast PAM94 to indicate that an instruction is to be stored in the fast memory. The blue is used to output the fast RAM address. The identification latch 506 output is outputted to the tilt multiplexer 512, and one of the latch signals is identified by the meshing 64. The Central Ministry of Economic Affairs Μ 工 消 # Cooperative is printed to N 0 R gate 5 1 4 based on the multiplexer Select the input to output a latch signal relative to one of the 64 outputs selected from DEMUX504. Others require an external fetch, because the fast RAM 94 cannot find the desired instruction. FIG. 15A is a block diagram of the ALU controller / instruction decoder 606 in FIG. 4A. As shown in FIG. 15, the ALU controller / instruction decoder 60 receives instructions from the fast RAM 94, the ROM controller 104, and the RAM controller 88. This Maliou chip assembly is not part of the ALU / instruction decoder 60, but the circle 15 shows only that the paper fully uses the Chinese National Standard (CNS) TM specification (210X2 Machi public) gg 81. 7. 20,000 ^ (11) Μ 2145¾8 5. The purpose of the invention is 9 (). (Please read the precautions and fill in this page first) The multiplexer 525 chooses one command to cycle through the fast RAM94, ROM controller 104, or RAM controller 88. And lose this to follow the instructions to the parallel pipe latch 527. The multiplexer 525 is used to select between RAM or ROM based instructions, depending on the predetermined bit shape of the program code register, also bit 4 ,. Therefore, the ROM or RAM commands will be decoded according to the address information loaded into the program code register. S — the optional multiplexer 525 selects a tilt command from the fast RAM 94, depending on the state of the control letter CACHE CTC of one hall of the fast controller 68, indicating that a tilt command within the range of the fast RAM 94 will be executed, and Set an appropriate inclination miscellaneous element and connect it to the fast controller 68. Parallel pipe latch 527, receiving a tooth 8-bit command from the multiplexer 525, when using a dysprosium program counter to enable the letter PCEN.IL. IH, if a value command is being fetched from R0H (or RAM), then The enable signal is generated by the ROM controller 104 (or the RAM controller 88). Because fetching a backup command from RAM or ROM takes more than a processing time, use R0M or RAM to control the program counters generated by 104, 88 to enable multiple PCEN to decode the command decoding operation. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. On the other hand, if the executed instruction is outside the fast RAM94 fan park, all time program counters are enabled. »PgEN is active and executes the instruction at the full processor clock signal . Because the access time is slower than the access time of fast RAM or cassette RAM. The frequency interval of the PCEN multiples generated by BB for accessing the ROM is lower than the relevant fast RAM or dynamic or static RAM decoding enable signal. The instructions stored when the parallel pipeline latch 527 is temporarily stored are rounded to λΛΛΛ / ΙϋΛ tee 3fi # ^ (CNS) T4 «ffi (21〇x297 ^ *) 8 9 81. 7. 20,000 sheets (丨 丨)

2145BB Λ 6 η 6 Printed by the Ministry of Economic Affairs, Central Bureau of Industry and Commerce, Beigong Consumer Cooperative V. Description of invention 9 (°) Futong command decoding circuit, represented by gate circuits 537, 539 and 541, to generate operation code 1 , 2 ... N signal indication. The 5 2 7 instruction loaded into the parallel pipe latch is also integrated into the look-ahead logic 551. Looking forward (Look-ahead) logic 551 provides a pre-decode instruction of the operation code, which is regarded as the Malioujing H register block 76, and the appropriate register is selected. Therefore, to optimize the execution speed before decoding the lotus code, quickly determine the register to be accessed, so as to enable high-speed access to the required data. Looking ahead at the logic 551, it corresponds to the instruction operation code bit and decodes the control flag with various different programs. The instruction decoding circuit 60 includes program control flag detector logic 543, which responds to the previously decoded opcode to generate ACT1 and AOT2 signals, indicating that the relevant pre-instructions have been decoded as described above. The related ACT1 PRE signal is also generated using the sassafras detector logic 543 as described below. In addition, IL and IH signals are generated to indicate the immediate data required for the decoded instruction. (Where L and Η indicate low byte and high byte). The ΙΗ and IL flags pre-exclude this immediate data open command and are decoded into codes. Therefore, I L (ΤΊΓ) and I Η (ΤΤΓ) are not required to enable the parallel pipe latch 5 2 7. As mentioned before, ACT1 and ACT2 are modified after picking to generate the operation code, and input to the decoding logic 5 3 7, 5 3 9, 5 4 1, etc. For example, the gate circuit 541 modifies the round lot code based on these signals previously discussed. Looking forward, the logic 551 generates the register selection. This signal is based on the pre-decoded lotus code and the signal generated when the previous operation was decoded (e.g., the preamble ACT1 or ACT2). For example, as shown in the program control flag detection logic 543, if the decoding logic 545 is used to decode the ACT1 signal, a paper-based ft scale is used. The "Home" standard (CNS) T4 specification (210X297 public; ¢) 81.7 . 20,000 sheets (II) (please read the precautions before writing this page) 21.4588 Μ Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives. 5. Invention Instructions? 1) ACTl PRE signal, which uses the program to control the flag The signal output of the standard detector series 5 43 is output, and the signals are sequentially connected to the forward looking series 531 via the OR gate 549 network. The ACT1 PRE signal also sets the ACT1 latch 547. The OR gate 549 also outputs the ACT1 signal from the latch 547, and the ACT1 signal is meshed, and the ACT1 multiple number is combined to the decoding logic 537, 539, 541, etc. / Fig. 15 schematically represents a look forward to the album, showing how to generate 4-value register selection control bits XSELO, XSEL1, XSEL2, and XSEL3. Then these 4 control bits are coupled to the multiplexers 6 2 0 and 6 2 2, which are connected to the control logic 76 of the 17th register, select the content of one of the 16th register, and Round-trip to X bus is used by an executing instruction. Therefore, before being loaded into the parallel pipeline 527, the one-tilt instruction erbium is combined with the forward-looking logic element 529, which generates a one-tilt register to fill the select bit XSEL- Dong 0. In sequence, the latch is in the latch 535 , And then as a signal XSEL0 round out £ .1. The latch 535 is enabled using the program counter signal PCEN. Similarly, the Xuanlu 531 generates XSEL-U1, which is latched in the latch 533, and output as the signal XSEL1. The ALT1 PRE multiples are combined into various decode logic circuits 529, 531, etc. Looking ahead at logic 551 here. And it is used to define the appropriate register selected by the register control logic 76. For example, as shown in the forward-looking circuit 551, the ACT1 PRE signal is coupled to one of the logic circuit 531 signals, generates XSEL-U1, is latched on the latch 553, and sequentially outputs the signal XSEL1. The example timing signal shown in FIG. 15B is used to prove the operation of the forward looking 551. In FIG. 15B, a clock signal CK and a dysprosium example instruction code are used for fast RAM data access. The timing signal shown also indicates when the parallel pipeline latch 527 is loaded, when the instruction decoding operation is performed. When produced (please read the precautions before filling in this page) The paper size is far away from the home use «Rate (CNS) T4 specification (210 X 297 gm":> gj 81 · 7. 20,000 sheets (||) 214588

66 Du Printed by the Consumer Standards Cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs V. Description of the Invention (92) When the register selection signal is generated, and the information from the register is loaded on the Z bus. As shown in group 15B, the fast RAM data operation code lotus code 1) becomes effective, like at some point after the rising edge of the clock signal pulse CK. The opcode is stored in the parallel pipe latch 527 until, for example, the falling edge of the second clock signal pulse, at which time opcode 2 is loaded into the latch 527. The instruction decoder 60 starts to decode the instruction with the phase 1 of the lotus code, and it just receives the round from the latch 227, the time of which is indicated by circle 18. The result of the instruction decoding will be as described above, and the control signal will be appropriately meshed to the Malio components, such as ALU50, fast controller 68, and picture hardware 52, etc. Looking ahead at the circuit 551 as shown in FIG. 15, at the time point before the decoding of the operation code 52, this temporary register selection decoding process is started by generating a healthy signal XSEL-U. Before being latched to the door latch 535, the XSEL-ϋΟ signal represents the output of the decode logic 529. Use the latch 535 to output the XSEL-0 signal. At this time, the required data can be accessed as early as possible during the instruction execution cycle, and it can be quickly integrated into the sleep bus. As shown in plaque 16, a part of the register control logic 78 is used to generate Y and Z bus phase register selection signals. The multiplexer 604 selects the value written from the Z bus to the 16-value register. The multiplexer 606 selects the buffer to feed the Y bus. Multiplexers 604 and 606 receive input from 4-bit registers 600 and 602. The registers 600 and 602 are used to implement the aforementioned w T0 〃 and * FROM " pre-commands. Use the "T0" and "FROM" pre-decoding enable registers 60 0 and 602 to operate the lower bits of the network instruction bus to the register 600 and (please read the opposite first Matters needing attention # 塡 write this page), Γ "

T In the selection of the size of this paper, the standard of β-stricken home sample (CNS) A 4 specifications (210X297 g *) 92 .7. 20,000 sheets (Η) 21.4538 Λ 6 Π 6 Central Standards Bureau of the Ministry of Economy Μ 工 消 # Cooperation Du Yin Refer to 3) 602 for the description of the invention. The registers 600 and 602 are erased in response to a command, such as the reset control flag described above. In addition, multiplexers 604 and 606 receive input from different registers in register block 76. Multiplexers 604, 606 receive input from the lower bits of the command bus to implement the lower 4 bits of the command and define the destination or source register of the command. In addition, the predetermined lower bit from the super NES address bus is incorporated into multiplexers 604 and 606 to provide super HES access to this register group. The multiplexers 6 0 4 and 6 06 select the register feed Z and Y bus. Circle 17 shows the register block 76, and the additional register selection control logic implemented in the register control logic 78 in FIG. 4B. Set the FR0MX register 618, use a decoded FR0MSET signal generated by the FROM instruction. After receiving the FRO MSET signal, the contents of the Y bus are loaded into the register 618. The data loaded in the register 618 becomes the data used for the execution of the post-winding instruction. The contents of the temporary register 618 are used for one of the synthesis rounds to the multiplexer 622. The multiplexer 622 also receives the contents of the R0 register (which uses a preset register) as one of its inputs. The other input of the multiplexer 622 is the input of the multiplexer 620. The multiplexer 620 receives the content input of the program counter (that is, the register R15), and then inputs it from the register used to execute the MERGE instruction, and the register R1 (for example, used to execute this drawing instruction). The multiplexer 620 selects one of the inputs and generates the state of the XSEL2 and XSEL3 bits based on using the look-ahead transition 551 as shown in Fig. 15A. Multiplexer 622—increasing the input and meshing the contents of the Y bus to place the same data on the X bus, such as on the Y bus. As previously mentioned, the paper size is used in the beta national standard (CNS) A 4 specifications (210X297; ¢) 9 3 81. 7. 20,000 sheets (II) (please read the precautions before writing this page ) 214588 λ 6 __Η6 V. Invention description? 4) As mentioned, the input to the multiplexer 622S is tilted, like the output of the FROM X register 618 described above. The output of the multiplexer 622 is selected, based on the state of the generated XSEL0 and XSEL1 bits, and is coupled to the X bus. In the above description, the special purpose functions of many temporary registers ~ R15 will not be repeated here. The output of the register ~ R3 is broadcast to the multiplexer 608, the output of the register R4 ~ R7 is combined to the multiplexer 610, the output of the registers R8, R11 is combined to the multiplexer 612, temporary storage The output networks of the devices R12 ~ R15 are connected to the multiplexer 614. To one of the multiplexers 608, 610, 612, and 614, one of the different inputs, using YSEL1 and YSEL0 bit selection, as shown by _16 from the multiplexer 606 output. The output from the multiplexers 608, 610, 612 and 614 is input to the multiplexer 616 in sequence. The selection to one of the multiplexers 616-4 is based on the state output from the YSEL2 and YSEL3 bits of the multiplexer 606 as shown in FIG. The output of the multiplexer 616 is coupled to the buffer register 617, and its output is sequentially coupled to the Y bus. Printed by the 3rd Industrial and Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Reference registers R0 to R15 are input. Each register has an enable input. It is selected using the ZSEL bits 0 to 3 generated as shown in FIG. Each bow register also has an I clock signal input CK and a data input Data-in. After proper buffering, data is received from the Z bus. The temporary storage 124 is used for various multiplication operations. It also includes the rounding of disabling low and disabling high bits, and the input of disabling low and enabling high bits. Temporary register R15, program counter PC, receive a value signal CCHCD from the fast loader 400 of the ROM controller in U13, prohibit a slap skip operation until the current 16-byte fast segment is loaded into the fast RAM . In addition, the program counter receives an indefinite signal from the command decoder, which is 81. 7. 20,000 sheets (II) (please read the precautions to be filled out by Sun to fill in this page first). This paper »簋 度 遑 用 中 《B 家The standard (CNS) A 4 specifications (210x297 g; 94 Λ 6 η 6 V. Invention description gas 5) LOOPEN, the command should generate a jump operation and enable the PC to load the contents of the register R13. In addition, the register R15 receives a power-on reset signal RESET, and when a loop command is executed, a PN input causes the program counter to load the contents of the register R13. As described above, the graphics co-processor of the present invention is combined with the main TV player system to facilitate the use of different special effects, including, for example, the rotation, enlargement, and / or reduction of polygon-based objects. The example of Fig. 18 is a flow chart of the Maliou chip program, which is used to draw a slap trapezoid, describing how to program the Maliou chip to produce a part of the polygonal base sample that is displayed. The Ma Jingou program that generates this polygonal target will be explained in detail together with how Ma Li hardware executes this program as follows. Referring first to the high level of the flowchart shown in FIG. 18, initially, some of the registers in register blocks R1 to R15 are related to variables that generate trapezoids. (That is, the register R1 stores the pixel X position, the register R2 stores the pixel Y position line, and the register R7 stores the trapezoidal height, etc.). Thereafter, as indicated by block 650, a loop counter is set and the starting pixel value is calculated. Printed by the Zhengong Consumer Cooperative of the Bureau of Standards and Economics of the Ministry of Economic Affairs (please read the back-end notes #fill this page), as indicated by box 652, do a value check to determine the height of one of the trapezoidal horizontal lines. If the result of subtracting the end point of the line from the starting point of the line is a negative value (-VE), the routine jumps to block 660. If the line start point minus the line end point is a positive inclination value, and the length of the line indicates that the length of the line does not exceed, then the loop counter (654) is decremented, and a one-turn circle pixel instruction is executed to obtain an appropriate pixel picture. As shown in block 6 58, a value check is performed to determine whether the content of the loop counter is zero. If the Xunchen counter is not zero, then execute a value skipping paper »Standard Universal Use BH home« Bi (CNS) A 4 specifications (210X297; it) 9 5 81. 7. 20,000i | t (II) ^- -V. Description of Invention A6) Return to block 654 to decrease the cycle counter (654) and draw another pixel (656). If the Xunchen counter is equal to zero, the X-shaped sample of the left polygonal side and the X-shaped polygon of the right polygonal side are updated (660). Later, the Y height of the trapezoidal trapezoid (662) will be eliminated. And if the result is not zero, it will jump back to block 650 (664) and execute the routine, and increase the Y coordinate, and move to the next scan line (665). If the height is equal to zero, this routine will be fully executed and this trapezoid (666) will be completed. To illustrate the use of the Maruio chip command to generate thumbnails for drawing a trapezoidal example program, an embodiment like the flowchart of FIG. 18 will be described below. : Draw trapezoidal loop r X = 1; draw X position rx = 2; draw Y position rxl = 3; top left X position rxlinc = 4; top left X position increases rx2 = 5; top right X position increases Central Bureau of Economic Affairs Printed by the employee consumer cooperative (please read the back-to-back notes #fill this page) r X 2 inc = 6; increase rdy = 7 at the top right x position; trapezoidal y height r 1 en = 12; Xunchen count, hline height γΙοορ = 13; Xunchen logo hi ines iwt rloop, hline2; set the start of h 1 ine cycle hi ine 1 paper Λ scale, use the "Guo" standard (CNS) Ή specification (2 丨 0X297 public; it) 96 81 7. 20,000¾ (I!) Λ 6 Η 6 Printed by the Beigongxiao F Cooperative of the Central Bureau of Standards of the Ministry of Economy V. Description of Invention) nfr ο β r χ 1 Luot ο r χ η hib fro »xr 2 ihib in tor 1 en hire subrx ίο bmih 1 ines 3 η η oprlncr 1 en hi ines 2 m 1 ο op «plot hi ines 3 pass withrx 1 aiadd rxlinc awithrx 2 baddrx 2 incadexrdy; x = (rxl) > > 8» bne hlinesl mine ry; length, rlen = (rx2 > > 8)-(rxl > >8); result r 1 e n < 0 then jump h 1 ine; often draw a prostrate pixel: draw h 1 ine; rxl + = rxl inc; rx2 + = rx2inc; rdy-= 1; repeat rdy times; and complete the next attempt to prove that Maluou is hard How to execute the one-incline program in the body operation, the following describes the program generated by the above trapezoid. Before executing the trapezoidal generation program, the main computer's "Paper" application "National« Standard (CNS) A 4 specifications (210X297 public address) 81. 7. 20,000 sheets (II) (please read the precautions before reading (Fill in this page) -Installed-97 / 5¾¾ Π 6 _ Δ ^ _____---------- V. Description of invention times 8) (Please read the notes on the contrary to write this page by Sun Cheng) , Super HES, write directly to the code group register, and enter the screen picture base register, as explained above in the flow chart of Figure 5. In addition, the Super NES writes the XEQ address of the lower byte to a healthy local register of the ROM controller 104 to decode from the Super NES address bus HA. Then the Super NES writes the high-order group to the ROM controller 104, combines the contents of the local register, and integrates it to the Z bus. After that, enable the register R15 which is used as the Maliou chip program counter. After detecting the above-mentioned super HES write operation to the back edge of the ROM controller 104, the Mario w G0〃 flag is set. If the program counter decrements the fast base register, which is greater than the size of the fast memory, or if the fast flag is double the program counter, subtract the fast base register divided by 16, equal to zero, the program counter content is sent to R0M10 And the ROM timing counter is started (block 406 in FIG. 13). The variable used for the trapezoidal cycle program before executing the trapezoidal subprogram, which is related to the super mario register, as shown at the beginning of the ladder program list, for example, v rx 〃 是 * 耋The position of Figure X is related to the register R1, and the variable w rloop " phase is relative to the register R13. Printed by the Employee Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs

After specifying these registers, execute the ladder program as follows. When the ROM timing counter 406 of the ROM controller 104 reaches the count of 5 (approximately 200 withdrawal seconds / hour, the first instruction w IWT rloop, hline, 2〃 will be executed, and the ROM data bus latch will enter Figure 4A The parallel pipeline register 62 is shown. At the same time, the data is written to the fast RAM 94. When the instruction IWT rloop, h 1 ines 〃 is executed, the program counter is increased. The w IC " and w I Μ " flag settings are set to indicate The second byte of the back stream of the instruction stream is an immediate data. When the paper size of the ROM is used, the "B Family Standard (CNS) A 4 specification (210x297 g; ¢) 98 81. 7. 20,000 ^ (11) Λ 6 B6 Ministry of Economic Affairs, Central Bureau of Biography CS: Printed by the Industrial and Consumer Cooperatives V. Description of Invention 9 Township) Timing counter 406 to 5 5, immediate data (low byte) is written to the fast RAH94, and kept in the ROM controller 104 Temporary register. The ROM capture mechanism is repeated, and the high-order byte of the immediate data is combined with the low-order byte, and goes along the way to the Z bus. The enable register R13 is used to store the contents of the Z bus, and the counter to be set is to be set. From this sticky of the routine, each instruction is fetched from the memory until a loop instruction is encountered. When the FROM RX1 instruction is executed, the lowest 4 bits of the instruction code are loaded into the 4-bit a FROM Y 〃 register of the scratchpad controller (refer to Figure 16). In addition, the data from RX1 (register R3) is enabled to enter Y bus, and the 16-bit * FROM X " register 618 remains. When executing the * TO RX " instruction, the lowest 4 bits of the instruction code are loaded into the 4-bit " Enable Z " register 600 of the scratchpad controller (refer to FIG. 16). Execute the "HIB" instruction and use the 16-bit content of the setting FROM FROM X "to enter the X bus. ALU places the highest byte of the X bus, enters the lower byte of the Z bus, and sets the highest byte of the Z bus to zero. The X position of this moving part, and leaving the starting point, is used for the first horizontal line in the register (register R1). When executing the '' FROM RX2 " instruction, it is similar to the above operation of executing a FROM RX1〃 instruction. The operation caused by the " HIB " instruction, (similar to the above), relative to the uppermost right X block of the trapezoid, leaving the end of the first horizontal line in the register R0 (this preset register operates like a stack Integrator). When executing the w RLEN " instruction and the ‘SUB RX " instruction, the end of the line that is subtracted from the beginning RLEN (R12) = Ro-Rx. If there is a negative result, set a plus or minus flag to indicate a negative error condition. (Please read the precautionary notes and fill in this I first) Binding · Binding · Thread · The size of the paper used in the BiTiMS standard (〇Νδ) Ή specifications (210X297 ft) 〇〇8 丨 .7. 20,000 sheets (II ) Λ 6 Η 6 Printed by the Consumer Labor Cooperative of the National Bureau of Standards of the Ministry of Economic Affairs V. Invention Statement》 Ιι〇 < Ρ) '' BMI HLLNES3 " instruction is a 2-byte instruction, if the sign is set , Then the first byte sets a bow flag. If the condition flag is set, the second byte is the skip offset. (Where R15 is equal to R15 plus this instruction). If not, R15 remains unchanged and the normal program is executed. Execute the INC RLEN " instruction and increase the line length register by 1 to ensure that at least one pixel is drawn. The LOOP " instruction operation makes R12 = R12-1 calculation. If R12 is not zero, R15 (program counter) is loaded with the contents of R13, so there is a value jump. If the program is within the range of the fast RAM 94 at this point, the fast manned circuit 400 will detect the jump, and load the execution succession as it did into the fast RAM 94. When it is finished, the program counter is loaded with the new value, and the next instruction is fetched from the fast RAM 94. To execute, the PLOT instruction, the loop / drawing instruction will form a horizontal level day chart algorithm. a PLOT 〃 command will use Rl, R2 (as X and Y blocks) to set the screen pixel address to the color setting of the color register " 54 as shown in FIG. 4A. The map hardware 52 is used to calculate the character address including pixels. The new pixel data remains in the character line buffer (color matrix) until the Maliop chip moves into the drawing at different character positions. When all the color information is copied to the second layer of the double buffer machine in the color matrix, the information is written to the external RAM. Execute the WITH RX1 " and * ADD RX1 LNC " instructions to update the left X-frame of the trapezoid. Similarly, w WITH RX2 " AND, ADD RX2 INC 〃 image operation updates the right side of the trapezoid. , 'DEC RDY〃, w BEN, the paper size is used in the B country «quasi (CNS)> P4 specifications (210X297 public; ft) 1 〇〇81. 7. 20,000¾ (I!) (Please read the back And the matters needing attention will be written on this page) Λ 6 Π 6 214588 V. Description of Invention ι (〇1)

Hlinesl, and INC RY " instruction move to the next value γ position (next tooth scanning line) until the trapezoid is completed. The following program list demonstrates how to program the 8-bit X, Υ, and Z points of the Martial Array Rotating Array. This routine is like a program drawing co-processor according to an embodiment of the present invention. The following is a list of the routines. From the turn list :; rotate an 8-bit array of X, Υ, and Z points; use a rotation matrix of the register; r «atl21 1, rmat2 1 1 3, rmat 2 3 22, rmat 3 2 3 1, rnat0033 ; Matrix elements are 8-bit with positive and negative signs; for example, 1 2 7 = 1 2 7/1 28 = approximately 1; -128 = -128 / 128 = -1; they are closely stored as each register 28-bit elements (please read the back and notes # fill in this page) printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs r ζ rt rnatl211 raat2113 rnat2322 rmat3231 rmat0033 routyptr 10; temp; matrix elements 1 1 and 1 2 ; Matrix elements 1 3 and 2 1; Matrix elements 22 and 23: Matrix elements 31 and 32; Matrix elements 33; Pt "The paper to the buffer of the rotation point" scale is used in B «Household Standard (CNS) T4 specification (210x297 Public *) 10 1 81. 7. 20,000 sheets (II) 214588 Λ 6 Β 6 Printed by the Employee Consumer Cooperative of the Central Standards Bureau of the Ministry of Economy V. Invention Instructions 1) fflsh ** roti > oints8 biwt rl4, pointsaddr ffl iwt rl2, nun points »iwt routptr.m-rotpn ncache ove r 1 3, pc imatrotploop in torx id getb mine r14 afroa rna tl211 to r t is a u 1 t r x m t o r y n g e t b nine r 1 4 m t r o m riaat 2113 n h i b

; ROM ptr to the point to be rotated; the number of points to be rotated ts; RAM Ptr to the rotation point buffer plaque; set the fast memory address; start cycle address; get X; 11; η 1 1 $ X; Obtain y (please read the precautions before filling in this page) η nu 1 try to rtnaddrt; 2 1 »π 2 1 -S y this paper" Standard "Chinese National Standards (CNS) A 4 specifications ( 210X297 male; ¢) 102 81. 7. 20,000 sheets (Η) A 6 Η 6 5. Description of the invention 1 (0 3) nt 〇r ζ mgetb nine r 1 4 iatr * 〇 Bi rai £ it3231 mmu 1 trzaaddrt; get z ； 31 ； a »3 1 窣 z is addro si hib

Bstb (routptr); store rotation x (please read back to the precautions # fill out this page) ffi ine routpt btro iB rmatl211 ffl hibbtort η nu 1 trx; 12 printed by the Ministry of Economic Affairs Central Standards Bureau employee consumer cooperatives mfrosa n is u 1 tryntortsaddrt »trom raat3231 mhib This paper is used in the" National «Standard (CNS) f 4 specifications (210X297 public *); 22«! B 2 2 ^ y 103 81. 7. 20,000 sheets (Η) 214538 Λ 6 η 6 V. Description of the invention 10 4) Printed by the Ministry of Economic Affairs Central Standards Bureau Employee Consumer Cooperatives mmu 1 trz; m 32 ^ z add rtaaddroahibnstb (ro U t P t Γ) »Storage rotation y nine rout P t Γ B t Γ 0 ffi rna t21 13 9 13 house t 0 rt η nu 1 t Γ X > a 1 3 vx 1 t Γ 0 ffi rnat 2 322 t 23 nhib η nu 1 tryta 2 3 * ymtortnaddrt ffl fro brewing group 8 t 0 0 3 3 9 33 霣 通 u 1 trz bi 3 3 ^ znaddrt is addr 0 ahib (please read the back-end precautions # fill out this page) 装-資 _ 線-本 纸》 會 遑China β country «quasi (CNS) TM specifications (210X297 public address) 104 81. 7. 20,000 sheets (II) 214588 Λ 6 Η 6 V. Description of invention 1 ^ 5) Xinjiang stb (routptr); storage rotation z nine routptr when Using the programmable graphics co-processor of the present invention, combined with the host computer system, such as the Super NES, can produce some unique effects as shown in the examples of FIGS. 19, 20, and 21. As shown in Figure 19, the side view of the target, the helicopter, is drawn. This image does not accurately reflect the high-quality display produced by the Malio wafer. Figures 20 and 21 are enlarged and rotated views of Figure 19 previously described. Using the drawing co-processor of the present invention produces 3D-type (and other) waiting effects, including changing polygon-based targets that rotate at high speeds. And there is only a minimum burden on the main TV game instrument processing system. The present invention has been described in detail, and the detailed description of the present invention is only for the purpose of illustration and example. When the aforementioned embodiment is the best embodiment, there are still many changes and modifications for professionals familiar with the industry. The following patent applications include these changes and modifications in the spirit and scope of the present invention (please read the precautions before writing this page). The textbook "Zhang Scale Uses China's" Family Standard "悀 4 Specifications (2 丨 0x297 g; it) 105 81. 7. 20,000 sheets (Π)

Claims (1)

214588 Revision-丨 Supplement H3 H / Attachment No. 81 104859 Patent Application Φ Please revise the scope of the patent (June 19, 1982) 1. An external record and system of an information processing system (20, 19) (19 ), The information processing system includes a display screen daytime (36) 9 and has a micro-processor > used to execute an image drawing ΓΒΠ painting program 9 Μ and an image memory (30) > Stores character data representing multiple characters. It defines a display frame when combined. The external memory hip system (19) is characterized by: a program memory (10) 9 for storing at least some of the images The instruction Η of the drawing program and a conversion circuit (2, 52) t which are coupled to the program memory (10), are used to receive the display data represented by the pixel specification and process the pixel specification and Change the pixel specification resource f to be the character data format used by the image memory (30) 0 2. For example, Φ Please refer to the external memory system 9 of the patent scope item 1 The pixel specification 9 includes coordinate data Define the position 9 of the pixel on the display screen (36) and the conversion circuit (2,52) $ Receive the pixel specification 0 3 from the program memory. If the external memory system of the patent scope item 2 is requested Describe the conversion circuit (E 2) »Including the address conversion circuit (202, 204a, Fa, 21, 216) f for receiving pixel coordinate data t and generating-'character specified address 〇4. Such Patent application item 1 of the external memory system 鈳 »which includes a random access memory (RAM) (6 8), and Yuanyuanchong memory device (2 0 6), which is temporarily stored with 1 β generated from the Conversion of the word capital 4 (210X297U 韪) 1 2145B8 H3 material 1 and the device for coupling the character data stored in the buffer memory to the RAM (2 0 6, 22 8, 88) 3 5. External memory% system, including the recording device 9 for temporarily storing the pixel coordinate data 0 6 of the program memory (202,204). If the external memory of the patent scope item 1 is requested The system includes a programmable graphics processor (2), coupled to the program memory, and the conversion circuit (52) is implemented in the graphics processor. 7. If applying for an external memory system in item 6 of the special scope, the programmable graphics processor described includes a first source common bus (X) > a second source common bus (Y), Common bus (Z) with a destination, the conversion circuit receives data from the first source bus (X) 9 and the second source bus (Y), and is used to forward data to the destination bus Row (B). 8. As in the external memory system of claim 1, the pixel specification t includes the display coordinates of a pixel, and color information related to the display coordinates > and further includes a color register device (54) , Used to receive and temporarily store the color information 0 9. For example, the external memory system of the patent application item 8, which includes a register matrix (206) for receiving from the color register device Pixel color information 0 • 10 • For example, the external memory system of patent application item 1, which includes a random access memory (R AM) (6, 8) > and a RA Μ controller (8 8 ) t is used to control access to the RAM, and the conversion circuit, including the address conversion device 9 is used to generate-drawing character address (2 02,204, H A, FA, A 4 (210Χ 297 father) 214588 H3 2 1 4, 2 1 6) and character data generating device 9 Used to generate character data »It includes information about the pixel specification (202, 20 6) and transmission (206, 2 16), using the character address and word generated by the conversion circuit Meta information 9 to the device of the RAM controller (88). 11. An external memory system as claimed in item 1 of the patent scope, which includes a random access memory (RAM) (6, 8), and a device for coupling character information to the conversion circuit, from The RAM corresponding to the pixel specification uses the conversion circuit (82, 206) to process the pixel specification. 12. An external memory system as claimed in item 1 of the patent scope, which includes a device P for storing character data, wherein the conversion circuit (52) includes a device for receiving 9 from the device for storing The character data information about other pixels in the vicinity of the pixel is processed before 0 13. For example, please refer to the external memory% system of the first item of the patent scope, the program memory (1 0) and the conversion circuit ( 2, 52) t is implemented in the video game instrument cassette (1 9) 0 1 4 As the external memory system of the patent application item 1, the conversion circuit 1 includes a color matrix (2 0 6) , Used to store data, this data is related to the specified pixel and other pixels in this character t, including this specified pixel 〇15. If the external memory system of the patent scope item 14, the color The matrix (206) includes a plurality of rows and columns. The color matrix is loaded with columns and read out with rows. For example, Φ claims the external memory system of item 15 of the patent scope, which includes a register device (202 ), For temporarily storing the pixel specifications, including pixel coordinate data »and addressing the color matrix (206), part of it is 4 (210X 297 public life) 3 214588 H3 uses at least part of the contents of the register device 0-17 For example, the external memory% system of the first patent application range »which includes a device with undetermined bits t used to record whether the pixel to be processed is part of the hundred first characters to be processed (2 10) 0 18 If the patent scope item 17 of the external memory system is requested > which includes a random access memory device (R AM) (6, 8) and character data generated by using the conversion circuit (52) t to the RAM device, which It depends on the status of the undetermined device (2 10) of this bit. 19 If Φ please request the external memory system in item 1 of the patent scope > which includes a device indicating the processing of the one character that is not required to update (2 10)-a pixel specification of a character bit device. 20 If a patent is applied for The conversion circuit (52) described in the external memory system of the scope item 19 »includes a device for generating a character address» M in response to a predetermined state used to indicate the device 0 2 1 If a patent is applied Item 1 of the scope of the external memory system> which includes an address register device t for storing a character address i generated by the conversion circuit (2 16) and an address comparator (2 18), coupled to the address register device y for comparing the address of the giant pre-character generated by the conversion circuit with a previously generated address 0 22 such as the external memory of patent application item 21 System 1 which includes a character memory device> for storing character data (6, 8), and a control device (200), in response to the address comparator, for writing out the address stored in the address The address t of the register device to the character memory device 0 23 A graphics processor (2) for displaying the day surface of the screen, including: a device that receives-* pixel specifications (5 6, 5 8) ; And A 4 (210X 297 male creeper) 4 214588 _ 'H3 Yi-converting circuit (25) $ for processing the pixel specification t and generating a character specification specifying a character including the specified pixel 0 24 such as Φ please patent The pixel specification described in the graphics processor 1 of the scope item 23 includes a display coordinate 9 of a pixel and color information 9 related to the display coordinate. A color register device 9 is also included for receiving and temporarily storing the Color Information 0 25. Rushen The graphics processor of patent item 23, which includes a register matrix (206) for receiving pixel color information from the color register device (54). Item's graphics processor »which includes a long access memory (R AM) (6, 8) 9 and a device 9 for coupling character information from the RAM to the conversion circuit 9 which utilizes the conversion circuit (82 , 206) Process the specifications related to the pixel. 27 A graphics processor (2) for an information processing system (20, 19), this system has a main processing unit (2 0) »for executing one stored in at least one memory device (1 0) Image drawing program > The drawing processor (2) is characterized by: a device 9 > λ and ringtones for receiving program instructions from the at least-Yi Ji Yi (I HS TR, 6 2, 6 0) At least one device for pre-determined program commands > for converting the pixel-based format of the at least one pre-determined command > into a character-based data format (52) 0 28 as claimed in item 2 · 7 Graphics processor, which includes a first source common bus (X), a second source common bus (II), and a-destination common bus (Z) Μ and the conversion from the first 4 (210X 297 gong) 5 H3 214588 1 The data received by the source bus and the second source bus, and the device that forwards the data to the destination bus. _ 29. The graphics processor according to item 27 of the patent application scope, said graphics processor is used to be coupled to a random access memory (RAM) (6, 8), in which a RA Μ controller (8 8), for controlling access to the RA Μ, the device for conversion (52), which includes address conversion device for generating a character address (202, 204, HA, FA, 214, 216), And character data generating device for generating character data, including devices related to the pixel-based data (202,206), K, and transmitting (206,216), the character address and Character resource, to the RA M controller (8 8). 6 A 4 (210Χ 297 offices)