TW202403536A - Modulation of display resolution using macro-pixels in display device - Google Patents

Abstract

Embodiments relate to a foveated display, in which a display device receives image data to be displayed that comprises a plurality of display regions associated with different image resolutions, and metadata that is indicative of locations of the plurality of display regions associated with different image resolutions. A display driver integrated circuit (DDIC) of the display device comprises an expander circuit configured to determine locations of one or more macropixels to be displayed by the display area based on the received metadata, wherein each macropixel corresponds to a grouping of native pixels of the display area onto which image data is loaded to concurrently.

Description

Using macropixels in a display device to modulate display resolution

The present invention relates to a display device, and in particular to a light emitting diode (LED) or organic light emitting diode (OLED) related display with configurable resolution. Cross-references to related applications

This application claims U.S. Provisional Patent Application No. 63/323,966 filed on March 25, 2022, U.S. Provisional Patent Application No. 63/339,286 filed on May 6, 2022, and U.S. Provisional Patent Application No. 63/339,286 filed on March 24, 2023 18/125,727, which application is hereby incorporated by reference in its entirety.

Display devices are often used in virtual reality (VR) or augmented reality (AR) as a head-mounted display (HMD) or a near-eye display (NED). in the system. To display high-resolution images, it is beneficial to increase the number of pixels in a display device and operate the display device at a higher frame rate. However, as the number of pixels in a display device operating at a higher frame rate increases, the time allocated to preparing and writing data to the pixels decreases. In addition, utilizing an increased number of pixels can result in higher charging frequency, thereby increasing power consumption.

In some aspects, the techniques described herein relate to a method that includes receiving image data to be displayed by a display device, wherein the image data includes a plurality of display areas associated with different image resolutions. ; Generate metadata based on the received image data, wherein the metadata indicates the positions of a plurality of display areas associated with different image resolutions; transmit the image data together with the generated metadata to the display device; during display At a display driver integrated circuit (DDIC) of a device, wherein the display device includes a display area including a plurality of pixels arranged in a plurality of columns and rows: transmitted image data with metadata is received ; Determine the position of one or more macro pixels to be displayed by the display area based on the metadata, where each macro pixel corresponds to a grouping of native pixels in the display area, and the image data is simultaneously loaded onto the display area; to the control signal Configured for grouping columns and rows of the display area in determined timing based on determined macropixel positions; displaying image data by providing control signals in accordance with the determined timing.

In some aspects, the technology described herein relates to a display device, including a display driver integrated circuit (DDIC) that includes a receiver configured to receive image data to be displayed by the display device, wherein The image data includes a plurality of display areas associated with different image resolutions, and metadata indicating the positions of the plurality of display areas associated with different image resolutions; the expander circuit is configured to: based on the metadata Data determines the position of one or more macropixels to be displayed by the display area, where each macropixel corresponds to a grouping of native pixels of the display area onto which image data is simultaneously loaded; and configuring the control signal for grouping columns and rows of a display area in determined timing based on determined macropixel positions; and a source driver circuit; a display area including a plurality of pixels arranged in a plurality of columns and rows, each column including a plurality of pixels arranged in a plurality of columns and rows; A demultiplexer is configured to provide a gate enable signal to a respective gate line of the pixels of the row, and each row includes a respective data line configured to provide image data to the pixels of the row. A signal line of the source driver circuit, and configured to selectively couple data lines in a data line set of respective data lines to the signal line according to the control signal to charge the data line; wherein based on the determined macro pixel In a position, a control signal is provided to the demultiplexer to simultaneously couple a plurality of data lines in the data line set to the signal line period to simultaneously charge the plurality of data lines during one or more time periods.

Reference will now be made in detail to specific examples, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, the specific examples described may be practiced without such specific details. In other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure the appearance of the specific examples.

Specific examples of the invention may include or be implemented in conjunction with artificial reality systems. Artificial reality is a form of reality that has been adjusted in a certain way before being presented to the user. It can include, for example, virtual reality (VR), augmented reality (AR), mixed reality (MR), Mixed reality or a combination and/or derivative thereof. Artificial reality content may include fully generated content or generated content combined with captured (eg, real-world) content. Artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of these may be presented in a single channel or in multiple channels (such as stereoscopic video that produces a three-dimensional effect on the viewer). Additionally, in some embodiments, artificial reality may also be associated with applications that are used, for example, to generate content in the artificial reality and/or to otherwise be used in the artificial reality (e.g., to perform activities in the artificial reality). , products, accessories, services, or a combination thereof. Artificial reality systems that provide artificial reality content can be implemented on a variety of platforms, including head-mounted displays (HMDs) connected to host computer systems, stand-alone HMDs, mobile devices or computing systems or capable of providing artificial reality content to Any other hardware platform for one or more viewers.

1A and 1B are diagrams of a head mounted display (HMD) 100 including a near-eye display (NED) 110 according to some embodiments. NED 110 can present media to users. Examples of media that may be presented by NED 110 include one or more images, video, audio, or some combination thereof. In some embodiments, audio may be presented via an external device (eg, speakers and/or headphones) that receives audio information from HMD 100, a console (not shown), or both and based on the audio Information presents audio data to the user. HMD 100 is typically configured to operate as a virtual reality (VR) HMD. However, in some embodiments, HMD 100 may be modified to also operate as an augmented reality (AR) HMD, a mixed reality (MR) HMD, or some combination thereof. For example, in some embodiments, the HMD 100 may augment a view of a physical real-world environment with computer-generated elements (eg, still images, videos, sounds, etc.).

The HMD 100 shown in Figure 1A or Figure 1B may include a frame 105 and a display 110. Frame 105 may include one or more optical elements that together display media to the user. That is, display 110 may be configured for a user to view content presented by HMD 100. As discussed below in connection with Figure 2, display 110 may include at least one source assembly for generating image light to present optical media to the user's eyeballs. The source assembly may include, for example, a source, an optical system, or some combination thereof.

Figures 1A and 1B are only examples of virtual reality systems, and the display systems described herein may be incorporated into other such systems.

Figure 2 is a cross-section 200 of the HMD 100 illustrated in Figure 1A or Figure 1B according to some embodiments of the present invention. Cross-section 200 may include at least one display assembly 210 and exit pupil 230. The exit pupil 230 is the position where the eyeball 220 can be positioned when the user wears the HMD 100 . In some embodiments, the frame 105 may represent the frame of eyeglasses. For purposes of illustration, FIG. 2 shows a cross-section 200 associated with a single eyeball 220 and a single display assembly 210 , but in an alternative embodiment not shown, separate from the display assembly 210 shown in FIG. 2 Or another integrated display assembly can provide image light to the other eyeball of the user.

The display assembly 210 may guide image light to the eyeball 220 via the exit pupil 230 . Display assembly 210 may be constructed of one or more materials (eg, plastic, glass, etc.) that have one or more refractive indices that effectively reduce the weight of HMD 100 and broaden its field of view.

In alternative configurations, HMD 100 may include one or more optical elements (not shown) between display assembly 210 and eyeball 220 . As various examples, the optical elements may be used to correct aberrations in the image light emitted from the display assembly 210 , amplify the image light emitted from the display assembly 210 , perform some other function on the image light emitted from the display assembly 210 Optical adjustment, or a combination thereof. Exemplary optical elements may include apertures, Fresnel lenses, convex lenses, concave lenses, filters, or any other suitable optical element that affects image light.

In some embodiments, display assembly 210 may include a source assembly for generating image light to present media to the user's eyeballs. The source assembly may include, for example, a light source, an optical system, or some combination thereof. According to various embodiments, the source assembly may include light-emitting diodes (LEDs), such as micro-LEDs, organic light-emitting diodes (OLEDs), or other types of LEDs. In some embodiments, the source assembly may correspond to other types of displays in which pixels are arranged in columns and rows and connected to respective gate and data lines, such as a liquid crystal display (LCD).

Figure 3 illustrates a perspective view of a waveguide display 300 according to some embodiments. Waveguide display 300 may be a component of HMD 100 (eg, display assembly 210). In alternative embodiments, waveguide display 300 may form part of some other HMD or other system that directs display image light to specific locations.

Waveguide display 300 may include source assembly 310, output waveguide 320, and controller 330, among other components. For purposes of illustration, FIG. 3 shows waveguide display 300 associated with a single eyeball 220 , but in some embodiments, another waveguide display separate (or partially separate) from waveguide display 300 may provide image light to the user. the other eyeball. For example, in a partially separate system, one or more components may be shared between waveguide displays for each eyeball.

Source assembly 310 generates image light. Source assembly 310 may include source 340, light conditioning assembly (eg, decoupling element 360), and scanning mirror assembly 370. Source assembly 310 may generate image light 345 and output it to coupling element 350 of output waveguide 320 .

Source 340 may include a light source that produces at least coherent or partially coherent image light 345. Source 340 may emit light based on receiving one or more lighting parameters from controller 330 . Source 340 may include one or more source elements, including but not limited to light emitting diodes, such as micro-OLEDs, as described in detail below with reference to Figures 4-7B. Although the following description primarily describes source 340 as including OLEDs and/or micro-OLEDs, it should be understood that in other embodiments, source 340 may include other types of source elements, such as micro-LEDs or LCDs.

The output waveguide 320 may be configured as an optical waveguide that outputs image light to the user's eyeball 220 . The output waveguide 320 receives the image light 345 via one or more coupling elements 350 and guides the received input image light 345 to one or more decoupling elements 360 . In some embodiments, coupling element 350 couples image light 345 from source assembly 310 into output waveguide 320 . Coupling element 350 may be or include a diffraction grating, a hologram grating, some other element that couples image light 345 to output waveguide 320, or some combination thereof. For example, in the embodiment where coupling element 350 is a diffraction grating, the spacing between the diffraction gratings can be selected such that total internal reflection occurs and image light 345 propagates internally toward decoupling element 360 . For example, the spacing between diffraction gratings may range from approximately 300 nm to approximately 600 nm.

Decoupling element 360 decouples the total internally reflected image light from output waveguide 320 . Decoupling element 360 may be or include a diffraction grating, a hologram grating, some other element that decouples image light out of output waveguide 320, or some combination thereof. For example, in the embodiment in which decoupling element 360 is a diffraction grating, the spacing between the diffraction gratings may be selected so that incident image light exits output waveguide 320 . The orientation and position of the image light emitted from the output waveguide 320 can be controlled by changing the orientation and position of the image light 345 entering the coupling element 350.

Output waveguide 320 may be constructed of one or more materials that promote total internal reflection of image light 345 . Output waveguide 320 may be constructed of, for example, silicon, glass, or polymer, or some combination thereof. The output waveguide 320 may have a relatively small appearance, such as for use in a head mounted display. For example, output waveguide 320 may be approximately 30 mm wide along the x dimension, 50 mm long along the y dimension, and 0.5 mm to 1 mm thick along the z dimension. In some specific examples, output waveguide 320 may be a planar (2D) optical waveguide.

The controller 330 may be used to control the scanning operation of the source assembly 310 . In some embodiments, controller 330 may determine scan instructions for source assembly 310 based at least on one or more display instructions. Display instructions may include instructions to render one or more images. In some examples, the display instructions may include image files (eg, bitmaps). Display commands can be received from, for example, a console (not shown in the figure) of the virtual reality system. The scan instructions may include instructions for use by source assembly 310 to generate image light 345 . The scan command may include, for example, the type of image light source (eg, single color, multicolor), scan rate, orientation of the scan mirror assembly 370 and/or one or more lighting parameters. Controller 330 may include a combination of hardware, software, and/or firmware not shown here to avoid obscuring other aspects of the invention.

According to some specific examples, source 340 may include a light emitting diode (LED), such as an organic light emitting diode (OLED). An organic light-emitting diode (OLED) is a light-emitting diode (LED) having an electroluminescent layer that may include a thin film of an organic compound that emits light in response to an electric current. The organic layer is typically located between a pair of conductive electrodes. One or both of the electrodes may be transparent.

As will be understood, OLED displays can be driven by passive matrix (PMOLED) or active matrix (AMOLED) control schemes. In a PMOLED approach, each column (and line) in the display can be controlled sequentially, while AMOLED control typically uses a thin film transistor backplane to directly access and turn on or off individual pixels, which allows for higher resolution degree and larger display area.

In other embodiments, the OLED display is embodied as part of a display panel that does not include any waveguides. OLED displays can be screens that are viewed directly by the user's eyeballs rather than passing light through waveguides.

Figure 4 depicts a simplified OLED structure according to some specific examples. As shown in the exploded view, the OLED 400 may include a substrate 410, an anode 420, a hole injection layer 430, a hole transport layer 440, a light emitting layer 450, a blocking layer 460, an electron transport layer 470, and a cathode 480 from bottom to top. In some embodiments, substrate (or backplane) 410 may include monocrystalline or polycrystalline silicon or other suitable semiconductors (eg, germanium).

Anode 420 and cathode 480 may include any suitable conductive material, such as a transparent conductive oxide (TCO, such as indium tin oxide (ITO), zinc oxide (ZnO), and the like). Anode 420 and cathode 480 are configured to inject holes and electrons, respectively, into one or more organic layers within light emitting layer 450 during device operation.

Hole injection layer 430 disposed above anode 420 receives holes from anode 420 and is configured to inject holes deeper into the device, while adjacent hole transport layer 440 can support hole transport to light-emitting layer 450 . The light emitting layer 450 converts electrical energy into light. The light-emitting layer 450 may include one or more organic molecules or luminescent fluorescent dyes or dopants, which may be dispersed in a suitable matrix known to those of ordinary skill in the art.

Barrier layer 460 can improve device functionality by confining electrons (charge carriers) to light emitting layer 450 . The electron transport layer 470 can support the transport of electrons from the cathode 480 to the light emitting layer 450.

In some embodiments, the generation of red, green, and blue light (to display a full-color image) may include forming red, green, and blue OLED sub-pixels in each pixel of the display. Alternatively, OLED 400 may be adapted to produce white light in each pixel. White light can pass through color filters to produce red, green and blue sub-pixels.

Any suitable deposition process can be used to form OLED 400. For example, one or more of the layers that make up an OLED may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), evaporation, spray coating, spin coating, or atomic layer deposition (atomic layer deposition; ALD) and the like. In other aspects, OLED 400 can be manufactured using thermal evaporators, sputtering systems, printing, stamping, etc.

According to some specific examples, OLED 400 may be a micro-OLED. According to various examples, "micro-OLED" may refer to a specific type of OLED with a small active light-emitting area (e.g., less than 2,000 µm in some examples, less than 20 µm or less than 10 µm in other examples). In some embodiments, the light-emitting surface of a micro-OLED may have a diameter of less than approximately 2 µm. Such micro-OLEDs can also have collimated light output, which can increase the brightness level of light emitted from small active light-emitting areas.

5 is a schematic diagram of an OLED display device architecture including a display driver integrated circuit (DDIC) 510 according to some embodiments. According to some specific examples, an OLED display device 500 (eg, a micro-OLED die) may include an active display area 530 having an active matrix 532 (such as OLED 400 ) disposed over a monocrystalline (eg, silicon) backplane 520 . The combined display/backplane architecture (ie, display element 540 ) may be coupled directly or indirectly (eg, at or around interface A) to DDIC 510 . As shown in Figure 5, DDIC 510 may include an array of drive transistors 512 that may be formed using conventional CMOS processes. One or more display driver integrated circuits may be formed over a single crystal (eg, silicon) substrate.

In some embodiments, active display area 530 may have at least one area dimension (ie, length or width) greater than approximately 1.3 inches, for example, approximately 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2.0, 2.25, 2.5 , 2.75 or 3 inches, including the range between any of the preceding values, but covering larger area displays.

The backplane 520 may include a monocrystalline or polycrystalline silicon layer 523 with silicon through holes 525 for electrically connecting the DDIC 510 and the active display area 530 . In some embodiments, active display area 530 may further include a transparent encapsulation layer 534, a color filter 536, and a protective glass cover 538 disposed over upper emitting surface 533 of active matrix 532.

According to various embodiments, the active display area 530 and the underlying backplane 520 can be manufactured separately from the DDIC 510 and later bonded to the DDIC, which can simplify the formation of the OLED active area, including the formation of the active matrix 532, color filters 536, etc. .

DDIC 510 may be directly bonded to the backside of the backplane opposite active matrix 532 . In other embodiments, chip-on-flex (COF) packaging technology may be used to optionally connect the display element 540 to the DDIC 510 via a data selector (ie, multiplexer) array (not shown). Integrated to form OLED display device 500. As used herein, in some instances, the term "multiplexer" or "data selector" refers to a device adapted to combine or select from a plurality of analog or digital input signals, These analog or digital input signals are routed to a single output. Multiplexers can be used to increase the amount of data that can be transmitted within a given amount of space, time, and bandwidth.

As used herein, in some examples, "wafer flexure" (COF) may refer to a microchip or die, such as an OLED wafer, being mounted directly on and electrically connected to a flexible circuit, such as a direct driver circuit. The assembly technology of sexual circuit. In COF assembly, microchips can avoid some traditional assembly steps used in individual IC packages. This simplifies the overall design and manufacturing process while improving performance and yield.

According to some embodiments, the assembly of the COF may include attaching the die to the flexible substrate, electrically connecting the die to the flex circuit, and encapsulating the die and wires using, for example, epoxy resin to provide environmental protection. In some embodiments, the adhesive (not shown) used to bond the wafer to the flexible substrate may be thermally conductive or insulating. In some embodiments, ultrasonic or thermal ultrasonic wire bonding techniques may be used to electrically connect the wafer to the flexural substrate.

FIG. 6 is a schematic diagram of a display device 600 according to some specific examples. The display device 600 may be an OLED display device and includes a DDIC 510 and a display element 540, as well as other components. The display device 540 may be an integrated circuit including a backplane 520 , an active display area 530 , bonding pads 640 and a control circuit for controlling the active display area 530 . The control circuit may include gate driver 635 . The DDIC 510 may include a timing controller 610, a data processing circuit 615, an input/output (I/O) interface 625, a mobile industry processor interface (MIPI) receiver 630, a source driver circuit 645, and signal lines. 624. In other embodiments, one or more components of DDIC 510 may be disposed in display element 540 .

Timing controller 610 may be configured to generate timing control signals for gate driver 635 , source driver circuit 645 , and other components in display element 540 . The timing control signal may include one or more clock signals, vertical synchronization signals, horizontal synchronization signals and start pulses. However, the timing control signal provided from the timing controller 610 according to specific examples of the present invention is not limited thereto.

The data processing circuit 615 may be configured to receive the image data DATA from the MIPI receiver 630 and convert the data format of the image data DATA to generate a data signal that is input to the source driver circuit 645 for displaying the image in the active display area 530 .

The I/O interface 625 is a circuit that receives control signals from other sources and sends operating signals to the timing controller 610 . The control signals may include a reset signal RST for resetting the display element 540 and a signal for digital data transmission based on a serial peripheral interface (SPI) or inter-integrated circuit (I2C) protocol. signal. Based on the received control signals, the I/O interface 625 may process commands from a system on a chip (SoC), a central processing unit (CPU), or other system control chips.

MIPI receiver 630 may be a MIPI display serial interface (DSI), which may include a high-speed packet-based interface for delivering video data to pixels in active display area 530 . The MIPI receiver 630 can receive the image data DATA and the clock signal CLK, and provide the timing control signal to the timing controller 610 and the image data DATA to the data processing circuit 615.

The active display area 530 may include a plurality of pixels arranged in columns and rows, where each pixel includes a plurality of sub-pixels (eg, red sub-pixels, green sub-pixels, blue sub-pixels). Each subpixel may be connected to a gate line GL and a data line DL, and driven to act upon a data signal received via the connected data line DL when the connected gate line GL provides a gate-on signal to the subpixel. to emit light.

Backplane 520 may include conductive traces for electrically connecting pixels in active display area 530, gate driver 635, source driver circuitry 645, and bonding pads 640. The bonding pads 640 are conductive areas on the backplane 520 that are electrically coupled to the signal lines 624 of the DDIC 510 to receive timing control signals from the timing controller 610 and data signals from the source driver circuit 645 . Bond pad 640 connects to gate driver 635 and other circuit components in backplane 520 . In the specific example shown in FIG. 6 , DDIC 510 generates data signals and timing control signals and transmits these signals to bonding pads 640 of display element 540 . However, in other embodiments, the timing controller 610, the source driver circuit 645, and/or the data processing circuit 615 may be in the display device 540 instead of the DDIC 510. When the timing controller 610 and/or the data processing circuit 615 are on the display device 540, there may be fewer bonding pads 640 because the data signals and timing control signals can be transmitted directly to the corresponding components without the bonding pads 640. .

The gate driver 635 may be connected to the plurality of gate lines GL and provide gate-on signals to the plurality of gate lines GL at appropriate times. The gate driver 635 includes a plurality of stages, wherein each stage is connected to a gate line GL that outputs a gate-on signal to a column of pixels.

The source driver circuit 645 may receive the data signal from the data processing circuit 615 and provide the data signal to the active display area 530 via the data line DL. The source driver circuit 645 may include a plurality of source drivers, each source driver being connected to a row of pixels via a data line DL.

Figure 7A illustrates an exemplary pixel configuration of a display device according to some embodiments. The pixel configuration includes a row of pixels 712A through 712N (hereinafter also collectively referred to as "pixels 712"), a row of pixels 722A through 722N (hereinafter also collectively referred to as "pixels 722"), a row of pixels 732A through 732N (hereinafter also collectively referred to as "pixels 722") rows of "pixels 732") and rows of pixels 742A through 742N (hereinafter also collectively referred to as "pixels 742"), and so on. Although not shown in Figure 7A, additional rows of pixels may be disposed to the right and/or left of the rows of pixels shown. Each of the pixels (eg, pixel 712B) is connected to a corresponding data line (eg, DL1) and gate line (eg, GLB). In some specific examples, each of pixels 712, 722, 732, and 742 correspond to OLED pixels. In other embodiments, each pixel 712, 722, 732, and 742 is another type of pixel, such as a micro-LED pixel, an LCD pixel, and/or the like.

Data lines (eg, DL1 to DL4) are connected via signal lines 748 to a demultiplexer 716, which is connected to source driver circuit 645, to receive the multiplexed pixel data. Although only a single demultiplexer 716 is shown in Figure 7A, other demultiplexers connected to different signal lines and other pixel rows may be configured to the right and/or left of demultiplexer 716 to program additional pixel rows. . For example, in some embodiments, the display element includes a plurality of demultiplexers, each demultiplexer connected to the source driver circuit 645 via a respective signal line and connected to a respective pixel row via a respective set of data lines. gather.

The pixel data V _DATA used to program the rows of pixels is time multiplexed by a multiplexer (not shown) and then demultiplexed by demultiplexer 716, resulting in fewer signal lines (e.g., line 748) Can be used between the source driver circuit 645 and the pixel array. Because each demultiplexer receives pixel data V _DATA for use in parallel programming of the pixels of its respective pixel set row, the amount of time required to program all pixels of a particular column n of the display unit (called the column period T _ROW ) may be defined by the amount of time to program the pixels corresponding to column n of a particular demultiplexer. Although it is beneficial to use multiplexers and demultiplexers to multiplex pixel data for more data lines, the settling time associated with the reference voltage used to compensate for the threshold voltage of the drive transistors in the pixel can limit Degree of multitasking/demultitasking.

In some specific examples, each of pixels 712, 722, 732, and 742 corresponds to a sub-pixel associated with a particular color channel. For example, in some embodiments as discussed above, each pixel of the display contains three sub-pixels corresponding to the red, green, and blue channels. In some embodiments, pixels 712, 722, 732, and 742 connected to common demultiplexer 716 correspond to sub-pixels of different color channels. For example, pixels 712, 722, and 732 may correspond to red, green, and blue subpixels, respectively, of a given row of pixels, while pixel 742 corresponds to a red subpixel of another row of pixels. In other embodiments, pixels 712, 722, 732, and 742 connected to common demultiplexer 716 correspond to sub-pixels of the same color channel. For example, pixels 712, 722, 732, and 742 may correspond to red sub-pixels of different pixel rows of the display.

Gate lines GLA through GLN provide gate-on signals from gate driver 635 to the pixels. In the example of FIG. 7A , each pixel column is connected to one of the gate lines GLA to GLN to receive the gate-on signal. The gate-on signal indicates when the pixel column should be connected to the data line to receive pixel data for programming the pixel by controlling the data select switch (SEL) of each pixel (e.g., as shown in Figure 7B), where SEL The switch is on when the gate-on signal is active but off when the gate-on signal is inactive.

The display device 540 further includes timing signal lines (not shown) from the gate driver 635 to provide other timing signals. For example, display element 540 may include horizontal lines carrying timing signals for operating various switches in the pixels, as described below with reference to Figure 7B.

Figure 7B is a circuit diagram of a pixel according to some specific examples. Pixel 700 may be any pixel in display element 540, including but not limited to pixels 712, 722, 732, or 724. Although FIG. 7B illustrates pixels 700 as OLED pixels, it should be understood that in other embodiments, the pixels of display element 540 may be implemented as other types of pixels (eg, LED pixels, LCD pixels, etc.). The pixel 700 may include a switch SEL, a driving transistor _MD , an OLED, a switch REST, a switch SW, capacitors Cst1 and Cst2, and other components. The OLED is connected between the low voltage source ELVSS and the drain of the driving transistor _MD . When the switch SW is turned on and the switch REST is turned off, the driving transistor _MD generates a current in its drain, which current increases as the voltage stored by the storage capacitor Cst1 increases. Current is then provided to the OLED to drive the OLED. The OLED then generates light with an intensity corresponding to the amount of current provided by the drive transistor _MD .

The switch SEL controls the connection between the gate terminal of the drive transistor _MD and the data line DL. When the gate line GL provides a gate-on signal (e.g., goes low), the switch SEL is turned on, thereby connecting the gate of the drive transistor _MD to the data line DL, and based on the pixel data at the data line DL The storage capacitor Cst1 is charged by the voltage difference between the ELVDD voltage and the high voltage level (ELVDD). When the gate-on signal is disconnected in the gate line GL, the switch SEL is turned off, thereby disconnecting the gate of the driving transistor _MD from the data line DL.

The switch REST enables or not current from the drive transistor _MD to flow in the OLED. When the switch REST is turned on, the current from the driving transistor _MD flows through the switch REST to the ground (AGND), which has a lower potential than the low voltage level ELVSS. On the contrary, when the switch REST is turned off, the current from the driving transistor _MD flows in the OLED.

The switch SW is turned on or off to couple the high voltage source ELVDD to the source of the driving transistor _MD . When the switch SW is turned off, the capacitor Cst2 stores the voltage difference between the high voltage source ELVDD and the source of the driving transistor _MD .

In some specific examples, the driving transistor _MD , the selection switch (SEL), the reset switch (RES) and the emission switch (SW) are each implemented as a P-channel metal-oxide-semiconductor; PMOS ) transistor, in which the gate signals of the select switch (SEL), reset switch (RES) and emission switch (SW) are controlled by the timing signal provided by the gate driver circuit system of the display. In other embodiments, one or more of these components may be implemented using other types of switches (eg, NMOS transistors).

In some specific examples, data is sequentially written to each pixel row of a display panel (eg, display element 540) of the display device. For example, in some embodiments, gate driver 635 includes a pulse or shift gate signal (also referred to herein as an "enable" signal) that travels along a series of shift registers corresponding to columns of display panels. pulse"). The enable pulse acts as a gate-on signal provided along a gate line connecting a row of pixels, and each column of the display panel is programmed during a time period T _Row (also known as a gate-on period or column period) ation, during which an enable pulse is provided to the gate line GL of the column. The frame rate of the display is based on the column period T _Row used for each column of the stylized display panel. Additionally, as discussed above, the pixels of each column are grouped based on one or more demultiplexers, where the column period T _Row may be based on the amount of time used to program the pixels of the column corresponding to a particular demultiplexer.

In some embodiments, the display device is configured for stylized grouping of pixels in multiple columns and/or rows, wherein the same data value is provided to each pixel in multiple columns and/or rows simultaneously, such that Generates "virtual pixels" (also called "macropixels") composed of multiple native pixels. For example, the display device may group native pixels in m rows by n columns (where m and n are integers, and at least one of m or n is greater than 1), where each pixel in m rows and n columns is simultaneously Driven to produce m × n macropixels. As used herein, rows may refer to pixels arranged in a direction parallel to the data lines of the display, and columns may refer to pixels arranged in a direction parallel to the gate lines of the display, although some figures may be drawn from The same applies to data lines extending in the horizontal direction and gate lines extending in the vertical direction for illustration purposes.

In some embodiments, grouping native pixels into macropixels is performed to reduce the overall effective resolution of the display panel. For example, by grouping a 2×2 set of native pixels into macropixels, the effective resolution of the display is reduced by a factor of 4. In other embodiments, grouping pixels into macropixels is performed as part of implementing a foveated display, where different regions of the display panel are configured to display image data at different resolutions. For example, in some embodiments, the display device is configured to display image data in a first display area at native resolution and in one or more display areas at a lower resolution based on the size of macropixels in each area. Display image data in an additional display area. In some embodiments, the position of each display area within the display is fixed (called fixed foveated rendering, or FFR). In some embodiments, the position of the display area of the foveated display panel is dynamically configured based on the user's gaze direction (referred to as gaze-tracked foveation rendering or GFR), for example, where surrounding the user's gaze direction ( For example, a display area (centered on the display corresponding to the position at which the user is looking) is configured to display image data at native resolution, while other areas of the display are configured to display image data at a lower resolution.

8 illustrates a high-level diagram illustrating an implementation of a foveation display, according to some specific examples. In some specific examples, the display device receives input image data 802 to be displayed on the display panel, where the input image data 802 includes first image data 804 of a first resolution (eg, a native resolution of the display device) and a second Lower resolution second image data 806. In embodiments that do not use macropixel grouping, the image data is amplified (eg, by mapping each pixel of the second image data 806 to a plurality of native pixels of the display) to produce the displayed image data 808 , which is entirely based on the display device. native resolution display. On the other hand, in a specific example using macropixel grouping, the displayed image data 810 is displayed using the native pixels of the display device in the first area 812 and is displayed using macropixels in the second area 814, the macropixels include using A group of native pixels that are simultaneously stylized with the same data. In some embodiments, different regions of the display may be associated with different macropixel grouping sizes. For example, the display image data 810 may further include a third region 816 that includes macropixels of a different size than the macropixels of the second region 814 .

In some embodiments, by grouping native pixels into macropixels, the power consumption of the display device can be reduced. In other embodiments, macropixel grouping is used to reduce the refresh rate of the display. In some embodiments, the use of macropixels allows the use of a display with a native resolution that is greater than otherwise achievable at a given refresh rate. For example, in some embodiments, displays with higher than a certain native resolution (e.g., 5k+native resolution) will not be able to perform at a desired refresh rate (e.g., 90 Hz) to implement. However, by implementing a foveated display that groups the display's native pixels into macropixels, the effective resolution of the display is reduced, allowing the use of displays with higher native resolutions while still maintaining the desired refresh rate.

9 illustrates a diagram illustrating a foveated display architecture according to some specific examples. In some embodiments, foveated image data 902 is initially generated at graphics processing unit (GPU) 910 and processed at display processing unit (DPU) 920 before being transmitted to an OLED display that includes DDIC 930 and display Component 940 (which may correspond to DDIC 510 and display component 540 illustrated in Figure 6). In some embodiments, GPU 910 and DPU 920 are part of the same system on a chip (SoC). In some specific examples, the SoC may include multiple GPUs and/or multiple DPUs. In some embodiments, GPU 910 and DPU 920 are located on a separate processor or console from the OLED display.

In some specific examples, the GPU 910 and the DPU 920 perform one or more image processing functions on the received gaze point image data 902 . For example, in the case where the initial gaze point image data 902 includes multiple layers, the GPU 910 and the DPU 920 may perform the composite function 912 on the image data 902 that combines the layers of image data (eg, combines into a single layer). In some specific examples, the DPU 920 performs color aberration compensation (CAC) 914 on the image data, which can be used to compensate for chromatic aberration caused by magnifying lenses used in VR or AR displays. In some specific examples, such functions may be performed on GPU 910 or DPU 920.

The metadata generation module 916 generates metadata 904 associated with the gaze point image data 902 . In some embodiments, the metadata generation module 916 collects metadata describing the foveated image data 902 from the CPU or GPU. In some embodiments, the generated posterior data specify the location of two or more display areas of the display, the effective resolution and/or macropixel size of each display area, or some combination thereof. In other embodiments, where the display is configured to implement GFR, the metadata may indicate the gaze position, and the DDIC is then based on the received gaze position (e.g., a central display area with native resolution centered at the gaze position , one or more peripheral display areas with lower effective resolution outside the central area, etc.) to determine the positions of different display areas. In some embodiments, image data 902 may have native resolution, and metadata 904 is used by the DDIC to downsample portions of image data 902 to generate foveated image data. In some embodiments, metadata generation module 916 generates metadata in a format compatible with a display stream compression algorithm, such as Display Stream Compression (DSC) or VESA Display Compression M (VDC-M). , in order to facilitate the transfer of metadata from GPU 910/DPU 920 to DDIC 930. Figure 9 shows the metadata generation module 916 that generates post-set data of the fixation point image data 902 between execution of different image processing functions (for example, between execution of composite function 912 and CAC 914), but it should be understood that in other In a specific example, the metadata generation module 916 can generate metadata of the gaze point image data 902 before executing the image processing function or after executing different image processing functions. In some embodiments, the metadata generation module 916 may be located on the GPU 910 , while in other embodiments, the metadata generation module 916 may be located on the DPU 920 .

The transmitter 918 encodes the foveated image data 902 and the generated posterior setting data 904 into a stream of packets 906 to be transmitted to the DDIC 930 . In some embodiments, the transmitter 918 includes an encoder that encodes packets using a compression algorithm such as DSC, VDC-M, etc. In some embodiments, transmitter 918 encodes portions of image data 902 and metadata 904 into a common packet. In other embodiments, the transmitter 918 encodes the image data 902 and the metadata 904 into independent packets. In specific instances where dual transmission channels are available, image data and metadata can be transmitted via separate channels. In other embodiments where only one channel is available, packets of image data and metadata may be multiplexed, or metadata may be embedded as part of packets of image data.

DDIC 930 receives a packet 906 containing foveated image data 902 and metadata 904 via a receiver 932, which decodes the received packet to retrieve foveated image data 902 and metadata 904. In some embodiments, receiver 932 may correspond to MIPI receiver 630 illustrated in FIG. 6 . In some embodiments, the DDIC 930 performs one or more image processing functions 934 on the received foveation image data 902, such as digital to analog conversation (DAC) and filtering, such as low-pass. ; LP), band-pass (band-pass; BP) or high-pass (high-pass; HP) filtering. The image processing function 934 may also include a timing control circuit (TCON). In some embodiments, TCON generates the timing of control signals (eg, demultiplexer control signals, column enable pulses, etc.) used to configure pixels of the display (described in more detail below).

DDIC 930 includes expander circuitry (or "expander") 936 configured to synthesize the positions of macropixels displayed by display element 940 based on received metadata 904 to display foveated image data 902 . For example, expander 936 uses metadata 904 to determine groupings of columns and rows of display elements 940 to create macropixels spanning m × n pixels that simultaneously load common image values. In some embodiments, expander 936 sets the grouped demultiplexing parameters for grouping the set of m rows, and the control code for performing a grouped gate scan to group the set of n columns. Create m × n macropixels. In some embodiments, metadata 904 may directly indicate the number of columns and rows to be grouped by expander 936 . In other embodiments, where metadata 904 does not directly indicate the grouping of columns and rows (such as where metadata 904 indicates the center of the display in a GFR display), the expander may be based on the metadata. 904 determines which columns and rows of the display are to be grouped. In some embodiments, expander 936 is implemented as part of data processing circuit 615 illustrated in FIG. 6 .

In some embodiments, by expanding the foveated image data after transmitting it to the DDIC 930, the amount of image data that needs to be transmitted can be reduced. For example, because the foveated image data will be displayed using macropixels, where each pixel within a macropixel is simultaneously loaded with the same image data, the foveated image data 902 does not need to indicate the pixel value of each native pixel of the display. Instead, foveated image data 902 may only need to contain pixel data values for each macropixel of the image to be displayed, resulting in a lower number of pixel values that need to be transmitted for each image.

As discussed above, m × n macropixels may correspond to a grouping of m rows and n columns of a display such that all pixels at the intersection of m rows and n columns are simultaneously programmed with the same image data as if they were a single pixel . In some specific examples, m rows of a display are grouped using grouped demultiplexing (GDX), discussed in more detail below. Grouped gate scanning (GGS) is used to group the n columns of the display. The gate lines of multiple columns are grouped together, so that the data from the data lines of the display are written to the grouped columns at the same time. Each pixel in the grouped column receives the same image data. By grouping different sets of columns and rows at different parts of the display, different display areas with different effective resolutions (eg, different sizes of macropixels) can be produced.

10 is a diagram illustrating an example of extending image data to be displayed on a foveated display with macropixels of different sizes, according to some embodiments. As shown in Figure 10, image data 1002 (which may correspond to image data 902 illustrated in Figure 9 received by the GPU) may be in a compressed format. For example, for each macropixel to be displayed, image data 1002 may specify a single pixel value that corresponds to the image data for all pixels of the macropixel, thereby reducing the total number of pixels in image data 1002 and reducing the time spent on the GPU/ The amount of data transferred between the DPU and DDIC. Based on the received metadata indicating the macropixel grouping to be displayed, image data 1002 is expanded at the DDIC (eg, by expander 936) to produce image data 1004. For example, as shown in Figure 10, image data 1004 includes a plurality of display areas, each display area having a different effective resolution resulting from different groupings of columns and rows to produce macropixels of different sizes. In some embodiments, the size and location of the display area may be selected based on the expected field of view of the user's eyeballs when viewing the display. For example, in some embodiments, the center display area of the display may be selected to correspond to approximately 20 degrees of the user's field of view in both horizontal and vertical directions.

The number of columns and rows grouped together can be independently configured in different areas of the display to produce macropixels of different sizes. For example, in center region 1006, no grouping of columns or rows is performed, so that the effective resolution of this region is the same as the native resolution. However, in region 1008, the foveated display groups the set of two columns together while leaving the rows ungrouped, resulting in 1×2 macropixels in these regions, resulting in an effective resolution of half the native resolution. Spend. Similarly, in region 1010, the foveated display groups a set of two rows and a set of two columns, resulting in 2×2 macropixels, resulting in an effective resolution of 1/4 of the native resolution in these regions . This extends outward to area 1012, corresponding to the corner area furthest from the central area 1006, where the set of four columns and the set of four rows are grouped together, resulting in an effective resolution of 1/16. In some embodiments, the expander configures groupings of columns and rows based on the location of regions within the image data based on the received metadata. For example, in some embodiments where row grouping is applied across an entire column, for columns with mixed resolutions (e.g., 1×1 pixel and 2×1 pixel), row grouping may be implemented based on the higher resolution such that in Image data for each column of lower-resolution pixels (including multiple native pixels spanning multiple rows) are provided over separate time periods rather than simultaneously. Because the data provided to the data lines via the signal lines is constant over a single period of time, some power savings can be achieved relative to stylized rows of higher resolution pixels.

As discussed above, in some embodiments, the data lines of the display are connected to a plurality of demultiplexers (e.g., demultiplexer 716 shown in Figure 7A), which time-multiplex the data from the DDIC The signal line (for example, signal line 748/624) is provided to the data line. 11A and 11B illustrate diagrams illustrating different configurations in which a demultiplexer may be coupled to data lines of a display, according to some specific examples. In the first example shown in FIG. 11A , each demultiplexer 1102 (demultiplexers 1102A to 1102I) connects a respective signal line of the DDIC to four data lines of the display, where each data line corresponds to The color channel of a specific pixel row. In the specific example shown in Figure 11A, each demultiplexer is connected to a data line corresponding to a different color channel. For example, first demultiplexer 1102A is connected to the red, green, and blue data lines of a first row of pixels and the red data lines of a second subset of pixels, and second demultiplexer 1102B is connected to The green and blue data lines of the second row and the red and green data lines of the third row of pixels. Demultiplexer 1102 is controlled using control signals DMX1 through DMXn (eg, DMX1 through DMX4), which are sequentially enabled to cause each of demultiplexer 1102 to provide data from its respective signal line to Corresponding data line.

According to some specific examples, grouping rows of a display using grouped demultiplexing (GDX) involves configuring demultiplexers that provide data from the signal lines of the DDIC to the data lines of the display to simultaneously The same data is provided to multiple pixels. In some embodiments, to facilitate the ability for the same data to be provided to different pixels (e.g., different rows of pixels to be grouped together to form a macropixel), the demultiplexer is not connected to data lines corresponding to different color channels. , but are configured to connect to the same color channel of different pixels, so that each demultiplexer can provide image data to multiple pixels simultaneously for a specific color channel. 11B illustrates an exemplary configuration of a demultiplexer by which GDX may be executed, according to some embodiments. As shown in FIG. 11B , each of demultiplexers 1104A through 1104F is each configured to receive image data corresponding to a single color channel (red, green, or blue), and based on the received control signals DMX1 through DMX6 provides image data to up to six different data lines corresponding to six different rows of pixels. Because each demultiplexer is associated with only a single color channel, each pixel is connected via a separate data line to three different demultiplexers (for example, one configured to provide red channel image data to the first multiplexer of the pixel). processor, a second multiplexer configured to provide blue channel image data to the pixels, and a third demultiplexer configured to provide green channel image data to the pixels), and may be based on the control signal DMX1 Programmed to the activation of a single control signal to DMX6. For example, when the control signal DMX1 is activated, the data line of the first pixel 1106A is loaded with R, G, and B color channel data via the demultiplexers 1104A, 1104B, and 1104C. In some embodiments, each of the demultiplexers 1104 is implemented using a long metal segment 1108 extending under the control lines DMX1 through DMXn (eg, DMX1 through DMX6 ), each connected via a respective contact 1110 to control line. In some embodiments, metal segments 1108 extending beneath a plurality of control lines enable easy layout modifications because each segment can be connected to any one of the control lines based on the placement of contacts 1110 .

By configuring the demultiplexer to provide any data for a specific color channel only to its connected data lines, each signal line connected to the demultiplexer provides only image data for that specific color channel. This can be used to reduce the amount of power required to drive the display panel due to changes in image data values for different color channels compared to adjacent pixels of the same color channel, especially when displaying image content with large areas of flat texture. Changes in image data values are typically small. For example, in some embodiments, the power consumption of a display is based on the amount of current used to drive the data lines, the amount of current being the switching frequency of the source driver and data lines and the switching frequency at the source driver and data lines. A function of the voltage difference for each transition. When each signal line provides data corresponding to a specific color channel of adjacent pixels of the display, the switching frequency and voltage difference are reduced, thereby reducing power consumption.

12A and 12B illustrate diagrams illustrating how to control the demultiplexer of a display to perform GDX according to some specific examples. Figure 12A illustrates demultiplexer 1202, where for ease of illustration, the data lines connected to demultiplexer 1202 are shown extending in the horizontal direction, and the gate lines of the display are shown extending in the vertical direction, even though along Pixels along the same data line are still called rows, and pixels along the same gate line are called columns. Demultiplexer 1202 is configured to provide blue channel data to a plurality of data lines 1204 (eg, six data lines) that are connected to a plurality of pixel rows (eg, , six pixel rows) of blue sub-pixels. The specific pixels on which rows have data loaded during a given time period are based on the active gate lines 1206 of the display during that time period. In some embodiments, different timings of the demultiplexer control signals may be used during different column periods T _row to allow different columns to contain different pixel groups. For example, FIG. 12A illustrates an example in which, for six data lines controlled by demultiplexer 1202, pixel grouping is not performed on the pixels in the first column, and two groupings are performed on the pixels in the second column. , perform grouping of 3 on the pixels in the third column, and perform grouping of six on the pixels in the fourth column.

12B illustrates a timing diagram illustrating control signal timing for grouping different combinations of pixels illustrated in FIG. 12A when performing GDX, according to some embodiments. As shown in FIG. 12B , throughout each of a plurality of column periods T _row , data is loaded onto data lines 1204 by demultiplexer 1202 based on control signals DMX1 through DMX6 based on the rows in the column. Which gate line 1206 (eg, SEL1, SEL2, SEL3, or SEL4 corresponding to the first, second, third, and fourth columns) is activated during a cycle to write to one or more columns of pixels. During the first column period (during which pixel grouping is not performed), the control signals DMX1 to DMX6 of the demultiplexer are provided sequentially, thereby allowing the demultiplexer 1202 to provide different data to be loaded onto each data line via the signal line. Image data (for example, data values B1 to B6). Each control signal is activated within a time period T, which corresponds to an amount of time sufficient to charge the data lines. As discussed above, because the display's demultiplexer loads data onto its respective set of data lines in parallel, the column period T _ROW can be based on the use by a particular demultiplexer to load data onto its data lines. load time (e.g. based on 6T).

By controlling the timing of control signals DMX1 to DMX6, pixels in adjacent rows can be grouped and provided simultaneously with the same image data. For example, to group pairs of pixels on adjacent rows, multiple control signals are provided simultaneously, and the demultiplexer 1202 provides the same image data to multiple data lines simultaneously. For example, as shown in Figure 12B, during the second column period T _ROW , the control signals DMX1 to DMX6 are activated in pairs (eg, DMX1 and DMX2, DMX3 and DMX4, and DMX5 and DMX6), such that demultiplexing Device 1202 couples the signal line to a pair of data lines 1204 at a time (for example, to provide data value B1 to the data line corresponding to DMX1 and DMX2, to provide data value B3 to the data line corresponding to DMX3 and DMX4, and to The data value B5 is provided to the data lines corresponding to DMX5 and DMX6), so that the data from the signal line is provided to both data lines simultaneously. In addition, since coupling a signal line to multiple data lines at once can increase the charging time required to load data onto the data lines, over a longer period of time (e.g., approximately 2T) than providing only a single control signal at a time Provides each pair of control signals. However, since the number of transitions is reduced due to the control signals provided in pairs, the overall column period _TROW does not increase.

As shown in Figure 12B, during the third column period, the control signals DMX1 to DMX6 are activated in three sets, each set being provided for a time period of approximately 3T, allowing the demultiplexer 1202 to couple the signal lines at a time to three data lines 1204 to generate 3 rows of macropixels (e.g., the first macropixel provides data value B1, which includes pixels on the data lines corresponding to DMX1, DMX2, and DMX3, and the second macropixel provides data value B4, It contains pixels on the data lines corresponding to DMX4, DMX5 and DMX6). Additionally, during the fourth column period, control signals DMX1 through DMX6 are all activated together (eg, within a time period of approximately 6T) to generate macropixels spanning six rows. For example, as shown in Figure 12A, when all control signals DMX1 through DMX6 are enabled, demultiplexer 1202 provides the same signal line value (eg, B1) to all six of its connected data lines 1204 simultaneously. These data lines are loaded onto pixels in a specific column of the display when a column gate select signal (eg, SEL4) is received.

For specific examples such as those shown in Figures 12A and 12B, where each demultiplexer is connected to six data lines, rows 2, 3, and 6 macropixels can be configured by applying the demultiplexer control signal to 2, Groups of 3 or 6 are constructed in groups because 2, 3, and 6 are divisible by 6. 12C and 12D illustrate diagrams illustrating how to control a demultiplexer of a display to generate 4-pixel macropixels according to some specific examples. As shown in Figure 12C, since 4 is not divisible by 6, when multiple 4-row macropixels are generated, some of the macropixels may span data lines corresponding to different multiplexers. For example, FIG. 12C illustrates a first demultiplexer 1212A for providing blue channel data to a first set of six data lines, and as a first demultiplexer 1212A for providing blue channel data to the six data lines. Second set of second demultiplexers 1212B. Control signals DMX1 to DMX6 are shared between all demultiplexers, including the first demultiplexer 1212A and the second demultiplexer 1212B, which may be used in the same manner as described above with respect to FIGS. 12A and 1212B. Data is provided to pixels on their respective sets of data lines in the same manner as discussed in 12B, as individual pixels (no grouping), 2-row macropixels, 3-row macropixels, and 6-row macropixels (not shown in FIG. 12C). Additionally, because control signals DMX1 to DMX6 are shared by the demultiplexers, 2x timing is used to implement 4 rows of macropixels, during which each demultiplexer provides data from its respective signal line to a pair of data lines. In some embodiments, this operation may be performed instead of grouping four data lines because the data lines to be grouped by each demultiplexer may be different, creating potential conflicts.

Although FIGS. 11A-12D show demultiplexers each connected to six data lines, it should be understood that in other embodiments, each demultiplexer may be configured with a different number of branches. In some embodiments, the number of branches per demultiplexer is selected based on a time period T sufficient to charge the display's data lines and a desired column period T _ROW (which may be based on a desired refresh rate of the display).

As discussed above, m × n macropixels (corresponding to the grouping of m rows and n columns of the display) can be generated by grouping m row pixels using GDX and grouping n column pixels using GGS. In some embodiments, the gate lines of each pixel column of the display may be configured to pass through an enable pulse when an enable pulse is received at the column, the enable pulse is sequentially shifted between the columns of the display, or at the The enable pulse is "skipped" when an enable pulse is received at a column but instead passes through the enable pulse when it is also passed through by an adjacent column, thus grouping the column with an adjacent column such that both columns write from the data lines simultaneously data to their respective pixels.

Figure 13 is a diagram illustrating how combinations of GDX and GGS can be used to generate macropixels of various sizes, according to some specific examples. Figure 13 illustrates a demultiplexer 1302 configured to provide green channel data to a set of six data lines 1304 based on control signals DMX1 through DMX6. Control signals are activated sequentially to load data onto each data line individually (without grouping) or grouped to produce multiple rows of macropixels (eg, 2 rows of macropixels or 3 rows of macropixels), similar to that described above with respect to Figures 12A and As discussed in Figure 12B. FIG. 13 also illustrates a timing diagram showing control signals received by demultiplexer 1302 and provided to gate lines 1306 used to construct macropixels of different sizes.

The gate lines 1306 of the display may be grouped to create columns of macropixels. For example, Figure 13 shows that the gate select lines of the first column are not grouped with any other columns and provide an enable signal (SEL1) when an enable pulse is received at that column. On the other hand, the gate circuitry of the second column is configured to be coupled to the gate circuitry of the third column such that when the enable pulse is received at the second column, the enable pulse does not pass through the gate circuitry of the third column. Crosses the enable pulse when the enable pulse is received at . Therefore, when the enable pulse is received at the second column, it is "skipped" and does not cross the gate line of the second column (shown as "SEL2 Skip" in Figure 13). The reality is that when the enable pulse is received at the third column, it passes through the gate lines (SEL2&SEL3) of both the third column and the second column, allowing the data on the load data line at that time to be written to both columns. pixels, resulting in macropixels spanning two columns. Figure 13 further shows the gate select lines of the fourth, fifth and sixth columns coupled together using similar principles such that when a shifted gate select is received at the last column of the group (e.g., the sixth column) signal, all three columns are written to produce 3 columns of macropixels.

As shown in Figure 13, by combining GDX and GGS, macro pixels of various sizes can be formed. For example, when the control signals are configured so that the demultiplexer 1302 simultaneously provides image data from the signal lines to the data line pairs during the column period in which the gate lines of the two columns are grouped together, forming a 2× 2 macro pixels. Similarly, when demultiplexer 1302 provides signal line data to a set of three data lines at a time and groups the gate lines of a set of three columns together, 3×3 macropixels are formed. It should be understood that other sizes of macropixels (eg, 2x3 macropixels, 3x2 macropixels, etc.) may be formed using similar techniques.

In some embodiments where the gate select lines of multiple columns are grouped, demultiplexer 1302 may be used to load signal line data onto the data lines over multiple column periods. For example, as illustrated in Figure 13, because SEL2 is skipped during the second column period, but is instead provided in conjunction with SEL3 during the third column period, the write to be made will occur in two column periods instead of one. The data line data for the pixels in these two columns is loaded. In some embodiments, this may allow for dynamic changes in column period duration to improve display refresh rate and/or reduced source driver bias current to improve power consumption, both of which are discussed in more detail below .

14 illustrates a high-level diagram showing electrical characteristics of a set of signal lines, demultiplexers, and data lines, according to some specific examples. Source driver 1402 provides source bias voltage for driving signal line 1404 and any of data lines 1408 connected to signal line 1404 via demultiplexer 1406 (eg, data lines 1408-1 through 1408-m) current. The amount of time required to charge each data line 1408 of the display is based on a time constant τ that depends on the relationship between the source driver (such as the source driver (SD) equivalent resistance R _S , the SD output electrostatic discharge (ESD) _The impedance _{associated with the} resistor _R The resistance of the connection. In some specific examples, τ can be calculated as . However, in the case where the demultiplexer selects multiple data lines in parallel, the value of the time constant τ does not scale linearly. For example, in the case of selecting m data lines in parallel, τ can be calculated as . In other words, . Because charging time does not scale with the number of data lines being charged at once, using a demultiplexer to group multiple data lines that are being charged together can be used to reduce line times (increase the refresh rate of the display, or allow the display to include additional pixel columns without reducing refresh rate), or reduce the display's power consumption (for example, by reducing the source bias current used when charging multiple data lines).

Figure 15A illustrates an example of how line time may be reduced when executing GDX, according to some specific examples. Figure 15A illustrates a first timing diagram 1502 showing control signals and data line voltages over three column periods (similar to the first three column periods shown in Figure 12B). As shown in FIG. 15A , the column period T _row corresponding to when grouped demultiplexing or grouped gate scanning will not be performed is shown as "1H". During the first column period, packet demultiplexing is not performed and control signals DMX1 to DMX6 are sequentially provided, each of which lasts for a time period T, which time period is sufficient based on the time constant Charge each of the corresponding data lines (eg, T≈5τ ₁ ). However, during the second column period and the third column period, group demultiplexing is used to group the two and three sets of control signals respectively to provide the signal line data sets to two and three data lines at a time collection. As shown in Figure 15A, where each set of two or three data lines is assigned a time of 2T or 3T, respectively, each set of data lines can be fully charged before the end of the assigned time period, resulting in an alien flat period 1504, during which charging is completed.

15A further illustrates a second timing diagram 1510 showing control signal and data line voltages over three column periods, where the length of the column periods is based on the level of packet demultiplexing performed, according to some embodiments. Variable. In the diagram of Figure 15A, the length of the column period (during which packetized demultiplexing is performed) is reduced by an amount Tm, where m corresponds to a number of packetized data lines (such that two/three packetized data lines Each set is allocated less than 2T/3T to charge) to allow the data lines to be fully charged while reducing or eliminating flat periods 1504 (during which no charging occurs). For example, in some specific examples, T2 ≈ 6×5τ ₁ - 3 ×5τ ₂ and T3 ≈ 6×5τ ₁ - 2 ×5τ ₃ . In some embodiments, the DDIC dynamically adjusts the duration of the column period of the display for different columns (e.g., using timing controller 610 illustrated in FIG. 6 ) based on the level of GDX performed on the pixels of the column Enable pulse timing by configuring).

Figure 15B illustrates an example of how line time can be reduced when executing GDX and GGS according to some specific examples. As discussed above, GGS involves the grouping of the gate lines of multiple columns so that data from the display's data lines are simultaneously written to the pixels of each of the grouped columns, such that each of the grouped columns receives the same image material. 15B illustrates a first timing diagram 1512, in which during the first column period, packet demultiplexing is not performed, and control signals DMX1 to DMX6 are provided sequentially, each of which lasts for a time period T. The time period is sufficient to charge each of the corresponding data lines (eg, T≈5τ ₁ ). However, during the second column period and the third column period, group demultiplexing is used to group the two sets of control signals to provide signal line data to the two sets of data lines at once, and the grouped gate scan to group the two columns together such that the enable pulse is skipped 1514 during the second column period and provided along with the enable pulse 1516 during the third column period (similar to that depicted in Figure 13). This grouping of two data lines and two columns produces a column of 2×2 macropixels. As shown in Figure 15B, because the data line can be fully charged in one column period 1H, it does not need to be further charged during the additional column periods associated with the grouped columns (eg, the third column period). Thus, the DDIC can dynamically adjust the duration of the column period so that the enable signal for the grouped columns is received within the 1H period. For example, the total time for grouping n columns using GGS can be reduced from n×1H to 1H, resulting in a time saving of (n-1) 1H. Therefore, when GDX and GGS are used in combination, the time savings can be expressed as Tm + (n-1)∙1H (for example, T2 + 1H, when n and m are both 2).

Reducing the column period for certain columns increases the overall refresh rate of the display. In some embodiments, due to the minimum amount of time required to charge the data lines of each demultiplexer individually, reduced column periods (via GDX, GGS, or both) for columns containing grouped pixels can cause the display to target A given supply voltage has a higher refresh rate than would otherwise be possible without performing pixel grouping (for example, if the monitor were to fully display image data using native resolution). Alternatively, in foveated displays, which are known to perform at least a certain amount of grouped demultiplexing to produce macropixels, the display can be constructed with a larger number of columns while maintaining at least a minimum refresh rate that A higher refresh rate than would otherwise be possible without performing pixel grouping. For example, in embodiments where the display includes a first region displayed using macropixels produced using grouped demultiplexing and a second region having native resolution (e.g., without grouped demultiplexing), the reduction in The time taken to display columns containing pixels grouped using group demultiplexing may allow additional charging time to be allocated to areas on the display with native resolution. This allows the display area of the display to include a larger number of columns and allow sufficient charging time to be allocated to each column without increasing the overall refresh rate of the display.

In some embodiments, the DDIC determines the column period duration assigned to each column of the display based on the size of the macropixels to be displayed on the column when using metadata to synthesize the locations of macropixels to be displayed by the display. For example, in some embodiments, using a larger group of grouped demultiplexed data lines can reduce the column cycle of the above column to be written with image data. Additionally, the column period may be further reduced based on the number of grouped displayed columns using grouped gate scanning. In some embodiments, the DDIC configures the duration of a column period by configuring the timing of demultiplexer control signals (e.g., DMX1 through DMX6) and controlling the clock rate that enables the shifting of pulses between columns of the display. time.

In some embodiments, packet demultiplexing can be used to reduce power consumption of a display (eg, by reducing the source bias current used when charging multiple data lines). 16A illustrates a timing diagram illustrating different column cycles during which different levels of packet demultiplexing are performed, according to some specific examples. The control signals shown in Figure 16A are similar to those of Figure 12B, with no demultiplexing performed during the first column period, and different levels of grouping performed during the second, third and fourth column periods. Demultiplex to produce 2, 3 and 6 rows of macro pixels respectively. Although the increased load of charging multiple data lines simultaneously reduces the charge slew rate, resulting in longer charging times, as discussed above, this increase is not linear. In some embodiments, the time required for a data line to be fully charged is approximately five time constants (eg, 5τ _n , where n corresponds to a large number of data lines being charged in parallel). For example, as shown in data line voltage level curve 1602 of Figure 16A, individual data lines can each be fully charged at T≈5τ ₁ . On the other hand, groups of two, three, and six data lines can be fully charged at 5τ ₂ , 5τ ₃ , and 5τ ₆ below the 2T, 3T, and 6T times respectively, resulting in a flat period 1604 during which Charging completed. In some embodiments, instead of reducing the column period, for example, as described with respect to FIG. 15 , the flat period 1604 can be reduced by reducing the source driver bias current used to charge the data line, thereby reducing the charge transfer of the data line. rate (as shown by the modified voltage charge curve 1606) so that the time required for the data line to fully charge is more closely aligned with the allocated time period (eg, 2T, 3T, or 6T). Additionally, the power consumption level of the display is reduced by reducing the bias current when charging certain rows of data lines.

In some embodiments, bias current reduction may also be used in conjunction with grouped gate scanning (GGS) to achieve power consumption savings. 16B illustrates a timing diagram showing different column periods during which GGS is used to group different sets of columns, according to some specific examples. For example, Figure 16B shows: a first column period corresponding to the first column, in which the data itself is written to the first column; and a second column period corresponding to the second column, in which the gate enable signal is not provided (SEL2 skipped) This is because the second and third columns are grouped, two of which are currently being written to during the third column cycle (SEL2&SEL3). Therefore, data line data to be written to the pixels of these two columns may be loaded in two column periods (the second column period and the third column period), similar to what was discussed above with respect to FIG. 13 . In specific examples where the data lines are charged over multiple column periods (such as the period illustrated in Figure 16B), charging can occur in multiple steps. For example, the data line corresponding to DMX1 may be charged to a first level during a first time period T 1612 and to a full charge remainder during a second time period T 1614 . Because the data lines are able to charge over longer periods of time than when column grouping is not performed, the source bias current provided to the signal lines can be reduced, thereby reducing power consumption while allowing full charging of the data lines. In some specific examples, the DDIC determines whether to be in different columns based on the size of the macropixels to be displayed on the column (based on both GDX and GGS) when using metadata to synthesize the positions of macropixels to be displayed by the display. Source driver bias current provided during cycle.

Although FIGS. 15A-15B and 16A-16B respectively discuss currently reducing the column period or reducing the source bias, it should be understood that in other embodiments, a combination of these may be performed. For example, the embodiment shown in Figure 16B can shorten the column period for skipping a column select, while still providing some additional charging time for the data lines allowing the source bias current to be reduced.

17 is a flowchart illustrating a method of configuring a display to display foveated image data according to some embodiments. In some specific examples, the method may be executed by a processor (including a GPU and/or a DPU) and a DDIC of the display device. The GPU and DPU may correspond to the GPU 910 and DPU 920 shown in FIG. 9, and the DDIC may correspond to the DDIC 510 shown in FIG. 6 and/or the DDIC 930 shown in FIG. 9.

The GPU/DPU receives (1710) image data to be displayed on the display in a gaze point manner. In some embodiments, the image data includes foveated image data that includes image data associated with different display areas having different resolutions. For example, in some specific examples, the image data includes at least image data in a first region of a first resolution (eg, native resolution) and image data in a second region of a second, lower resolution.

The GPU/DPU generates (1720) metadata based on the received image data indicating the location of different display areas associated with different resolutions. In some embodiments, the metadata specifies the location of two or more display areas of the display, the effective resolution and/or macropixel size of each display area, or some combination thereof. In other embodiments, the metadata may indicate the gaze location on the display.

The GPU/DPU transmits (1730) the received image data and the generated subsequent device data to the DDIC. In some specific examples, the GPU/DPU uses one or more display stream compression algorithms such as DSC or VDC-M to compress the image data and metadata to generate a stream of one or more packets, and transmit the packets to DDIC.

The DDIC receives (1740) image data and generated post-processing data from the GPU/DPU. In some specific examples, the DDIC receives the image data and metadata in the form of a stream of encoded packets, and the DDIC decodes the packets to extract the image data and metadata.

The DDIC synthesizes (1750) the locations of macropixels to be displayed by the display based on the received downstream data. In some embodiments, DDIC's expander module uses metadata to determine which columns and rows of the display are to be grouped using grouped demultiplexing and grouped gate selection to create simultaneous operations at specific locations on the display. Load macropixels spanning m × n pixels with common image values. In some embodiments, the metadata may directly indicate the number of columns and rows to be grouped by the expander module. In other embodiments, where the metadata does not directly indicate the grouping of columns and rows, the expander module infers which columns and rows of the display should be grouped based on the metadata.

The DDIC configures (1760) control signals for performing grouping of columns and rows of the display based on the synthesized macropixel locations. In some embodiments, the expander module of the DDIC sets grouped demultiplexing parameters for set grouping of m rows and control parameters for performing grouped gate scans of set grouping of n columns, and Provides the timing of these parameters to create m × n macropixels. In some embodiments, the DDIC may further configure column period duration and/or source driver bias current based on macropixel location, such as to perform grouped demultiplexing and/or grouped demultiplexing while writing data. Gate scanning of rows of pixels increases the refresh rate and/or reduces the display's power consumption.

The DDIC operates 1770 the display by providing control signals to the display according to determined timing. In some embodiments, demultiplexer control signals provided to the demultiplexer allow each demultiplexer to provide signal line data to multiple data lines simultaneously, thereby grouping pixels on multiple adjacent data lines. Additionally, control parameters provided to the gate control circuitry of columns of the display are used to selectively group gate lines of adjacent columns together such that during the same column period (e.g., when a signal is received at the last column of the group When pulses are enabled) the gate select signal is supplied to all gate lines of the group. A combination of selective grouping of pixels in different rows and pixels in different columns is used to create macropixels that span multiple rows and columns.

18 is a flowchart illustrating a method of configuring a display to perform grouped demultiplexing to group pixels of adjacent rows of a display device, according to some embodiments. In some embodiments, the method may be performed by a DDIC of a display device having signal lines connected to data lines of the display via a plurality of demultiplexers. Each of the demultiplexers is coupled to a signal line configured to provide image data for a particular color channel, and a plurality of data lines corresponding to the particular color channel for each of the plurality of rows of pixels. In some embodiments, each demultiplexer is coupled to six data lines corresponding to six different rows of pixels.

The DDIC receives (1810) data indicating the grouping of rows of pixels for displaying image data on the pixels of the display. In some embodiments, the data corresponds to metadata associated with the received fixation image data. In some embodiments, the information is determined based on received metadata. In some embodiments, the information indicates different groupings of rows corresponding to different column periods. For example, the display may be configured to group pixels of adjacent rows into a first set (eg, two-row groups) within a first set of column periods, and to group them into a second set within a column period. Second set (e.g., three-row group).

The DDIC sets (1820) the demultiplexer control signal based on the grouping of rows as indicated by the received data. In some embodiments, the DDIC configures the control signals for each of a plurality of column periods based on how the rows are grouped during each column period, based on which columns of the display are to contain adjacent rows of grouped pixels. For example, during unpacketed column periods, the control signals are set to cause the demultiplexer to provide signal line data to each data line sequentially. On the other hand, during the column period of the packet to be executed, the control signal is set to cause the demultiplexer to provide signal line data to multiple data lines simultaneously (for example, a set of two, three, or six data lines simultaneously) .

The DDIC optionally configures the duration of one or more column cycles based on the level of demultiplexer packets to be executed during the column cycle (1830). In some specific examples, the DDIC is configured to reduce the duration of a column cycle based on a time constant for charging multiple data lines simultaneously based on a demultiplexer packet level. Since the time constant of charging does not scale in a linear manner, this allows the grouped data lines to be fully charged while reducing the extraneous time during which the data lines are fully charged. This can be used to increase the refresh rate of the display, but reduce the duration of pixels assigned to writing to certain columns. Additionally, in some embodiments, the DDIC may further reduce the duration of a column period based on whether a column is grouped with other columns using grouped gate selection.

The DDIC optionally configures the source bias current to be provided to the signal line during one or more column periods based on the level of demultiplexer grouping to be performed during the column period (1840). In some specific examples, the DDIC is configured to reduce the source bias current to be provided to the signal lines during the column period based on the time constant for charging multiple data lines simultaneously based on the demultiplexer grouping level. Since the charging time constant does not scale linearly, this allows the grouped data lines to be fully charged within a column cycle while reducing the overall power consumption of the display. Additionally, in some embodiments, the DDIC can further reduce source bias current based on whether a column is grouped with other columns using grouped gate selection.

The DDIC operates (1850) the display by providing demultiplexer control signals to the display's demultiplexer during each column period. When the enable pulses are shifted between columns of the display according to the configured column period duration, the demultiplexer control signal writes data to the pixels of the column (and any other columns grouped with the current column) in adjacent rows. Grouped pixels are configured. By grouping pixels in this way, macropixels are formed that span multiple rows and are used to render areas with lower resolution in the foveated display. Combined with grouped columns, m × n macropixels can be formed, allowing fine control of the effective resolution of different display areas.

The language used in this specification has been selected principally for readability and instructional purposes, and it may not have been selected to delineate or define the subject matter of the invention. Therefore, it is intended that the scope of the invention be limited not by this detailed description, but rather by the scope of any claims issued based on application herein. Accordingly, the disclosure of specific examples is intended to illustrate, but not to limit, the scope of the invention as set forth in the following claims.

100: Head Mounted Display (HMD) 105: Frame 110: Near Eye Display (NED) 200: Cross Section 210: Display Assembly 220: Eyeball 230: Exit Pupil 300: Waveguide Display 310: Source Assembly 320: Output Waveguide 330 :Controller 340: Source 345: Image light 350: Coupling element 360: Decoupling element 370: Scanning mirror assembly 400: Organic light emitting diode (OLED) 410: Substrate 420: Anode 430: Hole injection layer 440: Electron Hole transmission layer 450: Light-emitting layer 460: Barrier layer 470: Electron transmission layer 480: Cathode 500: OLED display device 510: Display driver integrated circuit (DDIC) 512: Driving transistor 520: Single crystal backplane 523: Single crystal or Polycrystalline silicon layer 525: silicon perforation 530: active display area 532: active matrix 533: upper emitting surface 534: transparent encapsulation layer 536: color filter 538: protective glass cover 540: display element 600: display device 610: timing controller 615: Data processing circuit 624: Signal line 625: Input/output (I/O) interface 630: Mobile Industry Processor Interface (MIPI) receiver 635: Gate driver 640: Bonding pad 645: Source driver circuit 700: Pixel 712: pixel 712A: pixel row 712B: pixel row 712N: pixel row 716: demultiplexer 722: pixel 722A: pixel row 722B: pixel row 722N: pixel row 732: pixel 732A: pixel row 732B: pixel row 732N: pixel Row 742: Pixel 742A: Pixel row 742B: Pixel row 742N: Pixel row 748: Signal line 802: Input image data 804: First image data 806: Second image data 808: Displayed image data 810: Displayed image data 812: First area 814: Second area 816: Third area 902: Focal point image data 904: Metadata 906: Packet 910: Graphics processing unit (GPU) 912: Composite function 914: Color aberration compensation (CAC) 916: Post-equipment data generation module 918: transmitter 920: display processing unit (DPU) 930: DDIC 932: receiver 934: image processing function 936: expander circuit/expander 940: display component 1002: image data 1004: image data 1006: Center area 1008: Area 1010: Area 1012: Area 1102: Demultiplexer 1102A: First Demultiplexer 1102B: Second Demultiplexer 1102C: Demultiplexer 1102D: Demultiplexer 1102E: Demultiplexer Multiplexer 1102F: Demultiplexer 1102G: Demultiplexer 1102H: Demultiplexer 1102I: Demultiplexer 1104: Demultiplexer 1104A: Demultiplexer 1104B: Demultiplexer 1104C: Demultiplexer 1104D: Demultiplexer 1104E: Demultiplexer 1104F: Demultiplexer 1106A: First pixel 1108: Metal segment 1110: Contact 1202: Demultiplexer 1204: Data line 1206: Gate line 1212A: No. First demultiplexer 1212B: Second demultiplexer 1302: Demultiplexer 1304: Data line 1306: Gate line 1402: Source driver 1404: Signal line 1406: Demultiplexer 1408: Data line 1408-1 :Data line 1408-2: Data line 1408-m: Data line 1502: First timing diagram 1504: Exogenous flat period 1510: Second timing diagram 1512: First timing diagram 1514: Skip 1516: Enable pulse 1602: Data line voltage level curve 1604: flat period 1606: modified voltage charging curve 1612: first time period T 1614: second time period T 1710: receiving step 1720: generating step 1730: transmitting step 1740: receiving step 1750: Synthesis step 1760: Configuration step 1770: Operation step 1810: Reception step 1820: Setting step 1830: Configuration step 1840: Configuration step 1850: Operation step A: Interface AGND: Ground B1: Data value/signal line value B2: Data Value B3: data value B4: data value B5: data value B6: data value C _D : data line capacitance CLK: clock signal C _P : SD output pad capacitance Cst1: capacitor Cst2: capacitor DATA: image data DL: data line DL1 :Data line DL2: Data line DL3: Data line DL4: Data line DMX1: Demultiplexer control signal/control line DMX2: Demultiplexer control signal/control line DMX3: Demultiplexer control signal/control line DMX4: Demultiplexer control signal/control line DMX5: Demultiplexer control signal/control line DMX6: Demultiplexer control signal/control line DMXn: Control signal ELVDD: High voltage level/High voltage source ELVSS: Low voltage level Quasi/low voltage source GL: Gate line GLA: Gate line GLB: Gate line GLN: Gate line M _D : Driving transistor OLED: Organic light emitting diode R _D : Data line resistance R _E : SD output electrostatic Discharge (ESD) resistance REST: switch R _S : source driver (SD) equivalent resistance R _X : demultiplexer equivalent resistance RST: reset signal SEL: data selection switch SEL1: enable signal SEL2: gate line SEL3 :Gate line SEL4: Gate selection signal/gate line SW: Emission switch T: Time period T _ROW : Column period V _DATA : Pixel data

[FIG. 1A] and [FIG. 1B] are diagrams of a head-mounted display (HMD) including a near-eye display (NED) according to some specific examples.

[FIG. 2] is a cross-sectional view of the HMD as illustrated in FIG. 1A or 1B, according to some specific examples.

[Fig. 3] illustrates a perspective view of a waveguide display according to some specific examples.

[Figure 4] depicts a simplified organic light emitting diode (OLED) structure according to some specific examples.

[Fig. 5] is a schematic diagram of an OLED display device architecture including a display driver integrated circuit (DDIC) according to some specific examples.

[Fig. 6] is a schematic diagram of an OLED display device according to some specific examples.

[FIG. 7A] illustrates an exemplary pixel configuration of a display device according to some embodiments.

[FIG. 7B] is a circuit diagram of a pixel of a display device according to some specific examples.

[FIG. 8] illustrates a high-level diagram illustrating an implementation of a foveation display according to some specific examples.

[FIG. 9] illustrates a diagram illustrating a foveated display architecture according to some specific examples.

[FIG. 10] A diagram illustrating an example of extending image data to be displayed on a foveated display with macropixels of different sizes, according to some specific examples.

[FIG. 11A] and [FIG. 11B] illustrate diagrams showing different configurations in which a demultiplexer may be coupled to data lines of a display according to some specific examples.

[FIG. 12A] and [FIG. 12B] illustrate diagrams showing how to control the demultiplexer of a display to execute GDX according to some specific examples.

[FIG. 12C] and [FIG. 12D] illustrate diagrams showing how to control the demultiplexer of a display to generate 4-pixel macropixels according to some specific examples.

[Figure 13] illustrates a diagram showing how combinations of GDX and GGS can be used to generate macropixels of various sizes according to some specific examples.

[FIG. 14] illustrates a high-level diagram showing the electrical characteristics of a set of signal lines, demultiplexers, and data lines according to some specific examples.

[Figure 15A] illustrates an example of how line time can be reduced when executing GDX according to some specific examples.

[Figure 15B] illustrates an example of how line time can be reduced when executing GDX and GGS according to some specific examples.

[FIG. 16A] illustrates a timing diagram showing different column cycles during which different levels of packetized demultiplexing are performed according to some specific examples.

[FIG. 16B] illustrates a timing diagram showing different column periods during which GGS is used to group different sets of columns, according to some specific examples.

[FIG. 17] is a flowchart illustrating a method of configuring a display to display foveated image data according to some specific examples.

18 is a flowchart of a method of configuring a display to perform grouped demultiplexing to group pixels of adjacent rows of a display device according to an illustration of some specific examples.

The drawings depict specific examples of the invention for purposes of illustration only.

902:Focus image data

904: Metadata

906: Packet

910: Graphics Processing Unit (GPU)

912:Composite function

914: Color aberration compensation (CAC)

916: Metadata generation module

918:Transmitter

920: Display Processing Unit (DPU)

930:DDIC

932:Receiver

934:Image processing function

936:Expander circuit/expander

940:Display component

Claims (21)

A method that contains: receiving image data to be displayed by a display device, wherein the image data includes a plurality of display areas associated with different image resolutions; Generate metadata based on the received image data, wherein the metadata indicates the positions of the plurality of display areas associated with different image resolutions; transmit the image data together with the generated metadata to the display device; The display device includes a display area, and the display area includes a plurality of pixels configured in a plurality of columns and a plurality of rows. The method further includes, at a display driver integrated circuit (DDIC) of the display device: receive the transmitted image data with the metadata; The position of one or more macropixels to be displayed by the display area is determined based on the metadata, where each macropixel corresponds to a group of native pixels of the display area, and the image data is simultaneously loaded onto the display area. ; Configuring control signals for grouping columns and rows of the display area in a determined timing based on the determined positions of the one or more macropixels; The image data is displayed by providing the control signals according to the determined timing. The method of claim 1, wherein the metadata indicates a location on the display device corresponding to a gaze direction of a user, and the method further includes determining, at the DDIC of the display device, the gaze direction. The location of multiple display areas. The method of claim 1, wherein the metadata indicates the plurality of display areas and respective image resolutions associated with each display area. For example, the method of request item 1 further includes: Format the metadata to be compatible with a compression algorithm; and Transmitting the image data together with the generated metadata to the display device includes encoding the image data and the generated metadata according to the compression algorithm. The method of claim 4, wherein the compression algorithm is Display Stream Compression (DSC) or VESA Display Compression M (VDC-M). Such as the method of request item 1, where: Each column of the plurality of columns includes a respective gate line configured to provide a gate enable signal to the pixels of the column; Each row of the plurality of rows includes a respective data line configured to provide the image data to the pixels of the row, and wherein the display device includes a demultiplexer connected to a signal line from a source driver circuit and configured to demultiplex a data line of the respective data lines in accordance with the control signals The data lines in the set are selectively coupled to the signal lines to charge the data lines. The method of claim 6, wherein the data lines in the set of data lines correspond to a common color channel of adjacent rows of pixels in the plurality of rows. Such as the method of claim 6, wherein the control signals are configured to group the columns and rows of the display area to include: configuring the control signals provided to the demultiplexer to simultaneously couple a plurality of data lines in the set of data lines to the signal line based on the determined position of the one or more macropixels, to charge the plurality of data lines simultaneously during one or more time periods. The method of claim 6, wherein the determined timing is based on a timing at which an enable pulse is sequentially provided from a gate scan line to the gate scan driver circuits of the plurality of columns of the display area. Such as the method of claim 9, wherein the control signals are configured to group the columns and rows of the display area to include: The control signals provided to the gate scan driver circuits of the plurality of columns are configured to selectively group columns of the plurality of columns based on the determined position of the one or more macropixels. For example, the method of request item 9 further includes: The timing of the enable pulses is configured based on the grouping of columns and rows of the display area. The method of claim 11, wherein the configured timing of the enable pulses defines a refresh rate of the display device, and wherein the regions of the display area containing macropixels corresponding to groupings of columns and rows The timing of enable pulses is configured to increase the refresh rate of the display device beyond what would be possible if only native resolution image data were displayed in the display area. For example, the method of request item 1 further includes: A source driver power level of the display device is configured based on the grouping of columns and rows of the display area. A display device comprising: A display area including a plurality of pixels arranged in a plurality of columns and a plurality of rows, each column of the plurality of columns including a respective gate configured to provide a gate enable signal to the pixels of the column. epipolar lines, and each row of the plurality of rows includes a respective data line configured to provide image data to the pixels of that row; A display driver integrated circuit (DDIC) containing: A receiver configured to receive the image data to be displayed by the display device, wherein the image data includes a plurality of display areas associated with different image resolutions, and an indication of the image data associated with the different image resolutions. Metadata for the positions of multiple display areas; An expander circuit configured to: The position of one or more macropixels to be displayed at the display area is determined based on the metadata, where each macropixel corresponds to a grouping of native pixels in the display area, and the image data is simultaneously loaded into the display area. on; and Configuring control signals for grouping columns and rows of the display area in a determined timing based on the determined positions of the one or more macropixels; and a source driver circuit; A demultiplexer connected to a signal line from a source driver circuit and configured to selectively couple data lines in a set of respective data lines based on the control signals. Connect to the signal line to charge the data lines; Wherein based on the determined position of the one or more macro pixels, the control signals are provided to the demultiplexer to simultaneously couple a plurality of data lines in the data line set to the signal line, so as to Or charge the plurality of data lines simultaneously during multiple time periods. The display device of claim 14, wherein the metadata indicates a location on the display device corresponding to a gaze direction of a user, and wherein the expander circuit is further configured to determine the plurality of numbers based on the gaze direction. The position of the display area. The display device of claim 14, wherein the metadata indicates the plurality of display areas and respective image resolutions associated with each display area. The display device of claim 14, wherein the image data and the metadata are encoded according to a compression algorithm including at least one of Display Stream Compression (DSC) or VESA Display Compression M (VDC-M) packet is received. The display device of claim 14, wherein the data lines in the data line set correspond to a common color channel of pixels in adjacent rows in the plurality of rows. The display device of claim 14, wherein the determined timing is based on a timing at which an enable pulse is sequentially provided from a gate scan line to a gate scan driver circuit, and the gate scan driver circuits are connected The respective gate lines to the plurality of columns of the display area. The display device of claim 14, wherein the DDIC further includes a timing controller configured to set the timing of enable pulses based on the grouping of columns and rows of the display area. The display device of claim 14, wherein the DDIC is configured to modify a source driver power level of the display device based on the grouping of columns and rows of the display area.

Images