TW202203473A - Engineered substrate structure for power and rf applications - Google Patents

Abstract

A substrate includes a support structure comprising: a polycrystalline ceramic core; a first adhesion layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesion layer; a second adhesion layer coupled to the conductive layer; and a barrier layer coupled to the second adhesion layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystalline silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystalline silicon layer.

Description

Engineered substrate structures for power and RF applications

This patent application claims US Provisional Patent Application Serial No. 62/350,084, filed June 14, 2016, entitled "ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS" and the benefit of priority of U.S. Provisional Patent Application No. 62/350,077, filed June 14, 2016, entitled "ENGINEERED SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURE," for all The disclosures of these applications are hereby incorporated by reference in their entirety.

The present invention generally relates to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes.

Light emitting diode (LED) structures are usually epitaxially grown on sapphire substrates. There are many products currently using LED components, including lighting, computer monitors and other display devices.

Growing GaN-based LED structures on sapphire substrates is a heterogeneous epitaxial growth process because the substrate and epitaxial layers are composed of different materials. Due to the hetero-epitaxial growth process, epitaxially grown materials can exhibit various adverse effects, including reduced uniformity and reduced metrics related to the electronic/optical properties of the epitaxial layer. Accordingly, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures.

The present invention generally relates to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has been applied to methods and systems for providing substrate structures suitable for epitaxial growth characterized by a coefficient of thermal expansion (CTE) that substantially matches the epitaxial layers grown thereon. The methods and techniques can be applied to a wide variety of semiconductor processing operations.

According to an embodiment of the present invention, a substrate is provided. The substrate includes a support structure including: a polycrystalline ceramic core; a first adhesive layer coupled to the polycrystalline ceramic core; a conductive layer coupled to the first adhesive layer; a first adhesive layer coupled to the conductive layer two adhesive layers; and a barrier layer coupled to the second adhesive layer. The substrate also includes a silicon oxide layer coupled to the support structure, a substantially single crystal silicon layer coupled to the silicon oxide layer, and an epitaxial III-V layer coupled to the substantially single crystal silicon layer.

According to another embodiment of the present invention, a method of manufacturing a substrate is provided. The method includes forming a support structure by providing a polycrystalline ceramic core; encapsulating the polycrystalline ceramic core in a first adhesive shell; enclosing the first adhesive shell in a conductive shell; wrapping the conductive shell encapsulating in a second adhesive shell; and encapsulating the second adhesive shell in a barrier shell. The method also includes bonding a bonding layer to the support structure, bonding a substantially single crystal silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystal silicon layer, and by forming an epitaxial silicon layer on the substantially single crystal silicon layer An epitaxial III-V layer is formed by epitaxial growth on the epitaxial silicon layer.

According to an embodiment of the present invention, an engineering substrate structure is provided. The engineered substrate structure includes a support structure, a bonding layer coupled to the support structure, a substantially single crystal silicon layer coupled to the bonding layer, and an epitaxial single crystal silicon layer coupled to the substantially single crystal silicon layer. The support structure includes a polycrystalline ceramic core, a first adhesive layer coupled to the polycrystalline ceramic core, a conductive layer coupled to the first adhesive layer, a second adhesive layer coupled to the conductive layer, and a coupling to the barrier shell of the second adhesive layer.

Numerous benefits over conventional techniques are realized through the present invention. For example, embodiments of the present invention provide engineered substrate structures with CTE matched to gallium nitride series epitaxial layers suitable for optical, electronic and optoelectronic applications. The encapsulation layer, which acts as an integral part of the engineered substrate structure, prevents impurities present in the central portion of the substrate from diffusing to the semiconductor processing environment in which the engineered substrate is used. Key properties related to the substrate material, including thermal expansion coefficient, lattice mismatch, thermal stability, and shape control are independently designed to improve (eg, optimize) match to the GaN family of epitaxial and device layers, and Match with different component architectures and performance goals. Process integration is simplified because the layers of substrate material are integrated together in conventional semiconductor manufacturing processes. These and other embodiments of the present invention, together with their many advantages and features, are described in greater detail below and in the accompanying drawings.

Embodiments of the present invention relate to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention has been applied to methods and systems for providing substrate structures suitable for epitaxial growth characterized by a coefficient of thermal expansion (CTE) that substantially matches the epitaxial layers grown thereon. The methods and techniques can be applied to a wide variety of semiconductor processing operations.

FIG. 1 is a simplified schematic diagram illustrating an engineering substrate structure according to an embodiment of the present invention. The engineered substrate 100 illustrated in FIG. 1 is suitable for a wide variety of electronic and optical applications. The engineered substrate includes a core 110 that may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the epitaxial material to be grown on the engineered substrate 100 . The epitaxial material 130 is illustrated as optional because the epitaxial material 130 is not required as a component of the engineered substrate, but the epitaxial material 130 will typically be grown on the engineered substrate.

For applications involving the growth of gallium nitride (GaN) series materials (including epitaxial layers of GaN series layers), the core 110 may be a polycrystalline ceramic material such as polycrystalline aluminum nitride (AlN), polycrystalline Aluminum (AlN) may include bonding materials such as yttria. Other materials may be used for the core 110, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide ( Ga ₂ O ₃ ) and the like.

The thickness of the core may be on the order of 100 μm to 1,500 μm, eg 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which may be referred to as a shell or an encapsulation shell. In one embodiment, the first adhesive layer 112 includes a tetraethylorthosilicate (TEOS) layer with a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the bonding layer in some embodiments, other materials may be utilized to provide bonding between the subsequently deposited layer and underlying layers or materials (eg, ceramics, especially polycrystalline ceramics), in accordance with one embodiment of the present invention. For example, _SiO2 or other silicon oxides _{( SixOy} ) adhere well to ceramic materials and provide a suitable surface for subsequent deposition (eg, conductive materials). In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the first adhesive layer 112 may be formed using an LPCVD process. The first adhesive layer 112 provides a surface on which subsequent layers are adhered to form elements of the engineered substrate structure.

In addition to using LPCVD processes, furnace-based processes, etc. to form the encapsulated first adhesion layer, other semiconductor processes, including CVD processes or similar deposition processes, may be used in accordance with embodiments of the present invention. As an example, a deposition process that coats a portion of the core may be used, the core may be turned over, and the deposition process may be repeated to coat other portions of the core. Thus, while LPCVD techniques are used in some embodiments to provide fully encapsulated structures, other film formation techniques may be used depending on the particular application.

A conductive layer 114 is formed surrounding the adhesive layer 112 . In one embodiment, the conductive layer 114 is a polysilicon (ie, polysilicon) shell formed around the first adhesion layer 112, since polysilicon can exhibit poor adhesion to ceramic materials. In embodiments where the conductive layer is polysilicon, the thickness of the polysilicon layer may be on the order of 500-5,000 Å, eg, 2,500 Å. In some embodiments, the polysilicon layer may be formed as a shell completely surrounding the first adhesion layer 112 (eg, the TEOS layer), thereby forming a fully encapsulated first adhesion layer, and may be formed using an LPCVD process. In other embodiments, as discussed below, the conductive material may be formed on a portion of the adhesive layer, such as the lower half of the substrate structure. In some embodiments, the conductive material may be formed as a fully encapsulated layer and the conductive material on one side of the substrate structure subsequently removed.

In one embodiment, the conductive layer 114 may be a polysilicon layer doped to provide a highly conductive material, such as boron doped to provide a p-type polysilicon layer. In some embodiments, doping with boron is at a level of 1×10 ¹⁹ cm ⁻³ to 1×10 ²⁰ cm ⁻³ to provide high conductivity. Other dopants at different dopant concentrations (eg, phosphorous, arsenic, bismuth, etc. with dopant concentrations ranging from 1 x 10 ¹⁶ cm ^-3 to 5 x 10 ¹⁸ cm ^-3 ) can be used to provide suitable conductive layers of n-type or p-type semiconductor materials. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

The presence of conductive layer 114 is useful during electrostatically clamping an engineered substrate to a semiconductor processing tool, such as a tool with an electrostatic chuck (ESC). After processing in the semiconductor processing tool, the conductive layer 114 can be quickly de-clamped. Accordingly, embodiments of the present invention provide substrate structures that can be processed in the same manner as conventional silicon wafers. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

A second adhesive layer 116 (eg, a TEOS layer having a thickness on the order of 1000 Å) is formed surrounding the conductive layer 114 . In some embodiments, the second adhesion layer 116 completely surrounds the conductive layer 114 to form a fully encapsulated structure, and may be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including deposition of spin-on dielectrics.

A barrier layer 118 , such as a silicon nitride layer, is formed surrounding the second adhesion layer 116 . In one embodiment, the barrier layer 118 is a silicon nitride layer 118 having a thickness on the order of 2,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 116 to form a fully encapsulated structure, and may be formed using an LPCVD process. In addition to the silicon nitride layer, amorphous materials (including SiCN, SiON, AlN, SiC, etc.) can be used as the barrier layer. In some implementations, the barrier layer 118 includes several sublayers that are built to form the barrier layer. Thus, the term barrier layer is not intended to denote a single layer or a single material, but rather encompasses one or more materials layered in a composite manner. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

In some embodiments, barrier layer 118 (eg, a silicon nitride layer) prevents elements (eg, yttrium oxide (ie, yttrium oxide), oxygen, metal impurities, other trace elements, etc.) present within core 110 from diffusing and/or Outgases enter the environment of a semiconductor processing chamber in which engineered substrates may be present, such as during high temperature (eg, 1,000°C) epitaxial growth processes. Using the encapsulation layers described herein, ceramic materials, including polycrystalline AlN designed for non-clean room environments, can be used in semiconductor process flows and clean room environments.

FIG. 2A is a secondary ion mass spectrometry (SIMS) curve illustrating species concentration as a function of depth for engineered structures in accordance with one embodiment of the present invention. The engineered structure does not include barrier layer 118 . Referring to Figure 2A, several species present in the ceramic core, such as yttrium, calcium, and aluminum, are reduced to negligible concentrations in the engineered layers 120/122. Concentrations of calcium, yttrium, and aluminum decreased by three, four, and six orders of magnitude, respectively.

Figure 2B is a SIMS plot illustrating the species concentration as a function of depth after annealing for an engineered structure without a barrier layer in accordance with one embodiment of the present invention. As discussed above, during semiconductor processing operations, such as epitaxial growth of GaN series layers, engineered substrate structures provided by embodiments of the present invention may be exposed to high temperatures (~1,100°C) for several hours.

For the curve illustrated in Figure 2B, the engineered substrate structure was annealed at 1,100°C for 4 hours. As shown in Figure 2B, calcium, yttrium, and aluminum, originally present at low concentrations in the freshly deposited untreated sample, have diffused into the engineered layer to similar concentrations as the other elements.

Figure 2C is a SIMS plot illustrating the species concentration as a function of depth after annealing for an engineered structure with a barrier layer in accordance with one embodiment of the present invention. The integration of the diffusion barrier layer 118 (eg, a silicon nitride layer) into the engineered substrate structure prevents calcium, yttrium, and aluminum from diffusing into the engineered layer during the annealing process, which occurs when the diffusion barrier layer is not present. As illustrated in Figure 2C, after annealing, the calcium, yttrium, and aluminum present in the ceramic core remain in low concentrations in the engineered layer. Thus, the use of a barrier layer 118 (eg, a silicon nitride layer) prevents these elements from diffusing through the diffusion barrier layer, thereby preventing release of these elements into the environment surrounding the engineered substrate. Similarly, any other impurities contained in the bulk ceramic material will also be contained by the barrier layer.

Typically, the ceramic material used to form the core 110 is fired at a temperature in the range of 1800°C. It is expected that this process will drive off a large amount of impurities present in the ceramic material. Such impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttrium oxide as a sintering agent. Subsequent diffusion of these impurities is expected to be insignificant during subsequent epitaxial growth processes performed at much lower temperatures in the range of 800°C to 1100°C. However, contrary to conventional expectations, the inventors have determined that substantial diffusion of elements through the layers of the engineered substrate occurs during the epitaxial growth process even at temperatures much lower than the firing temperature of the ceramic material. Accordingly, embodiments of the present invention integrate barrier layers 118 (eg, silicon nitride layers) to prevent outdiffusion of background elements from polycrystalline ceramic materials (eg, AlN) to engineered layers 120/122 and epitaxial layers (eg, optional GaN layer 130). The silicon nitride layer 118, which encapsulates the underlying layers and materials, provides the desired barrier function.

As illustrated in FIG. 2B , elements originally present in core 110 , including yttrium, diffuse into and through first TEOS layer 112 , polysilicon layer 114 , and second TEOS layer 116 . However, the presence of the silicon nitride layer 118 prevents these elements from diffusing through the silicon nitride layer, thereby preventing the release of these elements into the environment surrounding the engineered substrate, as illustrated in Figure 2C.

Referring again to FIG. 1, a bonding layer 120 (eg, a silicon oxide layer) is deposited over a portion of the barrier layer 118 (eg, the top surface of the barrier layer), and the bonding layer is subsequently used in the bonding process of the substantially single crystal silicon layer 122 120. In some embodiments, the thickness of the bonding layer 120 may be about 1.5 μm.

The substantially monocrystalline layer 122 is suitable for use as a growth layer during the epitaxial growth process for forming the epitaxial material 130 . In some embodiments, epitaxial material 130 includes a 2 μm to 10 μm thick GaN layer that can be used as one of several layers used in optoelectronic components, RF components, power components, and the like. In one embodiment, substantially monocrystalline layer 122 includes a substantially monocrystalline silicon layer attached to silicon oxide layer 118 using a layer transfer process.

FIG. 3 is a simplified schematic diagram illustrating an engineering substrate structure according to an embodiment of the present invention. The engineered substrate 300 illustrated in FIG. 3 is suitable for a wide variety of electronic and optical applications. The engineered substrate includes a core 110 that may have a CTE that substantially matches the coefficient of thermal expansion (CTE) of the epitaxial material 130 to be grown on the engineered substrate 300 . The epitaxial material 130 is illustrated as optional because the epitaxial material 130 is not required as a component of the engineered substrate, but the epitaxial material 130 will typically be grown on the engineered substrate.

For applications involving the growth of gallium nitride (GaN) series materials, including epitaxial layers of GaN series layers, core 110 may be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core may be on the order of 100 μm to 1,500 μm, eg 725 μm. The core 110 is encapsulated in a first adhesive layer 112, which may be referred to as a shell or an encapsulation shell. In this embodiment, the first adhesive layer 112 fully encapsulates the core, although this is not required by the present invention, as discussed in additional detail with respect to FIG. 4 .

In one embodiment, the first adhesive layer 112 includes a tetraethylorthosilicate (TEOS) layer with a thickness on the order of 1,000 Å. In other embodiments, the thickness of the first adhesive layer varies, for example, from 100 Å to 2,000 Å. Although TEOS is used for the adhesion layer in some embodiments, other materials may be utilized to provide adhesion between the subsequently deposited layer and the underlying layer or material in accordance with one embodiment of the present invention. For example, _SiO2 , SiON, and the like adhere well to ceramic materials and provide a suitable surface for subsequent deposition (eg, conductive materials). In some embodiments, the first adhesive layer 112 completely surrounds the core 110 to form a fully encapsulated core, and the first adhesive layer 112 may be formed using an LPCVD process. The adhesive layer provides a surface on which subsequent layers adhere to form elements of the engineered substrate structure.

In addition to using LPCVD processes, furnace-based processes, etc. to form the encapsulated adhesion layer, other semiconductor processes may be used in accordance with embodiments of the present invention. As an example, a deposition process (eg, CVD, PECVD, or similar process) that coats a portion of the core may be used, the core may be turned over, and the deposition process may be repeated to coat other portions of the core.

A conductive layer 314 is formed on at least a portion of the first adhesive layer 112 . In one embodiment, the conductive layer 314 includes polysilicon (ie, polysilicon) formed on the lower portion (eg, lower half or backside) of the core/bond layer structure by a deposition process. In embodiments in which the conductive layer is polysilicon, the thickness of the polysilicon layer may be on the order of several thousand angstroms, such as 3,000 Å. In some embodiments, the polysilicon layer may be formed using an LPCVD process.

In one embodiment, the conductive layer 314 may be a polysilicon layer doped to provide a highly conductive material, eg, the conductive layer 314 may be doped with boron to provide a p-type polysilicon layer. In some embodiments, doping with boron is at a level ranging from about 1×10 ¹⁹ cm ⁻³ to 1×10 ²⁰ cm ⁻³ to provide high conductivity. The presence of conductive layers is useful during electrostatic clamping of engineered substrates to semiconductor processing tools, such as tools with electrostatic chucks (ESCs). The conductive layer 314 can be quickly de-clamped after processing. Accordingly, embodiments of the present invention provide substrate structures that can be processed in the same manner as conventional silicon wafers. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

A second adhesion layer 316 (eg, a second TEOS layer) is formed surrounding the conductive layer 314 (eg, a polysilicon layer). The thickness of the second adhesive layer 316 is on the order of 1,000 Å. In some embodiments, the second adhesive layer 316 may completely surround the conductive layer 314 and the first adhesive layer 112 to form a fully encapsulated structure, and may be formed using an LPCVD process. In other embodiments, the second adhesive layer 316 only partially surrounds the conductive layer 314 , eg, terminating at the location illustrated by the plane 317 , which may be aligned with the top surface of the conductive layer 314 . In this example, the top surface of conductive layer 314 would be in contact with a portion of barrier layer 118 . Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

A barrier layer 118 (eg, a silicon nitride layer) is formed surrounding the second adhesion layer 316 . In some embodiments, the thickness of the barrier layer 118 is on the order of 4,000 Å to 5,000 Å. In some embodiments, the barrier layer 118 completely surrounds the second adhesion layer 316 to form a fully encapsulated structure, and may be formed using an LPCVD process.

In some embodiments, a silicon nitride barrier layer is used to prevent elements present within the core 110 (eg, yttrium oxide (ie, yttrium oxide), oxygen, metal impurities, other trace elements, etc.) from diffusing and/or outgassing possible into it In the environment of semiconductor processing chambers where substrates are engineered, such as during high temperature (eg, 1,000°C) epitaxial growth processes. Using the encapsulation layers described herein, ceramic materials, including polycrystalline AlN designed for non-clean room environments, can be used in semiconductor process flows and clean room environments.

FIG. 4 is a simplified schematic diagram illustrating an engineering substrate structure according to another embodiment of the present invention. In the embodiment illustrated in FIG. 4 , the first adhesive layer 412 is formed on at least a portion of the core 110 but does not encapsulate the core 110 . In this embodiment, a first adhesive layer 412 is formed on the lower surface of the core 110 (the backside of the core 110) to enhance the adhesion of a subsequently formed conductive layer 414, as described more fully below. Although FIG. 4 only illustrates the bonding layer 412 on the lower surface of the core 110, it will be understood that depositing the bonding layer material on other portions of the core will not adversely affect the performance of the engineered substrate structure, and this Class materials may exist in various embodiments. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

The conductive layer 414 does not encapsulate the first adhesive layer 412 and the core 110 , but is generally aligned with the first adhesive layer 412 . Although conductive layer 414 is illustrated as extending along the bottom or backside of first adhesive layer 412 and up along a portion of the side of first adhesive layer 412, extending along vertical sides is not a requirement of the present invention. Thus, embodiments may utilize deposition on one side of the substrate structure, masking on one side of the substrate structure, and the like. The conductive layer 414 may be formed on a portion of one side (eg, bottom/back side) of the first adhesive layer 412 . Conductive layer 414 provides electrical conduction on one side of the engineered substrate structure, which can be advantageous in RF and high power applications. The conductive layer may include doped polysilicon discussed with respect to conductive layer 114 in FIG. 1 .

A portion of core 110, portions of first adhesive layer 412, and conductive layer 414 are covered by second adhesive layer 416 to enhance adhesion of barrier layer 418 to the underlying material. As discussed above, barrier layer 418 forms an encapsulation structure to prevent diffusion from underlying layers.

In addition to the semiconductor series conductive layers, in other embodiments, the conductive layer 414 is a metal layer, such as 500 Å titanium or the like.

Referring again to Figure 4, depending on the implementation, one or more layers may be removed. For example, layers 412 and 414 may be removed, leaving only single bond shell 416 and barrier layer 418 . In another embodiment, only layer 414 may be removed. In this embodiment, layer 412 may also balance the stress and wafer bow caused by layer 120 deposited on top of layer 418 . The construction of a substrate structure with an insulating layer on the top side of the core 110 (eg, only an insulating layer between the core 110 and the layer 120 ) would provide benefits for power/RF applications where a highly insulating substrate is required.

In another embodiment, barrier layer 418 may directly encapsulate core 110 , followed by conductive layer 414 and then adhesive layer 416 . In this embodiment, layer 120 may be deposited directly onto adhesive layer 416 from the top side. In yet another embodiment, an adhesive layer 416 may be deposited on the core 110 , followed by a barrier layer 418 , followed by a conductive layer 414 and another adhesive layer 412 .

Although some embodiments have been discussed with respect to layers, the term layer should be understood such that a layer may include several sub-layers constructed to form a layer of interest. Thus, the term layer is not intended to denote a single layer composed of a single material, but rather encompasses one or more materials layered in a composite manner to form a desired structure. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

5 is a simplified flow diagram illustrating a method of fabricating an engineered substrate in accordance with one embodiment of the present invention. The method can be used to fabricate substrates that match the CTE of one or more epitaxial layers grown on the substrate. The method 500 includes forming a shell (eg, a tetraethylorthosilicate (TEOS) shell) by providing a polycrystalline ceramic core (510), encapsulating the polycrystalline ceramic core in a first adhesive layer (512), and incorporating The first adhesive layer is encapsulated in a conductive shell (eg, a polysilicon shell) (514) to form a support structure. The first adhesive layer can be formed as a single layer of TEOS. The conductive shell can be formed as a single layer of polysilicon.

The method also includes encapsulating the conductive shell in a second adhesive layer (eg, a second TEOS shell) (516), and encapsulating the second adhesive layer in a barrier layer shell (518). The second adhesive layer can be formed as a single layer of TEOS. The barrier shell can be formed as a monolayer of silicon nitride.

Once the support structure is formed by processes 510-518, the method further includes bonding a bonding layer (eg, a silicon oxide layer) to the support structure (520), and bonding a substantially single crystal layer (eg, a substantially single crystal silicon layer) to the oxide Silicon layer (522). Other substantially single crystal layers may be used in accordance with embodiments _of the present invention, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, _Ga2O3 , ZnO, and the like. Bonding of the bonding layers may include depositing bonding material followed by performing a planarization process as described herein. In the embodiments described below, connecting a substantially monocrystalline layer (eg, a substantially monocrystalline silicon layer) to the bonding layer uses a layer transfer process, wherein the substantially monocrystalline layer is a monocrystalline silicon layer transferred from a silicon wafer.

Referring to FIG. 1, the bonding layer 120 may be formed by depositing a thick (eg, 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process to thin the oxide to a thickness of about 1.5 μm. The thick initial oxide is used to fill voids and surface features that exist on the support structure, which may exist after the polycrystalline core is fabricated and continue to exist when the encapsulation layer illustrated in Figure 1 is formed. The CMP process provides a substantially flat surface free of voids, particles or other features, which can then be used to bond the substantially monocrystalline layer 122 (eg, substantially monocrystalline silicon layer) to the bonding layer 120 during the wafer transfer process. It will be appreciated that the bonding layer 120 need not be characterized by an atomically flat surface, but rather should provide a generally flat surface that will support the bonded substantially single crystal layer (eg, a substantially single crystal silicon layer) with the desired reliability.

A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120 . In some embodiments, silicon wafers (eg, silicon (111) wafers) are implanted to form split planes. After wafer bonding, the silicon substrate can be removed along with the portion of the single crystal silicon layer below the split plane, resulting in the lift-off single crystal silicon layer 122 shown in FIG. 1 . The thickness of the substantially single crystal layer 122 can be varied to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 can be changed to meet the specifications of the application. Additionally, the doping level and distribution in the substantially single crystal layer 122 can be varied to meet the specifications of a particular application.

The method illustrated in Figure 5 may also include smoothing the substantially single crystal layer (524). In some embodiments, the thickness and surface roughness of the substantially single crystal layer 122 can be modified to obtain high quality epitaxial growth. Different device applications may have slightly different specifications with respect to the thickness and surface smoothness of the substantially single crystal layer 122 . The splitting process delaminates the substantially single crystal layer 122 from the bulk single crystal silicon wafer at the peak of the implanted ion distribution. After splitting, the substantially monocrystalline layer 122 can be adjusted or modified in several ways and then used as a growth surface for epitaxial growth of other materials, such as gallium nitride.

First, the transferred substantially single crystal layer 122 may contain a small residual hydrogen concentration and may have some crystal damage from the cloth plant. Therefore, it may be beneficial to remove thin portions of the transferred substantially single crystal layer 122 where the lattice is damaged. In some embodiments, the depth of the cloth plant can be adjusted to be greater than the desired final thickness of the substantially monocrystalline layer 122 . The additional thickness allows removal of the damaged thin portion of the transferred substantially single crystal layer, leaving an undamaged portion of the desired final thickness.

Second, the overall thickness of the substantially single crystal layer 122 may need to be adjusted. In general, it may be desirable to make the substantially monocrystalline layer 122 thick enough to provide a high quality lattice template for subsequent growth of one or more epitaxial layers, but thin enough to be highly compliant. When the substantially single crystalline layer 122 is relatively thin, the substantially single crystalline layer 122 may be referred to as "compliant" so that the physical properties of the substantially single crystalline layer 122 are less constrained and capable of mimicking the physical properties of surrounding materials and crystallization Less prone to defects. The compliance of the substantially single crystal layer 122 may be inversely proportional to the thickness of the substantially single crystal layer 122 . Higher compliance results in lower defect densities in epitaxial layers grown on templates and enables thicker epitaxial layers to be grown. In some embodiments, the thickness of the substantially single crystal layer 122 may be increased by epitaxially growing silicon on the exfoliated silicon layer.

Third, it may be beneficial to improve the smoothness of the substantially single crystal layer 122 . The smoothness of the layer may be related to the total hydrogen dosage, the presence of any co-located plant species, and the annealing conditions used to form the hydrogen-based splitting planes. The initial roughness resulting from layer transfer (ie, the splitting step) can be reduced by thermal oxidation and oxide stripping, as discussed below.

In some embodiments, removing the damaged layer and adjusting the final thickness of the substantially single crystal layer 122 can be accomplished by thermal oxidation stripping the top portion of the silicon layer followed by oxide layer stripping using hydrogen fluoride (HF) acid. For example, a lift-off silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to produce a silicon dioxide layer about 420 nm thick. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen may migrate to the surface. Therefore, subsequent oxide layer stripping can remove some of the damage. Also, thermal oxidation is usually performed at a temperature of 1000° C. or higher. Elevated temperatures can also repair lattice damage.

The silicon oxide layer formed on the top portion of the substantially single crystal layer during thermal oxidation can be stripped using an HF acid etch. The etch selectivity of HF acid to silicon oxide and silicon (SiO ₂ : Si) can be adjusted by adjusting the temperature and concentration of the HF solution and the stoichiometry and density of the silicon oxide. Etch selectivity refers to the etch rate of one material relative to another. The selectivity of the HF solution to ( _SiO2 :Si) may range from about 10:1 to about 100:1. High etch selectivity can reduce surface roughness by a factor similar to the initial surface roughness. However, the surface roughness of the resulting substantially single crystal layer 122 may still be greater than desired. For example, the bulk Si(111) surface may have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by 2 μm × 2 μm atomic force microscopy (AFM) scanning before additional processing. In some embodiments, the surface roughness required for epitaxial growth of gallium nitride material on Si(111) may be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm over an AFM scan area of 30 μm x 30 μm nm.

Additional surface smoothing may be performed if the surface roughness of the substantially single crystal layer 122 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness. There are several methods of smoothing the surface of silicon. Such methods may include hydrogen annealing, laser trimming, plasma smoothing, and contact polishing (eg, chemical mechanical polishing or CMP). Such methods may involve preferential erosion of high aspect ratio surface peaks. Therefore, high aspect ratio features on the surface can be removed faster than low aspect ratio features, resulting in a smoother surface.

It should be understood that the specific steps illustrated in Figure 5 provide a specific method of fabricating an engineered substrate in accordance with one embodiment of the present invention. Other sequences of steps may also be performed in accordance with alternative embodiments. For example, alternative embodiments of the present invention may perform the steps described above in a different order. Furthermore, the various steps illustrated in Figure 5 may include multiple sub-steps that may be performed in various orders as appropriate for a single step. Furthermore, additional steps may be added or removed depending on the application. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications in accordance with one embodiment of the present invention. In some LED applications, the engineered substrate structure provides a growth substrate capable of growing high quality GaN layers, and then removed from the engineered substrate structure. However, for RF and power component applications, the engineered substrate structure forms some portion of the finished component, and as a result, the electrical, thermal, and other properties of the engineered substrate structure or components of the engineered substrate structure are important for the particular application.

Referring to FIG. 1, the monocrystalline silicon layer 122 is typically a lift-off layer separated from the silicon donor wafer using implant and lift-off techniques. Typical cloth plants are hydrogen and boron. The electrical properties of layers and materials in engineered substrate structures are important for power and RF component applications. For example, some device architectures use highly insulating silicon layers with resistances greater than 10 ³ Ohm-cm to reduce or eliminate leakage through the substrate and interface layers. Other applications utilize designs that include a conductive silicon layer with a predetermined thickness (eg, 1 μm) to connect the source of an element to other elements. Therefore, in these applications, it is desirable to control the size and performance of the single crystal silicon layer. In designs where implant and lift-off techniques are used during layer transfer, residual implant atoms, such as hydrogen or boron, are present in the silicon layer, changing electrical properties. In addition, it can be difficult to control the thickness, conductivity, and other properties of the thin silicon layer by adjusting, for example, the implant dose, which affects the conductivity, as well as the full width at half maximum (FWHM), surface roughness, and surface roughness of the implant distribution. degree, and the accuracy of the position of the split surface, and the implantation depth which may affect the layer thickness.

In accordance with embodiments of the present invention, silicon epitaxy on an engineered substrate structure is utilized to achieve the desired properties of a single crystal silicon layer suitable for a particular device design.

Referring to FIG. 6 , an epitaxial/engineered substrate structure 600 includes an engineered substrate structure 610 and a silicon epitaxial layer 620 formed on the engineered substrate structure 610 . The engineered substrate structure 610 may be similar to the engineered substrate structures illustrated in FIGS. 1 , 3 , and 4 . Typically, after layer transfer, the substantially single crystal silicon layer 122 is on the order of 0.5 μm. In some processes, a surface conditioning process may be used to reduce the thickness of the single crystal silicon layer 122 to about 0.3 μm. In order to increase the thickness of the monocrystalline silicon layer to about 1 μm for making eg reliable ohmic contacts, an epitaxial monocrystalline silicon layer 620 is grown on the substantially monocrystalline silicon layer 122 formed by the layer transfer process using an epitaxial process. The epitaxial monocrystalline silicon layer 620 may be grown using various epitaxial growth processes, including CVD, ALD, MBE, and the like. The thickness of the epitaxial monocrystalline silicon layer 620 may be in the range of about 0.1 μm to about 20 μm, eg, between 0.1 μm and 10 μm.

FIG. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineered substrate structure in accordance with one embodiment of the present invention. As described below, the structure illustrated in FIG. 7 may be referred to as a double epitaxial structure. As illustrated in FIG. 7, an engineered substrate structure 710 including an epitaxial monocrystalline silicon layer 620 has a III-V epitaxial layer 720 formed thereon. In one embodiment, the III-V epitaxial layer includes gallium nitride (GaN).

The desired thickness of the III-V epitaxial layer 720 can vary widely depending on the desired functionality. In some embodiments, the thickness of the III-V epitaxial layer 720 may vary between 0.5 μm and 100 μm, eg, the thickness is greater than 5 μm. The resulting breakdown voltage of devices fabricated on the III-V epitaxial layer 720 may vary depending on the thickness of the III-V epitaxial layer 720 . Some embodiments provide a breakdown voltage of at least 100 V, 300 V, 600 V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.

In order to provide electrical conductivity between certain portions of the III-V epitaxial layer 720, which may include multiple sub-layers, in this example a pass through the epitaxial monocrystalline silicon layer 620 is formed from the top surface of the III-V epitaxial layer 720 A set of through holes 724. The vias 724 may be lined with an insulating layer (not shown) such that the vias 724 are insulated from the III-V epitaxial layer 720 . As an example, vias may be used to connect the electrodes of a diode or transistor to the underlying silicon layer by providing ohmic contacts through the vias, thereby mitigating charge accumulation in the device.

Obtaining such ohmic contacts through the vias would be difficult given the growth of a III-V epitaxial layer on the monocrystalline silicon layer 122, since it would be difficult to terminate the via etch in the monocrystalline silicon layer 122: eg reliable The 5 μm GaN is etched through the entire wafer and the etch is terminated in a 0.3 μm silicon layer. Embodiments of the present invention can provide monocrystalline silicon layers with a thickness of several micrometers, which is difficult using implant and lift-off processes because high implant energy is required to achieve large implant depths. Next, the thick silicon layer enables applications such as the illustrated vias that enable a wide variety of device designs.

In addition to increasing the thickness of the silicon "layer" by epitaxially growing the monocrystalline silicon layer 620 on the monocrystalline silicon layer 122, other adjustments can be made to the original properties of the monocrystalline silicon layer 122, including conductivity, crystallinity, etc. Modifications. For example, if a silicon layer on the order of 10 μm is required before additional epitaxial growth of III-V layers or other materials, such thick layers can be grown in accordance with embodiments of the present invention.

Because the implantation process can affect the properties of the monocrystalline silicon layer 122 , such as residual boron/hydrogen atoms can affect the electrical properties of silicon, the embodiment of the present invention removes a portion of the monocrystalline silicon layer 620 before epitaxially growing the monocrystalline silicon layer 620 . Silicon layer 122 . For example, the single crystal silicon layer 122 can be thinned to a thickness of 0.1 μm or less to remove most or all of the residual boron/hydrogen atoms. The subsequently grown single crystalline silicon layer 620 is then used to provide a single crystalline material whose electrical and/or other properties are substantially independent of the corresponding properties of the layers formed using the layer transfer process.

In addition to increasing the thickness of the single crystal silicon material coupled to the engineered substrate structure, the electrical properties, including conductivity, of the epitaxial single crystal silicon layer 620 may be different from the electrical properties of the single crystal silicon layer 122 . Doping the epitaxial monocrystalline silicon layer 620 during growth may produce p-type silicon by doping with boron and n-type silicon by doping with phosphorus. Undoped silicon can be grown to provide high resistivity silicon for use in devices with insulating regions. In particular, insulating layers can be used for RF elements.

The lattice constant of the epitaxial single crystal silicon layer 620 can be adjusted during growth to change the lattice constant of the single crystal silicon layer 122 to generate a strained epitaxial material. In addition to silicon, other elements may be epitaxially grown to provide layers, including strained layers containing silicon germanium or the like. For example, a buffer layer may be grown on the monocrystalline silicon layer 122, on the epitaxial monocrystalline silicon layer 620, or between layers to enhance subsequent epitaxial growth. Such buffer layers may include strained III-V layers, silicon germanium strained layers, and the like. Additionally, buffer layers and other epitaxial layers can be graded in molar fractions, dopants, polarities, and the like. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

In some embodiments, the strain present in the monocrystalline silicon layer 122 or the epitaxial monocrystalline silicon layer 620 may be relaxed during growth of subsequent epitaxial layers, including III-V epitaxial layers.

FIG. 8 is a simplified flow chart illustrating a method of fabricating an engineered substrate in accordance with another embodiment of the present invention. The method includes forming a support structure by providing a polycrystalline ceramic core (810), forming a first adhesive layer (812) coupled to at least a portion of the polycrystalline ceramic core. The first adhesive layer may include a tetraethylorthosilicate (TEOS) layer. The method also includes forming a conductive layer (814) coupled to the first adhesive layer. The conductive layer may be a polysilicon layer. The first adhesive layer may be formed as a single layer of TEOS. The conductive layer may be formed as a single layer of polysilicon.

The method also includes forming a second adhesive layer (816) coupled to at least a portion of the conductive layer, and forming a barrier shell (818). The second adhesive layer may be formed as a single layer of TEOS. The barrier shell can be formed as a single layer of silicon nitride or as a series of sublayers forming the barrier shell.

Once the support structure is formed by processes 810-818, the method further includes bonding a bonding layer (eg, a silicon oxide layer) to the support structure (820) and bonding a substantially single crystal silicon layer or a substantially single crystal layer to the silicon oxide layer (820). 822). Bonding of the bonding layer may include depositing bonding material as described herein, followed by a planarization process.

A layer transfer process may be used to bond the substantially single crystal silicon layer 122 to the bonding layer 120 . In some embodiments, silicon wafers (eg, silicon (111) wafers) are implanted to form split planes. After wafer bonding, the silicon substrate can be removed along with the portion of the single crystal silicon layer below the split plane, resulting in the lift-off single crystal silicon layer 122 shown in FIG. 1 . The thickness of the substantially single crystal silicon layer 122 can be varied to meet the specifications of various applications. In addition, the crystal orientation of the substantially single crystal layer 122 can be changed to meet the specifications of the application. Additionally, the doping level and distribution in the substantially single crystal layer 122 can be varied to meet the specifications of a particular application. In some embodiments, the substantially single crystal silicon layer 122 may be smoothed, as described above.

The method illustrated in FIG. 8 may also include forming an epitaxial silicon layer (824) by epitaxial growth on the substantially single crystal silicon layer, and forming an epitaxial silicon layer by epitaxial growth on the epitaxial silicon layer Layer III-V (826). In some embodiments, the epitaxial III-V layer may comprise gallium nitride (GaN).

It should be understood that the specific steps illustrated in FIG. 8 provide a specific method of fabricating an engineered substrate in accordance with another embodiment of the present invention. Other sequences of steps may also be performed in accordance with alternative embodiments. For example, alternative embodiments of the present invention may perform the steps described above in a different order. Furthermore, the various steps illustrated in Figure 8 may include multiple sub-steps that may be performed in various orders as appropriate for a single step. Additionally, additional steps may be added or removed depending on the particular application. Numerous changes, modifications, and substitutions will be recognized by those of ordinary skill in the art.

It should also be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes will be conceivable to those of ordinary skill in the art in view of these examples and embodiments, and are intended to be included within the spirit and scope of this application and the scope of the appended claims.

100: Engineering Substrates 110: core 112: The first adhesive layer 114: Conductive layer 116: Second adhesive layer 118: Barrier layer 120: Bonding Layer 122: Substantial monocrystalline silicon layer 130: Epitaxy material 300: Engineering Substrate 314: Conductive layer 316: Second Adhesive Layer 317: Flat 412: The first adhesive layer 414: Conductive layer 416: Second adhesive layer 418: Barrier Layer 500: Method 600: Epitaxy/Engineered Substrate Structure 610: Engineering Substrate Structure 620: silicon epitaxial layer 710: Engineering Substrate Structures 720:III-V epitaxial layer 724: Through hole

FIG. 1 is a simplified schematic diagram illustrating an engineering substrate structure according to an embodiment of the present invention.

Figure 2A is a SIMS curve illustrating the concentration of species as a function of depth for engineered structures in accordance with one embodiment of the present invention.

Figure 2B is a SIMS curve illustrating the species concentration as a function of depth for an engineered structure after annealing in accordance with one embodiment of the present invention.

FIG. 2C is a SIMS curve illustrating the species concentration as a function of depth after annealing for an engineered structure having a silicon nitride layer in accordance with one embodiment of the present invention.

FIG. 3 is a simplified schematic diagram illustrating the structure of an engineering substrate according to another embodiment of the present invention.

FIG. 4 is a simplified schematic diagram illustrating the structure of an engineering substrate according to yet another embodiment of the present invention.

5 is a simplified flow diagram illustrating a method of fabricating an engineered substrate in accordance with one embodiment of the present invention.

6 is a simplified schematic diagram illustrating an epitaxial/engineered substrate structure for RF and power applications in accordance with one embodiment of the present invention.

FIG. 7 is a simplified schematic diagram illustrating a III-V epitaxial layer on an engineered substrate structure in accordance with one embodiment of the present invention.

FIG. 8 is a simplified flow chart illustrating a method of fabricating an engineered substrate in accordance with another embodiment of the present invention.

Domestic storage information (please note in the order of storage institution, date and number) without Foreign deposit information (please note in the order of deposit country, institution, date and number) without

100: Engineering Substrates

110: core

112: The first adhesive layer

114: Conductive layer

116: Second adhesive layer

118: Barrier layer

120: Bonding Layer

122: Substantial monocrystalline silicon layer

130: Epitaxy material

Claims (10)

A method of manufacturing a substrate, the method comprising the steps of: A support structure is formed by the steps of: providing a polycrystalline ceramic core; forming a first adhesive layer coupled to the polycrystalline ceramic core; forming a conductive layer coupled to the first adhesive layer an adhesive layer; forming a second adhesive layer, the second adhesive layer being coupled to the conductive layer; and forming a barrier layer, the barrier layer being coupled to the second adhesive layer; forming a bonding layer, the bonding layers coupled to the support structure; bonding a substantially monocrystalline silicon layer to the bonding layer; and forming one or more epitaxial III-V layers coupled to The substantially single crystal silicon layer. The method of claim 1, wherein the polycrystalline ceramic core comprises aluminum nitride. The method of claim 2, wherein the one or more epitaxial III-V layers comprise an epitaxial gallium nitride layer. The method of claim 3, wherein the epitaxial gallium nitride layer has a thickness of about 5 μm or more. The method of claim 3, wherein the one or more epitaxial III-V layers further comprise an epitaxial aluminum nitride layer, or an epitaxial aluminum gallium nitride layer, or a combination thereof. The method of claim 1, wherein the step of bonding the substantially single crystal silicon layer is performed by lift-off. The method of claim 6, before the step of forming the one or more epitaxial III-V layers, further comprising the following steps: forming an epitaxial silicon layer coupled to the substantially single crystal silicon layer; wherein the one or more epitaxial III-V layers are coupled to the epitaxial silicon layer. The method of claim 7, wherein the epitaxial silicon layer is strained. A method as claimed in claim 1, wherein: the first adhesive layer comprises tetraethylorthosilicate (TEOS); the conductive layer comprises polysilicon; the second adhesive layer includes TEOS; the barrier layer comprises silicon nitride; and The bonding layer contains silicon oxide. The method of claim 9, wherein: the first adhesive layer encapsulates the polycrystalline ceramic core; the conductive layer encapsulates the first adhesive layer; the second adhesive layer encapsulates the conductive layer; and The barrier layer encapsulates the second adhesive layer.

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