TW202142846A - Embedded computing device - Google Patents

Abstract

According to an example aspect of the present invention, there is provided an apparatus comprising a first processing core configured to generate first control signals and to control a display by providing the first control signals to the display via a first display interface, a second processing core configured to generate second control signals and to control the display by providing the second control signals to the display via a second display interface, and the first processing core being further configured to cause the second processing core to enter and leave a hibernation state based at least partly on a determination, by the first processing core, concerning an instruction from outside the apparatus.

Description

Embedded computing device

Generally speaking, the present invention relates to, for example, implementing multi-core or multi-chip embedded solutions. Related applications

This case is a partial continuation of the U.S. Patent Application No. 15/784,234 filed on October 16, 2017. It is based on the Finnish Patent Application No. 20165790 filed on October 17, 2016 and on October 17, 2016. The UK patent application No. 1617575.4 filed at the same time claims priority.

An embedded device usually includes an object containing an embedded computing system, and the embedded computing system can be attached to the object. The embedded computer system can be designed in consideration of a specific purpose, or the embedded computer system can be at least partially universal in terms of enabling users to install software in it. The embedded computer system may be based on a microcontroller or a microprocessor (CPU), for example.

An embedded device may include one or more processors, a user interface, and a display, so that the user can interact with the device using the user interface. The user interface may include buttons, for example. The embedded device may include a connection function configured to communicate with a communication network such as a wireless communication network. The embedded device can be enabled to receive, for example, information related to the current time and current time zone from such a communication network.

More complex embedded devices such as mobile phones can allow users to install applications into the memory such as solid-state memory contained in the device. Compared with desktop computers or notebook computers, embedded devices are often resource-constrained. For example, the memory capacity may be more restricted than desktop or notebook computers, the processor may have lower computing power, and power may be obtained from batteries. The battery may be small and rechargeable.

Saving battery power is a key task in designing embedded devices. Lower current usage can make the time interval between battery charging longer. For example, a smart phone can survive a full day before it needs to be recharged, which benefits a lot, because in this way, the user can recharge the phone at night and enjoy uninterrupted use during the day.

By adjusting the processor clock frequency between the highest clock frequency and a lower clock frequency (for example, half of the highest clock frequency), battery resources can be saved. Since the display of content on the display causes the display to emit light that can be seen by humans, which consumes power, another way to save battery power is to turn off the display of the embedded device by itself, and then do not use the device.

The invention is defined by the characteristics of the independent claims. Some specific embodiments are defined in the dependent claims.

According to the first aspect of the present invention, the present invention provides a device including a first processing core and a second processing core. The first processing core is configured to generate a plurality of first control signals, and to control the display by providing the first control signals to the display through the first display interface. The second processing core is configured to generate a plurality of second control signals, and to control the display by providing the second control signals to the display through the second display interface. The first processing core is further configured to cause the second processing core to enter and leave the dormant state based at least in part on the judgment of the first processing core on the instruction from the outside of the device.

The various embodiments of the first aspect may include at least one feature in the following bulleted list: ●　The device is configured to obtain the microphone information inside the device from the microphone contained in the device. ●　The second processing core is electrically connected to at least one of the following: a cellular communication circuit, a non-cellular wireless communication circuit, and a second wired communication port. ●　 Both the first processing core and the second processing core are electrically connected to the shared random access memory. ●　The first processing core is configured to determine that pre-configured spoken commands are recorded in the microphone data, so that the second processing core leaves the dormant state. The commands come from outside the device and include pre-configured spoken commands. ●　The first processing core is configured to determine that the pre-configured auditory control signal is recorded in the microphone data, so that the second processing core leaves the dormant state. The command comes from the outside of the device and contains the pre-configured auditory control signal. ● "The first processing core is configured to make the second processing core leave the dormant state in response to the judgment that a notification is received in the device. The notification requires the capability of the second processing core. The command comes from outside the device and contains the notification. ●　The second graphics mode includes a simplified bird's-eye view graphics mode. ●　The first processing core is configured to make the second processing core enter the dormant state in response to the judgment that the user interface type not supported by the first processing core is no longer requested. ● "The device includes a display with a first electrical connection to the first display interface in the first processing core and a second electrical connection to the second display interface in the second processing core. ●　The first processing core and the second processing core are contained in the same integrated circuit. ● "The first processing core is contained in a microcontroller, and the second processing core is contained in a microprocessor, the microcontroller is outside the microprocessor and the microprocessor is outside the microcontroller. ● "The device is configured to at least partially store the context of the second processing core, which is related to the transition of the second processing core into a dormant state.

According to a second aspect of the present invention, the present invention provides a method for a device, which includes: generating a plurality of first control signals by a first processing core, and providing the first control signals to the display through the first display interface In order to control the display, the second processing core generates a plurality of second control signals, and controls the display by providing the second control signals to the display through the second display interface, and is based at least in part on the information received from the outside of the device by the first processing core The judgment of the instruction makes the second processing core enter and leave the dormant state.

Various embodiments of the second aspect may include at least one feature in the following bulleted list: ●　From the microphone contained in the device, obtain the microphone information inside the device. ●　The second processing core is electrically connected to at least one of the following: a cellular communication circuit, a non-cellular wireless communication circuit, and a second wired communication port. ●　 Both the first processing core and the second processing core are electrically connected to the shared random access memory. ●The method further includes: the first processing core responds to judging that the pre-configured spoken commands are recorded in the microphone data, and the second processing core leaves the dormant state. The commands come from outside the device and include the pre-configured spoken commands. The method further includes: the first processing core responds to determining that the pre-configured auditory control signal is recorded in the microphone data, so that the second processing core leaves the dormant state, and the command comes from the outside of the device and includes the pre-configured auditory control signal. ● The method further includes: the first processing core determines that a notification is received in the device in response to the judgment, and causes the second processing core to leave the dormant state. The notification requires the capability of the second processing core, and the instruction comes from outside the device and includes the notification. ●　The second graphics mode includes a simplified bird's-eye view graphics mode. ●　The method further includes: the first processing core determines in response to no longer requesting user interface types that are not supported by the first processing core, so that the second processing core enters the dormant state. ● "The method is executed in a device that includes a display with a first electrical connection to the first display interface in the first processing core and a second electrical connection to the second display interface in the second processing core. ●　The first processing core and the second processing core are contained in the same integrated circuit. ● "The first processing core is contained in a microcontroller, and the second processing core is contained in a microprocessor, the microcontroller is outside the microprocessor and the microprocessor is outside the microcontroller.

According to a third aspect of the present invention, the present invention provides a device including at least one processing core and at least one memory, the at least one memory includes computer code, the at least one memory and the computer code are configured to Perform with the at least one processing core: the first processing core causes the device to generate at least a plurality of first control signals, and the first control signals are provided to the display through the first display interface to control the display, and the second processing core generates A plurality of second control signals, by providing the second control signals to the display through the second display interface to control the display, and based at least in part on the judgment of the first processing core on the command from the outside of the device, the second processing core Enter and leave the dormant state.

According to a fourth aspect of the present invention, the present invention provides a device, which includes: a means for generating a plurality of first control signals by a first processing core, and by providing the first control signals to the display through the first display interface to control The means of the display, the means of generating a plurality of second control signals by the second processing core, the means of controlling the display by providing the second control signals to the display through the second display interface, and at least partly based on the pairing of the first processing core Regarding the judgment of the microphone data, it is a means to make the second processing core enter and leave the dormant state.

According to a fifth aspect of the present invention, the present invention provides a non-transitory computer-readable medium having a computer-readable instruction set stored therein, and when the computer-readable instruction set is executed by at least one processor, Make the device at least: a plurality of first control signals are generated by the first processing core, the first control signals are provided to the display through the first display interface to control the display, and the second processing core generates a plurality of second control signals, by The second control signals are provided to the display through the second display interface to control the display, and the second processing core enters and leaves the dormant state based at least in part on the judgment of the instruction from the outside of the device by the first processing core.

According to the sixth aspect of the present invention, the present invention provides a computer program configured to, when run, cause the method according to the second aspect to be executed. Industrial availability

At least some embodiments of the present invention have industrial applicability in embedded multi-chip or multi-core and optimization of power consumption.

The embedded device is equipped with two or more processor cores, of which at least some of the processor cores can control the display of the device, and the processing cores with lower capabilities are configured to switch the processor cores with higher capabilities to and from the sleep state And to save power. The sleep state may include, for example, the clock frequency of a processing core with a higher capability being set to zero. In the hibernation state, in addition to setting the clock frequency of the higher-capability processing core to zero, or as another option, the memory refresh rate of the memory used by the higher-capability core can be set to zero. As an alternative to zero, a low non-zero frequency can be used as the clock frequency and/or memory refresh frequency. In some embodiments, higher-capacity processing cores may use higher-density memory technologies, such as double data rate (DDR) memory, and lower-capacity processing cores may use lower-density memory technologies, such as static Random access memory (SRAM). In the hibernation state, the power of the dormant processing core (or more generally the processing unit) can be turned off. As an alternative to the processor core, in some embodiments, the entire processor can be converted to a sleep state. The advantage of putting the entire processor in the sleep state is that the circuits outside the core of the processor are also in the sleep state, thereby reducing current consumption.

Figure 1 shows an exemplary system that can support at least some embodiments of the present invention. The exemplary system of FIG. 1 includes a device 110, which may include an embedded device, such as a smart watch, a personal health monitor, a mobile phone, a smart phone, or other suitable devices.

In the example of FIG. 1, the device 110 is configured with a plurality of communication interfaces. The first communication interface enables the device 110 to receive satellite positioning information from the satellite constellation 140 via the satellite link 114. Examples of suitable satellite positioning constellations include the Global Positioning System (GPS), GLONASS, Beidou and Galileo satellite positioning constellations.

The second communication interface enables the device 110 to communicate with a cellular communication system, such as a wideband code division multiplexing (WCDMA) or long-term evolution (LTE) network. The cellular link 112 can be configured to transfer information between the device 110 and the base station 120. The cellular link 112 can be configured to comply with the same cellular communication standard supported by both the device 110 and the base station 120. The base station 120 may be included in a cellular wireless access network including multiple base stations. The base station 120 may be arranged to communicate with the core network node 150 through the connection 125. The core network node 150 may include, for example, a switch, a mobile management entity, or a gateway. The core network node 150 may be arranged to communicate with a further network 170 such as the Internet through a connection 157.

The third communication interface enables the device 110 to communicate with a non-cellular communication system, such as a wireless local area network (WLAN), Bluetooth, or a microwave access (WiMAX) system. Another example is the inductive underwater communication interface. The non-cellular link 113 can be configured to transfer information between the device 110 and the access point 130. The non-cellular link 113 may be configured to conform to the same non-cellular technology supported by both the device 110 and the access point 130. The access point 130 may be arranged to communicate with the gateway 160 through the connection 136. The gateway 160 can be arranged to communicate with another network 170 through the connection 167. Each of the connections 125, 157, 136, and 167 may be wired or at least partially wireless. Not all these connections need to be the same type. In some embodiments, at least one of the first communication interface, the second communication interface, and the third communication interface does not exist.

The fourth communication link enables the device 110 to communicate with the mobile device. For example, the low-power wireless interface allows the device 110 to communicate with mobile devices without cellular capabilities, and to communicate with mobile devices that have cellular capabilities and are different from the device 110. The low-power wireless interface is, for example, low-power Bluetooth (BLE) or Bluetooth Smart.

In use, the device 110 can use satellite positioning information from the satellite constellation 140 to determine the geographic location of the device 110. For example, the geographic location can be determined based on coordinates. The device 110 may be configured to present a map on a display that may be included in the device 110, the map having the determined geographic location of the device 110. For example, the device 110 may display surrounding streets or feature maps, and use symbols to indicate the current location of the device 110 on the map. Providing a map to indicate the current location of the device 110 on it and/or providing navigation instructions may be referred to as a map service.

In some embodiments, the device 110 may provide users with connection services, such as web browsing, instant messaging, and/or email. In some embodiments, the device 110 may be configured to provide connectivity services for its functions and/or applications, including enabling remote access to these functions and/or services via a network (such as the Internet). Therefore, for example, the device 110 can be tracked via the Internet. Such connection services can run on two-way communication links, such as the cellular link 112 and/or the non-cellular link 113. Generally speaking, the device 110 can provide a service to the user through a display, such as a map service or a connection service.

The device 110 may include two or more processing units. Two or more processing units may each include a processing core. Each processing unit may include one or more homogeneous or heterogeneous processor cores and/or different volatile and non-volatile memories. For example, the device 110 may include a microprocessor having at least one processing core and a microcontroller having at least one processing core. The processing cores do not need to be of the same type. For example, the processing cores in the microcontroller may have more limited processing power and/or memory technology with lower capabilities than the processing cores included in the microprocessor. In some embodiments, a single integrated circuit contains two processing cores, the first processing core has lower processing power and consumes less power, and the second processing core has higher processing power and consumes more Power. Generally speaking, the first of the two processing units may have lower processing power and consume less power, and the second of the two processing units may have higher processing power and consume more power . Each processing unit can be energized to control the display of the device 110. The processing unit with higher capability can be configured to provide a richer visual experience through the display. Processing units with lower capabilities can be configured to provide a simplified visual experience through the display. In one example, the simplified visual experience is a simplified color display mode instead of a rich color display mode. In another example, the simplified visual experience is a black and white visual experience. In one example, the rich visual experience is the visual experience using colors. For example, 16 bits or 24 bits can be used to represent colors.

Each of the two processing units may include a display interface configured to communicate with the display. For example, when the processing unit includes a microprocessor and a microcontroller, the microprocessor may include a transceiver circuit coupled to at least one metal pin under the microprocessor, and the at least one metal pin is electrically conductive. It is coupled to the input interface of the display control device. The display control device (which may be included in the display) is configured such that the display displays information according to the electrical signal received in the display control device. Similarly, in this example, the microcontroller may include a transceiver circuit that is coupled to at least one metal pin under the microcontroller, and the at least one metal pin is electrically coupled to the display control device Input interface. The display control device may include two input interfaces (one of which is coupled to each of the two processing units), or alternatively, the display control device may include a single input interface, where the two processing units can be provided through their respective display interfaces Input to this single input interface. Therefore, the display interface in the processing unit may include a transceiver circuit that enables the processing unit to transmit electrical signals to the display.

One of the processing units (for example, the one with lower or higher capacity) may be configured to at least partially control the other processing unit. For example, a processing unit with a lower capability (for example, a processing core with a lower capability) can switch a processing unit with a higher capability (for example, a processing core with a higher capability) to a dormant state or leave a dormant state. The occurrence of these conversions can be triggered by signals via internal processing unit interfaces such as the inter-core interface.

When transitioning from the active state to the sleep state, the transition processing unit can at least partially store its context in memory, such as pseudo-static random access memory (PSRAM), static random access memory (SRAM), flash Memory (FLASH) or Ferroelectric Random Access Memory (FRAM). The context may include, for example, register and/or addressing content. When transitioning from the dormant state using the context stored in the memory, the processing unit can continue processing faster and/or from the position where the processing unit was in the dormant state. In this way, the delay experienced by the user can be minimized. Sometimes alternate terms for situation include state and image. In the sleep state, the clock frequency of the processing unit and/or the associated memory can be set to zero, which means that the processing unit is powered off and does not consume power. The circuit configured to provide an operating voltage to the at least one processing unit may include, for example, a power management integrated circuit (PMIC). Since the device 110 includes another processing unit, the dormant processing unit can be completely powered off while maintaining the availability of the device 110.

When transitioning from the sleep state to the active state, the conversion processing unit can set its clock frequency to a non-zero value. The conversion processing unit can read the context from the memory, where the context can include a previously stored context, for example, a context stored in connection with the transition to a hibernation state, or the context can include a preset of the processing unit stored in the memory before leaving the factory. Set state or situation. For example, the memory may include pseudo-static random access memory, SRAM, FLASH and/or FRAM. For example, the memory used by the processing unit when it transitions to the sleep state and when it leaves the sleep state may include DDR memory.

When a processing unit is in a sleep state, the non-sleep processing unit can control the device 110. For example, the non-sleep processing unit can control the display through a display interface included in the non-sleep processing unit. For example, in a case where a processing unit with a lower capability has switched a processing unit with a higher capability to a sleep state, the processing unit with a lower capability may provide a simplified user experience at least partially through the display, for example. In one example, the simplified user experience is a map experience with a simplified visual experience, including black and white rendering of the map service. The simplified experience can be sufficient for users to benefit from it, and its advantage is that by sleeping a higher-capability processing unit, battery power can be saved. In some embodiments, a processing unit with higher capability (such as a microprocessor) may consume milliamps of current when it is in a non-sleeping low-power state, while a processing unit with lower capability (such as a microcontroller) may be It may only consume current in microamperes when it is in a non-sleeping low-power state. In the non-sleep state, the current consumption of the processing unit can be changed by setting the working clock frequency to a value between the highest clock frequency and the lowest non-zero clock frequency. In at least some embodiments, the processing unit (e.g., less capable processing unit) can be configured to power off for a short time before being awakened, such as 10 or 15 microseconds. In the context of this article, this situation is not called a sleep state, but an active low-power configuration. The average clock frequency calculated after several such cycles and the active cycle in between is positive and non-zero. For example, processing units with higher capabilities can be empowered to run the Android operating system.

The trigger events for the processing unit to switch to the sleep state include: the user indicates that the non-simplified experience is no longer needed, the communication interface of the processing unit is no longer needed, and the device 110 is not used for a predetermined length of time. Exemplary instructions that no longer require a non-simplified experience are situations where the user disables the full version of an application (for example, a map application). The trigger event for the processing unit to transition from the sleep state to the active state may include a user indicating that a non-simplified experience is required, requesting the communication interface of the processing unit and interacting with the device 110 after a period of inactivity. Alternatively or additionally, an external event may be configured as a trigger event, such as an event based on a sensor included in the device 110. For example, such an external event is a clock-based event that is configured to occur at a pre-configured time of the day, such as an alarm clock function. In at least some embodiments, the non-simplified experience includes using graphics modes that are not supported by the non-sleep processing unit but can be supported by the sleep processing unit. The graphics mode may include, for example, a combination of resolution, color depth, and/or refresh rate.

In some embodiments, user needs or user requests for non-simplified experiences can be predicted. This prediction may be based at least in part on the user's usage patterns, where the user tends to perform certain actions under the simplified experience before requesting the non-simplified experience. In this case, in response to determining that the user performs a specific action under a simplified experience, a non-simplified mode can be triggered.

If these processing units are located in separate devices or housings (for example, a wrist-worn computer and a handheld or fixed-mounted display device), the bus can be implemented in a wireless manner by using a wireless communication protocol. The radio transceiver units are functionally connected to their respective processing units, so they can perform the function of a bus to form a personal area network (PAN). The wireless communication protocol may be a protocol used for communication between computers and/or between any remote sensors, such as Bluetooth LE or a dedicated ANT+ protocol. These respectively use direct sequence spread spectrum (DSSS) modulation technology and adaptive isochronous network configuration. A description of the activation of various hardware necessary to implement wireless links can be obtained, for example: from the manual "Wireless Connection" of Texas Instruments (Texas Instrument®), which contains IC circuits and targets for working in the frequency bands below 1 GHz and 2.4 GHz The related hardware configuration of the agreement, such as ANT™, Bluetooth®, Bluetooth® low power consumption, RFID/NFC, PurePath™ wireless audio, ZigBee®, IEEE 802.15.4, ZigBee RF4CE, 6LoWPAN and Wi-Fi®.

Regarding hibernation, PAN can be kept operating by processing units that are not hibernating. Therefore, when hibernation ends, processing units leaving the sleep mode can access the PAN without re-establishing the PAN.

In some embodiments, the microphone data is used in the first processor to determine whether to trigger the second processor to leave the sleep state. Compared with the second processor, the first processor may have lower capabilities and consume less power. For example, the first processor may include a microcontroller and the second processor may include a microprocessor. The microphone data can be compared with reference data and/or preprocessed to identify features in the microphone data, so that it can be judged whether spoken language commands have been issued and recorded in the microphone data. As an alternative to spoken commands or in addition to spoken commands, the microphone data can be searched for auditory control signals, such as fire alarms or beep signals.

In response to the first processor detecting spoken commands and/or auditory control signals in the microphone data, the first processor can activate the second processor. In some embodiments, the first processor activates the second processor to a state selected by the first processor according to which spoken command and/or auditory control signal in the microphone data. Therefore, for example, in the case where the spoken command recognizes a web search engine, the second processor can be activated into the user interface of the specific web search engine. For example, in the case where the auditory control signal is a fire alarm, the second processor can be activated into the user interface of an application that provides emergency guidance to the user. Compared with the situation where the user or the second processor itself selects the state, selecting the existing initial state of the first processor for the second processor can save time.

If the microphone is included in the device, the microphone can be specially encapsulated in a waterproof casing. Although such a housing may hinder the generation of high-quality microphone data, it can allow the generation of relatively high-quality microphone data for the first processor to determine whether there are spoken commands and/or auditory control signals.

In some embodiments, the first processor is configured to process notifications delivered to the device and determines whether a second processor is needed to process the notifications. For example, the notification may be about a multimedia message or a video call. The notification may be about a software update proposed for the device, where the first processor can cause the second processor to leave the sleep state to process the notification. According to the notification, the first processor can select the initial state that the second processor enters when it leaves the sleep state. During the software update period, the second processor can switch the first processor to a sleep state.

Generally speaking, instructions from outside the device can be received by the device, and the first processor can correspondingly cause the second processor to leave the sleep state. Commands from outside the device can include, for example, notifications, spoken commands, or auditory control signals.

Figure 2 shows a first exemplary device capable of supporting at least some embodiments of the present invention. The illustrated device includes a microcontroller 210 and a microprocessor 220. The microcontroller 210 may include, for example, a Silabs EMF32 or Renesas RL78 microcontroller or the like. The microprocessor 220 may include, for example, a Qualcomm Snapdragon processor or an ARM Cortex-based processor. In the example of FIG. 2, the microcontroller 210 and the microprocessor 220 are communicatively coupled with an inter-core interface, and the inter-core interface may include, for example, a serial or parallel communication interface. More generally, the interface provided between the microcontroller 210 and the microprocessor 220 can be regarded as an interface between processing units.

In the illustrated example, the microcontroller 210 and the buzzer 270, the universal serial bus (USB) interface 280, the pressure sensor 290, the acceleration sensor 2100, the gyroscope 2110, the magnetometer 2120, the satellite positioning circuit 2130, the Bluetooth interface 2140, the user interface buttons 2150, and the touch interface 2160 are communicatively coupled. The pressure sensor 290 may include, for example, an atmospheric pressure sensor.

The microprocessor 220 is communicatively coupled with the optional cellular interface 240, the non-cellular interface 250 and the USB interface 260. The microprocessor 220 is further communicatively coupled with the display 230 through the microprocessor display interface 222. The microcontroller 210 is also communicatively coupled with the display 230 through the microcontroller display interface 212. The microprocessor display interface 222 may include the communication circuit included in the microprocessor 220. The microcontroller display interface 212 may include a communication circuit included in the microcontroller 210.

The microcontroller 210 can be configured to determine whether a trigger event occurs. In response to the trigger event, the microcontroller 210 can be configured to cause the microprocessor 220 to switch into and out of the aforementioned sleep state. When the microprocessor 220 is in the sleep state, the microcontroller 210 can control the display 230 through the microcontroller display interface 222. Therefore, when the microprocessor 220 is in the sleep state, the microcontroller 210 can provide a simplified experience to the user through the display 230, for example.

In response to a trigger event, the microcontroller 210 can make the microprocessor 220 switch from the sleep state to the active state. For example, in the case where the user indicates that he wants to start the cellular communication connection through the button 2150, since the cellular interface 240 can be controlled by the microprocessor 220, the microcontroller 210 can switch the microprocessor 220 to the active state. However, in the example of FIG. 2, the cellular interface 240 cannot be directly used by the controller 210. In some embodiments, when the microprocessor 220 is in the dormant state, the honeycomb interface 240 is also in the dormant state. The cellular interface 240 may include, for example, an electronic interface connected to a cellular transceiver. The cellular interface 240 may include the control circuit of the cellular transceiver.

In various embodiments, at least two components shown in FIG. 2 may be integrated on the same integrated circuit. For example, the microprocessor 220 and the microcontroller 210 can be disposed in the same integrated circuit as the processing core. In this case, the honeycomb interface 240 may be, for example, the honeycomb interface of the integrated circuit (which is included in the integrated circuit), where the honeycomb interface 240 can be controlled by the microprocessor 220 but cannot be controlled by the microcontroller 210 control. In other words, the individual hardware features of the integrated circuit can be controlled by one of the microcontroller 210 and the microprocessor 220, but cannot be controlled by both. On the other hand, certain hardware features can be controlled by any processing unit. For example, in such an integrated embodiment, the USB interface 260 and the USB interface 280 can be one and the same USB interface of an integrated circuit and can be controlled by any processing core.

The memory 2170 and the memory 2180 are further shown in FIG. 2. For example, the memory 2170 is used by the microprocessor 220 and can be based on DDR memory technology, such as DDR2 or DDR3. For example, the memory 2180 is used by the microcontroller 210 and may be based on SRAM technology.

Figure 3 shows a second exemplary device capable of supporting at least some embodiments of the present invention.

The illustrated device 300 may include, for example, the embedded device 110 of FIG. 1. The device 300 includes a processor 310. The processor 310 may include, for example, a single-core or a multi-core processor, where the single-core processor includes one processing core, and the multi-core processor includes more than one processing core. For example, the processor 310 may correspond to the structure shown in FIG. 2 (except for the display 230). The processor 310 may include more than one processor or processing unit. The processor 310 may include at least one dedicated integrated circuit ASIC. The processor 310 may include at least one field programmable gate array (FPGA). The processor 310 may be a device for executing method steps in the device 300. The processor 310 may be at least partially configured by computer instructions to perform actions.

The device 300 may include a memory 320. The memory 320 may include random access memory and/or permanent memory. The memory 320 may include volatile and/or non-volatile memory. The memory 320 may include at least one random access memory (RAM) chip. For example, the memory 320 may include magnetic, optical and/or holographic memory. The memory 320 may be at least partially accessible by the processor 310. The memory 320 may be a device for storing information. The memory 320 may include a plurality of computer instructions, and the processor 310 is configured to execute the computer instructions. When computer instructions configured to cause the processor 310 to perform certain actions are stored in the memory 320, and the device 300 as a whole is configured to run under the guidance of the processor 310 using computer instructions from the memory 320, the processing The processor 310 and/or at least one processing core thereof may be considered to be configured to perform the certain actions. The memory 320 may be at least partially included in the processor 310. The memory 320 may be at least partially external to the device 300 but can be accessed by the device 300.

The device 300 may include a transmitter 330. The device 300 may include a receiver 340. The transmitter 330 and the receiver 340 can be configured to respectively transmit and receive information according to at least one cellular or non-cellular standard. The conveyor 330 may include more than one conveyor. The receiver 340 may include more than one receiver. For example, the transmitter 330 and/or the receiver 340 may be configured to be used in accordance with Global System for Mobile Communications (GSM), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), IS-95, wireless Local area network (WLAN), Ethernet (Ethernet) and/or global interoperability microwave access (WiMAX) standards to operate. For example, through the cellular interface 240, the non-cellular interface 250 and/or the USB interface 280 of FIG. 2, the transmitter 330 and/or the receiver 340 can be controlled.

The device 300 may include a near field communication (NFC) transceiver 350. The NFC transceiver 350 may support at least one NFC technology, such as NFC, Bluetooth, Wibree or similar technologies.

The device 300 may include a user interface (UI) 360. The UI 360 may include at least one of a display, a keyboard, a touch screen, a vibrator arranged to vibrate the device 300 to communicate to the user, a speaker, and a microphone. The user's input to the UI 360 can be based on a pattern, for example, the user shakes the device 300 to take an action through the UI 360. The user may be able to operate the device 300 through the UI 360, such as receiving incoming calls, making phone calls or video calls, browsing the Internet, managing and storing in the memory 320 or through the transmitter 330 and receiver 340 or through the NFC transceiver 350. Fetch digital files from the cloud and/or play games. The UI 360 may include, for example, the button 2150 and the display 230 of FIG. 2.

The device 300 may include or be arranged to accommodate a user identification module 370. The user identification module 370 may include, for example, a user identification module (SIM) card, which may be installed in the device 300. The user identification module 370 may include subscribed information for identifying the user of the device 300. The user identification module 370 may include encrypted information, which may be used to verify the identity of the user of the device 300 and/or facilitate the encryption of communication information and calculate the communication cost through the device 300 for the user of the device 300.

The processor 310 may be equipped with a transmitter, which is arranged to output information from the processor 310 to other devices included in the device 300 through electrical wires inside the device 300. The transmitter may include a serial bus transmitter that is arranged to output information to the memory 320 for storage therein, for example, through at least one electrical wire. As an alternative to the serial bus, the transmitter may include a parallel bus transmitter. Similarly, the processor 310 may include a receiver, and the receiver is arranged to receive information from other devices included in the device 300 through the electrical wires inside the device 300 in the processor 310. The receiver may include a serial bus receiver that is arranged to receive information from the receiver 340 via at least one electrical wire for processing in the processor 310, for example. As an alternative to the serial bus, the receiver may include a parallel bus receiver.

The device 300 may include other devices not shown in FIG. 3. For example, when the device 300 includes a smart phone, it may include at least one digital camera. The several devices 300 may include a back camera and a front camera, where the back camera can be used for digital photography, and the front camera can be used for video phones. The device 300 may include a fingerprint sensor, which is arranged to at least partially authenticate the user of the device 300. In some embodiments, the device 300 lacks at least one of the aforementioned devices. For example, some devices 300 may lack the NFC transceiver 350 and/or the user identification module 370.

The processor 310, the memory 320, the transmitter 330, the receiver 340, the NFC transceiver 350, the UI 360, and/or the user identification module 370 can be connected to each other in a variety of different ways through electrical wires inside the device 300. For example, the aforementioned devices can be respectively connected to the main bus inside the device 300 to allow the devices to exchange information. However, as understood by those skilled in the art, this is only an example, and depending on the embodiment, without departing from the scope of the present invention, there are many ways to choose to connect at least two of the aforementioned devices to each other. .

Generally speaking, a diving information device is provided here, which includes a first processing core and a second processing core. Compared with the second processing core, the first processing core can have lower processing capacity and lower power consumption and can be configured to maintain diving information during diving. Diving may include diving under water, that is, the period during which the user is submerged. As will be described later, since the second processing core can remain in a dormant state in most cases, allowing the processing core with lower power consumption to maintain diving information will increase the time the device can maintain the diving information. The first processing core may control the display (which may be included in the diving information device) to display diving information and/or instructions derived from the diving information.

Since diving information can include, for example, at least one of the following: the remaining time before the ascent should begin, decompression data, safe stop data, remaining air volume, any possible information from other divers, and depth as a function of time, Diving information is very important for the safety of divers. In this way, because of the safety-critical information being processed, redundant information management systems are of concern. The redundant information in the diving information device is provided by a second processing core, which can be configured to switch from a sleep state to an active state periodically (for example, at a fixed period) to verify that the diving information is correct. For example, the second processing core may be configured to check that the gas level has progressed in a credible manner during the diving, the diving depth has not jumped suddenly, and the remaining time changes in accordance with other aspects of the diving information. In other words, the second processing core can verify that the diving information is not damaged due to bit errors, memory corruption, or a bug in the first processing core. In the case where the diving information is verified as correct, the second processing core may return to the dormant state in response to this verification.

For example, the second processing core may exit the sleep state every second, every five seconds, or even every minute (for example, every two minutes). The verification of diving information may only take a few milliseconds, so the second processing core will stay dormant for more than 90% of the time, saving energy and extending the time that the diving information device can be used before its battery needs to be recharged or replaced.

The diving information can be stored in at least one non-volatile memory, which will be described below in conjunction with FIG. 4.

The first processing core can be configured to restart in the event of an error and continue to maintain diving information from non-volatile memory. Since the memory is non-volatile, dive information will be saved at the restart time. Generally speaking, diving information can be stored in the form of multiple time series, so that diving can be reproduced by observing how the variables included in the diving information change over time. For example, one time series can be a time series of diving depth values, another time series can be a time series of remaining air values, and so on.

The second processing core can be configured to indicate that the diving information is damaged due to the verification of the diving information, so that the first processing core stops maintaining the diving information. This may include setting the first processing core to an inactive state. Then, the second processing core can take the role of maintaining dive information for the remainder of the dive. The second processing core may be further configured to try to repair the diving information, for example, by determining which variable is unreliable, for example, because the value of the variable changes suddenly and unnaturally, so that the variable is retrieved from another source. The second processing core may be configured to provide instructions to divers that the diving information may become unreliable. The second processing core may be configured to stop providing any indication of a specific variable of diving information to the display, which specific variable has been determined to be unreliable or possibly unreliable. This preserves the advantage that the diver will have confidence in the information provided, and the diver may suspend the dive to put safety first.

In some embodiments, the second processing core is triggered from the dormant state to the active state in response to the judgment that it should begin to rise to the water surface quickly (for example, within one minute or within three minutes). For example, this judgment can be made based on diving information. The reason why the second processing core can be activated in this case is that the second processing core may be able to present a more visually eye-catching indication on the display to indicate that it should start to rise quickly. Since the first processing core has lower capabilities, it may only be able to provide a monochrome and/or slowly updated display mode, while the second processing core may be able to provide a more vivid and/or animated display and is suitable for delivering warnings. Attract the user's attention.

Figure 4 shows an exemplary diving information device according to at least some embodiments of the present invention. Two processing cores (CORE1 and CORE2) are depicted. For example, the core may be a microcontroller core, or one of the cores may be a microcontroller core, and the other may be a microprocessor core. One core can have a higher capacity and consume more power than another core. Therefore, for example, when the cores CORE1 and CORE2 are both microcontroller cores, the first microcontroller core may consume more power than the other microcontroller core. The cores CORE1 and CORE2 may be contained in the same or different integrated circuits (for example, one or more microcontrollers or one or more microprocessors).

The system of Figure 4 further includes two non-volatile memories (one for each processing core), and a copy mechanism configured to copy diving information between the non-volatile memories. In fact, the first processing core CORE1 maintains diving information in non-volatile memory 1, and the copy mechanism maintains the same diving information in non-volatile memory 2. The replication mechanism may be external to the first processing core and the second processing core, so that if one of the processing cores fails, the replication will continue. As an alternative to two non-volatile memories, the diving information device can include a single non-volatile memory, so that the two processing cores can access a single non-volatile memory. Non-volatile memory can be of different types, such as those produced by different manufacturers and/or based on different basic technologies (such as NAND and NOR flash memory). The different types make it less likely that two non-volatile memories will fail at the same time. The non-volatile memory may be external to the processing core and/or the integrated circuit including the processing core. In some embodiments (in embodiments where the processing cores are included in the same integrated circuit), as with two processing cores, one or more non-volatile memories are included in the same integrated circuit.

Optionally, the second processing core CORE2 may have an interface connected to the non-volatile memory 1, and the first processing core CORE1 may have an interface connected to the non-volatile memory 2. These optional interfaces make it possible to check whether the copy mechanism is working properly.

Generally speaking, the diving information device may include two pressure sensors (air pressure sensor and a second pressure sensor), which are configured to determine the water depth of the diving information device according to the water pressure. The air pressure sensor can be configured to measure, for example, air pressure and water pressure up to a depth of ten or twenty meters. The second pressure sensor may be configured to measure water pressure up to 40, 50, 60, 80 or 100 meters, for example. In detail, there may be an overlapping depth area of the effective range of the pressure sensor. For example, between the water surface and a depth of ten or twenty meters, both pressure sensors can produce pressure readings.

The two pressure sensors can be integrated on the same chip, or they can be installed as different components in the diving information equipment.

Both the first processing core and the second processing core can receive inputs from both pressure sensors. When the diving information equipment is in the overlapping depth area, one or two processing cores can compare the pressure readings from the two pressure sensors, and in response to judging that the pressure sensors produce inconsistent information indicating two different depths, it can be used The person providing a warning signal indicates that in-depth information has become unreliable. In other words, in response to determining that the two pressure sensors provide inconsistent pressure data with each other, a warning can be provided to the user. Then, the user can choose to abort the dive. In the event that one of the pressure sensors fails during diving, the above situation may occur and may cause a dangerous situation. For example, when you are still in the depth overlap area, you can avoid descent to an area deeper than the depth overlap area by stopping the dive.

If the user descends to the lower limit of the depth overlap area, the diving information device can be configured to isolate the air pressure sensor from the water to prevent it from being damaged by high pressure. On the other hand, additionally or alternatively, when the diver approaches the depth overlap area from below, the diving information device may be configured to expose the air pressure sensor to water pressure once the device re-enters the depth overlap area. Another mechanism to protect the air pressure sensor is to separate it from the current source when it drops to the lower limit of the overlap area. The separation can be performed without the isolation and/or exposure mentioned in this paragraph, or it can be performed in combination with the isolation and/or such exposure.

Fig. 5 is a first flowchart of a first method according to at least some embodiments of the present invention. The stages of the illustrated method may be executed in the apparatus 110 of FIG. 1 or in the equipment of FIG. 2, for example.

Stage 510 includes: the first processing core maintains diving information related to the progress of the diving during the diving. The stage 520 includes: the first processing core generates a plurality of first control signals, and the first processing core provides the first control signals to the display through the display interface to control the display. Stage 530 includes: the second processing core repeatedly switches from the dormant state to the active state during the dive, the second processing core verifies the dive information and switches back to the dormant state as the dive information is verified to be correct state. Stage 540 includes: storing the diving information in at least one non-volatile memory included in the diving information device.

Fig. 6 is a state transition diagram according to at least some embodiments of the present invention.

The processing unit PU1 corresponds to the processing unit 1, for example, a processing unit with a lower capability. The processing unit PU2 corresponds to the processing unit 2, for example, a processing unit with higher capability. For example, these units may be similar to the units explained in conjunction with FIG. 4. In the initial state, the device containing the processing units PU1 and PU2 is in an inactive state, where 0 represents the state of the processing units PU1 and PU2. Both processing units PU1 and PU2 are turned off.

Starting from the initial power-off state, first the processing unit PU1 is powered on, the state of the processing unit PU1 is represented as "1", and the processing unit PU2 remains in the power-off state (represented by 0). Therefore, the composite state is "10", which corresponds to the case where the processing unit PU1 is active but the processing unit PU2 is inactive. In this state, the device may provide a simplified user experience and consume less battery reserve current.

In addition to the power-off state, or alternatively, the processing unit PU1 and/or PU2 may have an intermediate low-power state, from which the transition to the active state may be faster than from the completely power-off state. For example, the processing unit can be set to this intermediate low power state before it is set to the power-off state. In case the processing unit is needed soon afterwards, it can be switched back to the powered state. If it is deemed that the processing unit is not needed within the pre-configured time, the processing unit can be converted from the intermediate low-power state to the power-off state.

The arrow 610 represents the transition from the state "10" to the state "11". In other words, the processing unit PU2 transitions from the sleep state to the active state (for example, the state where its clock frequency is non-zero). The processing unit PU1 may, for example, cause the transition indicated by the arrow 610 to occur in response to a trigger event. In state "11", the device may be able to provide a richer experience at the expense of faster battery power consumption.

The arrow 620 represents the transition from the state "11" to the state "10", in other words, the transition of the processing unit PU2 from the active state to the sleep state. The processing unit PU1 may, for example, cause the transition indicated by the arrow 620 to occur in response to a trigger event.

It should be understood that the disclosed embodiments of the present invention are not limited to the specific structures, processing steps, or materials disclosed herein, but are extended to equivalents that can be recognized by those with ordinary knowledge in the related field. It should be better understood that the terminology used herein is only used for the purpose of describing specific embodiments, rather than as a limitation.

Throughout the specification, “one embodiment” or “an embodiment” means that a specific feature, structure, or characteristic described in relation to the embodiment is included in at least one embodiment of the present invention. Therefore, the terms "in one embodiment" or "in an embodiment" appearing in various places throughout the specification do not all refer to the same embodiment.

As used herein, for convenience, multiple items, structural elements, constituent elements, and/or materials may be presented in a common list. However, these lists should be understood to mean that each component in the list is individually identified as a separate and unique component. Therefore, no other component in the list is understood to be actually equivalent to any other component in the same list based on their appearance in the common group without any indication of difference. In addition, various embodiments and examples of the present invention may be referred to together with alternatives for various components thereof. It should be understood that such embodiments, examples, and equivalents should not be construed as actual equivalents to each other, but should be construed as independent and autonomous embodiments of the present invention.

In addition, the features, structures, or characteristics described in one or more embodiments can be combined in any suitable or technically feasible manner. In the following description, many specific details are provided, such as examples of length, width, shape, etc., for a thorough understanding of the embodiments of the present invention. However, those skilled in the relevant art will recognize that the present invention can be implemented without one or more specific details, or with other methods, components, materials, etc. In other cases, conventional structures, materials, or operations have not been shown or described in detail to avoid obscuring the aspect of the present invention.

Although the above examples illustrate the principles of the present invention in one or more specific applications, for those with ordinary knowledge in the technical field, the form and usage of the implementation can be adjusted without departing from the principles and concepts of the present invention. Make multiple changes to details without having to be creative. Accordingly, except for the scope of the following patent applications, it is not intended to limit the present invention.

110: device 112: Cellular link 113: non-cellular link 114: Satellite link 120: base station 125: connection 130: access point 136: connection 140: Satellite constellation 150: core network node 157: connection 160: Gateway 167: connection 170: Network 210: Microcontroller 212: Microcontroller display interface 220: Microprocessor 222: Microprocessor display interface 230: display 240: Honeycomb interface 250: non-cellular interface 260: Universal Serial Bus Interface 270: Buzzer 280: Universal Serial Bus Interface 290: Pressure Sensor 2100: Acceleration sensor 2110: gyroscope 2120: Magnetometer 2130: Satellite positioning circuit 2140: Bluetooth interface 2150: User interface buttons 2160: Touch interface 2170: memory 2180: memory 300: device 310: processor 320: memory 330: Teleporter 340: Receiver 350: Near Field Communication Transceiver 360: user interface 370: User Identification Module CORE1: core CORE2: core 510: stage 520: stage 530: stage 540: stage PU1: Processing unit PU2: Processing Unit 610: Arrow 620: Arrow

[Fig. 1] An exemplary system capable of supporting at least some embodiments of the present invention is shown.

[Figure 2] shows a first exemplary device capable of supporting at least some embodiments of the present invention.

[Figure 3] shows a second exemplary device capable of supporting at least some embodiments of the present invention.

[Figure 4] shows an exemplary diving information device according to at least some embodiments of the present invention.

[Figure 5] is a first flowchart of a first method according to at least some embodiments of the present invention.

[Figure 6] is a state transition diagram according to at least some embodiments of the present invention.

Claims (24)

A diving information equipment, including: The first processing core is configured to maintain diving information related to the progress of the dive during the dive, generate a plurality of first control signals, and provide the first control signals to the display through the display interface to control the Display; and The second processing core is configured to repeatedly switch from the dormant state to the active state during the dive, verify the diving information, and switch back to the dormant state when the diving information is verified as correct; Wherein, the diving information is stored in at least one non-volatile memory included in the diving information device. The diving information device according to claim 1, wherein the first processing core consumes less energy when it is in the active mode than when the second processing core is not in the dormant state. The diving information device according to claim 2, wherein the first processing core is included in a microcontroller, and the second processing core is included in a microprocessor, and the microcontroller is external to the microprocessor and The microprocessor is external to the microcontroller. The diving information device of claim 1, further comprising two pressure sensors, wherein the first processing core is configured to be when the diving information device overlaps between the effective ranges of the two pressure sensors When in the depth area, the pressure sensor data is received from the two pressure sensors, and a warning is provided to the user in response to judging that the two pressure sensors provide pressure data that are inconsistent with each other. The diving information device according to claim 1, wherein the diving information includes at least one of the following: the remaining time before the ascent should begin, the amount of remaining air, information from other divers, and the depth as a function of time. The diving information device according to claim 1, wherein the first processing core is configured to store the diving information in a first non-volatile memory, and the second processing core is configured to access the second The diving information in the non-volatile memory, the first non-volatile memory and the second non-volatile memory are arranged to copy the diving information. The diving information equipment according to claim 6, wherein the first non-volatile memory and the second non-volatile memory are not of the same type. The diving information device according to claim 1, wherein the first processing core is configured to restart in response to an error condition occurring during diving, and continue to maintain the diving information after the restart. The diving information device according to claim 1, wherein the second processing core is configured to stop maintaining the diving information because the diving information is verified to be incorrect. The diving information device according to claim 9, wherein the second processing core is configured to maintain the diving information for the remainder of the dive after stopping the maintenance of the diving information by the first processing core. The diving information device according to claim 1, wherein the at least one non-volatile memory is external to the first processing core and the second processing core. The diving information device according to any one of claims 1 to 11, wherein the diving information device is further configured to trigger the second processing core in response to determining that the remaining time before the ascent to the surface should be started is less than a predetermined length of time From the dormant state to the active state, and use the second processing core to provide a graphical alert to the user, the graphical alert belongs to a type that the first processing core cannot provide. A method for diving information equipment, including: The first processing core maintains diving information related to the progress of the dive during the dive. The first processing core generates a plurality of first control signals, and the first processing core provides the information through the display interface. Wait for the first control signal to the display to control the display; and The second processing core repeatedly switches from the dormant state to the active state during the dive, and the second processing core verifies the diving information and switches back to the dormant state as the diving information is verified to be correct; Wherein, the diving information is stored in at least one non-volatile memory included in the diving information device. The method according to claim 13, wherein when the first processing core is in the active mode, energy consumption is lower than when the second processing core is not in the dormant state. The method of claim 14, wherein the first processing core is included in a microcontroller, and the second processing core is included in a microprocessor, the microcontroller is external to the microprocessor and the micro The processor is external to the microcontroller. The method according to claim 13, wherein the diving information device further includes two pressure sensors, and wherein, when the diving information device is in an overlapping depth area between the effective ranges of the two pressure sensors The first processing core receives pressure sensor data from the two pressure sensors, and in response to determining that the two pressure sensors provide pressure data that are inconsistent with each other, provide a warning to the user. The method of claim 13, wherein the diving information includes at least one of the following: the remaining time before the ascent should begin, the remaining air volume, information from other divers, and the depth as a function of time. The method according to claim 13, comprising: storing the diving information in a first non-volatile memory by the first processing core, and accessing the diving information in a second non-volatile memory by the second processing core The diving information in the body, the first non-volatile memory and the second non-volatile memory are arranged to replicate the diving information. The method according to claim 18, wherein the first non-volatile memory and the second non-volatile memory are not of the same type. The method according to claim 13, further comprising: restarting the first processing core in response to an error state occurring during diving, and after the restarting, the first processing core continues to maintain the diving information. The method according to claim 13, further comprising: the second processing core stops maintaining the diving information because the diving information is verified as incorrect. The method according to claim 21, wherein the second processing core maintains the diving information for the remainder of the dive after stopping the first processing core to maintain the diving information. The method according to any one of claims 13-22, wherein the at least one non-volatile memory is external to the first processing core and the second processing core. A non-transitory computer-readable medium having a computer-readable instruction set stored therein. When the computer-readable instruction set is executed by at least one processor, the diving information equipment is at least: The first processing core maintains diving information related to the progress of the dive during the dive. The first processing core generates a plurality of first control signals, and the first processing core provides the information through the display interface. Wait for the first control signal to the display to control the display; and The second processing core repeatedly switches from the dormant state to the active state during the dive, and the second processing core verifies the diving information and switches back to the dormant state as the diving information is verified to be correct; Wherein, the diving information is stored in at least one non-volatile memory included in the diving information device.

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