TW202135134A - Glass wafers for semiconductor device fabrication - Google Patents

Abstract

Embodiments of a glass wafer for semiconductor fabrication processes are described herein. In some embodiments, a glass wafer includes: a glass substrate comprising: a top surface, a bottom surface opposing the top surface, and an edge surface between the top surface and the bottom surface; a first coating disposed atop the glass substrate, wherein the first coating is a doped crystalline silicon coating having a sheet-resistance of 100 to 1,000,000 ohm per square; and a second coating having one or more layers disposed atop the glass substrate, wherein the second coating comprises a silicon containing coating, wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm.

Description

Glass wafers for semiconductor component manufacturing

This application claims the right of priority based on the patent law of the U.S. Provisional Application Serial No. 62/940,996 filed on November 27, 2019, the content of which relies on this and is incorporated herein by reference in its entirety.

The embodiments of the disclosed invention generally relate to semiconductor manufacturing processes, and more specifically to glass wafers for semiconductor component manufacturing.

For decades, various forms of silicon wafers have been used to manufacture integrated circuits. Therefore, modern semiconductor manufacturing equipment was established to inspect and process silicon wafers.

For example, manufacturing tools used in the process of manufacturing integrated circuits and other equipment include automatic loading and unloading equipment (for example, automatic loading and unloading of wafer cassettes in lithography equipment, etching equipment, etc.). These wafer cassette autoloaders rely on a variety of sensors to determine the placement, position, and position confirmation of wafers when they enter and exit the tool. This is done through the use of wafer planes, notches, or other similar mechanisms located at the edge of the wafer, which must be correctly oriented within the tool.

Silicon is the main semiconductor material used today. In order to use glass in manufacturing equipment designed to inspect and process silicon wafers, semiconductor manufacturing equipment needs to be adjusted to suit the glass. For example, one problem is that many sensors are designed to sense silicon wafers. Existing sensors are mechanical, optical and/or inductive/capacitive in nature. Although mechanical type sensors can be used with other materials, electrical or optical sensors are not always used with other materials. Although each sensor on the tool can be changed to be able to sense wafers made of other (ie, non-silicon) materials, this is undesirable in a manufacturing environment. Another problem is that the electrostatic chuck usually used in semiconductor manufacturing equipment uses an electrostatic field to hold the wafer in place, but the electrostatic chuck configured for silicon wafers is not suitable for those that are not susceptible to electrostatic fields (such as dielectrics). Wafer material such as glass material.

Therefore, the inventor has developed an improved glass substrate for semiconductor element manufacturing process.

This document describes an example of a glass wafer used for semiconductor components. In some embodiments, the glass wafer for semiconductor components includes: a glass substrate, which includes: a top surface (102), a bottom surface (104) opposite to the top surface, and an edge surface between the top surface and the bottom surface (106); The first coating (108), which is arranged above the glass substrate, wherein the first coating is a silicon coating of doped crystals with a sheet resistance of 100 to 1,000,000 ohms per square; a second coating Layer (110), the second coating has one or more layers disposed on the glass substrate, wherein the second coating includes a silicon-containing coating, and the average transmittance of the glass wafer in the entire wavelength range from 400nm to 1000nm ( T) is less than 50%.

In some embodiments, the glass wafer for semiconductor components includes: a glass substrate, which includes: a top surface (102), a bottom surface (104) opposite to the top surface, and an edge surface between the top surface and the bottom surface (106); Coating (110), the coating (110) has one or more layers disposed on the glass wafer, wherein the coating includes a silicon-containing coating, and the glass wafer is in the entire wavelength of 400nm to 1000nm The average transmittance (T) in the range is less than 50%.

In some embodiments, a method of manufacturing an electronic component includes: loading a glass wafer on a substrate support in a substrate aligner chamber, wherein the substrate aligner includes a light source; and an optical sensor, the optical sensor The detector is configured to detect the light beam from the light source, wherein the glass wafer includes: a glass substrate, which includes: a top surface, a bottom surface opposite to the top surface, and an edge surface between the top surface and the bottom surface; Layer, which is arranged above the glass substrate, wherein the first coating is a silicon coating of doped crystals with a sheet resistance of 100 to 1000000 ohms per square; the second coating has a silicon coating arranged above the glass substrate One or more layers, where the second coating includes a silicon-containing coating, where the average transmittance (T) of the glass wafer in the entire wavelength range from 400nm to 1000nm is less than 50%; the substrate support is rotated to position the glass wafer on A predetermined position in the substrate aligner chamber, where the light beam from the light source reaches the predetermined position when the optical sensor detects the light beam; and the glass wafer is transferred to the semiconductor processing chamber for further processing.

In some embodiments, the glass wafer for semiconductor components includes: a glass substrate, which includes: a top surface (102), a bottom surface (104) opposite to the top surface, and an edge surface between the top surface and the bottom surface (106); and a silicon-containing coating disposed on a glass substrate, wherein the silicon-containing coating includes at least two silicon-containing layers, and the difference in refractive index values of adjacent layers is greater than 0.5.

Other and further embodiments of the disclosed invention are described below.

In the following detailed description, for the purpose of explanation and not limitation, example embodiments disclosing specific details are set forth to provide a thorough understanding of various principles of the disclosed invention. However, it will be obvious to a person of ordinary skill in the art that the disclosed invention can be practiced in other embodiments different from the specific details disclosed herein. In addition, descriptions of well-known devices, methods, and materials may be omitted so as not to obscure the description of various principles of the disclosed invention. Finally, where applicable, the same component symbols indicate the same components.

Unless expressly stated otherwise, it is by no means intended to interpret any method set forth herein as requiring its steps to be executed in a specific order. Therefore, in the case that the method claim does not actually state the order in which the steps are to be followed, or the scope of the patent application or the specification does not specify in other ways that the steps should be limited to a specific order, it does not mean that in any respect Can infer the order. This applies to any possible non-expressive interpretation basis, including: logical problems related to the arrangement of steps or operating procedures; simple meanings derived from grammatical organization or punctuation; and the number or type of embodiments described in the specification.

As used herein, the term "and/or" when used in a list of two or more items means that any one of the listed items can be used alone, or any combination of two or more of the listed items Available items. For example, if the composition is described as comprising parts A, B and/or C, the composition may comprise A alone; B alone, or C alone; A and B combined; A and C combined; B and C combined ; Or A, B and C combination.

Semiconductor components are manufactured through a series of manufacturing steps, such as thin film deposition, oxidation or nitrification, etching, polishing, and thermal and lithographic processing. Although multiple manufacturing steps can be performed in a single processing apparatus, for at least some manufacturing steps, wafers must be transported between different processing tools.

The semiconductor manufacturing steps are carried out using automated machinery. Wafers are stored in conveyors for transfer between processing tools and other locations. Before being transported to the processing tool, the transported wafers must be correctly aligned to enable the processing tool to complete the necessary manufacturing steps.

Commonly used orientation methods involve the use of optical sensors that have a light source, usually a visible light source, and a detector for generating and detecting a light beam. A silicon wafer with notches along its edges is located on the rotating support surface. The surface of the silicon wafer is opaque and will block the light beam from passing between the light source and the detector. However, when the silicon wafer is rotated so that the notch is at the position of the beam, the detector senses the beam and stops the rotation of the support surface. Then, the stopped support surface maintains the silicon wafer and is then in place for transfer to, for example, a lithography device for processing the wafer to form a circuit.

Since the glass wafer is transparent, the light beam from the light source will pass through the glass wafer and the notch. That is, the sensor cannot distinguish between the glass wafer and the notch. Therefore, the glass wafer will not stop rotating, and the transfer to the manufacturing tool will not occur.

The presently disclosed invention describes glass wafers for semiconductor device manufacturing, which overcomes the problems associated with sensors that do not work with glass wafers. As used herein, the term "wafer" refers to a supporting surface suitable for forming electronic components thereon. In addition, glass has certain unique characteristics that make it ideal for certain applications. For example, for radio frequency (RF) components, glass has lower RF loss and lower non-linearity compared to ordinary silicon. Products such as radio frequency switches and antenna tuners can benefit from glass in next-generation networks and mobile phones. The embodiments of glass wafers described herein have various coatings formed thereon. For convenience, the term "coating" is intended to include a film, coating, or layer disposed on a surface.

The coating layer disposed on the glass wafer is formed by any method known in the art, including discrete deposition or continuous deposition process. In some embodiments, the coating is deposited by plasma enhanced chemical vapor deposition (PECVD) as commonly used in the art. In some embodiments, as commonly used in the art, the coating is deposited by physical vapor deposition (PVD). As used herein (eg, with respect to glass wafer 100), the term "arrangement" includes coating, depositing, and/or forming materials on a surface using any method known in the art. The arranged material may constitute a coating as defined herein. The phrase "placed on" includes an example of forming a material on a surface so that the material is in direct contact with the surface, and also includes an example of forming a material on the surface, in which one or more intermediate materials are placed between the material and the surface. between. As defined herein, the intermediate material may constitute the coating.

The embodiment of the glass wafer described herein includes a glass substrate 118 including a top surface 102, a bottom surface 104 opposite to the top surface 102, and an edge surface 106 between the top surface 102 and the bottom surface 104, The first coating and the second coating. FIG. 1A depicts a glass substrate 118 that includes a top surface 102, a bottom surface 104 opposite to the top surface 102, and an edge surface 106 between the top surface 102 and the bottom surface 104. The top surface 102 is the surface of a glass substrate 118, which has various coatings disposed thereon, as described herein. In some embodiments, the glass substrate 118 may be any size suitable for use with existing semiconductor manufacturing equipment. For example, in some embodiments, the glass substrate 118 may have a diameter of 300 mm. In some embodiments, the glass substrate 118 may have a diameter of 200 mm. In some embodiments, the glass substrate 118 has a diameter of 300 mm and a thickness of 0.3 mm to 1 mm, preferably a thickness of 0.5 mm to 0.8 mm, more preferably a thickness of 0.75 mm to 0.8 mm. In some embodiments, the glass substrate 118 has a diameter of 300 mm and a thickness of 0.775 mm. In some embodiments, the glass substrate 118 has a diameter of 200 mm and a thickness of 0.725 mm.

In some embodiments, the glass substrate 118 may be high-purity fused silica (HPFS) glass, or alkali-free silicate glass, or borosilicate glass, or alkali metal aluminosilicate glass, or alkali metal aluminum. Borosilicate glass, or alkaline earth boroaluminosilicate glass, etc. High-purity fused silica (such as Corning's HPFS® high-purity fused silica 7980 glass) has extremely high purity due to its manufacturing process and is 100% compatible with the front end of the production line (FEOL) environment. The front end of the production line (FEOL) refers to the first part of integrated circuit manufacturing, where individual components (such as transistors, capacitors, resistors, etc.) are patterned in the semiconductor. Therefore, the front end of the production line (FEOL) processing is sensitive to the introduction of contaminants (materials that are not normally present in integrated circuit manufacturing). In addition, in many FEOL treatments, non-silicon-based metals are not allowed. Therefore, the coatings discussed below are silicon-containing materials, such as amorphous silicon, polysilicon, silicon nitride, silicon dioxide, or silicon oxynitride. In some embodiments, the coating discussed below may be amorphous germanium (a-Ge). As described below, although interference-based coatings can provide broadband and low transmittance, some optical sensors may require extremely low transmittance, which can only be achieved with reflective or absorptive filters. Although many metals are good reflective materials, they are not friendly to FEOL and therefore are not accepted in typical semiconductor manufacturing. On the other hand, germanium is widely accepted as a suitable material in semiconductor manufacturing processes. Amorphous germanium is an exemplary material with absorption and transmission characteristics, which can be used to deliver coatings with low transmittance in the visible spectrum window, while the transmittance up to 1000 nm in the near infrared (NIR) window is less than 40%. Figure 9A shows the transmittance of a 300nm thick a-Ge layer on a 775 µm thick fused silica substrate. Figure 9B shows the transmittance of a 300nm thick a-Ge layer combined with a 50nm doped nanocrystalline silicon layer on a 775µm thick fused silica substrate. The latter combination will provide the optical and electrical performance required by a typical semiconductor factory, where the semiconductor factory is configured to process silicon wafers. The transmittance of a 300nm thick a-Ge layer at 650nm is less than 0.01%, which is a typical sensor wavelength used with LED light sources.

In some embodiments, the glass substrate 118 is melt-formed glass. Melt stretching treatment may produce a brand-new polished glass surface, thereby reducing the surface adjustment distortion of high-resolution TFT backplanes and color filters. The down-draw sheet stretching process can be used herein, and especially the melting process described in US Patent Nos. 3,338,696 and 3,682,609 (both of Dockerty), which are incorporated into this case by reference. Without being bound by any particular theory of operation, it is believed that melt processing can produce glass substrates that do not require polishing. The average surface roughness of the glass substrate produced by the melting process is less than 0.2nm (Ra) measured by atomic force microscopy. This low roughness helps in critical applications that require bonding to another flat surface.

In some embodiments, as shown in FIG. 2, the glass substrate 118 may have a passivation coating 112. For glass substrates 118 that are not pure silicon dioxide (ie 100% by weight silicon dioxide), the passivation coating 112 prevents non-silicon glass components from migrating out and contaminating semiconductor manufacturing equipment. In some embodiments, the passivation coating 112 is provided on the top surface 102, the bottom surface 104 and the edge surface 106 of the glass substrate 118. In some embodiments, the passivation coating 112 is one of silicon nitride, silicon dioxide, or silicon oxynitride. The thickness of the passivation coating 112 may be adjusted based on the density and porosity of the passivation coating and based on the temperature and temperature exposure time of the coating in the semiconductor manufacturing process. In some embodiments, the passivation coating 112 has a thickness of 100 angstroms to 10,000 angstroms, preferably 500 angstroms to 1000 angstroms.

3A and 3B depict a glass wafer 100 having a glass substrate 118 with an (optional) passivation coating 112 and a first coating 108 and a second coating 110.

The first coating 108 is a doped crystalline silicon coating, and its silicon crystal size is in the range of nanometers to micrometers (a range of nanocrystals to microcrystals). Exemplary dopants that can be used include phosphorus, boron, or arsenic. The typical electrostatic chuck in semiconductor manufacturing equipment is designed to suck wafers, so glass wafers cannot be sucked without a significantly higher operating voltage. Therefore, the first coating 108 provided on one side of the glass substrate 118 provides a typical electrostatic chuck with sufficient conductivity (that is, at a working voltage suitable for the adsorption of silicon wafers) to attract the glass substrate to the electrostatic Sucker. In order to enable the glass wafer 100 to be adsorbed to the electrostatic chuck, the sheet resistance of the doped crystalline silicon coating is 100 ohms per square to 1,000,000 ohms per square, preferably 100 ohms per square to 250,000 ohms per square, and more preferably It ranges from 100 ohms per square to 50,000 ohms per square. As used herein, the term "sheet resistance" refers to the isotropic resistivity of a layer relative to its thickness. The sheet resistance can be measured using the four-point probe method. The four-point probe method is a common test method used to measure the resistivity of any semiconductor material. The four-point probe setup consists of four tungsten tips with finite radius and equal spacing. The other end of each tip is supported by a spring to minimize damage to the sample during detection. The four metal tips are part of an automated mechanical platform that moves up and down during the measurement process. The high impedance current source is used to provide current through the two external probes; the voltmeter measures the voltage of the two internal probes to determine the resistivity of the sample. The typical probe pitch is about 1 mm.

In some embodiments, the thickness of the doped crystalline silicon coating 108 is at least 100 angstroms, and preferably at least 500 angstroms. In some embodiments, the doped crystalline silicon coating 108 is phosphorus-doped nanocrystalline silicon, which has a thickness of 500 angstroms and a sheet resistance of 2000 ohms/square.

In some embodiments, the second coating 110 is a silicon-containing coating composed of one or more layers. In some embodiments, the second coating 110 includes an undoped amorphous silicon layer. In some embodiments, the second coating 110 includes an undoped amorphous germanium layer. In some embodiments, the second coating layer 110 includes a silicon nitride layer, an undoped amorphous silicon layer, and a silicon dioxide layer, wherein the silicon nitride layer is disposed on the undoped amorphous silicon layer and is undoped The hetero amorphous silicon layer is arranged above the silicon dioxide layer, and the silicon dioxide layer is above the doped crystalline silicon coating. The above-mentioned coatings and their order are exemplary, and can be modified by a person of ordinary skill in the art to realize a glass substrate having a transmittance (T) range described below.

In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 5 microns. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 4 microns. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 3 microns. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 2 microns. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 1 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is greater than 0.1 micrometers to less than 5 micrometers. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is greater than 0.1 micrometer to less than 1 micrometer.

In some embodiments, the doped crystalline silicon coating 108 is provided on the top surface 102 of the glass substrate 118. In some embodiments, as shown in FIGS. 3A-3B, the doped crystalline silicon is disposed on the entire top surface 102 of the glass substrate 118. In some embodiments, the doped crystalline silicon coating 108 is directly disposed on the top surface 102 of the glass substrate 118 (ie, there is no intermediate coating between the glass substrate 118 and the doped crystalline silicon coating 108). In some embodiments, as shown in FIG. 3A, the doped crystalline silicon coating 108 is directly disposed on the passivation coating 112. In some embodiments, as shown in FIG. 3B, the doped crystalline silicon coating 108 may be part of a multilayer stack formed by a second coating (described below), where the second coating includes at least two layers and the first A coating 108 is located between at least two layers of the second coating 110a, 11b.

In some embodiments, as shown in FIG. 3A, the second coating 110 is directly disposed on the doped crystalline silicon coating 108. In some embodiments, the second coating 110 is directly disposed on the glass substrate 100 (ie, there is no passivation coating and no first coating). In some embodiments, the second coating 110 is directly disposed on the passivation coating 112 (ie, there is no first coating). In some embodiments, the second coating 110 covers the entire top surface of the layer directly below (eg, the entire surface of the glass substrate 118). In some embodiments, the second coating 110 covers a portion of the surface directly below, the portion having a radial distance of 2 mm from the edge to the center of the surface facing directly below.

The following Table 1 depicts an example of a glass wafer according to some embodiments of the presently disclosed invention, in which the glass substrate 118 is high-purity fused silica glass, which has phosphorus-doped nanocrystals disposed above the high-purity fused silica glass substrate. _{A silicon layer, a silicon dioxide (SiO 2} ) layer arranged above the phosphorus-doped nanocrystalline silicon layer, an amorphous silicon layer arranged above the silicon dioxide layer, and a silicon nitride layer arranged above the amorphous silicon layer. Table 1 also shows the refractive index of each layer of the silicon-containing coating disposed on the glass substrate. The coating shown in Table 1 has four silicon-containing layers, where the difference in refractive index values between adjacent layers is greater than 0.5. In some embodiments, the difference in refractive index values between adjacent layers is greater than one. In some embodiments, the difference in refractive index values between adjacent layers is greater than two. In the embodiment shown in Table 1, the outermost layer (that is, the layer farthest from the substrate) is silicon nitride. In some embodiments, the outermost layer may be silicon dioxide or silicon oxynitride. In some embodiments, the outermost layer of silicon nitride or silicon oxynitride provides mechanical wear resistance to the glass wafer. Table 1 Floor Material 510nm refractive index Body thickness (nm) 1 Silicon nitride 1.84 75 2 Amorphous silicon 4.52 52 3 Silicon dioxide (SiO ₂ ) 1.48 116 4 Phosphorus-doped nanocrystalline silicon 4.11 45 Substrate High purity fused silica (HPFS) 1.46

Figure 7A depicts the relationship between transmittance and wavelength, in which the thickness of each layer of the coating in Table 1 is randomly adjusted (for example, increased or decreased) through a random number, and the random number corresponds to its average value. A Gaussian distribution with the design thickness of the layer and its variance equal to 10% of the design thickness of the layer. Calculate the transmittance of the coating randomly adjusted in the wavelength range of 400nm to 1000nm. This process is executed 100 times, and produces the curve shown in FIG. 7A. As shown in FIG. 7A, for a random thickness change of 10%, the transmittance of the coating in Table 1 is less than 40% in the wavelength range of 400 nm to 1000 nm.

Figure 7B depicts the relationship between transmittance and wavelength, where the thickness of each layer of the coating in Table 1 is randomly adjusted (for example, increased or decreased) through a random number, the random number corresponding to its average value for the layer design Thickness and its variance is a Gaussian distribution of 10% of the layer design thickness, and the refractive index of each layer is randomly adjusted (for example, increased or decreased) through a random number, which corresponds to the average value of the layer refractive index and its The variance is a Gaussian distribution of 5% of the refractive index of the layer. Calculate the transmittance of the coating randomly adjusted in the wavelength range of 400nm to 1000nm. This process is executed 100 times, and the curve shown in FIG. 7B is produced. As shown in FIG. 7B, for a random thickness change rate of 10% and a random refractive index change rate of 5%, the transmittance of the coating in Table 1 is less than 50% in the wavelength range of 400 nm to 1000 nm.

The following Table 2 depicts an example of a glass wafer according to some embodiments of the presently disclosed invention, in which the glass substrate 118 is high-purity fused silica glass, which has a nanocrystalline silicon layer disposed on the high-purity fused silica glass substrate _{, A silicon dioxide (SiO 2} ) layer arranged on the nanocrystalline silicon, an amorphous silicon layer arranged on the silicon dioxide layer, and a silicon dioxide layer arranged on the amorphous silicon layer. Table 1 also shows the refractive index of each layer of the silicon-containing coating disposed on the glass substrate. Table 2 Floor Material 950nm refractive index Body thickness 1 Silicon dioxide 1.45 50 nm 2 Amorphous silicon 3.60 38 nm 3 Silicon dioxide (SiO ₂ ) 1.45 99 nm 4 Nanocrystalline silicon 4.11 75 nm Substrate High purity fused silica (HPFS) 1.46 0.7mm

Figure 8A depicts the relationship between transmittance and wavelength, where the thickness of each layer of the coating in Table 2 is randomly adjusted (for example, increased or decreased) through a random number, which corresponds to the average value of the layer A Gaussian distribution with a design thickness and a variance of 10% of the layer design thickness. Calculate the transmittance of the coating randomly adjusted in the wavelength range of 400nm to 1000nm. This process is performed 100 times, and produces the curve shown in FIG. 8A. As shown in FIG. 8A, for a random thickness change of 10%, the transmittance of the coating in Table 2 is less than 40% in the wavelength range of 400 nm to 1000 nm.

Figure 8B depicts the relationship between transmittance and wavelength, in which the thickness of each layer of the coating in Table 2 is randomly adjusted (for example, increased or decreased) through a random number, the random number corresponding to its average value for the layer design Thickness and its variance is a Gaussian distribution of 10% of the layer design thickness, and the refractive index of each layer is randomly adjusted (for example, increased or decreased) through a random number, which corresponds to the average value of the layer refractive index and its The variance is a Gaussian distribution of 5% of the refractive index of the layer. Calculate the transmittance of the coating randomly adjusted in the wavelength range of 400nm to 1000nm. This process is executed 100 times, and the curve shown in FIG. 8B is produced. As shown in FIG. 8B, for a random thickness change rate of 10% and a random refractive index change rate of 5%, the transmittance of the coating in Table 2 is less than 60% in the wavelength range of 400 nm to 1000 nm.

The glass wafer 100 has an average transmittance (T) value of less than 50%, preferably less than 40%, and more preferably less than 30% in the entire wavelength range of 400 nm to 1000 nm. As used herein, the "average transmittance value" refers to the sum of the transmittance values at each wavelength in the defined wavelength range divided by the number of wavelengths in the defined wavelength range. In some embodiments, the glass wafer 100 has an average transmittance (T) value of less than 50%, preferably less than 40%, and more preferably less than 30% in the entire wavelength range of 400 nm to 2500 nm. In some embodiments, the glass wafer 100 has a transmittance value of less than 50%, preferably less than 40%, and more preferably at each wavelength in a defined wavelength range (for example, 400nm to 1000nm or 400nm to 2500nm) Land is less than 30%. As used herein, the term "transmittance" is defined as the percentage of incident light power transmitted through the glass wafer 100 within a given wavelength range. Generally, transmittance is measured using a specific line width.

FIG. 4 depicts an exemplary wafer according to some embodiments of the disclosed invention, the exemplary wafer being located in some exemplary semiconductor manufacturing systems according to the disclosed invention. In order to correctly position or orient the glass wafer in each step of the forming process, the glass wafer may have a notch along a part of the edge, and the notch is used for orientation in the substrate aligner chamber 408. Figure 1B depicts a glass wafer 100 with notches 114 along its edges. The notch is specified in the SEMI™ semiconductor wafer standard.

In some embodiments, a method of manufacturing an electronic component includes loading a glass wafer 400 as described in the above embodiments on a substrate support (not shown) in a substrate aligner chamber 408. The substrate aligner chamber 408 includes a light source 404 and an optical sensor 406 configured to detect the light beam from the light source 404. The glass wafer 404 includes a top surface, a bottom surface opposite to the top side, an edge surface between the top surface and the bottom surface, the first coating layer as described in the above embodiment and the first coating layer as described in the above embodiment. Two coatings. In some embodiments, the glass wafer 404 may also include a passivation coating. The substrate support rotates the glass wafer 400 to a predetermined position in the substrate aligner chamber. When the optical sensor detects the light beam from the light source, it will reach a predetermined position. When the glass wafer 400 is rotated in the substrate aligner chamber 408 shown in FIG. 4, the optical sensor 406 cannot read the light from the light source 404 due to the second coating 110 provided on the glass wafer 400 . When the notch 402 reaches the light beam, the notch is read by the optical sensor 406, and the glass wafer 400 is therefore in place for transfer to the manufacturing tool 410 for further processing.

In some embodiments, the glass wafer may undergo a semiconductor manufacturing process in which the glass wafer is heated and then cooled to room temperature. After heat treatment at 350 degrees Celsius for 2 hours, and cooling to room temperature (for example 25 degrees Celsius) at a cooling rate of 10 degrees per minute, the glass wafers described in the examples herein compare the average transmittance to the The transmittance at each wavelength in the wavelength range is maintained at less than 50%, preferably less than 30%.

5A and 5B show the transmittance versus wavelength diagram of an exemplary glass wafer having a doped nanocrystalline silicon coating, nitrogen, and a doped nanocrystalline silicon coating directly disposed on the top surface 102 of the glass wafer 100 A silicon layer, an undoped amorphous silicon layer and a silicon dioxide layer. The silicon nitride layer is arranged above the undoped amorphous silicon layer. The undoped amorphous silicon layer is arranged above the silicon dioxide layer. The silicon dioxide layer is on top of the doped nanocrystalline silicon coating.

The graph 500 depicted in FIG. 5A shows that an exemplary glass wafer has been heat treated at 350 degrees Celsius for 2 hours and cooled to room temperature (eg, 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute ("heat treatment") The subsequent transmittance curve 504 and the transmittance curve 502 before the heat treatment of the glass wafer. For the graph 500, transmittance data is collected from two points along the edge of the glass wafer on the uncoated side. The graph 506 depicted in FIG. 5B shows the transmittance curve of an exemplary glass wafer after being heat treated at 350 degrees Celsius for 2 hours and cooled to room temperature (eg, 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute 508, and the transmittance curve 510 of the glass wafer before being subjected to the heat treatment. For graph 506, transmittance data is collected from two points along the edge of the glass wafer on the coated side. Based on the graphs 5A and 5B, the exemplary glass wafer maintains an average transmittance and transmittance at each wavelength in the wavelength range from 400 nm to 1100 nm to be less than 50% even after the above-described heat treatment.

FIGS. 6A-6D show the relationship between reflectivity and wavelength of the exemplary glass transport wafer described above with respect to FIGS. 5A-5B. 6A is a graph 600 of reflectance versus wavelength, which shows that the glass wafer has been heat treated at 350 degrees Celsius for 2 hours and cooled to room temperature (for example, 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute. The reflectance curve 602 of, and shows the reflectance curve 604 for the glass wafer before the heat treatment, where the reflectance is measured from the uncoated surface of the glass wafer at an incident angle of 5 degrees.

Figure 6B is a graph 606 of reflectance versus wavelength, showing the glass wafer after being heat treated at 350 degrees Celsius for 2 hours and cooled to room temperature (for example, 25 degrees Celsius) at a cooling rate of 10 degrees per minute. The reflectance curve 608, and the reflectance curve 610 of the glass wafer before heat treatment, where the reflectance is measured from the uncoated surface of the glass wafer at an incident angle of 45 degrees.

6C is a graph 612 of reflectance versus wavelength, which shows the glass wafer after being heat-treated at 350 degrees Celsius for 2 hours and cooled to room temperature (for example, 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute The reflectance curve 614 of the glass wafer, and the reflectance curve 616 of the glass wafer before the heat treatment, where the reflectance is measured from the coated surface of the glass wafer at an incident angle of 5 degrees. As shown in FIG. 6C, after the heat treatment of the glass wafer, the reflectance value in the wavelength range of 400 nm to 1100 nm is substantially similar to the reflectance value before the heat treatment.

Figure 6D is a graph 618 of reflectance versus wavelength, showing the glass wafer after being heat treated at 350 degrees Celsius for 2 hours and cooled to room temperature (for example, 25 degrees Celsius) at a cooling rate of 10 degrees per minute. The reflectance curve 620, and the reflectance curve 622 of the glass wafer before the heat treatment, where the reflectance is measured from the coated surface of the glass wafer at an incident angle of 45 degrees.

In some embodiments, the wafer used in the semiconductor processing equipment has a minimum reflectivity value to enable the equipment to sense the presence of the wafer. Figure 6D shows the reflectance values of silicon (a commonly used wafer material) in the wavelength range of 400nm to 1100nm. As shown in FIG. 6D, the glass wafer with the exemplary coating has an average reflectance value that meets or exceeds silicon in the wavelength range of about 510 nm to 1100 nm. In some embodiments, the reflectance value at each wavelength in the wavelength range of approximately 510 nm to 1100 nm meets or exceeds the reflectance value of silicon. As used herein, "average reflectance value" refers to the sum of reflectance values at each wavelength in a defined wavelength range (for example, 510 nm to 1100 nm) divided by the number of wavelengths in the defined wavelength range.

Although the foregoing content is directed to the embodiments of the disclosed invention, other and further embodiments of the disclosed invention can be designed without departing from the basic scope of the disclosed invention.

102: top surface 104: bottom surface 106: edge surface 108: First coating 110: second coating 100: glass wafer 118: Glass substrate 112: Passivation coating 108: doped crystalline silicon coating 100: glass substrate 408: aligner chamber 114: Notch 400: Glass wafer 404: light source 406: Optical Sensor 402: Notch 410: Manufacturing Tools 500: curve graph 504: Transmittance curve 502: Transmittance curve 506: curve graph 602: reflectivity curve 600: curve graph 604: reflectivity curve 606: curve graph 608: reflectivity curve 610: reflectivity curve 612: Graph 614: reflectivity curve 616: reflectivity curve 618: curve graph 620: reflectivity curve 622: reflectivity curve

By referring to the illustrative embodiments of the presently disclosed invention depicted in the accompanying drawings, the embodiments of the presently disclosed invention may be briefly summarized above and discussed in more detail below. However, it should be noted that the drawings only show typical embodiments of the disclosed invention, and therefore should not be considered as limiting its scope.

Figures 1A-1B depict exemplary glass substrates according to some embodiments of the disclosed invention.

Figure 2 depicts an exemplary glass substrate with a passivation coating according to some embodiments of the disclosed invention.

Figures 3A-3B depict exemplary glass wafers according to some embodiments of the disclosed inventions.

4 depicts an exemplary glass wafer according to some embodiments of the disclosed invention located within an exemplary semiconductor manufacturing system according to some embodiments of the disclosed invention.

5A and 5B show graphs of transmittance versus wavelength of exemplary glass wafers according to some embodiments of the presently disclosed invention.

6A-6D show graphs of reflectance versus wavelength of exemplary glass wafers according to some embodiments of the presently disclosed invention.

FIG. 7A depicts a graph of the transmittance versus wavelength of the exemplary coating in Table 1, and the thickness change rate of each layer is 10%.

FIG. 7B depicts a graph of the transmittance versus wavelength of the exemplary coating in Table 1, each of which has a thickness change rate of 10% and a refractive index change rate of 5%.

FIG. 8A depicts a graph of the transmittance versus wavelength of the exemplary coating in Table 2, and the thickness change rate of each layer is 10%.

FIG. 8B depicts a graph of the relationship between transmittance and wavelength of the exemplary coatings in Table 2. The thickness change rate of each layer is 10%, and the refractive index change rate is 5%.

Figure 9A depicts the transmission of a 300nm thick a-Ge layer on a fused silica substrate.

Figure 9B shows the transmission of a 300nm thick a-Ge layer and a 50nm doped nanocrystalline silicon layer combined on a fused silica substrate.

For ease of understanding, the same component symbols are used where possible to represent the same components in the drawings. The drawings are not drawn to scale and may be simplified for clarity. It is expected that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further description.

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102: top surface

104: bottom surface

106: edge surface

118: Glass substrate

Claims (13)

A glass wafer for semiconductor components, including: A glass substrate comprising: a top surface; a bottom surface opposite to the top surface; and an edge surface between the top surface and the bottom surface; and A first coating layer disposed on the glass substrate, wherein the first coating layer is a doped crystalline silicon coating having a sheet resistance of 100 to 1,000,000 ohms per square; and A second coating, the second coating having one or more layers disposed on the glass substrate, wherein the second coating includes a silicon-containing coating, Wherein, the average transmittance (T) of the glass wafer in an entire wavelength range from 400 nm to 1000 nm is less than 50%. The glass wafer according to claim 1, wherein a transmittance at each wavelength in the wavelength range is less than 50%. The glass wafer according to claim 1, wherein: (i) the first coating is directly disposed on the top surface of the glass substrate, and the second coating is directly disposed on the first coating Or (ii) the second coating layer includes at least two layers, and wherein the first coating layer is located between the at least two layers of the second coating layer. The glass wafer according to claim 1, wherein the doped crystalline silicon coating is one of a phosphorus-doped crystalline silicon, a boron-doped crystalline silicon, or an arsenic-doped crystalline silicon. The glass wafer according to claim 1, wherein the second coating layer includes: an undoped amorphous silicon layer. The glass wafer according to claim 1, wherein the second coating layer includes: a silicon nitride layer, an undoped amorphous silicon layer, and a silicon dioxide layer, The silicon nitride layer is disposed above the undoped amorphous silicon layer, Wherein the undoped amorphous silicon layer is disposed above the silicon dioxide layer, and The silicon dioxide layer is above the doped crystalline silicon coating. The glass wafer according to any one of claims 1-6, further comprising a passivation coating on the top surface, the bottom surface and the edge surface of the glass substrate, wherein the passivation coating is nitrogen One of silicon dioxide, silicon dioxide or silicon oxynitride. A glass wafer for semiconductor components, including: A glass substrate comprising: a top surface; a bottom surface opposite to the top surface; and an edge surface between the top surface and the bottom surface; and A coating having one or more layers disposed on the glass wafer, wherein the coating includes a silicon-containing coating, and wherein the glass wafer has an average transmission in the entire wavelength range of 400 nm to 1000 nm The rate (T) is less than 50%. The glass wafer according to claim 8, wherein: (i) the coating covers an entire top surface of the glass substrate, or (ii) the coating covers a part of the top surface of the glass substrate, and the part is from A radial distance from the edge surface to a center of the top surface is 2 mm. The glass wafer according to claim 8, wherein a transmittance at each wavelength in the wavelength range is less than 50%. The glass wafer according to claim 8, wherein the coating includes: (i) an undoped amorphous silicon layer, or (ii) a silicon nitride layer, an undoped amorphous silicon layer, and Silicon dioxide layer, The silicon nitride layer is disposed above the undoped amorphous silicon layer, The undoped amorphous silicon layer is arranged above the silicon dioxide layer. A glass wafer for semiconductor components, including: A glass substrate comprising: a top surface; a bottom surface opposite to the top surface; and an edge surface between the top surface and the bottom surface; and A silicon-containing coating is arranged on the glass substrate, wherein the silicon-containing coating includes at least two silicon-containing layers, and the difference between the refractive index values of adjacent layers is greater than 0.5. The glass wafer according to claim 12, wherein the coating comprises: a silicon nitride layer, an undoped amorphous silicon layer, a silicon dioxide layer and a phosphorus-doped crystalline silicon layer, wherein the A silicon nitride layer is disposed above the undoped amorphous silicon layer, wherein the undoped amorphous silicon layer is disposed above the silicon dioxide layer, and the silicon dioxide layer is disposed above the phosphorus-doped crystalline silicon layer .

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