TW202107433A - LED display drive circuit, LED drive current modulation method, and LED display including a bit register, a display grayscale buffer, a display grayscale comparison unit, a drive PWM signal generation module, and a current source unit - Google Patents

Abstract

An LED display drive circuit includes: a bit register, a display grayscale buffer, a display grayscale comparison unit, a drive PWM signal generation module, and a current source unit. The LED display drive circuit of the present invention can pre-determine high and low grayscale values according to a data clock signal and a sequence data input signal, and generate corresponding groups of drive currents to a LED display panel according to comparison results of the grayscale values, so as to minimize interferences caused by a high grayscale display area to a low grayscale display area to the most significant extent, while reducing a cross-board color difference of the LED display panel.

Description

LED display drive circuit, LED drive current modulation method, and LED display

The present invention relates to an LED display driving chip, in particular to an LED display driving circuit and an LED driving current modulation method, and an LED display having the LED display driving circuit or applying the LED driving current modulation method.

Light-emitting diode (LED) has many advantages such as small size, light weight, long service life, sturdy structure, and high luminous efficiency. Therefore, it has become the main choice of backlight light source for display screens of portable electronic products. At present, portable electronic products with various functions, such as smart phones, notebook computers, tablet computers, digital cameras, navigation devices, car audio-visual equipment, etc., are mostly equipped with LCD screens with white LED backlight modules, making The function of LED driver chip and its cost performance have also been paid more and more attention.

Please refer to FIG. 1, which shows a structure diagram of a conventional LED display. As shown in FIG. 1, the conventional LED display includes: an LED display panel 1', a row driver 2', a column drive module 3', and a display controller 4'; wherein, the display controller 4'is usually A Field Programmable Gate Array (FPGA) chip is coupled to a video electrical connector, the row driver module 3'and the row driver 2'. The video electrical connector can be a connector such as HDMI, DVI, or VGA. It is worth noting that Figure 1 also shows that the LED display panel 1'includes Y×X LED elements 11'; wherein, the anodes of the LED elements 11' in the Yth row are commonly connected to the row line G _Y , and the X-th column The cathodes of the LED elements 11' are commonly connected to the column line S _X.

FIG. 2 shows a circuit block diagram of the column driving module 3'of FIG. 1. Electronic engineers who are familiar with the design of LED display driver chips should know that, generally speaking, the driver module 3'of this column includes: a (16) bit register 31', an output latch 32', and an output current The driver 33', a current source unit 34', and an output current regulator 35'; wherein the bit register 31' is coupled to a data transmitted by the bit register 31' of the previous group of column driver modules 3' The clock signal DCLK is also coupled to a series of data input signals SDI transmitted by the display controller 4'. On the other hand, the output latch 32' is coupled to the enable signal LE transmitted by the display controller 4'and is also coupled to the bit register 31'. It is worth noting that the output current driver 33' is simultaneously coupled to a luminance (gray scale) clock signal GCLK transmitted by the display controller 4'and the output latch 32'. Furthermore, the output current regulator 35' adjusts the current supply unit 34' based on a current adjustment signal Iset transmitted by the display controller 4'to provide to each of the column lines (S ₁ , S ₂ , ... S ₁₆ ) Of the drive current.

It is easy to understand that the brightness of each column of LED elements 11' is controlled by the driving current transmitted to each column. Fig. 3 shows a set of working waveform diagrams of the conventional LED display of Fig. 1, where G[Y] is the row driving signal of the Yth row, and PWM[X] is the PWM of the Xth column output by the output current driver 33' Signal, and S[X] is the drive current signal of the Xth column. It is worth noting that, as shown in FIG. 3, it takes a period of time for the row drive signal of the Y-th row to rise to a bias voltage, and this rise time will be affected by the number of current sources contained in the current source unit 34' . The actual application situation shows that the more the number of column currents contained in the current source unit 34', the slower the rising speed of G[Y], that is, the longer the required rise time of the bias voltage. The td1 in Figure 3 refers to the waiting time of the column, and when a bias voltage rise time of G[Y] is greater than td1, the difference between G[Y] and S[X] will be unstable, thus Cause the corresponding drive current signal S[X] to be unstable.

In addition, the existing LED display usually includes several LED display panels 1'and array drive modules 3'. It must be understood that, without properly solving the aforementioned problem that the difference between G[Y] and S[X] is unstable and the driving current signal S[X] is unstable, when the LED display operates at a high refresh rate , The instability of the driving current signal S[X] will cause serious high-contrast interference and cross-board chromatic aberration in the LED display panel 1', where the cross-board chromatic aberration refers to two modular modules adjacent to each other Obvious color difference appears between the LED display panels 1'.

Therefore, there is an urgent need in the art for a novel LED display drive circuit and LED drive current modulation method.

The main purpose of the present invention is to provide an LED drive current modulation method for an LED display drive circuit, which can pre-judge high and low grayscale values based on the data clock signal and the serial data input signal, and generate corresponding grayscale values based on the comparison result of the grayscale values. Each group drives the current signal to the LED display panel, so as to minimize the interference caused by the high grayscale display area to the low grayscale display area, and at the same time reduce the cross-board color difference phenomenon of the LED display panel.

To achieve the above objective, an LED display drive circuit is proposed, which is coupled to X column lines of an LED display panel and a display control chip, X is an integer greater than 1, and it includes:

A bit register, coupled to a data clock signal and a sequence of data input signals transmitted from the display control chip;

A display grayscale buffer is coupled to the bit register and a latch enable signal transmitted from the display control chip, wherein the display grayscale buffer is based on the control of the latch enable signal to control the The sequence data input signal is buffered;

A display gray scale comparison unit, coupled to the display gray scale buffer and a gray scale clock signal transmitted from the display control chip, wherein, based on the control of the gray scale clock signal, the display gray scale comparison unit buffers in the display gray scale The sequence of data input signals in the display gray-scale buffer is compared with a gray-scale threshold, and then X basic PWM signals are generated;

A driving PWM signal generating module, coupled to the display gray scale comparison unit, and including a pull-up control signal generating unit, a pull-down control signal generating unit, and a driving PWM signal generating unit, wherein, according to the X basic PWM Signal, the pull-up control signal generation unit and the pull-down control signal generation unit each generate X pull-up control signals and X pull-down control signals, and the drive PWM signal generation unit is based on the X basic PWM signals, X The pull-up control signal and the X pull-down control signals correspondingly generate X driving PWM signals; and

A current source unit, coupled between the X row lines and the driving PWM signal generating module, for outputting X driving current signals to the X rows based on the control of the X driving PWM signals line.

In one embodiment, the display gray scale comparison unit includes X comparators, and the first comparator is used to input the sequence data into a Least Significant Bit (LSB) of the signal and the The gray-scale threshold is compared, and sequentially, the X-th comparator is used to compare a Most Significant Bit (MSB) of the sequence data input signal with the gray-scale threshold.

In an embodiment, each of the driving PWM signals includes a plurality of sub-PWM display areas, and each of the sub-PWM display areas has a sub-display period 2 ^N(i) , i=1, 2, 3,...,n , N(i) is a positive integer.

In an embodiment, each of the sub-display periods 2 ^N(i) includes four sub-time intervals, including: a pull-up time interval, a pull-down time interval, a data display time interval, and a pull-up waiting time interval.

In a possible embodiment, the ^{pull-up time interval of the first sub-display period 2 N(i)} is further defined as a line feed waiting time.

In a possible embodiment, the driving PWM signal generating module further includes: a configuration register, which is coupled between the driving PWM signal generating unit, the pull-up control signal generating unit, and the pull-down control signal generating unit. To configure each of the sub-display periods of each of the driving PWM signals.

In addition, the present invention also proposes an LED drive current modulation method, which includes the following steps:

Receiving a data clock signal and a sequence of data input signals transmitted by a display control chip;

Buffer the sequence data input signal in a display gray scale buffer according to a latch enable signal sent by the display control chip;

According to a grayscale clock signal transmitted by the display control chip, the sequence of data input signals buffered in the display grayscale buffer is compared with a grayscale threshold, and then X basic PWM signals are generated;

Generate X pull-up control signals and X pull-down control signals based on the X basic PWM signals, and further based on the X basic PWM signals, X pull-up control signals, and X pull-down control signals The signal correspondingly generates X driving PWM signals; and

X driving PWM signals are used to control a current source unit to output X driving current signals.

In an embodiment, each of the driving PWM signals includes a plurality of sub-PWM display areas, and each of the PWM display areas has a sub-display period 2 ^N(i) ; i=1, 2, 3,...,n, N(i) is a positive integer.

In an embodiment, each of the sub-display periods 2 ^N(i) includes four sub-time intervals, including: a pull-up time interval, a pull-down time interval, a data display time interval, and a pull-up waiting time interval.

In addition, the present invention also provides an LED display, which includes:

One LED display panel;

A row driver, coupled to the Y row lines of the LED display panel;

A display controller coupled to the row driver; and

A column drive module is coupled to the X column lines of the LED display panel and includes the LED display drive circuit as described above.

In order to enable your reviewer to further understand the structure, features, purpose, and advantages of the present invention, drawings and detailed descriptions of preferred specific embodiments are attached as follows.

FIG. 4 shows a structural diagram of an embodiment of an LED display including the LED display driving circuit of the present invention. As shown in FIG. 4, the LED display includes: an LED display panel 1, a row driver 2, an LED display driving circuit 3, and a display controller 4; wherein, the display controller 4 is usually a field programmable gate. Array (Field Programmable Gate Array, FPGA) chip, and is coupled to the LED display driving circuit 3 and the row driver 2. In addition, the LED display panel 1 includes Y×X LED elements 11, where X and Y are integers greater than 1, the anodes of the LED elements 11 in the Yth row are connected to the row line G _Y , and the X-th column The cathodes of the LED elements 11 are commonly connected to the column line S _X.

As shown in FIG. 4, the LED display driving circuit 3 of the present invention is coupled to the X column lines S _X of the LED display panel 1 and the display controller 4. In particular, based on a specially designed control method, the LED display drive circuit 3 of the present invention can be based on a data clock signal DCLK (please refer to FIG. 5) and a sequence of data input signal SDI (please refer to the figure) sent by the display controller 4 5) Pre-judge the high and low grayscale values, and generate corresponding driving current signals to the LED display panel 1 according to the comparison results of the grayscale values, so as to minimize the high grayscale display area caused by the low grayscale display area At the same time, the cross-board color difference phenomenon of the LED display panel 1 is reduced.

FIG. 5 shows a circuit diagram of an embodiment of the LED display driving circuit 3 of FIG. 4. As shown in FIG. 5, the LED display driving circuit 3 of the present invention mainly includes: a bit register 31, a display gray scale buffer 3S, a display gray scale comparison unit 30, a driving PWM signal generating module 33, and a current Source unit 34. In order to allow the LED display driving circuit 3 to adaptively generate X driving current signals to the X column lines S _{X of} the LED display panel 1, the present invention also specifically designs an LED driving current modulation method. FIG. 6 shows a flowchart of an embodiment of the LED driving current modulation method of the present invention.

As shown in FIG. 6, the LED driving current modulation method of the present invention includes the following steps: Step a: Receive a data clock signal DCLK and a serial data input signal SDI transmitted by a display controller 4; Step b: Control according to the display A latch enable signal LE transmitted by the device 4 buffers the sequence data input signal SDI in a display grayscale buffer 3S; step c: according to a grayscale clock signal GCLK transmitted by the display controller 4, Compare the sequence data input signal SDI buffered in the display gray scale buffer 3S with a gray scale threshold VGREF, and then generate X basic PWM signals; step d: generate X based on the X basic PWM signals Pull-up control signals and X pull-down control signals, and further generate X driving PWM signals correspondingly based on the X basic PWM signals, X pull-up control signals, and X pull-down control signals; and Step d: Utilize the X drive PWM signals to control a current source unit 34 to output X drive current signals.

Hereinafter, in conjunction with FIG. 4, FIG. 5, and FIG. 6, it will be described in detail how to enable the LED display driving circuit 3 of the present invention to adaptively generate X driving current signals to the X column lines S _{X of} the LED display panel 1. According to the design of the present invention, the bit register 31 is coupled to the display controller 4 to receive a data clock signal DCLK and a serial data input signal SDI. The display gray scale buffer 3S is coupled to the bit register 31 and the display controller 4, and is temporarily stored in the bit register 31 based on a control pair of a latch enable signal LE transmitted from the display controller 4 The sequence data input signal SDI is buffered. Further, the display gray scale comparison unit 30 is coupled to the display gray scale buffer 3S and the display controller 4, and based on the control of a gray scale clock signal GCLK transmitted from the display controller 4, buffers the display in the display The sequence data input signal SDI in the gray level buffer 3S is compared with a gray level threshold V _GREF , and then X basic PWM signals are generated.

Continue to refer to FIG. 4, FIG. 5, and FIG. 6, and also refer to FIG. 7, which shows a circuit block diagram of an embodiment of the driving PWM signal generating module 33 of the LED display driving circuit 3 of FIG. According to the design of the present invention, the driving PWM signal generating module 33 is coupled to the display gray scale comparison unit 30, and includes a pull-up control signal generating unit 331, a pull-down control signal generating unit 332, and a driving PWM signal generating unit 333 . In particular, according to the X basic PWM signals, the pull-up control signal generation unit 331 and the pull-down control signal generation unit 332 respectively generate X pull-up control signals and X pull-down control signals, and the drive PWM signal generation unit 333 further generates X driving PWM signals correspondingly based on the X basic PWM signals, the X pull-up control signals, and the X pull-down control signals. In addition, the current source unit 34 is coupled between the X column lines S _X and the driving PWM signal generating module 33 for outputting X driving current signals to X based on the control of the X driving PWM signals. The column lines S _X.

In addition, FIG. 5 shows that the LED display driving circuit 3 of the present invention further includes: an output current adjusting unit 35, a first buffer U1, a second buffer U2, a third buffer U3, and a fourth buffer U4 And a fifth buffer U5, wherein the output current adjusting unit 35 is coupled to the current source unit 34 and a current adjusting signal Iset transmitted from the display controller 4; the first buffer U1 is coupled to the gray scale Between the clock signal GCLK and the display gray scale comparison unit 30; the second buffer U2 is coupled between the enable control signal LE and the latch 32; the third buffer U3 is coupled to the data clock Between the signal DCLK and the bit register 31; the fourth buffer U4 is coupled between the serial data input signal SDI and the bit register 31; and the fifth buffer U5 is coupled to the bit register 31 Between the serial data output terminal SDO of the LED display driving circuit. Electronic engineers who are familiar with the design and production of LED drive display chips should know that the LED display panel 1 shown in Figure 5 has adopted a modular design, and the same LED display can contain more than two LED display panels 1. In this case, the LED display driving circuit 3 of the present invention can also be connected in series with more than two. When connected in series, the first LED display driving circuit 3 is coupled to the serial data input terminal SDI of the second LED display driving circuit 3 through its serial data output terminal SDO, and the second LED display driving circuit 3 also needs to be coupled The data clock signal DCLK.

Please refer to FIG. 8 at the same time, which shows a set of operating waveforms of the driving PWM signal generating module 33 in FIG. 7, where UP is the pull-up control signal generated by the pull-up control signal generating unit 331; DN[X] Is the pull-down control signal generated by the pull-down control signal generation unit 332; PWM[X] is the drive PWM signal generated by the drive PWM signal generation unit 333; and G[Y] is the row driver 2 transmitted to the Yth The row driving signal of the row line G _Y (please refer to FIG. 4). It can be found from FIG. 8 that each of the driving PWM signals includes a plurality of sub-PWM display areas, and each of the PWM display areas has a sub-display period 2 ^N(i) ; i=1, 2, 3,...,n, N(i) is a positive integer. For example, in one embodiment, the driving PWM signal includes 4 sub-PWM display areas A (Tc-Td), B (Tg-Th), C (Ti-Tj), and D (Tk-Tl); among them, The sub-display periods of the display area A, the display area B, and the display area C are 2 ^N(1) , 2 ^N(2) , and 2 ^{N(3), respectively} . In particular, FIG. 7 shows the PWM driving signal generation module 33 further includes a configuration register 334, which is coupled to the PWM driving signal generating unit 333 for each of the subset of the arrangement of the PWM signal driving the display period 2 ^{N (i)} . That is, the values of N(1), N(2), and N(3) can be set through the configuration register 334.

It can be further learned from FIG. 8 that each of the sub-display periods 2 ^N(i) includes four sub-time intervals, including: a pull-up time interval (ta-tb, te-tf,...), a pull-down time interval (tb- tc, tf-tg,...), data display time interval (tc-td, tg-th,...), and pull-up waiting time interval (td-te, th-th',...). Similarly, each time interval can be set by the configuration register 334. It is worth noting that the ^{pull-up time interval (ie, ta-tb) of the first sub-display period 2 N(i} ) is further defined as a line feed waiting time, which can also be regarded as a column waiting output time. The line feed waiting time referred to here means that the line drive signal jumps from line Y-1 to line Y. At the same time, for each sub-display period 2 ^N(i) , the data display time interval includes the time width of the actual data and the width of the PWM expansion.

By setting the configuration register 334, each of the display areas (sub-display periods) can be independently controlled. For example, after eliminating any two pull-up control signals and pull-down control signals in the 4 display areas (A, B, C, D), only two of the driving PWM signals PWM[X] will remain There are two display areas (sub-display periods), and the remaining two display areas (sub-display periods) will not be affected by the display data of the eliminated display areas. It is easy to infer that after eliminating the three pull-up control signals and pull-down control signals in the three display areas (A, B, C, D), only one display will be left in the driving PWM signal PWM[X] Area, that is, all display areas are combined into a complete display area; at this time, a complete data display time interval also includes the time width of the actual data and the width of the PWM expansion.

It is supplemented that, as shown in FIG. 5 and FIG. 7, the display gray scale comparison unit 30 includes X comparators 301. In particular, all the bits of the serial data input signal SDI are buffered in the display grayscale buffer 3S. Therefore, each of the comparators 301 can correspondingly fetch the corresponding ones from the display grayscale buffer 3S. To compare the grayscale values. For example, the first comparator 301 is used to compare a Least Significant Bit (LSB) of the sequence data input signal SDI with the gray threshold V _GREF , and sequentially, the first The X comparators 301 are used to compare a Most Significant Bit (MSB) of the sequence data input signal SDI with the gray threshold V _GREF . Therefore, the comparison results of the grayscale values of the X comparators 301 can be temporarily stored in the configuration register 334. In this way, the driving PWM signal generating unit 333 can configure the display data below the threshold value through the configuration register 334 to configure its starting display position, and can also configure the display data above the threshold value through the configuration register 334 to configure its starting display position.

In this way, the above system has completely and clearly explained the LED display driving circuit and LED driving current modulation method of the present invention, and the LED display having the LED display driving circuit or applying the LED driving current modulation method; and it can be known from the above The present invention has the following advantages:

The present invention improves an LED display driving circuit and its LED driving current modulation method, in particular, it judges high and low gray scale values according to a data clock signal and a sequence of data input signals, and generates a basic PWM signal according to the comparison result of the gray scale values, A pull-up control signal and a pull-down control signal, and then based on the basic PWM signal, the pull-up control signal, and the pull-down control signal to correspondingly generate a driving PWM signal, so that the driving PWM signal includes a plurality of sub-display periods 2 ^N(i) (Sub-PWM display area), so as to minimize the interference caused by the high grayscale display area to the low grayscale display area, and at the same time reduce the cross-board color difference phenomenon of the LED display panel.

It must be emphasized that the foregoing disclosures in this case are preferred embodiments, and any partial changes or modifications that are derived from the technical ideas of this case and are easily inferred by those who are familiar with the art will not deviate from the patent of this case. Right category.

In summary, regardless of the purpose, means and effect of this case, it is shown that it is very different from the conventional technology, and its first invention is suitable for practicality, and it does meet the patent requirements of the invention. I implore the examiner to check it out and grant the patent as soon as possible. Society is for the best prayer.

<The present invention> 1: LED display panel 2: Row drive 3: LED display drive circuit 4: display controller 11: LED components 31: bit register 3S: Display gray buffer 30: Display gray scale comparison unit 33: Drive PWM signal generation module 34: current source unit 35: Output current adjustment unit 301: Comparator U1: first buffer U2: second buffer U3: third buffer U4: Fourth buffer U5: Fifth buffer 331: Pull-up control signal generation unit 332: Pull-down control signal generation unit 333: drive PWM signal generating unit 334: configuration register Step a: Receive a data clock signal and a sequence of data input signals sent by a display controller Step b: buffer the sequence of data input signals in a display gray scale buffer according to a latch enable signal sent by the display controller Step c: According to a grayscale clock signal sent by the display controller, compare the sequence of data input signals buffered in the display grayscale buffer with a grayscale threshold, and then generate X basic PWM signals Step d: Generate X pull-up control signals and X pull-down control signals based on the X basic PWM signals, and further based on the X basic PWM signals, X pull-up control signals, and X pull-up control signals Pull down the control signal to generate X drive PWM signals Step e: Use X of the driving PWM signals to control a current source unit to output X driving current signals

＜Acquaintances＞ 1’: LED display panel 2’: Row drive 3’: Column drive module 4’: Display Controller 11’: Display panel 31’: Bit register 32’: Output latch 33’: Output current driver 34’: Current source unit 35’: Output current regulator

Figure 1 shows a structure diagram of a conventional LED display; FIG. 2 shows a circuit block diagram of the column driving module of FIG. 1; Fig. 3 shows a set of working waveform diagrams of the conventional LED display of Fig. 1; 4 shows a structural diagram of an embodiment of an LED display including an LED display driving circuit of the present invention; FIG. 5 shows a circuit diagram of an embodiment of the LED display driving circuit of FIG. 4; Figure 6 shows a flowchart of an embodiment of the LED drive current modulation method of the present invention; FIG. 7 shows a circuit block diagram of an embodiment of the driving PWM signal generating module of the LED display driving circuit of FIG. 5; and Figure 8 is a waveform diagram of a complex array signal.

3: LED display drive circuit

4: display controller

31: bit register

3S: Display gray buffer

30: Display gray scale comparison unit

33: Drive PWM signal generation module

34: current source unit

35: Output current adjustment unit

301: Comparator

U1: first buffer

U2: second buffer

U3: third buffer

U4: Fourth buffer

U5: Fifth buffer

Claims (10)

An LED display driving circuit is used to couple X column lines of an LED display panel and a display controller. X is an integer greater than 1, and includes: A bit register, coupled to a data clock signal and a sequence of data input signals transmitted from the display controller; A display grayscale buffer is coupled to the bit register and a latch enable signal sent from the display controller, and the display grayscale buffer is based on the control of the latch enable signal to the sequence data The input signal is buffered; A display gray scale comparison unit, coupled to the display gray scale buffer and a gray scale clock signal transmitted from the display controller, and the display gray scale comparison unit buffers the display in the display based on the control of the gray scale clock signal The sequence data input signal in the gray-scale buffer is compared with a gray-scale threshold, and then X basic PWM signals are generated; A driving PWM signal generation module, coupled to the display gray scale comparison unit, and including a pull-up control signal generation unit, a pull-down control signal generation unit, and a driving PWM signal generation unit, the pull-up control signal generation unit and the The pull-down control signal generation unit generates X pull-up control signals and X pull-down control signals respectively according to the X basic PWM signals, and the drive PWM signal generation unit is based on the X basic PWM signals and the X pull-down control signals. The pull-up control signal and the X pull-down control signals correspondingly generate X driving PWM signals; and A current source unit, coupled between the X said column lines and the drive PWM signal generating module, for outputting X drive current signals to the X said column lines based on the control of the X drive PWM signals . According to the LED display driving circuit described in item 1 of the scope of patent application, the display gray scale comparison unit includes X comparators, and the first comparator is used to input the sequence of data into a least effective signal The bit is compared with the gray threshold, and sequentially, the X-th comparator is used to compare a most significant bit of the sequence data input signal with the gray threshold. According to the LED display driving circuit described in item 1 of the scope of patent application, each of the driving PWM signals includes a plurality of sub-PWM display areas, and each of the sub-PWM display areas has a sub-display period 2 ^N(i) ; i=1, 2, 3,...,n, N(i) is a positive integer. For the LED display driving circuit described in item 3 of the scope of patent application, each of the sub-display periods 2 ^N(i) includes four sub-time intervals, including: a pull-up time interval, a pull-down time interval, a data display time interval, and Pull up the waiting time interval. According to the LED display driving circuit described in item 4 of the scope of patent application, the pull-up time interval of the first ^{sub-display period 2 N(i) is a line feed waiting time.} According to the LED display driving circuit described in item 4 of the scope of patent application, the driving PWM signal generating module further includes: a configuration register coupled to the driving PWM signal generating unit, the pull-up control signal generating unit, and Between the pull-down control signal generating units, each of the sub-display periods 2 ^{N(i) of} each of the driving PWM signals is configured. An LED drive current modulation method, which includes the following steps: Receiving a data clock signal and a sequence of data input signals sent by a display controller; Buffer the sequence of data input signals in a display gray scale buffer according to a latch enable signal sent by the display controller; According to a grayscale clock signal sent by the display controller, the sequence data input signal buffered in the display grayscale buffer is compared with a grayscale threshold, and then X basic PWM signals are generated, and X is greater than 1. Integer Generate X pull-up control signals and X pull-down control signals based on the X basic PWM signals, and further based on the X basic PWM signals, X pull-up control signals, and X pull-down control signals Correspondingly generate X driving PWM signals; and X driving PWM signals are used to control a current source unit to output X driving current signals. According to the LED driving current modulation method described in item 7 of the patent application, each group of the driving PWM signal includes a plurality of sub-PWM display areas, and each of the sub-PWM display areas has a sub-display period 2 ^{N(i )} ; i=1, 2, 3,...,n, N(i) is a positive integer. The LED drive current modulation method described in item 8 of the scope of patent application, wherein each of the sub-display periods 2 ^N(i) includes four sub-time intervals, including: pull-up time interval, pull-down time interval, and data display time Interval, and pull-up waiting time interval. An LED display includes: an LED display panel; a row driver coupled to Y row lines G _Y of the LED display panel, where Y is an integer greater than 1; a display controller coupled to the row driver; and a column driver module The group is coupled to the X column lines of the LED display panel, and it includes the LED display driving circuit described in any one of items 1 to 6 of the scope of the patent application.

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