TW202024901A - Flash memory device and controlling method thereof - Google Patents

Abstract

A flash memory device and a controlling method are provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module and a latency-aware module. The in-place update module is used for performing a program procedure or a garbage collection procedure via a bit erase operation or a page erase operation on the memory array. The out-of-place update module is used for performing the program procedure or the garbage collection procedure via a block erase operation or a migration operation on the memory array. The latency-aware module is used for determining a relationship between a first overhead of the in-place update module and a second overhead of the out-of-place update module.

Description

Flash memory device and its control method

This disclosure relates to a memory device and its control method, and more particularly to a flash memory device and its control method.

With the development of semiconductor technology, various types of memory are constantly being introduced. A flash memory device is an electronic (solid-state) non-volatile memory, which can be erased or written electronically. However, the flash memory device has the following limitations: Although the flash memory can read or write a page during random access, the flash memory can only erase one block. Usually all bits will be set to 1. At the beginning, any part of the free block can be written. However, once a bit is set to 0, the entire block must be erased to change 0 back to 1, which is the so-called block erase operation.

Please refer to Figure 1, which shows the garbage collection procedure of a traditional flash memory device. Due to the limitation of block erasing operation, an invalid page (or used page) in a block cannot be erased as a free page independently. Therefore, the valid pages of this block must be migrated, and then the whole block is erased to create free pages. Frequent migration and erasure can easily cause latency and endurance issues.

This disclosure relates to a flash memory and its control method. It proposes a new design of the flash translation layer (FTL), which includes a latency-aware program mechanism. , A latency-aware garbage collection mechanism, a cyclic endurance spreading mechanism, and a hot-data-aware fine-granularity mechanism, with Make full use of the new state of bits to modify the bit-alterable flash memory array (bit-alterable flash memory array) bit erase operation (bit erase operation) or page erase operation (page erase operation), resulting in delay and durability The problem can be effectively solved.

According to the first aspect of this disclosure, a flash memory device is provided. The flash memory device includes a memory array, an in-place update module, an out-of-place update module, and a latency-aware module ). The in-place update module is used to perform a program procedure or a memory recovery procedure on the memory array through a bit erase operation or a page erase operation (Garbage collection procedure). The external update module is used to perform a write process or a memory recovery process on the memory array through a block erase operation or a migration operation. The delay sensing module is used to determine the magnitude relationship between the first load of the in-situ update module and the second load of the external update module.

According to the second aspect of this disclosure, a method for controlling a flash memory device is proposed. The flash memory device includes a memory array, an in-place update module, an out-of-place update module, and a latency-aware module ). The control method includes the following steps. The delay sensing module is used to determine the magnitude relationship between the first load of the in-situ update module and the second load of the foreign update module.

In order to have a better understanding of the above and other aspects of the present disclosure, the following embodiments are specially cited, and the accompanying drawings are described in detail as follows:

Please refer to FIG. 2, which shows a flash memory device 1000 according to an embodiment. The flash memory device 1000 includes a file system (file system) 100, a flash translation layer (FTL) 200, a memory technology device (MTD) 300, and a memory array 400. The memory array 400 is a bit-alterable flash memory array, which can be a NAND memory, a NOR memory, a 3D memory, a phase change random access memory Body (Phase Change RAM, PCM) or a variable resistance memory (Resistive random-access memory, ReRAM).

Please refer to Figures 3A to 3B, which illustrate various operations of bit-modifiable flash memory arrays. In the bit-modifiable memory array, +FN hole injection and -FN electron injection are used for writing and erasing. As shown in FIG. 3A, some bits in the bit-modifiable memory array are written to form different voltage distributions. As shown in Figure 3B, when the block is erased, all bits are "1". Then, some bits can be written as "0". Then, some bits can be erased as "1". In other words, the bit-modifiable memory array can perform bit erase operations or page erase operations.

Please refer to Figure 4, which explains the garbage collection procedure through the page wipe operation. In the page erasing operation, an invalid page (or used page) of a block can be erased independently as an idle page. Therefore, the valid pages in the block do not need to be migrated, and only part of the block is erased to create free pages. Therefore, the migration operation can be omitted to reduce the load.

As mentioned above, the memory array 400 of the flash memory device 1000 in FIG. 2 is a bit-modifiable memory array. The program procedure and the garbage collection procedure can be completed by bit erase operation, page erase operation or block erase operation. In order to effectively execute the writing process and the memory recovery process, the flash memory conversion layer 200 provides a bit-alterable-aware management unit 210. As shown in Figure 2, the bit-modifiable perception management unit 210 includes a hot-data-aware module 211, a latency-aware module 212, and an in-situ update module. Group (in-place update module) 213, an out-of-place update module (out-of-place update module) 214, and a spreading module (spreading module) 215. Bit modifiable sensing management unit 210, thermal data sensing module 211, delay sensing module 212, in-place update module 213, foreign update module 214, and propagation module 215 are, for example, a circuit, a chip, and a circuit board , Software programs, or storage devices for storing program codes. These components will be described later.

Please refer to FIG. 5, which shows a flowchart of the "delay-aware writing mechanism" of the control method of the flash memory device 1000. In step S510, the delay sensing module 212 determines whether the first load of the in-situ update module 213 executing the writing process is less than the second load of the external updating module 214 executing the writing process. If the first load is less than the second load, go to step S520; if the first load is not less than the second load, go to step S530.

In step S520, the in-place update module 213 performs a write process on the memory array 400 through a bit erase operation or a page erase operation. For example, please refer to Fig. 6, which illustrates an example of a write process performed by a page erase operation. In this example, "LBA2" on page PN-1 needs to be replaced with "LBA2*". Before executing the writing procedure, the pages P0, P2, P3, P4, ... are all invalid pages, and the pages P1, PN-1, PN are all valid pages. After executing the writing process, the page PN-1 of the block BKA is erased, and "LBA2*" is written to the page PN-1 of the block BKA.

In step S530, the foreign update module 214 performs a write process on the memory array 400 through a block erase operation migration operation. Please refer to Figure 7, which illustrates an example of the write process performed by the migration operation. In this example, "LBA2" on page PN-1 needs to be replaced with "LBA2*". Before executing the writing process, the pages P0, P2, P3, P4, ... are all invalid pages, the pages P1, PN-1 are all valid pages, and the page PN is an idle page. After executing the writing process, the page PN-1 of the block BKA is read, and "LBA2*" is written into the page PN of the block BKA. Page PN-1 becomes an invalid page, and page N becomes a valid page.

Please refer to FIG. 8, which shows a flow chart of the "delay-aware memory recovery mechanism" of the control method of the flash memory device 1000. In step S810, the delay sensing module 212 determines whether the first load of the in-place update module 213 performing the memory recycling process is less than the second load of the external update module 214 performing the memory recycling process. If the first load is less than the second load, the process goes to step S820; if the first load is not less than the second load, the process goes to step S830.

In step S820, the in-place update module 213 performs a memory recovery process on the memory array 400 through a bit erase operation or a page erase operation. For example, please refer to Figure 9, which illustrates an example of a memory recovery process performed by a page erase operation. In this example, the space of invalid pages needs to be released. Before the memory recovery procedure is executed, the pages P0, P2, P3, P4, ..., PN are all invalid pages, and the pages P1, PN-1 are all valid pages. After the memory reclamation process is executed, the pages P0, P2, P3, P4, ..., PN of the block BKA are erased as free pages, and the pages P1, PN-1 of the block BKA remain unchanged.

In step S830, the foreign update module 214 performs a block erase operation or a migration operation to perform a memory recovery process on the memory array 400. Please refer to Figure 10, which illustrates an example of the memory recovery process performed by the migration operation and the block erase operation. In this example, the space of invalid pages needs to be released. Before the memory reclamation process is executed, pages P0, P2, P3, P4, ..., PN are all invalid pages, and pages P1, PN-1 are all valid pages. After the memory reclamation process is executed, the pages P1 and PN-1 of the block BKA are migrated to another block BKB, and the block BKA is completely erased.

Please refer to Figure 11 and Figure 12. FIG. 11 is a flowchart of the "cyclic persistence propagation mechanism" of the control method of the flash memory device 1000. Figure 12 illustrates the steps of Figure 11. In step S111, the propagation module 215 determines whether the access count is greater than a threshold. If the access count is greater than the critical value, the process proceeds to step S112; if the access count is not greater than the critical value, the process returns to step S111.

In step S112, the propagation module 215 resets the reference indication BP. For example, as shown in Figure 12, page P0 includes cache lines CL0 to CLN. The benchmark indicates that the BP is moved from the first entity column to the second entity column.

In step S113, the propagation module 215 reallocates the data according to the reference instruction BP. For example, as shown in FIG. 12, the reference indicates BP, and the data of the cache line CL0 is moved from the first physical row to the second physical row.

As shown in Figure 12, the benchmark indicates that the BP system moves periodically so that the persistent effect can be propagated between the cache lines CL0 ~ CLN.

表一Please refer to Figure 13 and Table 1. FIG. 13 is a flowchart of the "hot-data-aware fine-granularity mechanism" of the control method of the flash memory device 1000. Table 1 is a hash table, and its data is searched by a hash function (such as mod 4). In step S131, the thermal data sensing module 211 determines whether a page has been accessed recently. If the page has been accessed recently, the process proceeds to step S132; if the page has not been accessed recently, the process proceeds to step S133.

Table I

In step S132, the thermal data sensing module 211 sets the hash bit of this page to 1. In step S132, the thermal data sensing module 211 sets the hash bit of this page to 0.

According to the above various embodiments, the newly designed flash memory conversion layer contains "delay-aware write mechanism", "delay-aware memory recovery mechanism", "circular persistence propagation mechanism" and "thermal data sensing fineness mechanism". The bit erasing operation or page erasing operation of the flash memory array can be modified by making full use of the new state of the bit, so that the problem of delay and durability can be effectively solved.

To sum up, although the present disclosure has been disclosed as above by the embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field to which this disclosure belongs can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be subject to the scope of the attached patent application.

1000: Flash memory device 100: File system 200: Flash memory conversion layer 210: Bit modifiable perception management unit 211: Thermal data perception module 212: Delayed perception module 213: In-place update module 214: Foreign Update Module 215: Propagation Module 300: Memory Technology Device 400: Memory Array BKA, BKB: Block BP: Benchmark Indicator CL0, CL1, CL2, CL3, CL4, CL5, CLN-1, CLN: Cache Lines P0, P1, P2, P3, P4, PN-1, PN: pages S510, S520, S530, S810, S820, S830, S111, S112, S113, S131, S132, S133: steps

Figure 1 shows the memory recovery process of a conventional flash memory device. FIG. 2 shows a flash memory device according to an embodiment. Figures 3A to 3B illustrate various operations of bit-modifiable flash memory arrays. Figure 4 illustrates the memory recovery process through the page erase operation. Figure 5 shows a flow chart of the "delay-aware write mechanism" of the control method of the flash memory device. Figure 6 illustrates an example of a write process performed by a page erase operation. Figure 7 illustrates an example of a write process performed by a migration operation. Figure 8 shows a flow chart of the "delay-aware memory recovery mechanism" of the control method of the flash memory device. Figure 9 illustrates an example of the memory recovery process performed by the page erase operation. Figure 10 illustrates an example of the memory recovery process performed by the migration operation and the block erase operation. Figure 11 shows the flow chart of the "cyclic persistence propagation mechanism" of the control method of the flash memory device. Figure 12 illustrates the steps of Figure 11. Figure 13 shows the flow chart of the "thermal data sensing fineness mechanism" of the flash memory device control method.

1000: Flash memory device

100: file system

200: Flash memory conversion layer

210: bit modifiable perception management unit

211: Thermal data sensing module

212: Delay perception module

213: In-situ update module

214: Field Update Module

215: Communication Module

300: Memory Technology Device

400: Memory array

Claims (20)

A flash memory device includes: a memory array; an in-situ update module for performing a write process or a memory on the memory array through a bit erase operation or a page erase operation Volume recovery process; a foreign update module for executing the write process or the memory recovery process on the memory array through a block erase operation or a migration operation; and a delay sensing module for Determine the magnitude relationship between a first load of the in-situ update module and a second load of the external update module. For example, the flash memory device described in item 1 of the scope of patent application, wherein if the first load of the in-place update module is less than the second load of the foreign update module, the in-place update module executes the Write procedure or this memory recovery procedure. For the flash memory device described in item 2 of the scope of patent application, in the process of the in-place update module executing the writing process, one page of a block is erased, and data is written to the page. For example, the flash memory device described in item 2 of the scope of patent application, in which at least one invalid page of a block is erased as a free page when the in-place update module executes the memory recovery process, And at least one valid page of the block remains unchanged. Such as the flash memory device described in item 1 of the scope of patent application, wherein if the first load of the in-place update module is not less than the second load of the foreign update module, the foreign update module executes the Write procedure or this memory recovery procedure. For the flash memory device described in item 5 of the scope of patent application, in the process of executing the writing process by the foreign update module, one page of a block is read and data is written into another page. As for the flash memory device described in item 6 of the scope of patent application, in the process of executing the memory recovery procedure by the foreign update module, at least one valid page of one block is transferred to another block, and All of the block is erased. For example, the flash memory device described in item 1 of the scope of patent application further includes: a propagation module for resetting a reference indicator when the access count is greater than a threshold value and redistributing data according to the reference indicator . The flash memory device described in item 8 of the scope of patent application further includes: a thermal data sensing module for setting a hash bit of a page to 1 when a page has been accessed recently. For the flash memory device described in item 9 of the scope of patent application, the in-situ update module, the foreign update module, the delay sensing module, the propagation module, and the thermal data sensing module are arranged in A flash memory conversion layer. A control method for a flash memory device, wherein the flash memory device includes a memory array, an in-place update module, a foreign update module, and a delay sensing module, the control method includes: using the delay The sensing module determines the magnitude relationship between a first load of the in-situ update module and a second load of the foreign update module. For example, the control method described in item 11 of the scope of patent application further includes: if the first load of the in-place update module is less than the second load, the in-place update module performs a bit erasing operation or a The page erasing operation executes a write process or a memory recovery process on the memory array. According to the control method described in item 12 of the scope of patent application, in the step in which the in-situ update module executes the writing procedure, one page of a block is erased, and data is written to the page again. The control method described in claim 12, wherein in the step of the in-place update module executing the memory recovery process, at least one invalid page of a block is erased as a free page, and the area At least one valid page of the block remains unchanged. For example, the control method described in item 11 of the scope of patent application further includes: if the first load of the in-place update module is not less than the second load, the foreign update module performs a block erase operation or a In the migration operation, the write process or the memory recovery process is executed on the memory array. According to the control method described in claim 15, wherein in the step of executing the writing procedure by the foreign update module, one page of a block is read, and data is written to another page. For example, in the control method described in item 15 of the scope of patent application, in the step of executing the memory recovery procedure by the foreign update module, at least one valid page of one block is transferred to another block, and the All were erased. For example, the control method described in item 11 of the scope of patent application further includes: judging by a propagation module whether an access count is greater than a threshold; if the access count is greater than the threshold, resetting by the propagation module A benchmark instruction; and redistribute data based on the benchmark instruction. For example, the control method described in item 18 of the patent application further includes: using a thermal data sensing module to determine whether a page has been accessed recently; and when the page has been accessed recently, using the thermal data sensing module Set one of the hash bits of this page to 1. Such as the control method described in item 19 of the scope of patent application, wherein the in-place update module, the foreign update module, the delay sensing module, the propagation module and the thermal data sensing module are set in a flash In the memory conversion layer.

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