TW202002192A - 晶片封裝件 - Google Patents

晶片封裝件 Download PDF

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TW202002192A
TW202002192A TW108113518A TW108113518A TW202002192A TW 202002192 A TW202002192 A TW 202002192A TW 108113518 A TW108113518 A TW 108113518A TW 108113518 A TW108113518 A TW 108113518A TW 202002192 A TW202002192 A TW 202002192A
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Taiwan
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layer
integrated circuit
conductive
singulated
thermal paste
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TW108113518A
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English (en)
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TWI744628B (zh
Inventor
陳冠宇
蘇安治
葉德強
黃立賢
葉名世
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台灣積體電路製造股份有限公司
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Publication of TWI744628B publication Critical patent/TWI744628B/zh

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Abstract

一種晶片封裝件，包括積體電路組件、導熱層、絕緣包封體及重佈線路結構。所述積體電路組件包括位於所述積體電路組件的後表面處的非晶半導體部分。所述導熱層覆蓋所述積體電路組件的所述非晶半導體部分，其中所述導熱層的導熱率大於或實質上等於10 W/mK。所述絕緣包封體在橫向上對所述積體電路組件及所述導熱層進行包封。所述重佈線路結構設置在所述絕緣包封體及所述積體電路組件上，其中所述重佈線路結構電連接到所述積體電路組件。

Description

晶片封裝件
本發明的實施例是有關於一種晶片封裝件。
由於各種電子組件（即，電晶體、二極體、電阻器、電容器等）的積體密度的持續提高，半導體行業已經歷快速增長。在很大程度上，積體密度的此種提高來自於最小特徵尺寸（minimum feature size）的不斷減小，此使得更多較小的組件能夠整合到給定面積中。與先前的封裝件相比，這些較小的電子組件也需要利用較小面積的較小的封裝件。半導體組件的一些較小類型的封裝件包括四面扁平封裝件（quad flat package，QFP）、引腳柵陣列（pin grid array，PGA）封裝件、球柵陣列（ball grid array，BGA）封裝件等等。
當前，積體扇出型封裝件因其緊密而正變得日漸流行。從積體扇出型封裝件的積體電路組件產生的熱量因晶粒貼合膜的低導熱率（例如，k ＜ 1 W/mK）而無法有效地分散。
本發明實施例的一種製作晶片封裝件的方法，所述方法包括：通過第一熱膏將積體電路組件貼合在載體上，其中所述第一熱膏的導熱率介於約10 W/mK到約250 W/mK的範圍內；形成絕緣包封體，以對貼合在所述載體上的所述積體電路組件進行包封；以及在所述絕緣包封體及所述積體電路組件上形成重佈線路結構，其中所述重佈線路結構電連接到所述積體電路組件。
本發明實施例的一種製作晶片封裝件的方法，所述方法包括：提供積體電路組件，所述積體電路組件上形成有金屬層；通過晶粒貼合膜將所述積體電路組件貼合在載體上，以使所述金屬層位於所述積體電路組件與所述晶粒貼合膜之間，其中所述金屬層的導熱率大於所述晶粒貼合膜的導熱率；形成絕緣包封體，以對貼合在所述載體上的所述積體電路組件進行包封；以及在所述絕緣包封體及所述積體電路組件上形成重佈線路結構，其中所述重佈線路結構電連接到所述積體電路組件。
本發明實施例的一種晶片封裝件，包括積體電路組件、導熱層、絕緣包封體以及重佈線路結構。積體電路組件包括位於所述積體電路組件的後表面處的非晶半導體部分。導熱層覆蓋所述積體電路組件的所述非晶半導體部分，其中所述導熱層的導熱率介於約10 W/mK到約250 W/mK的範圍內。絕緣包封體對所述積體電路組件及所述導熱層進行包封。重佈線路結構設置在所述絕緣包封體及所述積體電路組件上，其中所述重佈線路結構電連接到所述積體電路組件。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本公開。當然，這些僅為實例而非旨在進行限制。舉例來說，在以下說明中，在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外，本公開在各種實例中可重複使用參考編號和/或字母。此種重複使用是為了簡明及清晰起見，且自身並不表示所論述的各個實施例和/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在…之下（beneath）”、“在…下方（below）”、“下部的（lower）”、“在…上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外還囊括元件在使用或操作中的不同定向。裝置可具有其他定向（旋轉90度或處於其他定向），且本文中所用的空間相對性描述語可同樣相應地進行解釋。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以幫助對三維（three-dimensional，3D）封裝或三維積體電路（three-dimensional integrated circuit，3DIC）元件進行驗證測試。所述測試結構可包括例如在重佈線層中或在基底上形成的測試墊，以使得能夠對三維封裝或三維積體電路進行測試、對探針和/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，本文中所公開的結構及方法可結合包括對已知良好晶粒（known good die）進行中間驗證的測試方法來使用，以提高良率並降低成本。
圖1到圖15示出根據本公開一些實施例的用於製作積體扇出型封裝件的製程流程。
參照圖1，提供晶圓100，晶圓100包括排列成陣列的多個半導體晶粒或積體電路組件200。在對晶圓100執行晶圓切割製程（wafer dicing process）之前，晶圓100的各積體電路組件200是彼此連接的。在一些實施例中，晶圓100可包括半導體基底110、形成在半導體基底110上的多個導電墊120及鈍化層130。鈍化層130形成在半導體基底110之上且具有多個接觸開口132，以使導電墊120被鈍化層130的接觸開口132局部地露出。舉例來說，半導體基底110可為矽基底，所述矽基底包括形成在所述矽基底中的主動組件（例如，電晶體等）及被動組件（例如，電阻器、電容器、電感器等）；導電墊120可為鋁墊、銅墊或其他合適的金屬墊；且鈍化層130可為氧化矽層、氮化矽層、氮氧化矽層或由其他合適的介電材料形成的介電層。
如圖1所示，在一些實施例中，晶圓100還可包括形成在鈍化層130上的後鈍化層（post-passivation layer）140。後鈍化層140覆蓋鈍化層130且具有多個接觸開口142。被鈍化層130的接觸開口132露出的導電墊120會被後鈍化層140的接觸開口142局部地露出。舉例來說，後鈍化層140可為聚醯亞胺（polyimide，PI）層、聚苯並噁唑（polybenzoxazole，PBO）層或由其他合適的聚合物形成的介電層。
參照圖2，在導電墊120上形成多個導電柱150。在一些實施例中，在導電墊120上電鍍導電柱150。以下詳細闡述導電柱150的電鍍製程。首先，可將晶種層濺鍍到後鈍化層140上及被接觸開口142露出的導電墊120上。接著，可通過微影（photolithography）在晶種層之上形成圖案化光阻層（未示出），其中圖案化光阻層露出晶種層的與導電墊120對應的部分。可以電鍍槽（plating bath）的方式，將晶圓100浸入到電鍍溶液中，所述晶圓100包括形成在其上的圖案化光阻層，以使導電柱150電鍍在晶種層的與導電墊120對應的部分上。在形成電鍍導電柱150之後，剝除所述圖案化光阻層。之後，通過利用導電柱150作為硬罩幕，可例如通過刻蝕（etching）移除晶種層的未被導電柱150覆蓋的部分直到露出後鈍化層140為止。在一些實施例中，電鍍導電柱150可為電鍍銅柱。
參照圖3，在形成導電柱150之後，在後鈍化層140上形成保護層160以覆蓋導電柱150。在一些實施例中，保護層160可為具有足以包封及保護導電柱150的厚度的聚合物層。舉例來說，保護層160可為聚苯並噁唑（PBO）層、聚醯亞胺（PI）層或其他合適的聚合物。在一些替代實施例中，保護層160可由無機材料製成。
參照圖3及圖4，在形成保護層160之後，對晶圓100的後表面執行背側研磨（back-side grinding）製程。在背側研磨製程期間，通過研磨輪來對半導體基底110進行研磨，以使得薄化晶圓100'形成，薄化晶圓100'包括薄化半導體基底110'、形成在薄化半導體基底110'上的導電墊120、鈍化層130、後鈍化層140、導電柱150及保護層160。在執行背側研磨製程之後，如圖4所示，在薄化半導體基底110'的後表面處形成由背側研磨製程形成的非晶半導體部分110S（例如，非晶矽層）。在一些實施例中，非晶半導體部分110S的厚度可介於約10納米到約50納米的範圍內。另外，用於研磨半導體基底110的研磨輪的砂粒大小可介於約3微米到約15微米的範圍內。
參照圖5，在執行背側研磨製程之後，在切割膠帶DT上安裝薄化晶圓100'，以使薄化半導體基底110'的後表面與切割膠帶DT黏在一起。在一些實施例中，切割膠帶DT可支撐安裝在切割膠帶DT上的薄化晶圓100'且臨時與薄化晶圓100'的後表面黏在一起。
參照圖5及圖6，在將薄化晶圓100'安裝在切割膠帶DT上之後，對薄化晶圓100'執行晶圓切割製程，以使薄化晶圓100'中的各積體電路組件200彼此單體化。在單體化製程之後，形成與切割膠帶DT黏在一起的多個經單體化的積體電路組件200。如圖6所示，經單體化的積體電路組件200中的每一者包括半導體基底110a、形成在半導體基底110a上的導電墊120、鈍化層130a、後鈍化層140a、導電柱150及保護層160a。半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的材料及特性與半導體基底110、鈍化層130、後鈍化層140及保護層160的材料及特性相同。因此，省略了對經單體化的積體電路組件200中的半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的詳細說明。
在所述背側研磨製程及所述晶圓切割製程期間，保護層160可充分地保護積體電路組件200的導電柱150。另外，可保護經單體化的積體電路組件200的導電柱150不受隨後執行的製程（例如，經單體化的積體電路組件200的拾取及放置（picking-up and placing）製程、模塑（molding）製程等）的損壞。
參照圖6及圖7，提供上面形成有剝離層DB的載體C。在一些實施例中，載體C是玻璃基底，且剝離層DB是形成在玻璃基底上的光熱轉換（light-to-heat conversion，LTHC）釋放層。在一些替代實施例中，可在剝離層DB上形成介電層（未示出），以使剝離層DB位於載體C與介電層之間。舉例來說，介電層是形成在剝離層DB上的聚苯並噁唑（PBO）層。
在提供上面形成有剝離層DB的載體C之後，在剝離層DB上形成多個導電穿孔TV。在一些實施例中，所述多個導電穿孔TV可通過晶種層的濺鍍、光阻塗布、微影、穿孔的電鍍、光阻剝除及晶種層的圖案化來形成。舉例來說，導電穿孔TV包括銅支柱（copper post）或其他合適的金屬支柱。
如圖6及圖7所示，在一些實施例中，從切割膠帶DT拾取經單體化的積體電路組件200中的一者並將其放置在剝離層DB上，經單體化的積體電路組件200包括半導體基底110a、導電墊120、鈍化層130a、後鈍化層140a、導電柱150及保護層160a。在一些替代實施例中，從切割膠帶DT拾取多於一個經單體化的積體電路組件200並將其放置在剝離層DB上，其中放置在剝離層DB上的經單體化的積體電路組件200可排列成陣列。當放置在剝離層DB上的經單體化的積體電路組件200排列成陣列時，可將導電穿孔TV分類成各個群組且經單體化的積體電路組件200的數目對應於導電穿孔TV的群組的數目。
通過第一熱膏TP1將經單體化的積體電路組件200貼合在或黏在剝離層DB上，其中第一熱膏TP1的導熱率（k）大於或實質上等於10 W/mK。在一些實施例中，可通過分配（dispensing）或其他合適的製程在剝離層DB上形成第一熱膏TP1。舉例來說，第一熱膏TP1的導熱率（k）可介於約10 W/mK到約250 W/mK的範圍內。另外，第一熱膏TP1的材料可為含有金屬粉末的聚合物膏體。
如圖7所示，舉例來說，保護層160a的頂表面高於導電穿孔TV的頂表面，同時保護層160a的頂表面高於導電柱150的頂表面。然而，本公開並非僅限於此。在一些替代實施例中，保護層160a的頂表面可與導電穿孔TV的頂表面實質上對齊，且保護層160a的頂表面高於導電柱150的頂表面。
參照圖8，在剝離層DB上形成絕緣材料210以覆蓋經單體化的積體電路組件200及導電穿孔TV。在一些實施例中，絕緣材料210是通過模塑製程形成的模塑化合物。舉例來說，經單體化的積體電路組件200的保護層160a的頂表面被絕緣材料210覆蓋。換句話說，經單體化的積體電路組件200的保護層160a的頂表面未被露出而是被絕緣材料210保護住。在一些實施例中，絕緣材料210包含環氧樹脂或其他合適的介電材料。
參照圖8及圖9，對絕緣材料210進行研磨直到露出導電柱150的頂表面、導電穿孔TV的頂表面及保護層160a的頂表面為止。在一些實施例中，通過機械研磨製程和/或化學機械拋光（chemical mechanical polishing，CMP）製程來對絕緣材料210進行研磨。在對絕緣材料210進行研磨之後，形成絕緣包封體210'。在絕緣材料210的研磨製程期間，對保護層160a的一些部分進行研磨以形成保護層160a'。在一些實施例中，在絕緣材料210及保護層160a的研磨製程期間，也輕微地對導電穿孔TV的一些部分及導電柱150的一些部分進行研磨。
如圖9所示，絕緣包封體210'在橫向上包封經單體化的積體電路組件200的側壁，且絕緣包封體210'被導電穿孔TV穿透。換句話說，經單體化的積體電路組件200及導電穿孔TV嵌入在絕緣包封體210'中。應注意，導電穿孔TV的頂表面、絕緣包封體210'的頂表面、導電柱150的頂表面及保護層160a'的頂表面實質上處於同一水平高度。
參照圖10，在形成絕緣包封體210'及保護層160a'之後，在導電穿孔TV的頂表面上、絕緣包封體210'的頂表面上、導電柱150的頂表面上及保護層160a'的頂表面上形成重佈線路結構RDL。將重佈線路結構RDL製作成與位於下方的一個或多個連接件電連接。此處，前述連接件可為經單體化的積體電路組件200的導電柱150和/或嵌入在絕緣包封體210'中的導電穿孔TV。重佈線路結構RDL可包括交替地堆疊的多條重佈線接線與多個圖案化介電層，如圖10所示。舉例來說，重佈線接線可為銅接線且圖案化介電層的材料可包括聚醯亞胺（PI）、聚苯並噁唑（PBO）或其他合適的介電聚合物。另外，導電穿孔TV經由重佈線路結構RDL電連接到經單體化的積體電路組件200。
參照圖11，在形成重佈線路結構RDL之後，形成多個導電特徵B，所述多個導電特徵B電連接到重佈線路結構RDL。導電特徵B設置在重佈線路結構RDL上且排列成陣列。在一些實施例中，導電特徵B可為排列成陣列的導電球（例如，焊料球）。如圖11所示，在由載體C承載的剝離層DB上製作封裝結構P1，封裝結構P1包括第一熱膏TP1、經單體化的積體電路組件200、導電穿孔TV、絕緣包封體210'、重佈線路結構RDL及導電特徵B。
參照圖12，將剝離層DB及載體C從封裝結構P1剝離，以使導電穿孔TV的底表面、絕緣包封體210'的底表面及第一熱膏TP1的表面從載體C剝離並被露出。絕緣包封體210'的底表面與第一熱膏TP1的被露出的表面實質上處於同一水平高度。在一些實施例中，可向剝離層DB施加外部能量（例如紫外雷射、可見光或熱量），以使封裝結構P1與由載體C承載的剝離層DB可分離。
參照圖13，在執行剝離製程之後，可將封裝結構P1翻轉（上下倒置）並安裝到鋸切膠帶ST上，以使封裝結構P1的導電特徵B與鋸切膠帶ST黏在一起。在一些實施例中，鋸切膠帶ST可支撐安裝在鋸切膠帶ST上的上述封裝結構P1且臨時與封裝結構P1的導電特徵B黏在一起。由於第一熱膏TP1的導熱率（k）高（即，大於或實質上等於10 W/mK），因此第一熱膏TP1可有效地傳導及分散從經單體化的積體電路組件200產生的熱量。因此，可不需要移除第一熱膏TP1來增強封裝結構P1的散熱性能。
參照圖14，可形成第二熱膏TP2來覆蓋第一熱膏TP1的被露出的表面，其中第二熱膏TP2的導熱率（k）大於或實質上等於10 W/mK。舉例來說，第二熱膏TP2的導熱率（k）可介於約10 W/mK到約250 W/mK的範圍內。在一些實施例中，第一熱膏TP1的導熱率（k）可實質上等於第二熱膏TP2的導熱率（k）。在一些替代實施例中，第一熱膏TP1的導熱率（k）可大於或小於第二熱膏TP2的導熱率（k）。由於第一熱膏TP1及第二熱膏TP2二者的導熱率（k）高（即，大於或實質上等於10 W/mK），因此第一熱膏TP1及第二熱膏TP2可有效地傳導及分散從經單體化的積體電路組件200產生的熱量。
如圖14所示，第一熱膏TP1嵌入在絕緣包封體210'中且第一熱膏TP1接觸薄化半導體基底110'的非晶半導體部分110S。在一些實施例中，第二熱膏TP2可比第一熱膏TP1厚。在一些替代實施例中，第二熱膏TP2可比第一熱膏TP1薄。在一些其他實施例中，第一熱膏TP1與第二熱膏TP2的厚度可實質上相同。舉例來說，第一熱膏TP1的厚度可介於約1微米到約100微米的範圍內，而第二熱膏TP2的厚度可介於約1微米到約100微米的範圍內。另外，第二熱膏TP2可不僅覆蓋第一熱膏TP1的表面，而且還可局部地覆蓋絕緣包封體210'的表面。然而，第二熱膏TP2的分佈並非僅限於此。
當第一熱膏TP1及第二熱膏TP2中的至少一者含有金屬粒子（例如，銅粒子）時，薄化半導體基底110'的非晶半導體部分110S可捕獲第一熱膏TP1和/或第二熱膏TP2中含有的金屬粒子。換句話說，當第一熱膏TP1及第二熱膏TP2中的至少一者含有金屬粒子時，薄化半導體基底110'的非晶半導體部分110S可用作金屬粒子的擴散障壁。因此，封裝結構P1可容易地通過高溫工作壽命（high temperature operating life，HTOL）測試。
在一些替代實施例中，可省略第二熱膏TP2的製作，如圖31所示。
如圖14所示，第一熱膏TP1與第二熱膏TP2的組合可被視為覆蓋經單體化的積體電路組件200的非晶半導體部分110S的導熱層。在一些替代實施例中，當省略第二熱膏TP2的製作時，導熱層只包括第一熱膏TP1。
參照圖15，提供半導體元件P2並將半導體元件P2放置在封裝結構P1上以將半導體元件P2電連接到導電穿孔TV。半導體元件P2經由導電穿孔TV及重佈線路結構RDL電連接到積體電路組件200。在一些實施例中，半導體元件P2可經由多個導電凸塊BP電連接到封裝結構P1的導電穿孔TV。舉例來說，導電凸塊BP可為微凸塊、受控塌陷晶粒連接（controlled collapse chip connection，C4）凸塊等。
在一些實施例中，半導體元件P2可為其底表面上包括導電凸塊BP的記憶體元件（例如，DRAM）。舉例來說，半導體元件P2是球柵陣列（BGA）型封裝件。在半導體元件P2中，至少一個記憶體晶片可安裝在BGA電路板上，經由結合線電連接到BGA板且被模塑化合物包封。在將半導體元件P2安裝到封裝結構P1上之前，可通過例如絲網印刷製程（stencil printing process）向封裝結構P1的導電穿孔TV上施加焊料材料，且接著將包括導電凸塊BP的半導體元件P2放置在導電穿孔TV上。之後，執行回焊製程以在半導體元件P2與封裝結構P1的導電穿孔TV之間形成焊料接頭。
在執行上述回焊製程之後，在封裝結構P1與半導體元件P2之間形成底部填充膠UF以包封第二熱膏TP2及導電凸塊BP。在一些實施例中，底部填充膠UF的材料可包括含有填料的環氧樹脂且底部填充膠UF的導熱率可小於約1 W/mK。底部填充膠UF在橫向上包封導電凸塊BP且用作應力緩衝器，以最小化因封裝結構P1與半導體元件P2之間的熱膨脹係數（coefficient of thermal expansion，CTE）不匹配所導致的導電凸塊BP的疲勞（fatigue）。
在形成底部填充膠UF之後，對封裝結構P1執行鋸切製程以形成多個經單體化的疊層封裝（package-on-package，PoP）結構。在執行封裝結構P1的鋸切製程之後，經單體化的疊層封裝（PoP）結構與鋸切膠帶ST黏在一起。另外，底部填充膠UF可確保包括封裝結構P1及半導體元件P2的疊層封裝（PoP）結構的可靠性。
圖16到圖30示出根據本公開一些替代實施例的用於製作積體扇出型封裝件的製程流程。
參照圖16，提供晶圓100，晶圓100包括排列成陣列的多個半導體晶粒或積體電路組件200。在對晶圓100執行晶圓切割製程之前，晶圓100的各積體電路組件200是彼此連接的。在一些實施例中，晶圓100可包括半導體基底110、形成在半導體基底110上的多個導電墊120及鈍化層130。鈍化層130形成在半導體基底110之上且具有多個接觸開口132，以使導電墊120被鈍化層130的接觸開口132局部地露出。舉例來說，半導體基底110可為矽基底，所述矽基底包括形成在所述矽基底中的主動組件（例如，電晶體等）及被動組件（例如，電阻器、電容器、電感器等）；導電墊120可為鋁墊、銅墊或其他合適的金屬墊；且鈍化層130可為氧化矽層、氮化矽層、氮氧化矽層或由其他合適的介電材料形成的介電層。
如圖16所示，在一些實施例中，晶圓100還可包括形成在鈍化層130上的後鈍化層140。後鈍化層140覆蓋鈍化層130且具有多個接觸開口142。被鈍化層130的接觸開口132露出的導電墊120會被後鈍化層140的接觸開口142局部地露出。舉例來說，後鈍化層140可為聚醯亞胺（PI）層、聚苯並噁唑（PBO）層或由其他合適的聚合物形成的介電層。
參照圖17，在導電墊120上形成多個導電柱150。在一些實施例中，在導電墊120上電鍍導電柱150。以下詳細闡述導電柱150的電鍍製程。首先，可將晶種層濺鍍到後鈍化層140及被接觸開口142露出的導電墊120上。接著，可通過微影在晶種層之上形成圖案化光阻層（未示出），其中圖案化光阻層露出晶種層的與導電墊120對應的部分。可以電鍍槽的方式將晶圓100浸入到電鍍溶液中，所述晶圓100包括形成在其上的的圖案化光阻層，以使導電柱150電鍍在晶種層的與導電墊120對應的部分上。在形成電鍍導電柱150之後，剝除所述圖案化光阻層。之後，通過利用導電柱150作為硬罩幕，可例如通過刻蝕移除晶種層的未被導電柱150覆蓋的部分直到露出後鈍化層140為止。在一些實施例中，電鍍導電柱150可為電鍍銅柱。
參照圖18，在形成導電柱150之後，在後鈍化層140上形成保護層160以覆蓋導電柱150。在一些實施例中，保護層160可為具有足以包封及保護導電柱150的厚度的聚合物層。舉例來說，保護層160可為聚苯並噁唑（PBO）層、聚醯亞胺（PI）層或其他合適的聚合物。在一些替代實施例中，保護層160可由無機材料製成。
參照圖18及圖19，在形成保護層160之後，對晶圓100的後表面執行背側研磨製程。在背側研磨製程期間，對半導體基底110進行研磨，以使得薄化晶圓100'形成，薄化晶圓100'包括薄化半導體基底110'、形成在薄化半導體基底110'上的導電墊120、鈍化層130、後鈍化層140、導電柱150及保護層160。在執行背側研磨製程之後，如圖19所示，在薄化半導體基底110'的後表面處形成由背側研磨製程形成的非晶半導體部分110S（例如，非晶矽層）。在一些實施例中，非晶半導體部分110S的厚度可介於約10納米到約50納米的範圍內。
在執行背側研磨製程之後，在薄化半導體基底110'的後表面上形成金屬層M。舉例來說，通過濺鍍或其他合適的沉積製程在薄化半導體基底110'的後表面上形成金屬。金屬層M覆蓋且接觸薄化半導體基底110'的非晶半導體部分110S。金屬層M用作保護層來保護薄化半導體基底110'的非晶半導體部分110S不會被隨後執行的製程損壞或移除。金屬層M的厚度可小於約5000埃。舉例來說，金屬層M的厚度可介於約3000埃到約5000埃的範圍內。在一些實施例中，金屬層M可為單層金屬層（例如，銅層、銀層、鈦層或鎳層）或多層金屬層，且金屬層M的導熱率可大於或實質上等於20 W/mK。舉例來說，金屬層M的導熱率可介於約20 W/mK到約406 W/mK的範圍內。
參照圖20，在形成金屬層M之後，提供包括晶粒貼合膜DAF的切割膠帶DT並將薄化晶圓100'安裝在由切割膠帶DT承載的晶粒貼合膜DAF上，以使形成在薄化半導體基底110'的後表面上的金屬層M與切割膠帶DT上的晶粒貼合膜DAF黏在一起。在一些實施例中，切割膠帶DT可支撐安裝在切割膠帶DT上的薄化晶圓100'且晶粒貼合膜DAF可臨時與形成在薄化晶圓100'的後表面上的金屬層M黏在一起。另外，晶粒貼合膜DAF的材料可為黏性的且晶粒貼合膜DAF的導熱率（k）小於或實質上等於1 W/mK。在一些實施例中，晶粒貼合膜DAF的導熱率（k）可介於約0.01 W/mK到約1 W/mK的範圍內。
參照圖20及圖21，在將薄化晶圓100'安裝在切割膠帶DT上之後，對薄化晶圓100'、金屬層M及晶粒貼合膜DAF執行晶圓切割製程，以使薄化晶圓100'中的各積體電路組件200彼此單體化。在單體化製程之後，形成多個經單體化的積體電路組件200、多個經單體化的金屬層M1及多個經單體化的晶粒貼合膜DAF1，其中經單體化的金屬層M1位於經單體化的晶粒貼合膜DAF1與經單體化的積體電路組件200之間。如圖21所示，經單體化的積體電路組件200中的每一者包括半導體基底110a、形成在半導體基底110a上的導電墊120、鈍化層130a、後鈍化層140a、導電柱150及保護層160a。經單體化的金屬層M1覆蓋半導體基底110a的後表面，且經單體化的晶粒貼合膜DAF1與經單體化的金屬層M1黏在一起。半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的材料及特性與半導體基底110、鈍化層130、後鈍化層140及保護層160的材料及特性相同。因此，省略了對經單體化的積體電路組件200中的半導體基底110a、鈍化層130a、後鈍化層140a及保護層160a的詳細說明。
在所述背側研磨製程及所述晶圓切割製程期間，保護層160可充分地保護經單體化的積體電路組件200的導電柱150。另外，可保護經單體化的積體電路組件200的導電柱150不受隨後執行的製程（例如，經單體化的積體電路組件200的拾取及放置製程、模塑製程等）的損壞。
參照圖21及圖22，提供上面形成有剝離層DB的載體C。在一些實施例中，載體C是玻璃基底，且剝離層DB是形成在玻璃基底上的光熱轉換（LTHC）釋放層。在一些替代實施例中，可在剝離層DB上形成介電層（未示出），以使剝離層DB位於載體C與介電層之間。舉例來說，介電層是形成在剝離層DB上的聚苯並噁唑（PBO）層。
在提供上面形成有剝離層DB的載體C之後，在剝離層DB上形成多個導電穿孔TV。在一些實施例中，所述多個導電穿孔TV可通過晶種層的濺鍍、光阻塗布、微影、穿孔的電鍍、光阻剝除及晶種層的圖案化來形成。舉例來說，導電穿孔TV包括銅支柱或其他合適的金屬支柱。
如圖21及圖22所示，在一些實施例中，從切割膠帶DT拾取經單體化的積體電路組件200中的一者並將其放置在剝離層DB上。在一些替代實施例中，從切割膠帶DT拾取多於一個經單體化的積體電路組件200並將其放置在剝離層DB上，其中放置在剝離層DB上的經單體化的積體電路組件200可排列成陣列。當放置在剝離層DB上的經單體化的積體電路組件200排列成陣列時，可將導電穿孔TV分類成各個群組且經單體化的積體電路組件200的數目對應於導電穿孔TV的群組的數目。
通過經單體化的晶粒貼合膜DAF1將經單體化的積體電路組件200貼合在或黏在剝離層DB上，其中經單體化的晶粒貼合膜DAF1的導熱率（k）小於或實質上等於1 W/mK。在一些實施例中，經單體化的晶粒貼合膜DAF1的導熱率（k）可介於約0.01 W/mK到約1 W/mK的範圍內。另外，經單體化的晶粒貼合膜DAF1的材料可為黏性的。
如圖22所示，舉例來說，保護層160a的頂表面高於導電穿孔TV的頂表面，同時保護層160a的頂表面高於導電柱150的頂表面。然而，本公開並非僅限於此。在一些替代實施例中，保護層160a的頂表面可與導電穿孔TV的頂表面實質上對齊，且保護層160a的頂表面高於導電柱150的頂表面。
參照圖23，在剝離層DB上形成絕緣材料210以覆蓋經單體化的積體電路組件200及導電穿孔TV。在一些實施例中，絕緣材料210是通過模塑製程形成的模塑化合物。舉例來說，經單體化的積體電路組件200的保護層160a的頂表面被絕緣材料210覆蓋。換句話說，經單體化的積體電路組件200的保護層160a的頂表面未被露出而是被絕緣材料210保護住。在一些實施例中，絕緣材料210包括環氧樹脂或其他合適的介電材料。
參照圖23及圖24，對絕緣材料210進行研磨直到露出導電柱150的頂表面、導電穿孔TV的頂表面及保護層160a的頂表面為止。在一些實施例中，通過機械研磨製程和/或化學機械拋光（CMP）製程來對絕緣材料210進行研磨。在對絕緣材料210進行研磨之後，形成絕緣包封體210'。在絕緣材料210的研磨製程期間，對保護層160a的一些部分進行研磨以形成保護層160a'。在一些實施例中，在絕緣材料210及保護層160a的研磨製程期間，也輕微地對導電穿孔TV的一些部分及導電柱150的一些部分進行研磨。
如圖24所示，絕緣包封體210'在橫向上包封經單體化的積體電路組件200的側壁，且絕緣包封體210'被導電穿孔TV穿透。換句話說，經單體化的積體電路組件200及導電穿孔TV嵌入在絕緣包封體210'中。應注意，導電穿孔TV的頂表面、絕緣包封體210'的頂表面、導電柱150的頂表面及保護層160a'的頂表面實質上處於同一水平高度。
參照圖25，在形成絕緣包封體210'及保護層160a'之後，在導電穿孔TV的頂表面上、絕緣包封體210'的頂表面上、導電柱150的頂表面上及保護層160a'的頂表面上形成重佈線路結構RDL。將重佈線路結構RDL製作成與位於下方的一個或多個連接件電連接。此處，前述連接件可為經單體化的積體電路組件200的導電柱150和/或嵌入在絕緣包封體210'中的導電穿孔TV。重佈線路結構RDL可包括交替地堆疊的多條重佈線接線與多個圖案化介電層，如圖25所示。舉例來說，重佈線接線可為銅接線且圖案化介電層的材料可包括聚醯亞胺（PI）、聚苯並噁唑（PBO）或其他合適的介電聚合物。另外，導電穿孔TV經由重佈線路結構RDL電連接到經單體化的積體電路組件200。
參照圖26，在形成重佈線路結構RDL之後，形成多個導電特徵B，所述多個導電特徵B電連接到重佈線路結構RDL。導電特徵B設置在重佈線路結構RDL上且排列成陣列。在一些實施例中，導電特徵B可為排列成陣列的導電球（例如，焊料球）。如圖26所示，在由載體C承載的剝離層DB上製作封裝結構P11，封裝結構P11包括經單體化的金屬層M1、經單體化的晶粒貼合膜DAF1、經單體化的積體電路組件200、導電穿孔TV、絕緣包封體210'、重佈線路結構RDL及導電特徵B。
參照圖27，將剝離層DB及載體C從封裝結構P11剝離，以使導電穿孔TV的底表面、絕緣包封體210'的底表面及經單體化的晶粒貼合膜DAF1的表面從載體C剝離並被露出。絕緣包封體210'的底表面與經單體化的晶粒貼合膜DAF1的被露出的表面實質上處於同一水平高度。在一些實施例中，可向剝離層DB施加外部能量（例如紫外雷射、可見光或熱量），以使封裝結構P11與由載體C承載的剝離層DB分離。
參照圖28，在執行剝離製程之後，可將封裝結構P11翻轉（上下倒置）並安裝到鋸切膠帶ST上，以使封裝結構P11的導電特徵B與鋸切膠帶ST黏在一起。在一些實施例中，鋸切膠帶ST可支撐安裝在鋸切膠帶ST上的上述封裝結構P11且臨時與封裝結構P11的導電特徵B黏在一起。由於經單體化的晶粒貼合膜DAF1的導熱率（k）低（即，小於或實質上等於1 W/mK），因此經單體化的晶粒貼合膜DAF1可能無法有效地傳導及分散從經單體化的積體電路組件200產生的熱量。因此，可將經單體化的晶粒貼合膜DAF1移除直到露出經單體化的金屬層M1為止以增強封裝結構P11的散熱性能。舉例來說，可通過乾式刻蝕（例如，電漿處理）或其他合適的移除製程來移除經單體化的晶粒貼合膜DAF1。當移除經單體化的晶粒貼合膜DAF1時，經單體化的金屬層M1可保護薄化半導體基底110'的非晶半導體部分110S（圖29所示）不被損壞或移除。
參照圖29，在移除經單體化的晶粒貼合膜DAF1之後，可通過分配或其他合適的製程形成熱膏TP以覆蓋經單體化的金屬層M1的被露出的表面，其中熱膏TP的導熱率（k）大於或實質上等於10 W/mK。舉例來說，熱膏TP的導熱率（k）介於約10 W/mK到約250 W/mK的範圍內。在一些實施例中，熱膏TP的導熱率（k）可小於經單體化的金屬層M1的導熱率（k）。在一些替代實施例中，熱膏TP的導熱率（k）可大於或實質上等於經單體化的金屬層M1的導熱率（k）。由於熱膏TP及經單體化的金屬層M1二者的導熱率（k）高（即，大於或實質上等於10 W/mK），因此熱膏TP及經單體化的金屬層M1可有效地傳導及分散從經單體化的積體電路組件200產生的熱量。
如圖29所示，經單體化的金屬層M1嵌入在絕緣包封體210'中並接觸薄化半導體基底110'的非晶半導體部分110S。另外，熱膏TP覆蓋經單體化的金屬層M1且熱膏TP部分地嵌入在絕緣包封體210'中。在一些實施例中，熱膏TP可比經單體化的金屬層M1厚。舉例來說，熱膏TP的厚度可介於約1微米到約100微米的範圍內。在一些替代實施例中，熱膏TP可比經單體化的金屬層M1薄。在一些其他實施例中，熱膏TP與經單體化的金屬層M1的厚度可實質上相同。另外，熱膏TP可不僅覆蓋經單體化的金屬層M1的表面，而且還可局部地覆蓋絕緣包封體210'的表面。然而，熱膏TP的分佈並非僅限於此。
當熱膏TP含有金屬粒子（例如，銅粒子）時，經單體化的金屬層M1可用作金屬粒子的擴散障壁。另外，薄化半導體基底110'的非晶半導體部分110S可從經單體化的金屬層M1捕獲金屬粒子且可用作從經單體化的金屬層M1擴散的金屬粒子的擴散障壁。因此，封裝結構P11可容易地通過高溫工作壽命（HTOL）測試。
在一些替代實施例中，可省略熱膏TP的製作，如圖32所示。
如圖29所示，經單體化的金屬層M1與熱膏TP的組合可被視為覆蓋經單體化的積體電路組件200的非晶半導體部分110S的導熱層。在一些替代實施例中，當省略熱膏TP的製作時，導熱層只包括經單體化的金屬層M1。
參照圖30，提供半導體元件P2並將半導體元件P2放置在封裝結構P11上以將半導體元件P2電連接到導電穿孔TV。半導體元件P2經由導電穿孔TV及重佈線路結構RDL電連接到經單體化的積體電路組件200。在一些實施例中，半導體元件P2可經由多個導電凸塊BP電連接到封裝結構P11的導電穿孔TV。舉例來說，導電凸塊BP可為微凸塊、受控塌陷晶粒連接（C4）凸塊等。
在一些實施例中，半導體元件P2可為其底表面上包括導電凸塊BP的記憶體元件（例如，DRAM）。在將記憶體元件安裝到封裝結構P11上之前，可通過例如絲網印刷製程向封裝結構P11的導電穿孔TV上施加焊料材料，且接著將包括導電凸塊BP的半導體元件P2放置在導電穿孔TV上。之後，執行回焊製程以在半導體元件P2與封裝結構P11的導電穿孔TV之間形成焊料接頭。
在執行上述回焊製程之後，在封裝結構P11與半導體元件P2之間形成底部填充膠UF以包封熱膏TP及導電凸塊BP。在一些實施例中，底部填充膠UF的材料可包括含有填料的環氧樹脂且底部填充膠UF的導熱率可小於約1 W/mK。底部填充膠UF在橫向上包封導電凸塊BP且用作應力緩衝器，以最小化因封裝結構P11與半導體元件P2之間的熱膨脹係數（CTE）不匹配所導致的導電凸塊BP的疲勞。
在形成底部填充膠UF之後，對封裝結構P11執行鋸切製程以形成多個經單體化的疊層封裝（PoP）結構。在執行封裝結構P11的鋸切製程之後，經單體化的疊層封裝（PoP）結構與鋸切膠帶ST黏在一起。另外，底部填充膠UF可確保包括封裝結構P11及半導體元件P2的疊層封裝（PoP）結構的可靠性。
根據本公開的一些實施例，提供一種包括以下步驟的製作晶片封裝件的方法。通過第一熱膏將積體電路組件貼合在載體上，其中所述第一熱膏的導熱率介於約10 W/mK到約250 W/mK的範圍內。形成絕緣包封體，以對貼合在所述載體上的所述積體電路組件進行包封。在所述絕緣包封體及所述積體電路組件上形成重佈線路結構，其中所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在形成所述絕緣包封體之前，在所述載體上形成多個導電穿孔，以使所述多個導電穿孔被所述絕緣包封體包封，其中在形成所述重佈線路結構之後，所述多個導電穿孔經由所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在形成所述重佈線路結構之後，將所述第一熱膏及所述絕緣包封體從所述載體剝離；以及將半導體元件電連接到所述多個導電穿孔，以使所述第一熱膏位於所述積體電路組件與所述半導體元件之間，其中所述半導體元件經由所述多個導電穿孔及所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在所述積體電路組件與所述半導體元件之間形成底部填充膠以覆蓋所述第一熱膏。在實施例中，所述方法還包括：在形成所述重佈線路結構之後，將所述第一熱膏及所述絕緣包封體從所述載體剝離以露出所述第一熱膏的表面；在所述第一熱膏的被露出的所述表面上形成第二熱膏，其中所述第二熱膏的導熱率大於或實質上等於10 W/mK；以及將半導體元件電連接到所述多個導電穿孔，以使所述第一熱膏與所述第二熱膏位於所述積體電路組件與所述半導體元件之間，其中所述半導體元件經由所述多個導電穿孔及所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在所述積體電路組件與所述半導體元件之間形成底部填充膠以包封所述第二熱膏。在實施例中，所述積體電路組件包括位於所述積體電路組件的後表面處的非晶半導體部分，且所述積體電路組件的所述非晶半導體部分接觸所述第一熱膏。
根據本公開的一些實施例，提供一種包括以下步驟的製作晶片封裝件的方法。提供積體電路組件，所述積體電路組件上形成有金屬層。通過晶粒貼合膜將所述積體電路組件貼合在載體上，以使所述金屬層位於所述積體電路組件與所述晶粒貼合膜之間，其中所述金屬層的導熱率大於所述晶粒貼合膜的導熱率。形成絕緣包封體，以對貼合在所述載體上的所述積體電路組件進行包封。在所述絕緣包封體及所述積體電路組件上形成重佈線路結構，其中所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在形成所述絕緣包封體之前，在所述載體上形成多個導電穿孔，以使所述多個導電穿孔被所述絕緣包封體包封，其中在形成所述重佈線路結構之後，所述多個導電穿孔經由所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在形成所述重佈線路結構之後，將所述晶粒貼合膜及所述絕緣包封體從所述載體剝離；以及移除所述晶粒貼合膜以露出所述金屬層；將半導體元件電連接到所述多個導電穿孔，以使所述晶粒貼合膜位於所述積體電路組件與所述半導體元件之間，其中所述半導體元件經由所述多個導電穿孔及所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在所述積體電路組件與所述半導體元件之間形成底部填充膠以覆蓋所述金屬層。在實施例中，所述方法還包括：在形成所述重佈線路結構之後，將所述晶粒貼合膜及所述絕緣包封體從所述載體剝離以露出所述晶粒貼合膜；移除所述晶粒貼合膜以露出所述金屬層；在所述金屬層上形成熱膏；以及將半導體元件電連接到所述多個導電穿孔，以使所述金屬層及所述熱膏位於所述積體電路組件與所述半導體元件之間，其中所述半導體元件經由所述多個導電穿孔及所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述方法還包括：在所述積體電路組件與所述半導體元件之間形成底部填充膠以對所述熱膏進行包封。在實施例中，所述積體電路組件包括位於所述積體電路組件的後表面處的非晶半導體部分，且所述積體電路組件的所述非晶半導體部分接觸所述金屬層。在實施例中，所述金屬層的導熱率介於約20 W/mK到約406 W/mK的範圍內。
根據本公開的一些實施例，提供一種晶片封裝件，所述晶片封裝件包括積體電路組件、導熱層、絕緣包封體及重佈線路結構。所述積體電路組件包括位於所述積體電路組件的後表面處的非晶半導體部分。所述導熱層覆蓋所述積體電路組件的所述非晶半導體部分，其中所述導熱層的導熱率介於約10 W/mK到約250 W/mK的範圍內。所述絕緣包封體對所述積體電路組件及所述導熱層進行包封。所述重佈線路結構設置在所述絕緣包封體及所述積體電路組件上，其中所述重佈線路結構電連接到所述積體電路組件。在實施例中，所述導熱層包括第一熱膏，所述第一熱膏接觸所述積體電路組件的所述非晶半導體部分。在實施例中，所述導熱層包括第一熱膏以及第二熱膏。第一熱膏接觸所述積體電路組件的所述非晶半導體部分，所述第一熱膏的導熱率介於約10 W/mK到約250 W/mK的範圍內。第二熱膏覆蓋所述第一熱膏，其中所述第二熱膏的導熱率介於約10 W/mK到約250 W/mK的範圍內。在實施例中，所述導熱層包括金屬層，所述金屬層接觸所述積體電路組件的所述非晶半導體部分，且所述金屬層的導熱率介於約20 W/mK到約406 W/mK的範圍內。在實施例中，所述導熱層包括金屬層以及熱膏。金屬層接觸所述積體電路組件的所述非晶半導體部分。熱膏覆蓋所述金屬層，其中所述熱膏部分地嵌入在所述絕緣包封體中。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
100‧‧‧晶圓 100'‧‧‧薄化晶圓 110、110a‧‧‧半導體基底 110'‧‧‧薄化半導體基底 110S‧‧‧非晶半導體部分 120‧‧‧導電墊 130、130a‧‧‧鈍化層 132、142‧‧‧接觸開口 140、140a‧‧‧後鈍化層 150‧‧‧導電柱 160、160a、160a'‧‧‧保護層 200‧‧‧積體電路組件 210‧‧‧絕緣材料 210'‧‧‧絕緣包封體 B‧‧‧導電特徵 BP‧‧‧導電凸塊 C‧‧‧載體 DAF、DAF1‧‧‧晶粒貼合膜 DB‧‧‧剝離層 DT‧‧‧切割膠帶 M、M1‧‧‧金屬層 P1、P11‧‧‧封裝結構 P2‧‧‧半導體元件 RDL‧‧‧重佈線路結構 ST‧‧‧鋸切膠帶 TP‧‧‧熱膏 TP1‧‧‧第一熱膏 TP2‧‧‧第二熱膏 TV‧‧‧導電穿孔 UF‧‧‧底部填充膠
結合附圖閱讀以下詳細說明，會最好地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。 圖1到圖15示出根據本公開一些實施例的用於製作積體扇出型封裝件的製程流程。 圖16到圖30示出根據本公開一些替代實施例的用於製作積體扇出型封裝件的製程流程。 圖31示意性地示出根據本公開一些實施例的積體扇出型封裝件。 圖32示意性地示出根據本公開一些替代實施例的積體扇出型封裝件。
110'‧‧‧薄化半導體基底
110S‧‧‧非晶半導體部分
200‧‧‧積體電路組件
210'‧‧‧絕緣包封體
B‧‧‧導電特徵
P1‧‧‧封裝結構
RDL‧‧‧重佈線路結構
ST‧‧‧鋸切膠帶
TP1‧‧‧第一熱膏
TP2‧‧‧第二熱膏
TV‧‧‧導電穿孔

Claims (1)

  1. 一種晶片封裝件，包括： 積體電路組件，包括位於所述積體電路組件的後表面處的非晶半導體部分； 導熱層，覆蓋所述積體電路組件的所述非晶半導體部分，其中所述導熱層的導熱率介於約10 W/mK到約250 W/mK的範圍內； 絕緣包封體，對所述積體電路組件及所述導熱層進行包封；以及 重佈線路結構，設置在所述絕緣包封體及所述積體電路組件上，其中所述重佈線路結構電連接到所述積體電路組件。
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