TW201907380A - Display and related data distribution circuit - Google Patents

Abstract

A display is provided. The display includes a pane; a data driving circuit, arranged on the panel, capable of generating a first data signal; a dispatching circuit, arranged on the panel, capable of receiving the first data signal and generating a first sub-data signal and a second sub-data signal; and a gate driving circuit, arranged on the panel, capable of generating a first gate pulse and a second pulse. The pixel array includes a first pixel element and a second pixel element being adjacent to the first pixel element. The first pixel element receives the first sub-data signal and the first gate pulse, and the second pixel element receives the second sub-data signal and the second gate pulse.

Description

Display and related data distribution circuit

The invention relates to a display and a control circuit, and in particular to a display and a related data distribution circuit.

Please refer to FIG. 1, which is a schematic diagram of a conventional display. The display 100 includes a panel 110, a data driving circuit 120, a gate driving circuit 102, and a pixel unit p11 to p44, and the data driving circuit 120, the gate driving circuit 102, and the pixel unit p11 to p44 are all located on the panel 110, and the data driving The circuit 120 and the gate driving circuit 102 are electrically coupled to the pixel units p11 to p44, and each of the pixel units p11 to p44 includes a switching transistor.

Taking the first figure as an example, the pixel units p11 to p44 are arranged in a 4 × 4 pixel array. The pixel units in each column receive the same gate wave, and the pixel units in each row receive the same data signal. In other words, when looking at the pixel units p11, p12, p13, and p14 in the same column, the same gate pulse wave is received through the gate line G1, where the gate pulse wave is output by the gate driving circuit 102; Looking at the pixel units p11, p21, p31, and p41 of the same row, the same data signal is received through the data line D1, where the data signal is provided by the data driving circuit 120.

The pixel units p11 to p14 in the first column of FIG. 1 are taken as an example for illustration. When the gate driving circuit 102 inputs the gate pulse wave of high potential through the gate line G1, when the gate terminal of the switching transistor sw receives the gate pulse wave and is turned on, the pixel unit p11 can receive the data signal output from the data driving circuit 120. D1, the pixel unit p12 receives the data signal D2, the pixel unit p13 receives the data signal D3, and the pixel unit p14 receives the data signal D4, so that the pixel units p11 to p14 display the set image. Of course, the pixel units in other columns also have the same connection relationship and operation principle, which will not be repeated here.

The purpose of the present invention is to provide a display, which adds a data distribution circuit between the data driving circuit and the pixel array, so as to reduce the output pins of the data driving circuit.

The invention is a display, comprising: a panel; a data driving circuit that generates a first data signal, and the data driving circuit is located on the panel; a data distribution circuit that receives the first data signal and generates a first sub-signal A data signal and a second sub-data signal, and the data distribution circuit is located on the panel; and a gate driving circuit generates a first gate pulse and a second gate pulse, and the gate driving circuit is located on the panel; A pixel array is disposed on the panel, and the pixel array has a first pixel unit and a second pixel unit adjacent to each other, and the first pixel unit receives the first gate pulse wave and the first pixel unit. For the sub-data signal, the second pixel unit receives the second gate pulse wave and the second sub-data signal. The invention is a display, which comprises a data driving chip, a gate driving circuit and a pixel array. The gate driving circuit generates a first gate pulse wave and a second gate pulse wave. The pixel array has adjacent first pixel units and second pixel units, and the first pixel unit receives a first gate wave and the second pixel unit receives a second gate wave. At the first time, the gate driving chip outputs a first voltage value to the first pixel unit, and the first gate pulse wave is at the first level and the second gate pulse wave is at the second level. During the second period, the data-driven chip outputs a second voltage value to the second pixel unit, and the first gate wave is at the first level and the second gate wave is at the first level. During the third period, the data-driven chip outputs a third voltage value, the first gate wave is at the second level, and the second gate wave is at the first level.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are described in detail below in conjunction with the accompanying drawings:

Please refer to FIG. 2A and FIG. 2B, which are schematic diagrams of the display and related signals of the present invention. The display 200 includes: a panel 210, a data driving circuit 220, a data distribution circuit 230, a gate driving circuit 202, and pixel units p11 to p43. Specifically, the gate driving circuit 202 and the pixel units p11 to p43 are disposed on the panel 210, and each of the pixel units p11 to p43 includes a switching transistor and a storage capacitor. Taking the pixel unit p11 as an example, it includes a switching transistor sw1 and a storage capacitor cs1.

Taking FIG. 2A as an example, the pixel units p11 to p43 are arranged in a 4 × 3 pixel array. The pixel units in each column receive the same gate wave. In other words, when the pixel units p11, p12, p13, and p14 of the same column are viewed, the same gate pulse wave is received through the gate line G1, where the gate pulse wave is output by the gate driving circuit 102. In the present invention, the x-direction shown in FIG. 2A is defined as the direction of the columns, and the y-direction is defined as the direction of the rows. Moreover, FIG. 2A only shows the data signals D1 to D3, the conversion circuits 231 to 236, the gate pulses G1 to G4, and the sub data signals D1a to D3a, D1b to D3b. In fact, the present invention is not limited to this. Those skilled in the art can expand the display to any size according to the display 200 disclosed in FIG. 2A.

According to an embodiment of the present invention, the data distribution circuit 230 includes a plurality of conversion circuits 231 to 236. Referring to FIG. 2A, the conversion circuits 231 and 232 receive the data signal D1 output from the data driving circuit 220 and generate sub-data signals D1a and D1b, respectively. Similarly, the conversion circuits 233 and 234 receive the data signal D2 output from the data driving circuit 220 and generate sub-data signals D2a and D2b, respectively. The conversion circuits 235 and 236 receive the data signal D3 output from the data driving circuit 220 and generate sub-data signals D3a and D3b, respectively.

Furthermore, among the pixel units in the first row, odd pixel units p11 and p31 receive the sub-data signal D1a, and even pixel units p21 and p41 receive the sub-data signal D1b. Similarly, among the pixel units in the second row, the odd-numbered pixel units p12 and p32 receive the sub-data signal D2a, and the even-numbered pixel units p22 and p42 receive the sub-data signal D2b. In the third pixel unit, the odd pixel units p13 and p33 receive the sub data signal D3a, and the even pixel units p23 and p43 receive the sub data signal D3b. In other words, in the pixel units in the same row, two adjacent pixel units are electrically coupled to different sub-data signals. For example, two adjacent pixel units p21 and p31 are electrically Coupled to the sub-data signal D1b and the sub-data signal D1a. Of course, the present invention is not limited to FIG. 2A, and the odd-numbered pixel units in the first row may be connected to the data signal D1b and the even-numbered pixel units may be connected to the data signal D1a.

According to the embodiment of the present invention, the gate driving circuit 202 generates gate pulses G1 to G4, and among the gate pulse waves G1 to G4 generated by the gate driving circuit 202, any two gate pulses overlap each other at a high potential portion, Therefore, the pixel units of the two columns are turned on at the same time.

As shown in FIG. 2B, the period of the clock signal I is 2T, and the pulse width of the gate pulse waves G1 to G4 is 2T. Obviously, in the interval between the time point tb and the time point tc, the pixel units p11 to p13 of the first column and the pixel units p21 to p23 of the second column are all turned on. Similarly, in the interval between the time point tc and the time point td, the pixel units p21 to p23 of the second column and the pixel units p31 to p33 of the third column are all turned on. In the interval between the time point td and the time point te, the pixel units p31 to p33 of the third column and the pixel units p41 to p43 of the fourth column are all turned on. And so on.

As shown in FIG. 2B, the data signals D1 to D3 change their voltage values after every time T. For example, the data signals D1 to D3 output voltages v1, v5, and v9 from time point ta to time point tb, respectively, and output voltages v2, v6, and v10 from time point tb to time point tc. The voltages v3, v7, and v11 are output between time points td, and the voltages v4, v8, and v12 are output between time point te and time point tf.

According to the embodiment of the present invention, the conversion circuits 231, 233, and 235 receive the voltage values on the data signals D1 to D3 when the clock signal I is at a high level, and change the sub data signals D1a to D3a within 2T. To the received voltage value. Furthermore, when the conversion circuits 232, 234, and 236 are at the low level of the clock signal I, the voltage values on the data signals D1 to D3 are received, and the sub data signals D1b to D3b are changed to the received data within 2T. The voltage value.

As shown in FIG. 2B, between the time point ta and the time point tb, the clock signal I is at a high level, and the conversion circuits 231, 233, and 235 receive the voltages v1, v5, and v9 from the data signals D1 to D3. value. The conversion circuits 231, 233, and 235 change the voltage values of v1, v5, and v9 of the sub-data signals D1a to D3a between the time point ta and the time point tc.

In addition, between the time point tb and the time point tc, the clock signal I is at a low level, and the conversion circuits 232, 234, and 236 receive the voltage values of v2, v6, and v10 from the data signals D1 to D3. The conversion circuits 232, 234, and 236 change the voltage values of v2, v6, and v10 of the sub-data signals D1b to D3b between the time point tb and the time point td.

Moreover, between the time point tc and the time point td, the clock signal I is at a high level, and the conversion circuits 231, 233, and 235 receive the voltage values of v3, v7, and v11 from the data signals D1 to D3. The conversion circuits 231, 233, and 235 change the voltage values of v3, v7, and v11 of the sub-data signals D1a to D3a between the time point tc and the time point te.

In addition, between the time point td and the time point te, the clock signal I is at a low level, and the conversion circuits 232, 234, and 236 receive the voltage values of v4, v8, and v12 from the data signals D1 to D3. The conversion circuits 232, 234, and 236 change the voltage values of v4, v8, and v12 of the sub-data signals D1b to D3b between the time point td and the time point tf.

Please refer to FIG. 3A and FIG. 3B, which are schematic diagrams of the data distribution circuit and related signals of the present invention. In FIG. 3A, only the conversion circuits 231 and 232 in the data distribution circuit 230 are described as an example, and the other conversion circuits in the data distribution circuit 230 are similar in structure and will not be described again here. The conversion circuit is a voltage-to-current conversion circuit (V to I converting circuit).

The conversion circuit 231 includes transistors m1 to m4 and a capacitor c1. Specifically, the transistors m1 to m4 have a first terminal, a second terminal, and a control terminal, respectively. The control terminal of the transistor m1 receives the clock signal I, the first terminal receives the data signal D1, and the second terminal is a control terminal electrically connected to the transistor m2. The first terminal of the transistor m2 receives the power supply voltage Vdd, and the second terminal generates a sub-data signal D1a. The control terminal of the transistor m3 receives the reset signal R1, and the first terminal is electrically connected to the control terminal of the transistor m2, and the second terminal receives the power supply voltage Vdd. The control terminal of the transistor m4 receives the reset signal R1, the first terminal receives the bias voltage Vlb, and the second terminal is connected to the second terminal of the transistor m2. The first terminal of the capacitor c1 is electrically connected to the control terminal of the transistor m2, and the second terminal receives the power supply voltage Vss. Among them, transistors m1, m3, and m4 are n-type transistors, transistor m2 is a p-type transistor, and the power supply voltage Vdd is greater than the power supply voltage Vss, the bias voltage Vlb is greater than or equal to the power supply voltage Vss, and the power supply voltage Vss may be a ground voltage .

Similarly, the conversion circuit 232 also includes transistors m5 to m8 and a capacitor c2, where the transistors m5 to m8 have a first terminal, a second terminal, and a control terminal, respectively. The control terminal of the transistor m5 receives the clock signal I, the first terminal receives the data signal D1, and the second terminal is electrically connected to the control terminal of the transistor m6. The first terminal of the transistor m6 receives the power supply voltage Vdd, and the second terminal can generate the sub-data signal D1b. The control terminal of the transistor m7 receives the reset signal R2, and the first terminal is electrically connected to the control terminal of the transistor m6, and the second terminal receives the power supply voltage Vdd. The control terminal of the transistor m8 also receives the reset signal R2, and the first terminal receives the bias voltage Vlb, and the second terminal is electrically connected to the second terminal of the transistor m6. The first terminal of the capacitor c2 is electrically connected to the control terminal of the transistor m6, and the second terminal is received by the power voltage Vss. Among them, the transistors m5 and m6 are p-type transistors, and the transistors m7 and m8 are n-type transistors.

Furthermore, in the conversion circuits 231 and 232 of another modification of the present invention, the transistors m1, m3, m7, and m8 may be replaced with p-type transistors, and the transistors m2, m5, and m6 may be n-type transistors. To replace. In addition, for an n-type transistor, the control terminal can be a gate terminal, the first terminal can be a drain terminal, and the second terminal can be a source terminal; for a p-type transistor, the control terminal can be a gate terminal. The terminal may be a source terminal and the second terminal may be a drain terminal.

As shown in FIG. 3B, the period of the clock signal I is 2T, where the width of the high level of the clock signal I is T, and the width of the low level of the clock signal I is T. In this embodiment, the pulse wave widths of the gate pulse waves G1 and G2 are 2T. Specifically, the time during which the gate pulse waves are at a high level is 2T. That is, the pulse wave widths of the gate pulse waves G1 and G2 are substantially the same as one cycle of the clock signal I. In addition, the data signal D1 changes its voltage value after every time T. For example, the data signal D1 outputs the voltage v1 between time point ta and time point tb, the voltage v2 between time point tb and time point tc, and the voltage v3 between time point tc and time point td. Until the time point tf, the voltage v4 is output. The operation principle of the data distribution circuit 230 is described in detail below.

Please refer to FIG. 3A and FIG. 3B at the same time. Between the time point ta and the time point tb, the clock signal I is at a high level. As a result, the transistor m5 in the conversion circuit 232 is turned off, so that the conversion circuit 232 cannot receive the voltage v1 on the data signal D1. Furthermore, when the clock signal I is at a high level, the transistor m1 in the conversion circuit 231 is turned on, and the capacitor c1 in the conversion circuit 321 stores the voltage v1 on the data signal D1. In addition, the transistor m2 generates a charging current i1 based on the voltage v1.

Since the gate pulse wave G1 is at a high level and the gate pulse wave G2 is at a low level, the switching transistor sw1 in the pixel unit p11 is turned on, and the switching transistor sw2 in the pixel unit p21 is turned off. Therefore, the charging current i1 output by the conversion circuit 231 charges the storage capacitor cs1 in the pixel unit p11, so that the sub-data signal D1a and the voltage V11 of the storage capacitor cs1 gradually increase.

Between the time point tb and the time point tc, the clock signal I is at a low level. The transistor m1 in the conversion circuit 231 is not turned on and is turned off, so that it cannot receive the v2 voltage of the data signal D1. However, since the voltage of v1 is still stored in the capacitor c1, the transistor m2 continues to generate the charging current i1 according to the voltage of v1. Furthermore, because the gate pulse G1 is still at a high level, the charging current i1 output by the conversion circuit 231 continues to charge the storage capacitor cs1 in the pixel unit p11, which will cause the sub-data signal D1a and the voltage V11 of the storage capacitor cs1 to rise High to v1 voltage. During the same period, affected by the low level of the clock signal I, the transistor m5 in the conversion circuit 232 is turned on and turned on, so that the conversion circuit 232 receives the voltage v2 on the data signal D1. In this way, the capacitor c2 in the conversion circuit 232 stores the v2 voltage on the data signal D1, so that the transistor m6 can generate the charging current i2 according to the v2 voltage. At this time, the gate pulse G2 is at a high level, so that the switching transistor sw2 of the pixel unit p21 is turned on and turned on. Therefore, the charging current i2 output by the conversion circuit 232 can be input to the pixel unit p21, and then the voltage V21 of the storage capacitor cs2 is charged.

During the period from the time point tb to the time point tc, the gate pulse waves G1 and G2 are used as the high level, so that the switching transistors sw1 and sw2 of the pixel units p11 and p21 are turned on. The charging current i1 output from the conversion circuit 231 charges the storage capacitor cs1 in the pixel unit p11. At the same time, the charging current i2 output from the conversion circuit 232 charges the storage capacitor cs2 in the pixel unit p12, so that the sub-data signal D1b and the voltage V21 of the storage capacitor cs2 gradually increase.

Judging from the data signal D1 output by the data driving circuit 220, the data signal D1 is written into the conversion circuit 231 between the time point ta and the time point tb; and between the time point tb and the time point tc, the data signal D1 is written入 保护 电路 232.

From the perspective of the pixel unit p11, when the data signal D1 is written into the conversion circuit 231 from the time point ta to the time point tb, the conversion circuit 231 is converted into a sub-data signal D1a and input to the pixel unit p11. Furthermore, although the data signal D1 is not written into the conversion circuit 231 from time point tb to time point tc, since the capacitor c1 still stores the previous data signal D1, the conversion circuit 231 can still be converted into a sub data signal D1a and input to the pixel Unit p11. Therefore, in this embodiment, the time when the data signal D1 is written into the conversion circuit 231 is the time T, but the time when the conversion circuit 231 uses the data signal D1a to be input to p11 is extended to the time 2T.

At the time point tc, the reset signal R1 acts briefly, so that the conversion circuit 231 is reset. At this time, the transistors m3 and m4 are turned on, so that the transistor m2 receives the power supply voltage Vdd and is turned off, and the sub-data signal D1a returns the bias voltage Vlb.

Then, from the time point tc to the time point td, since the clock signal I is at a high level, the transistor m1 in the conversion circuit 231 is turned on, so that the conversion circuit 232 receives the v3 voltage on the data signal D1 and stores it in the capacitor c1. In addition, the transistor m2 generates a charging current i1 based on the voltage v3. Furthermore, the transistor m5 in the conversion circuit 232 is turned off, so that the conversion circuit 232 cannot receive the voltage v3 on the data signal D1. However, the capacitor c2 still stores the v2 voltage, so that the transistor m6 continues to generate the charging current i2 according to the v2 voltage. At this time, because the gate pulse G2 is still at a high level, the charging current i2 output by the conversion circuit 232 continues to charge the storage capacitor cs2 in the pixel unit p21, which will cause the sub-data signal D1b and the voltage V21 of the storage capacitor cs2 to rise. High to v2 voltage. During the same period, affected by the high level of the clock signal I and the gate wave G3, the transistor m1 in the conversion circuit 231 is turned on and turned on, so that the conversion circuit 231 receives the voltage v3 on the data signal D1. In this way, the capacitor c1 in the conversion circuit 231 stores the v3 voltage on the data signal D1, so that the transistor m2 can generate a charging current according to the v3 voltage and output it to the storage capacitor of the pixel unit p31 (not shown).

As can be seen from the above description, the data signal D1 between the time point ta and the time point tb (time length T) is the voltage v1. The conversion circuit 231 can transfer the v1 voltage of the data signal D1 to the storage capacitor cs1 of the pixel unit p11 between the time point ta and the time point tc (time length 2T). Similarly, the data signal D1 between the time point tb and the time point tc (time length T) is a voltage v2. The conversion circuit 232 can store the voltage v2 of the data signal D1 into the storage capacitor cs2 of the pixel unit p21 between the time point tb and the time point td (time length 2T). The data signal D1 between the time point tc and the time point td (time length T) is a voltage v3. The conversion circuit 231 can store the v3 voltage of the data signal D1 in the storage capacitor of the pixel unit p31 between the time point tc and the time point te (time length 2T). The data signal D1 between the time point td and the time point te (time length T) is a voltage of v4. The conversion circuit 232 can store the v4 voltage of the data signal D1 in the storage capacitor of the pixel unit p41 between the time point td and the time point tf (time length 2T). So on and so on.

Please refer to FIG. 2B and FIG. 3A at the same time. In the embodiment of the present invention, the data signal D1 will generate different gray scale states at each time T according to the grayscale state of the pixel unit (such as p11, p21). Voltage value, and the data signal D1 is selectively transmitted to adjacent pixel units in the same row through a clock signal I with a period of 2T. In addition, with the influence of the gate pulse width of 2T, the charging time obtained by each pixel unit can be extended to a time of 2T. In other words, in terms of the data signal D1, the sub data signal D1a is transmitted between time ta ~ tb, and the sub data signal D1b is transmitted between time tb and bc, so that the data signal D1 can be transmitted at each time T Different subdata signals. At the same time, the data signal D1 is selectively transmitted to the odd or even pixel units of the peer through the control signal I. For example, as shown in FIG. 3A, when the control signal I is at a high level, the data signal D1 is transmitted In the odd pixel unit p11, when the control signal I is at a low level, the data signal D1 is transmitted to the even pixel unit p21. Looking at the pixel unit p11, even if the data signal D1 is transmitted to D1a only at time ta ~ tb, the width of the gate pulse G1 is 2T and the storage voltage function of the conversion circuit 231 makes the pixel unit p11 available at time ta. They are all charged between ~ tc. Similarly, from the point of view of the pixel unit p21, even if the data signal D1 is transmitted to D1b only at time tb ~ tc, but the width of the gate pulse G2 is 2T and the storage voltage function of the conversion circuit 232 makes the pixel unit p21 capable of It is in a charging state between time tb ~ td.

As can be seen from the above description, an embodiment of the present invention provides a display and a related data distribution circuit. In the display, using the data driving circuit of the double data line and the data distribution circuit will make the panel have the effect of 1 gate extreme line and 2 data lines (1G2D). Furthermore, the display of the present invention increases the charging time of the pixel unit by a factor of two, so that the high-resolution panel can be charged to a required voltage more.

Furthermore, the present invention does not limit the position where the data distribution circuit is actually arranged. Those skilled in the art can make the data distribution circuit on the panel, or connect an independent circuit between the data driving circuit and the panel, or integrate the data distribution circuit in the data driving circuit.

In summary, although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

100, 200‧‧‧ Display

102, 202‧‧‧Brake driving circuit

110, 210‧‧‧ panels

120, 220‧‧‧ Data Drive Circuit

230‧‧‧Data Distribution Circuit

231 ~ 236‧‧‧ Conversion circuit

FIG. 1 is a schematic diagram of a conventional display. FIG. 2A and FIG. 2B are schematic diagrams of a display and related signals of the present invention. 3A and 3B are schematic diagrams of a data distribution circuit and related signals according to the present invention.

Claims (10)

A display includes: a panel; a data driving circuit that generates a first data signal, and the data driving circuit is located on the panel; a data distribution circuit that receives the first data signal and generates a first sub data signal and A second sub data signal, and the data distribution circuit is located on the panel; and a gate driving circuit generates a first gate pulse and a second gate pulse, and the gate driving circuit is located on the panel; a pixel array Is disposed on the panel, and the pixel array has a first pixel unit and a second pixel unit adjacent to each other, and the first pixel unit receives the first gate wave and the first sub-data signal The second pixel unit receives the second gate pulse wave and the second sub-data signal. The display according to item 1 of the scope of patent application, wherein the gate driving circuit generates a third gate pulse and a fourth gate pulse, and the pixel array has a third pixel unit and a first pixel adjacent to each other. A four pixel unit, and the third pixel unit receives the third gate wave and the first sub data signal, and the fourth pixel unit receives the fourth gate wave and the second sub data signal. The display according to item 1 of the patent application range, wherein the data distribution circuit includes a first conversion circuit and a second conversion circuit, and the first conversion circuit converts the first data signal into the first sub data signal The second conversion circuit converts the first data signal into the second sub-data signal. The display according to item 3 of the scope of patent application, wherein the first conversion circuit includes: a first transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal receives a clock signal, The first terminal receives the first data signal; a second transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal is electrically connected to the second terminal of the first transistor; The first terminal receives a first power voltage, and the second terminal generates the first sub-data signal. A third transistor has a first terminal, a second terminal, and a control terminal. The control terminal is connected to A first reset signal is received, the first terminal is electrically connected to the control terminal of the second transistor, and the second terminal receives the first power supply voltage; a fourth transistor has a first terminal, A second terminal and a control terminal, wherein the control terminal receives the first reset signal, the first terminal receives a bias voltage, and the second terminal is electrically connected to the second terminal of the second transistor; And a first capacitor having a first end and a second Wherein the first end is electrically connected to the control terminal of the second transistor, and the second terminal receives a second power supply voltage. The display according to item 4 of the scope of patent application, wherein the second conversion circuit includes: a fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal receives the clock signal The first terminal receives the first data signal; a sixth transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal is electrically connected to the first terminal of the fifth transistor; Two terminals, the first terminal receives the first power voltage, and the second terminal generates the second sub-data signal; a seventh transistor having a first terminal, a second terminal, and a control terminal, wherein the control The second terminal receives a second reset signal, the first terminal is electrically connected to the control terminal of the sixth transistor, and the second terminal receives the first power supply voltage; an eighth transistor has a first terminal, A second terminal and a control terminal, wherein the control terminal receives the second reset signal, the first terminal receives the bias voltage, and the second terminal is electrically connected to the second terminal of the sixth transistor ; And a second capacitor having a first end and a first End, wherein the first end is electrically connected to the control terminal of the sixth transistor, the second terminal receiving the second supply voltage. The display according to item 5 of the scope of patent application, wherein a pulse width of the first gate pulse wave and the second gate pulse wave is the same as a period of the clock signal. A display device includes: a data driving chip; a gate driving circuit that generates a first gate pulse and a second gate pulse; and a pixel array having an adjacent first pixel unit and a second pixel A pixel unit, and the first pixel unit receives the first gate wave, and the second pixel unit receives the second gate wave; wherein in a first period, the data drives the chip to output a first voltage In the first pixel unit, the first gate wave is a first level, and the second gate wave is a second level. In a second period, the data drives the chip to output a first level. Two voltage values in the second pixel unit, the first gate wave is the first level, and the second gate wave is the first level; and in a third period, the data drives the chip A third voltage value is output, the first gate wave is the second level, and the second gate wave is the first level. The display according to item 7 of the scope of patent application, wherein the data driving chip can receive a clock signal, and in the first period, the clock signal is the first level; in the second period, the time The pulse signal is the second level. The display according to item 7 of the scope of patent application, wherein the first pixel unit is charged to the first voltage value during the first period and the second period, and during the second period and the third period, the The second pixel unit is charged to the second voltage value. The display according to item 8 of the scope of patent application, wherein the data driving chip includes: a data driving circuit that generates a first data signal; and a data distribution circuit including: a first conversion circuit including: a first The transistor has a control terminal, a first terminal, and a second terminal, and the control terminal receives the clock signal, and the first terminal receives the first data signal; a second transistor has a control terminal, A first terminal and a second terminal, and the control terminal is connected to the second terminal of the first transistor, the first terminal receives a first power voltage, and the second terminal generates the first voltage value; and A first capacitor having a first terminal and a second terminal, the first terminal being connected to the control terminal of the second transistor, the second terminal receiving a second power supply voltage; and a second conversion circuit Including: a third transistor having a control terminal, a first terminal and a second terminal, and the control terminal receives A clock signal, the first terminal receives the first data signal; a fourth transistor having a control terminal, a first terminal and a second terminal, and the control terminal is connected to the first transistor of the third transistor; Two terminals, the first terminal receives the first power voltage, the second terminal generates the second voltage value; and a second capacitor having a first terminal and a second terminal, and the first terminal is connected to the The control terminal of the fourth transistor, and the second terminal receives the second power voltage.