TW201830334A - Diagnostic methods for the classifiers and the defects captured by optical tools - Google Patents
Diagnostic methods for the classifiers and the defects captured by optical tools Download PDFInfo
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Abstract
Description
本發明係關於缺陷偵測。The invention relates to defect detection.
半導體製造業之演進對良率管理及特定言之計量及檢驗系統提出更高要求。臨界尺寸在縮小而晶圓大小在增大。經濟性在驅動業界縮短達成高良率、高價值生產之時間。因此,最小化從偵測到一良率問題至解決它之總時間判定半導體製造商之投資報酬。 製造諸如邏輯及記憶體裝置之半導體裝置通常包含使用較大數目個製造程序處理一半導體晶圓以形成半導體裝置之各種特徵及多個層級。例如,微影係涉及將一圖案自一倍縮光罩轉印至配置於一半導體晶圓上之一光阻之一半導體製造程序。半導體製造程序之額外實例包含但不限於化學機械拋光(CMP)、蝕刻、沈積及離子植入。可在一單一半導體晶圓上之一配置中製造多個半導體裝置,且接著將其等分離成個別半導體裝置。 可使用演算法來偵測一晶圓上之缺陷。當使用機器學習演算法來產生缺陷分類器及妨害過濾器時,演算法傾向於被視為並未經調諧或診斷之黑箱解決方案。一檢驗配方之評估通常等待直至觀察到針對評估接收之一組新的標註資料或替代地不使用標註資料之一些部分且保留其用於驗證。此等技術之兩者皆浪費資源。 當設定一檢驗配方時,可基於用於訓練分類器之資料之品質及分類器學習且提取來自資料之資訊之能力實現總體效能評估。若資料之品質較差且實際缺陷及妨害並不具有一清晰分離邊界,則任何分類器皆有可能發生故障。 使用兩個量度:辨別力及可靠性來評估各配方之效能。存在許多辨別力量度。一個係訓練資料之混淆矩陣,其由一組狀況誤差率構成。根據此等狀況誤差率,回報率及妨害率可對半導體製造商係重要的。回報率係經正確分類之受關注缺陷(DOI)之數量與晶圓中之DOI之總數之比。妨害率係經分類為DOI之妨害之數量與分類為DOI之缺陷之總數之比。一較高之回報率及一較低之妨害率意味著一較佳之配方。然而,僅可在之前針對包含實際資料標誌之訓練資料集評估妨害率及回報率。 可靠性係展示分類器對其做出之決策有多確定之一量度。其為由分類器實現之後驗估計之一函數。之前,透過各缺陷之可信度計算評估分類器可靠性。 雖然辨別力及可靠性可為重要量度,但辨別力及可靠性可在DOI及妨害之下層分佈具有特定特性時掩蓋現實。此可稱為一遮蔽效應。 通常用於寬頻帶電漿(BBP)及雷射掃描(LS)工具上之分類器評估之方法係基於用於量測辨別力之訓練集之混淆矩陣及計算用於量測可靠性之可信度直方圖。如在圖1(a)中可見,僅基於訓練資料量測辨別力,若使用任何特殊取樣方法,則訓練資料偏差。可信度直方圖已經用於量測可靠性。對一使用者可不存在關於DOI之可靠性或使用此技術之妨害分類之資訊。 使用訓練集之混淆矩陣通常不足以理解整個晶圓上之配方之性質。若已經以特定方式(通常實現此以便減少用於掃描電子顯微鏡(SEM)檢視及手動分類之缺陷之數量)選擇訓練集中之缺陷,則訓練集之混淆矩陣偏向該等缺陷且並非整個晶圓上之分類器效能之一良好估計器。 先前解決方案基於在程序監測(生產取樣)期間獲得之手動分類重新訓練一二進位分類器(例如,妨害對比DOI)。此等先前解決方案使用經更新之分類器來產生對後續晶圓之新的DOI/妨害分離且使用新的儲格來產生生產樣本,其繼而用於調諧下一分類器。50%之先前解決方案之樣本係自最近分類器之DOI儲格隨機取樣,且其他50%為自整個群集隨機取樣。兩個樣本用於比較兩個檢驗之統計程序控制(SPC),且第二樣本亦提供「次臨限」缺陷以用於重新訓練分類器。 用於處理程序/晶圓變化之另一先前方法依賴於從頭開始建立分類器且藉助於SEM自動缺陷分類(ADC)反覆建立訓練集,且接著自新產生之DOI儲格產生生產樣本。然而,對在各晶圓上從頭開始建立一分類器之需要在SEM工具時間方面具有較高成本。另外,用於訓練BBP模型之認定實況係基於不具有人類驗證之SEM ADC,此潛在地使認定實況較不可靠。最後,此方法並不對利用自先前晶圓之缺陷,且因此,在訓練程序期間增加資料不足及不穩定之風險。 在無額外取樣的情況下,先前技術找不到整個晶圓上之回報率及妨害率(及針對未標註資料)之估計。因此,使用者不知道如何調諧配方可影響總體效能。先前技術亦不識別遮蔽效應。因此,需要一新的缺陷偵測技術及系統。The evolution of the semiconductor manufacturing industry places higher demands on yield management and, in particular, measurement and inspection systems. Critical dimensions are shrinking and wafer sizes are increasing. Economy is driving the industry to shorten the time to achieve high yield and high value production. Therefore, minimizing the total time from detecting a yield problem to resolving it determines the return on investment for a semiconductor manufacturer. Manufacturing semiconductor devices such as logic and memory devices typically involves processing a semiconductor wafer using a larger number of manufacturing processes to form the various features and multiple levels of a semiconductor device. For example, lithography involves transferring a pattern from a reticle to a semiconductor manufacturing process that is a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices can be manufactured in one configuration on a single semiconductor wafer and then separated into individual semiconductor devices. Algorithms can be used to detect defects on a wafer. When machine learning algorithms are used to generate defect classifiers and nuisance filters, algorithms tend to be viewed as black box solutions that have not been tuned or diagnosed. The evaluation of an inspection formula usually waits until it is observed that a new set of labeled data is received for the evaluation or instead some parts of the labeled data are not used and retained for verification. Both of these technologies are a waste of resources. When setting a test recipe, the overall performance evaluation can be achieved based on the quality of the data used to train the classifier and the ability of the classifier to learn and extract information from the data. If the quality of the data is poor and the actual defects and obstructions do not have a clear separation boundary, any classifier may fail. Two measures are used: discriminative power and reliability to evaluate the effectiveness of each formulation. There are many discriminative powers. A confusion matrix for training data, which consists of a set of conditional error rates. Based on these conditions, the error rate, the rate of return, and the rate of interference can be important to the semiconductor manufacturer. The rate of return is the ratio of the number of properly classified defects of interest (DOI) to the total number of DOIs in the wafer. The obstruction rate is the ratio of the number of obstructions classified as DOI to the total number of defects classified as DOI. A higher return rate and a lower nuisance rate mean a better formula. However, the obstruction rate and return rate can only be evaluated on training data sets containing actual data markers before. Reliability is a measure of how deterministic the classifier is in making decisions. It is a function of the posterior estimation implemented by the classifier. Previously, the reliability of the classifier was evaluated through the credibility calculation of each defect. Although discrimination and reliability can be important measures, discrimination and reliability can obscure reality when DOI and the underlying distribution have specific characteristics. This can be called a shadowing effect. The methods commonly used for classifier evaluation on Broadband Plasma (BBP) and Laser Scanning (LS) tools are based on the confusion matrix of the training set used to measure discriminative power and calculate the reliability of measurement Histogram. As can be seen in Figure 1 (a), the discriminative power is measured based on the training data only. If any special sampling method is used, the training data is biased. Credibility histograms have been used to measure reliability. There may be no information about the reliability of a DOI or a nuisance classification using this technology for a user. Using the confusion matrix of the training set is often insufficient to understand the nature of the recipe on the entire wafer. If defects in the training set have been selected in a specific way (usually achieved to reduce the number of defects used for scanning electron microscope (SEM) inspection and manual classification), the confusion matrix of the training set is biased toward those defects and not on the entire wafer One of the good estimators of classifier performance. Previous solutions retrained a binary classifier based on manual classification obtained during program monitoring (production sampling) (eg, obstruction vs. DOI). These previous solutions use updated classifiers to generate new DOI / obstruction separations for subsequent wafers and use new cells to generate production samples, which are then used to tune the next classifier. 50% of the previous solution samples were randomly sampled from the DOI bins of the nearest classifier, and the other 50% were randomly sampled from the entire cluster. Two samples are used to compare the statistical procedure control (SPC) of the two tests, and the second sample also provides a "subthreshold" defect for retraining the classifier. Another previous method for handling program / wafer changes relied on building a classifier from scratch and iteratively building a training set with the help of SEM automatic defect classification (ADC), and then producing production samples from the newly generated DOI bin. However, the need to build a classifier from scratch on each wafer has a high cost in terms of SEM tool time. In addition, the asserted facts used to train the BBP model are based on SEM ADCs without human verification, which potentially makes the asserted facts less reliable. Finally, this method does not take advantage of defects from previous wafers, and therefore increases the risk of insufficient data and instability during the training process. Without additional sampling, prior art could not find estimates of returns and obstructions (and for unlabeled data) across the wafer. As a result, users do not know how to tune the recipe can affect overall performance. The prior art also does not recognize shadowing effects. Therefore, a new defect detection technology and system are needed.
在一第一實施例中,提供一種用於偵測複數個晶圓中之受關注缺陷之系統。該系統包括:一中心儲存媒體,其經組態以儲存複數個經分類檢驗結果及一初始缺陷分類器;一晶圓檢驗工具;一影像資料獲取系統;及一處理器,其與該中心儲存媒體、該晶圓檢驗工具及該影像資料獲取系統電子通信。該處理器經組態以執行一檢驗引擎、一取樣引擎及一調諧引擎之指令。該檢驗引擎指示該處理器自該晶圓檢驗工具接收一第一晶圓之檢驗結果。該取樣引擎指示該處理器:自該中心儲存媒體擷取該初始缺陷分類器;基於該初始缺陷分類器過濾該等檢驗結果;基於該等經過濾檢驗結果自該影像資料獲取系統檢視該第一晶圓上之受關注位置;基於該初始缺陷分類器對該等經過濾檢驗結果進行分類;將該等經分類之經過濾檢驗結果儲存於該中心儲存媒體中;及基於該等經分類之經過濾檢驗結果識別該第一晶圓中之受關注缺陷。該調諧引擎指示該處理器基於儲存於該中心儲存媒體中之該等經分類之經過濾檢驗結果更新該初始缺陷分類器。針對各剩餘晶圓,該檢驗引擎指示該處理器自該晶圓檢驗工具接收一下一晶圓之檢驗結果。針對各剩餘晶圓,該取樣引擎指示該處理器:基於該初始缺陷分類器過濾該下一晶圓之該等檢驗結果;基於該下一晶圓之該等經過濾檢驗結果及歷史分析取樣使用該影像資料獲取系統檢視該下一晶圓上之受關注位置;基於該下一晶圓上之該等經檢視受關注位置對該下一晶圓之該等經過濾檢驗結果進行分類;將該下一晶圓之該等經分類之經過濾檢驗結果儲存於該中心儲存媒體中;基於儲存於該中心儲存媒體中之該下一晶圓之該等經分類之經過濾檢驗結果使用該處理器更新該缺陷分類器;及基於該下一晶圓之該等經分類之經過濾檢驗結果識別該下一晶圓中之受關注缺陷。 針對該等剩餘晶圓之各者,該調諧引擎可指示該處理器以基於儲存於該中心儲存媒體中之該下一晶圓之該等經分類之經過濾檢驗結果使用該處理器更新該缺陷分類器。該取樣引擎可指示該處理器基於該經更新缺陷分類器執行該過濾步驟。 該影像資料獲取系統可為一SEM檢視工具。 該晶圓檢驗工具可執行一熱掃描儀捕捉檢驗結果。例如,該晶圓檢驗工具可為一寬頻帶電漿檢驗工具。 該缺陷分類器可發送受關注缺陷資料及妨害資料以用於重新訓練該缺陷分類器。 識別受關注缺陷之該步驟可包括:接近一最近缺陷分類器之一分類邊界取樣;基於該缺陷分類器中之波動獲得關於分類器穩定性之資訊;觀察該分類邊界中之一移動;及基於該分類邊界中之預測移動識別該等受關注缺陷。 該等檢驗結果或經檢視之受關注位置可經儲存於該中心儲存媒體中。 在一第二實施例中,提供一種用於識別複數個晶圓中之受關注缺陷之方法。該方法包括在一處理器處自一晶圓檢驗工具接收一第一晶圓之檢驗結果。使用該處理器基於一初始缺陷分類器過濾該等檢驗結果。基於該等經過濾檢驗結果使用一影像資料獲取系統檢視該第一晶圓上之受關注位置。基於該第一晶圓上之該等經檢視之受關注位置使用該處理器對該等經過濾檢驗結果進行分類。該等經分類之經過濾檢驗結果經儲存於一中心儲存媒體中。基於該等經分類之經過濾檢驗結果識別該第一晶圓中之受關注缺陷。針對各剩餘晶圓,該方法包括在該處理器處自該晶圓檢驗工具接收一下一晶圓之檢驗結果。使用該處理器基於該初始缺陷分類器過濾該等檢驗結果。基於該下一晶圓之該等經過濾檢驗結果及歷史分析取樣使用該影像資料獲取系統檢視該下一晶圓上之受關注位置。基於該下一晶圓上之該等經檢視之受關注位置使用該處理器對該下一晶圓之該等經過濾檢驗結果進行分類。該下一晶圓之該等經分類之經過濾檢驗結果經儲存於該中心儲存媒體中。基於儲存於該中心儲存媒體中之該下一晶圓之該等經分類之經過濾檢驗結果使用該處理器更新該缺陷分類器。基於該下一晶圓之該等經分類之經過濾檢驗結果識別該下一晶圓中之受關注缺陷。 該影像資料獲取系統可為一SEM檢視工具。 該晶圓檢驗工具可執行一熱掃描儀捕捉檢驗結果。例如,該晶圓檢驗工具可為一寬頻帶電漿檢驗工具。 該缺陷分類器可發送受關注缺陷資料及妨害資料以用於重新訓練該缺陷分類器。 識別受關注缺陷之該步驟可包括:接近一最近缺陷分類器之一分類邊界取樣;基於該缺陷分類器中之波動獲得關於分類器穩定性之資訊;觀察該分類邊界中之一移動;及基於該分類邊界中之預測移動識別該等受關注缺陷。 針對該等剩餘晶圓之各者,該方法可包括基於儲存於該中心儲存媒體中之該下一晶圓之該等經分類之經過濾檢驗結果使用該處理器更新該缺陷分類器。可基於該經更新缺陷分類器執行該過濾步驟。 該等檢驗結果或經檢視之受關注位置可經儲存於該中心儲存媒體中。 基於儲存於該中心儲存媒體中之該等經分類之經過濾檢驗結果器更新該缺陷分類器之該步驟可包括:基於一經計算訓練混淆矩陣估計一回報率且基於該中心儲存媒體中之該缺陷分類器、該下一晶圓之該等經分類之經過濾檢驗結果及該經估計回報率估計一妨害率。該經計算訓練混淆矩陣係基於儲存於該中心儲存媒體中之該下一晶圓之該等經分類之經過濾檢驗結果。 該等經過濾檢驗結果可具有與該等經過濾檢驗結果相關聯之至少兩個臨限值。該至少兩個臨限值之一第一者係針對用於監測程序及缺陷之一檢驗。該至少兩個臨限值之一第二者小於該第一臨限值且經組態以在檢驗期間捕捉次臨限缺陷。In a first embodiment, a system for detecting a defect of interest in a plurality of wafers is provided. The system includes: a central storage medium configured to store a plurality of classified inspection results and an initial defect classifier; a wafer inspection tool; an image data acquisition system; and a processor, which is stored with the central storage The media, the wafer inspection tool, and the image data acquisition system are in electronic communication. The processor is configured to execute instructions of a inspection engine, a sampling engine, and a tuning engine. The inspection engine instructs the processor to receive an inspection result of a first wafer from the wafer inspection tool. The sampling engine instructs the processor: retrieve the initial defect classifier from the central storage medium; filter the inspection results based on the initial defect classifier; and review the first from the image data acquisition system based on the filtered inspection results The location of interest on the wafer; classifying the filtered inspection results based on the initial defect classifier; storing the classified filtered inspection results in the central storage medium; and based on the classified experiences The filtering inspection results identify the defects of interest in the first wafer. The tuning engine instructs the processor to update the initial defect classifier based on the classified filtered inspection results stored in the central storage medium. For each remaining wafer, the inspection engine instructs the processor to receive the next wafer inspection result from the wafer inspection tool. For each remaining wafer, the sampling engine instructs the processor: to filter the inspection results of the next wafer based on the initial defect classifier; based on the filtered inspection results and historical analysis sampling of the next wafer to use The image data acquisition system inspects the position of interest on the next wafer; classifies the filtered inspection results of the next wafer based on the inspected positions of interest on the next wafer; The classified filtered inspection results of the next wafer are stored in the central storage medium; based on the classified filtered inspection results of the next wafer stored in the central storage medium, the processor is used Update the defect classifier; and identify the defect of interest in the next wafer based on the classified filtered inspection results of the next wafer. For each of the remaining wafers, the tuning engine may instruct the processor to update the defect with the processor based on the classified filtered inspection results of the next wafer stored in the central storage medium Classifier. The sampling engine may instruct the processor to perform the filtering step based on the updated defect classifier. The image data acquisition system can be a SEM inspection tool. The wafer inspection tool can perform a thermal scanner to capture inspection results. For example, the wafer inspection tool may be a wideband plasma inspection tool. The defect classifier can send the concerned defect data and obstruction data for retraining the defect classifier. The step of identifying a defect of interest may include: approaching classification boundary sampling of one of the nearest defect classifiers; obtaining information about classifier stability based on fluctuations in the defect classifier; observing movement of one of the classification boundaries; The predicted movement in the classification boundary identifies the defects of interest. The inspection results or inspected locations of interest may be stored in the central storage medium. In a second embodiment, a method for identifying a defect of interest in a plurality of wafers is provided. The method includes receiving a first wafer inspection result from a wafer inspection tool at a processor. The processor is used to filter the inspection results based on an initial defect classifier. Based on the filtered inspection results, an image data acquisition system is used to view the location of interest on the first wafer. The processor is used to classify the filtered inspection results based on the inspected locations of interest on the first wafer. The classified filtered inspection results are stored in a central storage medium. A defect of interest in the first wafer is identified based on the classified filtered inspection results. For each remaining wafer, the method includes receiving the next wafer inspection result from the wafer inspection tool at the processor. The processor is used to filter the inspection results based on the initial defect classifier. Based on the filtered inspection results and historical analysis samples of the next wafer, the image data acquisition system is used to view the location of interest on the next wafer. The processor is used to classify the filtered inspection results of the next wafer based on the reviewed locations of interest on the next wafer. The sorted filtered inspection results of the next wafer are stored in the central storage medium. The processor is used to update the defect classifier based on the classified filtered inspection results of the next wafer stored in the central storage medium. A defect of interest in the next wafer is identified based on the classified filtered inspection results of the next wafer. The image data acquisition system can be a SEM inspection tool. The wafer inspection tool can perform a thermal scanner to capture inspection results. For example, the wafer inspection tool may be a wideband plasma inspection tool. The defect classifier can send the concerned defect data and obstruction data for retraining the defect classifier. The step of identifying a defect of interest may include: approaching classification boundary sampling of one of the nearest defect classifiers; obtaining information about classifier stability based on fluctuations in the defect classifier; observing movement of one of the classification boundaries; and based on The predicted movement in the classification boundary identifies the defects of interest. For each of the remaining wafers, the method may include updating the defect classifier using the processor based on the classified filtered inspection results of the next wafer stored in the central storage medium. The filtering step may be performed based on the updated defect classifier. The inspection results or inspected locations of interest may be stored in the central storage medium. The step of updating the defect classifier based on the classified filtered inspection result devices stored in the central storage medium may include: estimating a rate of return based on a calculated training confusion matrix and based on the defect in the central storage medium The classifier, the classified filtered inspection results of the next wafer, and the estimated rate of return estimate an obstruction rate. The calculated training confusion matrix is based on the classified filtered inspection results of the next wafer stored in the central storage medium. The filtered inspection results may have at least two threshold values associated with the filtered inspection results. One of the at least two thresholds is directed to an inspection procedure and an inspection of defects. A second one of the at least two thresholds is less than the first threshold and is configured to capture secondary threshold defects during inspection.
相關申請案之交叉參考 本申請案主張2017年1月10日申請之美國臨時申請案第62/444,694號、2017年3月22日申請之美國臨時申請案第62/475,030號及2017年11月3日申請之美國臨時申請案第62/581,378號之優先權,該等案之揭示內容以引用的方式併入本文中。 儘管將依據特定實施例描述所主張之標的,然其他實施例(包含未提供本文中闡述之全部優點及特徵之實施例)亦在本發明之範疇內。可在不脫離本發明之範疇之情況下進行各種結構、邏輯、程序步驟及電子改變。因此,僅參考隨附申請專利範圍定義本發明之範疇。 本文揭示之實施例解決用於在一積體電路製造程序之早期階段中處理程序及晶圓不穩定性質新的系統及方法。本發明之一項實施例係基於除生產取樣外在生產批次上產生一小樣本,彙總若干晶圓上方之樣本亦建立一最新分類器及使用分類器來在下一晶圓上產生新更新之樣本之理念。 本文揭示之實施例可至少出於下列原因尤其比現有方法更有利。當前揭示之系統及方法利用使用最近已知之程序狀況產生且良好適用於返回一優越分類器之一增補(擴充)樣本。最近已知之程序狀況及缺陷遠比當前使用之隨機樣本更有用於此目的。 最近已知之程序狀況亦係程序改變之一優越指示,且任何新的缺陷或展示最大變化之缺陷將在樣本中有效顯露。換言之,具有一小樣本大小之一有效增量發現導致較小之額外SEM檢視及分類成本。 此外,憑藉對程序不穩定性之額外監測,以及當前揭示之系統及方法量化該程序不穩定性之能力,增補樣本可經自動調諧以匹配該等程序狀況。 一般言之,所揭示之系統及方法容許具有更穩定妨害率及DOI捕捉率之更相關之寬頻帶電漿檢驗。所揭示之系統及方法容許較快發現在製造程序期間發生之新出現之缺陷,且容許製造程序之穩定性之一分析。 存在實施當前揭示之系統及方法之若干方式。一項實施例僅依賴於來自中心儲存媒體之資料,然後系統及方法在檢驗之剩餘部分利用分類器效能中對缺陷之手動分類。此等實施例使分類器比當前正檢驗之晶圓落後之一個晶圓。另一實施例增添藉由在晶圓缺陷檢視工具執行取樣且接著在中心儲存媒體上產生增補樣本而對當前晶圓更新分類器之能力。此實施例之一個優勢在於最近晶圓狀況亦包含於分類器中。 可針對其中實際標誌不可用之資料估計回報率及妨害率。因此,可提供回報率及妨害率之預期值。技術展示回報率、妨害率、後驗及可信度之所有估計係精確的或資料具有陰影分佈。由演算法產生之資料(除分類外)可提供無法使用手動產生之分類器(諸如線上缺陷組合器(iDO))獲得之診斷資訊。iDO係可在檢驗期間對缺陷進行即時分類之一演算法之一實例。 可評估一配方。此等方法包含回報率之估計;妨害率之估計;評估可展示回報率對比妨害率之受試者操作曲線(ROC)以用於精細調諧配方;及偵測遮蔽效應,此判定後驗、可信度、回報率及妨害率之估計是否係值得信賴的。ROC可為繪製真陽性率對比假陽性率之一曲線。替代ROC或與之協作,可使用DOI回報率(真陽性率)對比妨害率(其非假陽性率)。 來自分類器之兩個輸出可用於建立診斷工具。首先,可使用係由分類器提供之分類結果之決策。其次,可使用各缺陷之後驗。存在一分類器可找到後驗之不同方式。與各類別形心之距離或精確度之概率量測係兩個實例。 為估計回報率,可使用經正確分類之DOI之數量與訓練集中之DOI之總數之比。此可應用於測試集以找到測試資料中可能丟失之DOI之數量之估計。假定存在兩個類別(DOI及妨害),混淆矩陣如在表1中展示般出現。 表1
100‧‧‧方法100‧‧‧ Method
101‧‧‧步驟101‧‧‧ steps
102‧‧‧步驟102‧‧‧step
103‧‧‧步驟103‧‧‧step
104‧‧‧步驟104‧‧‧step
105‧‧‧步驟105‧‧‧ steps
106‧‧‧步驟106‧‧‧ steps
107‧‧‧步驟107‧‧‧ steps
108‧‧‧步驟108‧‧‧ steps
109‧‧‧步驟109‧‧‧step
110‧‧‧步驟110‧‧‧step
111‧‧‧步驟111‧‧‧ steps
112‧‧‧步驟112‧‧‧step
113‧‧‧步驟113‧‧‧step
200‧‧‧系統200‧‧‧ system
201‧‧‧晶圓檢驗工具201‧‧‧ Wafer Inspection Tools
202‧‧‧處理器202‧‧‧Processor
203‧‧‧中心儲存媒體203‧‧‧Center Storage Media
204‧‧‧影像資料獲取系統204‧‧‧Image data acquisition system
為更完全理解對本發明之性質及目的,應參考結合附圖進行之以下實施方式,其中: 圖1包含先前技術之流程圖(a)及(b); 圖2分別包含一回報率對比切割線曲線之圖表(a)、一妨害率對比切割線曲線之圖表(b)及一回報率對比妨害率曲線之圖表(c); 圖3包含分佈(a)、(b)及(c); 圖4包含分佈(a)及(b); 圖5係根據本發明之一陰影偵測演算法之一實施例之一流程圖; 圖6包含針對一一般晶圓(a)及一經遮蔽晶圓(b)之精確度對比集區中之缺陷之數量之圖表; 圖7係根據本發明之一診斷模型之一實施例之一流程圖; 圖8係根據本發明之一實施例之一流程圖; 圖9係根據本發明之一系統之一方塊圖; 圖10係根據本發明之具有動態取樣及穩定性分析之一動態分類器之一圖;及 圖11係根據本發明之具有動態取樣及穩定性分析之一靜態分類器之一圖。For a more complete understanding of the nature and purpose of the present invention, reference should be made to the following implementations in conjunction with the drawings, where: Figure 1 contains the prior art flowcharts (a) and (b); Figure 2 contains a return versus cutting line, respectively Graph (a) of the curve, graph (b) of a nuisance ratio versus cutting line curve, and (c) of a ROI curve (c); Figure 3 contains distributions (a), (b), and (c); 4 includes distributions (a) and (b); Figure 5 is a flowchart of an embodiment of a shadow detection algorithm according to the present invention; Figure 6 includes a general wafer (a) and a masked wafer ( b) a graph of accuracy versus the number of defects in the pool; Figure 7 is a flowchart of an embodiment of a diagnostic model according to the present invention; Figure 8 is a flowchart of an embodiment of the present invention; FIG. 9 is a block diagram of a system according to the present invention; FIG. 10 is a diagram of a dynamic classifier with dynamic sampling and stability analysis according to the present invention; and FIG. 11 is a diagram of dynamic sampling and stability according to the present invention. A graph of static classifiers for sexual analysis.
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