TW201739207A - Device and method for recovering clock and data - Google Patents

Abstract

A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which the phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and at least one second clock signal according to the adjustment signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Description

Clock data recovery device and method

This case is related to an integrated circuit, and in particular to the clock data recovery device and method.

Due to the rapid development of process technology, the operating speed of the integrated circuit has been greatly improved. In high-speed transmission communication systems, Clock and Data Recovery (CDR) devices are often used to ensure that the received input data is properly read.

In the prior art, a clock data recovery device using a phase-picking architecture is implemented by a feed forward circuit. If there is a frequency error between the transmission and reception clock signals, the clock data recovery device using the feedforward operation cannot instantaneously eliminate the frequency error, and thus leads to an error in the read data.

In order to solve the above problems, one aspect of the present disclosure is to provide a clock data recovery device. The clock data recovery device includes a data sampling module, a phase detecting circuit, a frequency estimator, a clock generation module, and a resource Material recovery module. The data sampling module is configured to sample the input data according to the plurality of first clock signals to generate a plurality of data values, wherein the phases of the plurality of first clock signals are different from each other. The phase detecting circuit is configured to detect a phase error in the input data according to the at least one second clock signal to generate an error signal. The frequency estimator is configured to generate an adjustment signal based on the error signal, the phase threshold, and the frequency threshold. The clock generation module is configured to generate a plurality of first clock signals and at least one second clock signal according to the adjustment signal and the reference clock signal. The data recovery module is configured to generate a response data corresponding to the input data according to the plurality of data values.

In some embodiments, the frequency estimator includes a first delta-sigma modulator, a second delta-sigma modulator, an integrator, a counter, and an adder. The first triangular integral modulator generates a phase integrated value for accumulating the error signal, and outputs a first control signal when the phase integrated value is higher than the phase threshold. The second triangular integral modulator is configured to accumulate the error signal to generate a frequency integrated value, and output a second control signal when the frequency integrated value is higher than the frequency threshold. The integrator is configured to accumulate the second control signal to generate an integrated signal. The counter is used to count according to the integrated signal to generate a third control signal. The adder is configured to add the first control signal and the third control signal to generate an adjustment signal.

In some embodiments, the data recovery module includes a data storage circuit, an edge detection circuit, and a data selection circuit. The data storage circuit is configured to store the plurality of data values. The edge detection circuit is configured to determine at least one transition point of the input data according to the plurality of data values to generate the selection signal. The data selection circuit is configured to select at least one of the plurality of data values from the data storage circuit according to the selection signal to generate the reply data.

In some embodiments, the data storage circuit is more local based The pulse signal synchronizes multiple data values.

In some embodiments, the clock generation module includes a multi-phase clock generator and a phase interpolator. The multi-phase clock generator is configured to generate a plurality of first clock signals and at least one second clock signal according to the local clock signal. The phase interpolator is configured to generate a local clock signal according to the adjustment signal and the reference clock signal.

Another aspect of the present disclosure is to provide a clock data recovery method, including the following operations: sampling input data according to a plurality of first clock signals to generate a plurality of data values, wherein the plurality of first The phases of the clock signals are different from each other; the phase error in the input data is detected according to the at least one second clock signal to generate an error signal; the adjustment signal is generated according to the error signal, the phase threshold value and the frequency threshold value; according to the adjustment signal and the reference The clock signal generates a plurality of first clock signals and at least one second clock signal; and generating response data corresponding to the input data according to the plurality of data values.

In some embodiments, the generating the adjustment signal comprises: accumulating the error signal via the first delta-sigma modulator to generate a phase integrated value, and outputting the first control signal when the phase integrated value is higher than the phase threshold; The triangular integral modulator cumulative error signal generates a frequency integrated value, and outputs a second control signal when the frequency integrated value is higher than the frequency threshold; accumulates the second control signal via the integrator to generate an integrated signal; The signal is counted to generate a third control signal; and the first control signal and the third control signal are added via an adder to generate an adjustment signal.

In some embodiments, the act of generating a reply data includes: Storing a plurality of data values; determining at least one transition point of the input data according to the plurality of data values to generate a selection signal; and selecting at least one of the plurality of data values according to the selection signal to generate a reply data.

In some embodiments, the clock data recovery method further comprises: synchronizing the plurality of data values according to the local clock signal.

In some embodiments, the generating the plurality of first clock signals and the at least one second clock signal comprises: generating a plurality of first clock signals and at least one second clock signal according to the local clock signal; The phase interpolator generates a local clock signal based on the adjustment signal and the reference clock signal.

100‧‧‧clock data recovery device

110‧‧‧ data sampling module

120‧‧‧ phase detection circuit

130‧‧‧frequency estimator

140‧‧‧clock generation module

150‧‧‧ Data Recovery Module

Din‧‧‧ Input data

D1‧‧‧ data value

112‧‧‧ data sampler

CLK1, CLK2‧‧‧ clock signal

VE‧‧‧ error signal

UP/DOWN‧‧‧Adjustment signal

CLKREF‧‧‧ reference clock signal

142‧‧‧ phase interpolator

CLKL‧‧‧ local clock signal

144‧‧‧Multi-phase clock generator

152‧‧‧Data storage circuit

Dout‧‧‧Reply information

156‧‧‧ data selection circuit

154‧‧‧Edge detection circuit

TS1, TS2‧‧‧ sampling time point

SE‧‧‧Selection signal

232‧‧‧Triangle integral modulator

231‧‧‧Triangle integral modulator

234‧‧‧ counter

233‧‧‧ integrator

AP‧‧‧ phase cumulative value

235‧‧‧Adder

VCP, VCF, VCT‧‧‧ control signals

MP‧‧‧ phase threshold

MF‧‧‧ frequency threshold

AF‧‧‧ frequency cumulative value

400‧‧‧ Clock data method

VI‧‧·Integral signal

S410~S450‧‧‧Steps

P1, P2, P3‧‧‧ phase

The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. Schematic diagram of the pulse data recovery device; FIG. 1B is a schematic diagram of a sampling operation of the clock data recovery device in FIG. 1A and a sampling operation of the related art according to some embodiments of the present disclosure; Some embodiments in the present disclosure are shown in the circuit diagram of the frequency estimator in FIG. 1A; FIG. 3 is a schematic diagram of the edge detection circuit in FIG. 1A according to some embodiments of the disclosure. FIG. 4 is a flow chart of a clock data recovery method according to some embodiments of the present disclosure.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

The terms "first", "second", etc., used herein are not intended to refer to the order or order, nor are they intended to limit the invention, only to distinguish between elements or operations described in the same technical terms. Only.

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

Please refer to FIG. 1A. FIG. 1A is a schematic diagram of a clock data recovery device 100 according to some embodiments of the present disclosure. For example, the clock data recovery device 100 includes a data sampling module 110, a phase detection circuit 120, a frequency estimator 130, a clock generation module 140, and a data recovery module 150.

The data sampling module 110 is configured to receive the input data Din and sample the input data Din according to the plurality of clock signals CLK1 to generate a plurality of data values D1. In some embodiments, the data sampling module 110 includes a plurality of materials. Sampler 112. The plurality of data samplers 112 are configured to receive the input data Din and are coupled to the clock generation module 140 to receive the plurality of clock signals CLK1, wherein the phases of the plurality of clock signals CLK1 are different from each other. With this arrangement, the plurality of data samplers 112 can sample the input data Din at different time points according to different clock signals CLK1 to generate the plurality of data values D1 described above. In some embodiments, the data sampler 112 can be implemented by an amplifier and a switched capacitor circuit, but the disclosure is not limited thereto.

The phase detecting circuit 120 is configured to receive the input data Din and detect the phase error of the input data Din according to the at least one clock signal CLK2 to generate the error signal VE. In some embodiments, the phase detecting circuit 120 can include two data samplers (not shown) and a phase detector (not shown). The two data samplers can sample the input data Din according to the two clock signals CLK2, and output the sampled two data values (not shown) to the phase detector. Accordingly, the phase detector can compare the two data values to generate an error signal VE. In some embodiments, the aforementioned two clock signals CLK2 have a phase difference of 90 degrees, and the two data values sampled above are in-phase data values and quadrature data values. . In some embodiments, the aforementioned phase detector is a bang-bang phase detector.

The manner of setting the phase detecting circuit 120 is merely an example, and the disclosure is not limited thereto. Various types of phase detection circuits 120 are also within the scope of the disclosure. For example, in other embodiments, phase detection circuit 120 includes a Hogge phase detector. In still other embodiments, the phase detection circuit 120 includes a Muller-Muller phase detector.

The frequency estimator 130 is coupled to the phase detector 120 to receive the error signal VE. The frequency estimator 130 is configured to generate an adjustment signal UP/DOWN to the clock generation module according to the error signal VE, the phase threshold (such as MP in FIG. 2), and the frequency threshold (such as MF in FIG. 2). 140.

The clock generation module 140 is coupled to the frequency estimator 130 to receive the adjustment signal UP/DOWN. The clock generation module 140 is configured to generate the foregoing plurality of clock signals CLK1 and at least one clock signal CLK2 according to the adjustment signal UP/DOWN and the reference clock signal CLKREF.

By way of example, in some embodiments, the clock generation module 140 includes a phase interpolator 142 and a multi-phase clock generator 144. The phase interpolator 142 is coupled to the frequency estimator 130 to receive the adjustment signal UP/DOWN, and generates a corresponding local clock signal CLKL according to the adjustment signal UP/DOWN and the reference clock signal CLKREF. For example, assume that the current local clock signal CLKL has a first phase. When the state of the adjustment signal UP/DOWN is UP, the phase interpolator 142 can generate the local clock signal CLKL having the second phase, wherein the second phase is ahead of the first phase. Alternatively, when the state of the adjustment signal UP/DOWN is DOWN, the phase interpolator 142 may generate the local clock signal CLKL having the third phase, wherein the third phase lags behind the first phase.

The multi-phase clock generator 144 is coupled to the phase interpolator 142 to receive the local clock signal CLKL. The multi-phase clock generator 144 is coupled to the data sampling module 110 to transmit a plurality of clock signals CLK1. The multi-phase clock generator 144 is coupled to the phase detecting circuit 120 to transmit at least one clock signal CLK2. The multi-phase clock generator 144 is set to be based on the local clock The signal CLKL generates the aforementioned plurality of clock signals CLK1 and at least one clock signal CLK2.

The manner of setting the clock generation module 140 is merely an example, and the disclosure is not limited thereto. Various types of clock generation modules 140 are also within the scope of the disclosure.

The data recovery module 150 is coupled to the data sampling module 110 to receive a plurality of data values D1. The data reply module 150 is configured to select a corresponding data value according to the plurality of data values D1 to generate a reply data Dout corresponding to the input data Din.

For example, in some embodiments, the data recovery module 150 includes a data storage circuit 152, an edge detection circuit 154, and a data selection circuit 156. The data storage circuit 152 is coupled to the plurality of data samplers 112 to receive and store a plurality of data values D1. In some embodiments, data storage circuit 152 is a scratchpad. In other embodiments, since the plurality of data values D1 are obtained according to a plurality of clock signals CLK1 having different phases, the data storage circuit 152 may further synchronize the plurality of data values D1 according to the local clock signal CLKL. And store the synchronized data values D1. The manner of setting the data storage circuit 152 is merely an example, and the disclosure is not limited thereto. Various types of data storage circuits 152 are also within the scope of the disclosure.

In various embodiments, edge detection circuitry 154 may be implemented by digital circuitry that performs various decision algorithms. The edge detection circuit 154 is coupled to the data storage circuit 152 to read a plurality of data values D1 from the data storage circuit 152. The edge detection circuit 154 determines the input according to the state of the plurality of data values D1. At least one transition point of the incoming data Din (eg, switching from a logic 1 to a falling edge of a logic 0, or a logic 0 to a rising edge of a logic 1) to generate a selection signal SE. In this manner, the data recovery module 150 can determine the relationship between the central data value and the boundary data value in the plurality of bit intervals of the plurality of data values D1 and the input data Din. For ease of understanding, a detailed description will be described in the third drawing to be described later.

The data selection circuit 156 is coupled to the edge detection circuit 154 to receive the selection signal SE and coupled to the data storage circuit 152 to read the plurality of data values D1. The data selection circuit 156 is configured to select at least one of the plurality of material values D1 according to the selection signal SE. For example, the data selection circuit 156 includes a Tally circuit (not shown), an address generation circuit (not shown), and a multiplexer (not shown). In this example, the selection signal SE is a plurality of bit data that reflects the position of the transition point. The counting circuit can generate a control signal according to the plurality of bit data of the selection signal SE, and the address generation circuit outputs the corresponding address signal according to the control signal. In this way, the plurality of multiplexers can select at least one of the plurality of data values D1 from the data storage circuit 152 according to the address signal, and output the data as the reply data Dout.

The manner of setting the data selection circuit 156 is merely an example, and the disclosure is not limited thereto. Various types of data selection circuits 156 are also within the scope of the disclosure.

Referring to FIG. 1B, FIG. 1B is a schematic diagram of a sampling operation of the clock data recovery device 100 in FIG. 1A and a sampling operation of the related art according to some embodiments of the present disclosure.

In some related technologies, phase selection is adopted. The phase-picking architecture of the clock data recovery device is implemented by a feed forward circuit. If there is a frequency error between the clock signal between the transmitting end and the receiving end, the reply data generated by the clock data recovery device of the related art may have a data error. For example, as shown in FIG. 1B, when a frequency error occurs, since the related art only uses a feedforward circuit structure, the sampling time point TS1 is gradually shifted, and the sampled data value is erroneous.

Compared with the above related art, in the clock data recovery device 100, the phase detection circuit 120, the frequency estimator 130, and the clock generation module 140 are configured as a feedback control mechanism. By means of the feedback control mechanism, when the frequency error of the input data Din is detected, the clock generation module 140 adjusts the local clock signal CLKL accordingly to reduce the influence of the frequency error. As a result, the accuracy of the reply data Dout is improved compared to the related art described above. For example, as shown in FIG. 1B, when a frequency error occurs, the sampling time point TS2 of the data sampling module 110 can be stabilized at a fixed time by the operation of the feedback control mechanism described above, so that the sampled data value is obtained. Can be maintained correctly.

The following paragraphs will present various embodiments to illustrate the functions and applications of the clock data recovery device 100, but the disclosure is not limited to the embodiments listed below.

Referring to FIG. 2, FIG. 2 is a circuit diagram of the frequency estimator 130 as shown in FIG. 1A according to some embodiments of the present disclosure. For ease of understanding, similar elements in Fig. 2 will be assigned the same reference numerals as in Fig. 1A.

In some embodiments, frequency estimator 130 includes a delta-sigma modulator 231, a delta-sigma modulator 232, an integrator 233, a counter 234, and an adder 235.

The triangular integral modulator 231 is coupled to the phase detecting circuit 120 in FIG. 1A to receive the error signal VE. The triangular integral modulator 231 is configured to accumulate the error signal VE to generate a phase integrated value AP, and compare the phase integrated value AP with the phase critical value MP. When the phase integrated value AP is higher than the phase threshold MP, the delta-sigma modulator 231 outputs the control signal VCP.

The triangular integral modulator 232 is coupled to the phase detecting circuit 120 in FIG. 1A to receive the error signal VE. The triangular integral modulator 232 is configured to accumulate the error signal VE to generate a frequency integrated value AF, and compare the frequency integrated value AF with the frequency threshold MF. When the frequency integrated value AF is higher than the frequency threshold MF, the delta-sigma modulator 232 outputs the control signal VCF.

In some embodiments, the phase threshold MP and the frequency threshold MF can be predetermined values. In other embodiments, the phase threshold MP and the frequency threshold MF may be pre-stored in the frequency estimator 130, and the values of the phase threshold MP and the frequency threshold MF may be dynamically adjusted via an external program or circuit.

The integrator 233 is coupled to the delta-sigma modulator 232 to receive the control signal VCF. The integrator 233 is used to accumulate the control signal VCF to generate an integrated signal VI. The counter 234 is coupled to the integrator 233 to receive the integrated signal VI. The counter 234 generates a control signal VCT based on the integrated signal VI. The adder 235 is coupled to the delta-sigma modulator 231 and the counter 234 to receive the control signal VCP and the control signal VCT, and the control signal VCP and the control signal After the VCT is added, the adjustment signal UP/DOWN is generated.

In some embodiments, the control signal VCP, the control signal VCF, the integrated signal VI, and the control signal VCT can be digital signals having multiple bits. When the frequency integrated value AF is higher than the frequency threshold MF, the delta-sigma modulator 232 switches the bit value of the control signal VCF to cause the counter 234 to start counting. Accordingly, the counter 234 generates a different control signal VCT to the adder 235. Alternatively, when the phase integrated value AP is higher than the phase threshold MP, the triangular integral modulator 231 can switch the bit value of the control signal VCP to cause the adder 235 to generate a different adjustment signal UP/DOWN. With the above setting manner, when the frequency error occurs in the input data Din, the clock generation module 140 can adjust the local clock signal CLKL according to the adjustment signal UP/DOWN to improve the accuracy of the reply data Dout.

The manner of setting the frequency estimator 130 is merely an example, and the disclosure is not limited thereto. Various types of frequency estimators 130 are also within the scope of the disclosure.

Referring to FIG. 3, FIG. 3 is a schematic diagram showing the operation of the edge detecting circuit 154 in FIG. 1A according to some embodiments of the present disclosure. For ease of understanding, similar elements in Fig. 3 will be assigned the same reference numerals as in Fig. 1A. For convenience of description, in this example, the data sampling module 110 samples the bit interval of the input data Din by using three clock signals CLK1, wherein the phases of the three clock signals CLK1 are P1, P2, and P3, respectively.

For example, as shown in FIG. 3, the first six data values D1 sequentially sampled by the plurality of data samplers 112 according to the three clock signals CLK1 are “0”, “1”, “1”, “ 1", "0", and "0". In this case, The edge detection circuit 154 can perform a mutual exclusion or operation on each of the two adjacent data values D1 to detect at least one transition point of the input data Din. For example, edge detection circuit 154 includes a plurality of mutually exclusive or gates. The first mutex or gate outputs a signal having a logic 1 based on the first data value D1 ("0") and the second data value D1 ("1"). The second mutex or gate outputs a signal having a logic 0 based on the second data value D1 ("1") and the third data value D1 ("1"). According to the signal of logic 1 of the first mutex or gate output, the input data Din can be determined for the corresponding two sampling times (that is, the clock signal CLK1 having the phase P1 and the clock signal CLK1 having the phase P2). There is a transition point between them. According to the second mutex or gate output signal having logic 0, the input data Din can be determined to be corresponding to the two sampling times (that is, the clock signal CLK1 having the phase P2 and the clock signal CLK1 having the phase P3). There is no transition point between them. And so on, the transition point of the input data Din can be analyzed according to multiple signals output by multiple mutually exclusive or gates.

For example, as shown in FIG. 3, the number of transition points occurring at the corresponding sampling time (ie, between phase P1 and phase P2) is 6, and occurs at other sampling times (ie, phase P2 and phase P3). The number of up-going points is 0. According to this, the edge detecting circuit 154 can analyze the data value D1 sampled according to the clock signal CLK1 having the phase P1 or P2 as the rising or falling edge of the input data Din, and sample according to the clock signal CLK1 having P3. The data value D1 obtained is the central data value of the input data Din. In this way, the edge detection circuit 154 outputs a corresponding selection signal SE, so that the data selection circuit 156 selects at least one of the plurality of data values D1 corresponding to the central data values of the input data Din. In some embodiments, the above is based on the number of transition points. The operation of judging the transition point of the input data Din is a center-picking algorithm. In some embodiments, the above-described operation of determining the number of transition points of the input data Din can be performed by the aforementioned Tally circuit.

In other embodiments, the edge detection circuit 154 can also implement a digital circuit implementation of a majority-voting algorithm. For example, as shown in FIG. 3, the first three data values D1 sequentially sampled by the plurality of data samplers 112 based on the three clock signals CLK1 are "0", "1", "1". Since the number of data values D1 having the logic 1 is large, the edge detecting circuit 154 can determine that the logic 1 is the central data value of the input data Din, and based on this, determine the data value sampled according to the clock signal CLK1 having the phase P1. D1 is the rising or falling edge of the input data Din.

The manner of setting the edge detection circuit 154 is merely an example, and the disclosure is not limited thereto. Various edge detection circuits 154 employing different decision algorithms are also within the scope of the disclosure.

FIG. 4 is a flow diagram of a clock data recovery method 400 in accordance with some embodiments of the present disclosure. For ease of understanding, please refer to FIG. 1A and FIG. 4 together, and the operation of the clock data recovery device 100 will be described together with the clock data recovery method 400.

In step S410, the data sampling module 110 samples the input data Din according to the plurality of clock signals CLK1 to generate a plurality of data values D1. For example, as shown in FIG. 1A, a plurality of data samplers 112 sample the input data Din based on a plurality of clock signals CLK1 of different phases to continuously generate a plurality of data values D1.

In step S420, the phase detecting circuit 120 detects the phase error in the input data Din according to the at least one second clock signal CLK2 to generate the error signal VE. As previously described, the phase detection circuit 120 can analyze the input data Din using various types of phase detectors to generate an error signal VE based on the phase error in the input data Din.

In step S430, the frequency estimator 130 generates an adjustment signal UP/DOWN based on the error signal VE, the phase threshold MP, and the frequency threshold MF. For example, as shown in the previous FIG. 2, the frequency estimator 130 can compare the error signal VE with the phase threshold MP and compare the error signal VE with the frequency threshold MF to generate a corresponding adjustment signal UP/DOWN.

In step S440, the clock generation module 140 generates a plurality of clock signals CLK1 and at least one clock signal CLK2 according to the adjustment signal UP/DOWN and the reference clock signal CLKREF. As previously described, phase detection circuit 120, frequency estimator 130, and clock generation module 140 are configured as feedback mechanisms. Equivalently, the clock generation module 140 can dynamically adjust the plurality of clock signals CLK1 and the at least one clock signal CLK2 according to the adjustment signal UP/DOWN.

In step S450, the data reply module 150 generates a reply data Dout corresponding to the input data Din according to the plurality of data values D1. For example, as previously described, the edge detection circuit 154 can determine the transition point of the input data Din by executing various decision algorithms to determine which of the plurality of data values D1 is the central data value of the input data Din. The data selection circuit 156 can select at least one of the plurality of data values D1 corresponding to the central data values of the input data Din to generate the reply data Dout.

The plurality of steps of the above-described clock data replying method 400 are merely examples, and are not limited to the sequential execution of the above examples. Various operations under the clock data recovery method 400 may be appropriately added, replaced, omitted, or performed in a different order, without departing from the scope of operation of the embodiments of the present disclosure.

In summary, the clock data recovery device 100 and the clock data recovery method 400 provided in the present invention can eliminate the frequency error on the input data through a feedback mechanism to improve the accuracy of the response data.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present case. Anyone skilled in the art can make various changes and refinements without departing from the spirit and scope of the case. Therefore, the scope of protection of this case is considered. The scope defined in the patent application is subject to change.

100‧‧‧clock data recovery device

110‧‧‧ data sampling module

120‧‧‧ phase detection circuit

130‧‧‧frequency estimator

140‧‧‧clock generation module

150‧‧‧ Data Recovery Module

Din‧‧‧ Input data

D1‧‧‧ data value

112‧‧‧ data sampler

CLK1, CLK2‧‧‧ clock signal

VE‧‧‧ error signal

UP/DOWN‧‧‧Adjustment signal

CLKREF‧‧‧ reference clock signal

142‧‧‧ phase interpolator

144‧‧‧Multi-phase clock generator

CLKL‧‧‧ local clock signal

Dout‧‧‧Reply information

152‧‧‧Data storage circuit

154‧‧‧Edge detection circuit

156‧‧‧ data selection circuit

SE‧‧‧Selection signal

Claims (10)

A clock data recovery device includes: a data sampling module for sampling an input data according to a plurality of first clock signals to generate a plurality of data values, wherein the first clock signals have different phases from each other a phase detecting circuit for detecting a phase error in the input data according to the at least one second clock signal to generate an error signal; a frequency estimator for using the phase threshold according to the error signal And a frequency threshold for generating an adjustment signal; a clock generation module configured to generate the first clock signal and the at least one second clock signal according to the adjustment signal and a reference clock signal; and a data reply The module is configured to generate a response data corresponding to the input data according to the data values. The clock data recovery device of claim 1, wherein the frequency estimator comprises: a first triangular integral modulator for accumulating the error signal to generate a phase integrated value, and the phase integrated value is higher than the a first control signal is outputted when the phase threshold is used; a second triangular integral modulator is configured to accumulate the error signal to generate a frequency integrated value, and output a second control when the frequency integrated value is higher than the frequency threshold a signal, an integrator for accumulating the second control signal to generate an integrated signal; a counter for counting according to the integrated signal to generate a third control signal; and an adder for adding the first control signal and the third control signal to generate the adjustment signal. The clock data recovery device of claim 1, wherein the data recovery module comprises: a data storage circuit for storing the data values; and an edge detection circuit for determining the input based on the data values At least one transition point of the data to generate a selection signal; and a data selection circuit for selecting at least one of the data values from the data storage circuit based on the selection signal to generate the reply data. The clock data recovery device of claim 2, wherein the data storage circuit further synchronizes the data values according to a local clock signal. The clock data recovery device of claim 1, wherein the clock generation module comprises: a multi-phase clock generator for generating the first clock signals and the at least one according to a local clock signal a second clock signal; and a phase interpolator for generating the local clock signal according to the adjustment signal and the reference clock signal. A clock data recovery method includes: sampling an input data according to a plurality of first clock signals to generate a plurality of data values, wherein phases of the first clock signals are different from each other; according to at least one second clock The signal detects a phase error in the input data to generate an error signal; generating an adjustment signal according to the error signal, a phase threshold, and a frequency threshold; generating the signal according to the adjustment signal and a reference clock signal a first clock signal and the at least one second clock signal; and generating a reply data corresponding to the input data according to the data values. The clock data recovery method of claim 6, wherein the generating the adjustment signal comprises: accumulating the error signal via a first triangular integral modulator to generate a phase integrated value, and the integrated value is higher in the phase The phase threshold value outputs a first control signal; accumulating the error signal via a second delta-sigma modulator to generate a frequency integrated value, and outputting a second control signal when the frequency integrated value is higher than the frequency threshold value; And accumulating the second control signal via an integrator to generate an integrated signal; counting by the counter according to the integrated signal to generate a third control signal; and adding the first control signal via an adder With the third control letter Number to generate the adjustment signal. The method of claim 6, wherein the generating the reply data comprises: storing the data values; determining, according to the data values, at least one transition point of the input data to generate a selection signal; And selecting at least one of the data values according to the selection signal to generate the reply data. The clock data replying method of claim 8, further comprising: synchronizing the data values according to a local clock signal. The clock data recovery method of claim 6, wherein the generating the first clock signal and the at least one second clock signal comprises: generating the first clock signals according to a local clock signal and The at least one second clock signal; and generating the local clock signal according to the adjustment signal and the reference clock signal via a phase interpolator.