TW201727778A - Wafer process for molded chip scale package with thick backside metallization - Google Patents

Abstract

A wafer process for molded chip scale package (MCSP) comprises: depositing metal bumps on bonding pads of chips on a wafer; forming a first packaging layer at a front surface of the wafer to cover the metal bumps; forming an un-covered ring at an edge of the wafer to expose two ends of each scribe line of a plurality of scribe lines; thinning the first packaging layer to expose metal bumps; forming cutting grooves; grinding a back surface of the wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer at a bottom surface of the wafer in the recessed space; cutting off an edge portion of the wafer; flipping and mounting the wafer on a substrate; depositing a metal layer covering the metal seed layer; removing the substrate from the wafer; and separating individual chips from the wafer by cutting through the first packaging layer, the wafer, the metal seed layers and the metal layers along the scribe lines.

Description

Wafer process for molded wafer level packages with thick back metallization

The present invention relates to a method of packaging a semiconductor device. Specifically, the present invention is directed to an improved wafer process for molded wafer level packaging (MCSP) to obtain a thin wafer package with a thick back metal and a molding compound on the front and/or back side of the semiconductor device.

In the wafer level wafer scale package (WLCSP) technology, the semiconductor wafer is completely completed on the wafer, and after the individual wafer package is separated from the wafer, the semiconductor wafer is directly packaged on the wafer level. Therefore, the size of the wafer package is the same as that of the original semiconductor wafer. In general, WLCSP technology is widely used in semiconductor devices. It is well known in the art that vertical power devices, such as common-drained metal oxide half field effect transistors (MOSFETs), have large on-resistances (Rdson). Therefore, it is necessary to thin the wafer to reduce the substrate resistance, thereby achieving the purpose of reducing Rdson. However, thin wafers are difficult to handle due to the thin wafers and lack of mechanical protection. In addition, in order to reduce Rdson in the vertical power device, a thick back metal is required to reduce the diffusion resistance. Conventional processes typically use a very thick leadframe to mount a semiconductor wafer on a thick leadframe. However, this method cannot achieve 100% wafer scale packaging.

In addition, in conventional wafer scale packaging techniques, wafers are diced directly along the scribe lines on the front side of the wafer to separate individual wafer packages from the wafer. However, prior to thinning the wafer, the front side of the packaged wafer typically has molding compounds to increase the mechanical support of the wafer and prevent wafer cracking. Therefore, the scribe line is covered by the molding compound. It is difficult to cut the wafer along the scribe line on the front side of the wafer.

Therefore, based on the description of the related art described above, it is necessary to prepare an ultra-thin wafer having a thick back metal and a molding compound on the front and/or back side of the semiconductor article of the WLCSP technology.

It is an object of the present invention to provide a wafer process for preparing a molded wafer level package with thick backside metallization to improve one or more of the problems in the prior art.

In the present invention, each of the semiconductor wafers includes a plurality of metal solder pads respectively formed on the front surface of each of the semiconductor wafers; the wafer process includes the steps of: preparing a corresponding metal bump on the plurality of metal solder pads; Forming a first encapsulation layer on the front side of the semiconductor wafer to cover the metal bumps, wherein the radius of the first encapsulation layer is smaller than the radius of the semiconductor wafer, thereby forming an uncovered ring at the edge of the semiconductor wafer, wherein the plurality of scribe lines Two ends of each of the scribe lines are located between two adjacent semiconductor wafers and extend to the front side of the uncovered ring; the first encapsulation layer is thinned to expose the metal bumps from the first encapsulation layer; a line connecting the ends of each of the scribe lines exposed on the front side of the uncovered ring, cutting the first encapsulation layer, and along each scribe line, thinning the front side of the first encapsulation layer to prepare a corresponding cutting groove; Back grinding of the semiconductor wafer to form a recessed space on the back side of the semiconductor wafer, forming a support ring at the edge of the semiconductor wafer; a bottom surface of the semiconductor wafer, depositing a metal seed layer; cutting an edge portion of the semiconductor wafer; flipping and mounting the semiconductor wafer on the substrate, the thinned first encapsulation layer is directly connected to the top surface of the substrate; and depositing a metal layer, Covering the metal seed layer; removing the substrate from the semiconductor wafer; and, by cutting the first encapsulation layer, the semiconductor wafer, the metal seed layer, and the metal layer along the dicing trench, separating and separating the individual semiconductor wafers from the semiconductor wafer; The first encapsulation layer is cut into a plurality of top encapsulation layers, and each of the plurality of top encapsulation layers covers a front surface of each of the semiconductor wafers, and the respective metal bumps are from the top of each of the semiconductor wafers. The encapsulation layer is exposed, the metal layer is cut into a plurality of bottom metal layers, and the bottom metal layers of each of the plurality of bottom metal layers cover the back surface of each of the semiconductor wafers.

Preferably, the dicing trench extends to the front side of the semiconductor wafer.

Preferably, the step of cutting the edge portion of the semiconductor wafer includes cutting the support ring.

Preferably, the radius of the recessed space is smaller than the radius of the first encapsulation layer, such that a portion of the first encapsulation layer overlaps with a portion of the support ring, wherein cutting the edge portion of the semiconductor wafer includes cutting the overlapping portion of the support ring and the first encapsulation layer.

Preferably, before the step of depositing the metal seed layer, further comprising depositing another second metal layer for ohmic contact on the bottom surface of the semiconductor wafer in the recessed space, so that the barrier formed for the metal seed layer is not Diffusion into semiconductor wafers.

Preferably, the recessed space is made of a grinding wheel having a radius smaller than a radius of the semiconductor wafer.

Preferably, after the step of depositing the metal layer covering the metal seed layer, further comprising preparing a second encapsulation layer on the metal layer, wherein separating the individual semiconductor wafer from the semiconductor wafer comprises cutting the first encapsulation layer along the cutting trench, a semiconductor wafer, a seed layer, a metal layer and a second encapsulation layer, wherein the second encapsulation layer is cut into a plurality of bottom encapsulation layers, wherein a bottom encapsulation layer of each of the plurality of bottom encapsulation layers covers a bottom metal of each of the semiconductor wafers Floor.

Preferably, the metal seed layer is deposited by evaporation or sputtering.

Preferably, the material of the seed layer is selected from the group consisting of TiNiAg, TiNi and TiNiAl.

Preferably, the metal layer is deposited by electroplating and/or electroless plating.

Preferably, the material of the metal layer is selected from the group consisting of Ag, Cu and Ni.

Preferably, after the back side of the semiconductor wafer is polished, the thinned first encapsulation layer is thicker than the semiconductor wafer.

Preferably, after depositing the metal layer covering the metal seed layer, the thickness of the metal layer is greater than 1/10 of the thickness of the semiconductor wafer.

These features and advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

The invention will be further illustrated by the following detailed description of the preferred embodiments. However, the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

FIG. 1A shows a top view of a wafer 100 having a plurality of semiconductor wafers 101 formed on the front side of the wafer, each scribe line 102 being located between two adjacent wafers 101. As is well known in the art, a separate wafer 101 is separated from wafer 100 by dicing along scribe line 102. Generally, a plurality of metal pads (not shown) are formed on the front side of each wafer 101, forming electrodes of the wafer, connected to a power source, a ground terminal, or a connection for signal transmission with an external circuit.

As shown in FIG. 1B, conductive bumps 110, such as metal bumps, are formed on each of the metal pads on the front side of each wafer 101. The metal bump 110 may be made of a conductive material such as copper, gold, silver, aluminum, or the like, or an alloy thereof. The shape of the metal bump 110 may be a spherical shape, an elliptical shape, a cubic shape, a cylindrical shape, or a wedge shape or the like.

As shown in FIG. 2B, a packaging material such as an epoxy resin or the like is deposited to prepare a first encapsulation layer 120 of a specific thickness covering the front side of the wafer 100 and all of the metal bumps 110. As shown in FIGS. 2A and 2B, the radius of the first encapsulation layer 120 is slightly smaller than the radius of the wafer 100, so that the first encapsulation layer 120 does not cover the entire front surface of the wafer 100, such as near the edge of the wafer. The cover ring 103 is not covered by the first encapsulation layer 120.

As shown in FIG. 3B, the first encapsulation layer 120 is polished to expose the metal bumps 110. In one embodiment, the first encapsulation layer 120 has a thickness of about 50 microns to 100 microns after grinding. The metal bumps 110 are preferably made of a relatively hard metal such as copper to eliminate the grinding of the first encapsulation layer 120 when dust on the metal bumps is adsorbed on the grinding wheel during the grinding of the first encapsulation layer. Unnecessary contamination of the surface. In FIG. 3B, a plurality of cutting grooves 121 are formed on the front surface of the thinned first encapsulation layer 120. As shown in FIGS. 2A and 2B, the radius of the first plastic encapsulation layer 120 is smaller than the radius of the wafer 100 to ensure that both ends of each of the scribe lines 102 in the uncovered ring 103 are not covered by the first plastic encapsulation layer 120. . By cutting the shallow lines on the front side of the first encapsulation layer 120, a dicing groove 121 can be formed, aligned with the scribe line 102, which extends from the bare ends of the cover ring 103. Specifically, each shallow line or cutting groove 121 overlaps with the corresponding scribe line 102 shown in FIG. 3A. The depth of the cutting groove 121 can be adjusted. In one embodiment, the dicing trench 121A (as indicated by the dashed line in FIG. 3B) may pass through the first encapsulation layer 120 to the front side of the wafer.

As shown in Fig. 4, the wafer 100 having an original thickness of 760 μm is ground on the back side to a predetermined thickness of 50 μm to 100 μm. In a preferred embodiment, the ground first plastic encapsulation layer is thicker than the ground wafer for mechanical support. In addition, in order to provide mechanical support for the thinned wafer, the support ring at the edge of the wafer is not ground. As shown in FIG. 4, the back surface of the wafer 100 is polished by a grinding wheel to form a recessed space 130 having a radius smaller than the radius of the wafer 100. The radius of the recessed space 130 is as large as possible to maximize wafer yield near the edge of the wafer. In this step, a support ring 104 is formed at the edge of the wafer 100, and the width of the support ring 104 is the difference between the radius of the wafer 100 and the radius of the recessed space 130. In this step, the design thickness of the thin wafer 100 can be adjusted by the depth of the recessed space 130. The support ring 104 and the thinned encapsulation layer 120 provide mechanical support for the thinned wafer 100 so that the thinned wafer does not break easily. In one embodiment, the radius of the recessed space 130 is less than the radius of the first encapsulation layer 120 to further maintain the mechanical strength of the thinned wafer 100 such that a portion of the first encapsulation layer 120 may partially overlap a portion of the support ring 104. In an example of the present invention, a second metal layer 140A may be selectively deposited on the bottom surface of the wafer 100 in the recessed space 130 for ohmic contact and used to prevent diffusion of the metal seed layer 140 (as shown in FIG. 5) to A barrier in the semiconductor wafer 100.

As shown in FIG. 5, it may be selected that the bottom surface of the exposed wafer 100 in the recessed space 130 is heavily doped with a dopant and then annealed to diffuse the dopant. A thin metal layer 140 (e.g., TiNiAg, TiNi, TiNiAl, or the like) is deposited (e.g., by evaporation or sputtering) on the bottom surface of the wafer 100. A thin metal layer 140 can be used as the seed layer 140 for depositing a thick metal layer in the next step.

As shown in FIG. 6, the edge portion 105 of the wafer 100 and the support ring 104 are cut and thinned. The overlapping portion 122 of the first encapsulation layer 120 is also cut away. The width of the cut edge portion 105 of the wafer is equal to or slightly larger than the width of the support ring 104.

As shown in Fig. 7, the entire wafer structure shown in Fig. 6 is inverted and mounted on the substrate 142. The substrate 142 may be a virtual wafer, a metal plate, or a resin plate. The entire wafer structure shown in FIG. 6 can be mounted on the substrate 142 using a double-sided tape, a heat release material, or glue.

As shown in FIG. 8, a thick bottom metal layer 124 is deposited over the thin metal layer 140 by electroplating and/or electroless plating. The metal layer 124 may be a metal such as Al, Ag, Cu, Ni, Au, or the like. The thickness of the bottom metal layer 124 is from about 10 microns to about 100 microns, depending on the size of the semiconductor wafer formed on the wafer. In general, for wafer polishing to 100 microns or less, the bottom metal layer 124 should be at least 1/10 of the wafer thickness. For wafers polished to 50 microns, the bottom metal layer should be at least 1/5 of the thickness of the wafer, preferably greater than 1/2 of the thickness of the wafer. In one embodiment, a bottom metal layer having a thickness greater than 50 microns is deposited by a ground wafer having a thickness of about 50 microns (as shown in FIG. 4). For wafer polishing less than 50 microns, the bottom metal layer 124 should be greater than 1/2 the thickness of the wafer. Since the metal layer 124 is formed by deposition, there is no bonding material such as solder or epoxy between the bottom surface of the wafer and the surface of the bottom metal layer. The thick metal layer not only provides the benefits of reduced impedance and better heat dissipation, but also provides mechanical support for the wafer and the semiconductor wafer as a whole, during the fabrication process, especially when the wafer thickness is reduced to less than 100 microns. Then, as shown in Fig. 9, the substrate 142 is removed from the wafer structure.

As shown in FIG. 10, the first encapsulation layer 120, the wafer 100, the seed layer 140, and the thick bottom metal layer 124 may be cut along the dicing trench 121 by the dicing machine 180 to make the individual wafers 101 and wafers 100. Separation. Therefore, the first encapsulation layer 120 is cut into a plurality of top encapsulation layers 1200, the seed layer 140 may be cut into a plurality of seed layers 1400, and the thick bottom metal layer 124 may be cut into a plurality of thick bottom metal layers 1240 to obtain a plurality of crystals. Round package structure 200A. Each package structure 200A includes a top package layer 1200 overlying the front side of each wafer 101, a seed layer 1400 overlying the back side of the wafer 101, and a thick bottom metal layer overlying the seed layer 1400, exposed from the top package layer 1200 The metal bump 110 serves as a contact end of the package structure 200A for electrically contacting an external circuit, and a thick bottom metal layer 1240 exposed at the bottom of the package structure 200A serves as a contact end of the package structure 200A and also for heat dissipation.

In one embodiment, wafer 101 is a vertical MOSFET (metal-oxide-semiconductor field effect transistor) in which current flows from the front side of the wafer to the back side, or vice versa. Therefore, the plurality of metal pads formed on the front side of the wafer each include a pad constituting the source electrode, and a pad constituting the gate electrode, and the bottom metal layer 1240 constitutes the drain electrode of the wafer. With the thick bottom metal layer 1240, the electrical resistance of the package structure 200A can be greatly reduced.

In another embodiment, as shown in Figures 11 through 13, a package structure 200B with a bottom encapsulation layer 1320 can be fabricated. As shown in FIG. 8, after depositing a thick bottom metal layer 124 over the thin metal layer 140, a second encapsulation layer 132 is formed overlying the thick bottom metal layer 124, as shown in FIG. Then, as shown in Fig. 12, the substrate 142 is removed from the wafer structure.

As shown in FIG. 13, the first encapsulation layer 120, the wafer 100, the seed layer 140, the thick bottom metal layer 124, and the second encapsulation layer 132 are diced to separate the individual wafers 101 from the wafer 100. Therefore, the first encapsulation layer 120 is cut into a plurality of top encapsulation layers 1200, the seed layer 140 is cut into a plurality of seed layers 1400, the thick bottom metal layer 124 is cut into a plurality of thick bottom metal layers 1240, and the second encapsulation layer 132 is cut into A plurality of bottom encapsulation layers 1320 are obtained to obtain a plurality of package structures 200B. Each package structure 200B includes a top package layer 1200 overlying the front side of each wafer 101, a seed layer 1400 overlying the back side of the wafer 101, a thick bottom metal layer 1240 overlying the seed layer 1400, and a bottom package layer 1320 covered with a thick layer. A bottom metal layer 1240, a metal bump 110 exposed from the top encapsulation layer 1200, serves as a contact end of the package structure 200B for electrically contacting an external circuit. In the present embodiment, since the thick bottom metal layer 1240 is covered by the bottom package layer 1320, the bottom metal layer 1240 cannot be used as a contact end for contacting an external circuit. Therefore, when the wafer 101 is a vertical MOSFET, a plurality of metal solder pads formed on the front surface of the wafer include a solder pad constituting the source electrode and a solder pad constituting the gate electrode, and the solder pad is electrically connected to the bottom metal layer 1240. A drain electrode is formed through a metal interconnection structure (not shown) formed in the wafer.

The above description is for explaining an exemplary embodiment of the present invention without limitation. Various modifications and changes are possible within the scope of the invention. The invention is defined by the scope of the appended claims.

100‧‧‧ wafer
101‧‧‧ wafer
102‧‧‧dick
103‧‧‧Uncovered ring
104‧‧‧Support ring
105‧‧‧Edge section
110‧‧‧Metal bumps
120‧‧‧First encapsulation layer
121, 121A‧‧‧ cutting trough
124, 1240‧‧‧ bottom metal layer
1200‧‧‧Top encapsulation layer
122‧‧‧ overlap
130‧‧‧ recessed space
132‧‧‧Second encapsulation layer
1320‧‧‧ bottom encapsulation layer
140, 1400‧‧ ‧ seed layer
140A‧‧‧Second metal layer
142‧‧‧Substrate
180‧‧‧Cutting machine
200A, 200B‧‧‧ package structure

Fig. 1A shows a plan view of a semiconductor wafer formed on the front surface of a semiconductor wafer.

Fig. 1B is a schematic cross-sectional view showing a semiconductor wafer in which metal bumps are formed on a metal pad of a semiconductor wafer.

2A and 2B are respectively a plan view and a cross-sectional view showing a step of depositing a first encapsulation layer to cover the front surface of the wafer.

3A and 3B are respectively a plan view and a cross-sectional view showing a step of grinding and thinning the first encapsulation layer and preparing a cutting groove on the first encapsulation layer.

Fig. 4 is a schematic cross-sectional view showing the steps of polishing the thinned wafer from the back side thereof.

Figure 5 is a schematic cross-sectional view showing the step of depositing a thin metal layer on the bottom surface of the thinned wafer.

Figure 6 is a cross-sectional view showing the step of cutting the edge portion of the wafer.

Fig. 7 is a cross-sectional view showing the step of flipping over and mounting the wafer shown in Fig. 6 on the substrate.

Figure 8 is a schematic cross-sectional view showing the step of depositing a thick metal layer on a thin metal layer at the bottom of a thinned wafer.

Fig. 9 is a schematic cross-sectional view showing the step of removing the substrate from the wafer prepared in the step shown in Fig. 8.

Figure 10 is a cross-sectional view showing the step of separating the exposed back metal from the individual package structure by cutting the first encapsulation layer, the wafer, and the metal layer.

Figure 11 is a cross-sectional view showing the steps of preparing a second encapsulation layer on the thick metal layer of the semiconductor device structure shown in Figure 8 before the substrate is removed and the individual package structures are separated.

Fig. 12 is a schematic cross-sectional view showing the step of removing the substrate from the wafer prepared in the step shown in Fig. 11.

Figure 13 shows a separate package of the wafer formed on the top and bottom sides of the package structure by cutting the first encapsulation layer, the wafer, the metal layer and the second encapsulation layer, and the wafer formed in the step shown in Fig. 12. A schematic cross-sectional view of the structural separation step.

101‧‧‧ wafer

110‧‧‧Metal bumps

180‧‧‧Cutting machine

1200‧‧‧Top encapsulation layer

1240‧‧‧ bottom metal layer

1320‧‧‧ bottom encapsulation layer

1400‧‧‧ seed layer

200B‧‧‧Package structure

Claims (13)

A wafer process for packaging a wafer-level package of semiconductor wafers formed on a front surface of a semiconductor wafer, each of the semiconductor wafers comprising a plurality of metal solder pads respectively formed on a front surface of each of the semiconductor wafers; The circular process includes the following steps: preparing a corresponding metal bump on the plurality of metal solder pads; preparing a first encapsulation layer on the front surface of the semiconductor wafer to cover the metal bump, wherein the first encapsulation layer a radius smaller than a radius of the semiconductor wafer to form an uncovered ring at an edge of the semiconductor wafer, wherein each of the plurality of scribe lines is located between two adjacent semiconductor wafers, and Extending to the front side of the uncovered ring; thinning the first encapsulation layer to expose the metal bump from the first encapsulation layer; each of the lines by being exposed along a front surface of the uncovered ring a straight line at both ends of the line, cutting the first encapsulation layer, along each of the scribe lines, preparing a corresponding cutting groove on the front side of the first encapsulation layer; on the semiconductor wafer Surface grinding to form a recessed space on the back surface of the semiconductor wafer, forming a support ring at the edge of the semiconductor wafer; depositing a metal seed layer on the bottom surface of the semiconductor wafer in the recessed space; An edge portion of the semiconductor wafer; flipping and mounting the semiconductor wafer on the substrate, the thinned first encapsulation layer is directly connected to the top surface of the substrate; depositing a metal layer covering the metal seed layer; and the semiconductor crystal Removing the substrate from the circle; and cutting the separate semiconductor wafer from the semiconductor wafer by cutting the first encapsulation layer, the semiconductor wafer, the metal seed layer and the metal layer along the dicing trench; Cutting the first encapsulation layer into a plurality of top encapsulation layers, wherein each of the plurality of top encapsulation layers covers a front surface of each of the semiconductor wafers, and each of the metal bumps is from each of the semiconductor wafers The respective top encapsulation layers are exposed, the metal layer is cut into a plurality of bottom metal layers, and the bottom metal layers of the plurality of bottom metal layers are respectively Each covering the back surface of the semiconductor wafer. The wafer process of claim 1, wherein the dicing trench extends to a front side of the semiconductor wafer. The wafer process of claim 1, wherein the step of cutting the edge portion of the semiconductor wafer comprises cutting the support ring. The wafer process of claim 3, wherein the recessed space has a radius smaller than a radius of the first encapsulation layer, such that a portion of the first encapsulation layer overlaps with a portion of the support ring, wherein the semiconductor wafer is cut away The edge portion includes an overlapping portion that cuts off the support ring and the first encapsulation layer. The wafer process of claim 1, wherein before the step of depositing the metal seed layer, further comprising depositing another second for ohmic contact on the bottom surface of the semiconductor wafer in the recessed space The metal layer is such that a barrier formed for the metal seed layer does not diffuse into the semiconductor wafer. The wafer process of claim 1, wherein the recessed space is made of a grinding wheel having a radius smaller than a radius of the semiconductor wafer. The wafer process of claim 1, wherein after depositing the metal layer to cover the metal seed layer, further comprising preparing a second encapsulation layer on the metal layer from the semiconductor wafer Separating the individual semiconductor wafers includes cutting the first encapsulation layer, the semiconductor wafer, the metal seed layer, the metal layer and the second encapsulation layer along the dicing trench; wherein the second encapsulation layer is diced into a plurality of a bottom encapsulation layer, wherein a bottom encapsulation layer of each of the plurality of bottom encapsulation layers covers a respective bottom metal layer of each of the semiconductor wafers. The wafer process of claim 1, wherein the metal seed layer is deposited by evaporation or sputtering. The wafer process of claim 8, wherein the material of the metal seed layer is selected from the group consisting of TiNiAg, TiNi, and TiNiAl. The wafer process of claim 8, wherein the metal layer is deposited by electroplating and/or electroless plating. The wafer process of claim 10, wherein the material of the metal layer is selected from the group consisting of Ag, Cu, and Ni. The wafer process of claim 1, wherein the first package layer that is thinned is thicker than the semiconductor wafer after the back surface of the semiconductor wafer is polished. The wafer process of claim 1, wherein the metal layer has a thickness greater than 1/10 of the thickness of the semiconductor wafer.