TW201423390A - Computer system and operating method thereof - Google Patents

Abstract

A computer system and an operating method thereof are disclosed herein. The computer system includes at least one monitored device and a logic control device. The logic control device is connected to the monitored device, and is configured to monitor status signals from the monitored device so as to determine whether the monitored device is in an error state. When the monitored device is in the error state, the logic control device counts a predetermined time period, and determines whether the monitored device recovers to normal after the predetermined time period, and determines whether the monitored device has been reset during the predetermined time period. If the monitored device does not recover to normal and the monitored device has not been reset during the predetermined time period, then the logic control device resets the monitored device.

Description

Computer system and its operation method

The present invention relates to an electronic system and method of operating the same, and more particularly to a computer system and method of operating the same.

With the development of digital technology, computer systems have been widely used in people's lives, such as desktop computers, notebook computers, and network processors and servers for providing network services. Wait.

In general, a computer system includes a plurality of separately operated devices, such as a central processing unit, a south bridge chip, a storage device, a basic input/output system, and the like. When an error occurs in these devices, it can transmit an error message to a management controller (such as a baseboard management controller) in the computer system to cause the management controller to restart the devices. However, the management controller itself may be in error or invalid, so that the management controller fails to restart when an error occurs in the device. As a result, the computer system may be in an error state for a long time. If the computer system is a server that provides network services, the quality of the network service may be degraded, and the user may be further dissatisfied.

Therefore, in order to ensure the reliability of the computer system error response, the above problems have an urgent need to solve.

One aspect of the present invention is a computer system that utilizes a logic control device for signal monitoring and error recovery.

According to an embodiment of the invention, a computer system includes at least one monitored device and a logical control device. The logic control device is connected to the monitored device for monitoring the status signal of the monitored device to determine whether the monitored device is in an error state. When the monitored device is in an error state, the logic control device counts a preset time, and after the preset time, determines whether the monitored device returns to normal, and determines whether the monitored device resets within the preset time. If the monitored device does not return to normal and the monitored device does not reset within this preset time, the logical control device resets the monitored device.

According to an embodiment of the invention, the logic control device further includes a state mapping table, and the logic control device stores the status signal of the monitored device in a corresponding address in the state mapping table as the correct operation data.

According to an embodiment of the invention, the logic control device compares the status signal of the monitored device with the correct operation data stored in the corresponding address in the state mapping table to determine whether the monitored device is in an error state.

According to an embodiment of the invention, the logic control device further includes a timer for counting the preset time.

According to an embodiment of the invention, the logic control device determines whether the monitored device is in an error state according to whether the normal signal sent by the monitored device is not received or whether the monitored device issues an error signal.

According to an embodiment of the invention, the logic control device restarts the main power rail to cause the monitored device to be powered back on.

One aspect of the present invention is a method of operating a computer system. According to an embodiment of the invention, a computer system includes a logic control device and at least one monitored device, and the logic control device is connected to the monitored device, and the operation method includes: monitoring a status signal of the monitored device; and according to the status signal of the monitored device To determine whether the monitored device is in an error state; when the monitored device is in an error state, time is counted for a preset time; after the preset time, it is determined whether the monitored device is restored to normal, and it is determined whether the monitored device is preset here The reset is performed within the time; and if the monitored device does not return to normal and the monitored device does not reset within this preset time, the monitored device is reset.

According to an embodiment of the invention, the logic control device includes a state mapping table, and the step of determining whether the monitored device is in an error state according to the status signal of the monitored device includes: storing the status signal of the monitored device in the state mapping table. The corresponding address is used as the correct operation data; then, the status signal of the monitored device and the correct operation data stored in the corresponding address in the state mapping table are compared to determine whether the monitored device is in an error state.

According to an embodiment of the invention, the step of determining whether the monitored device is in an error state according to the status signal of the monitored device includes: whether the normal signal sent by the monitored device is not detected, or whether the monitored device is issued according to whether The error signal is used to determine if the monitored device is in an error state.

In accordance with an embodiment of the invention, the step of resetting the monitored device includes restarting the primary power rail to cause the monitored device to reboot.

In summary, when the above-mentioned embodiment is applied, when an error occurs in the internal device of the computer system, the logic control device can be used to reply. Because the logic control device can be implemented by logic components, it is less prone to error, so that it can provide more reliable. Error response mechanism.

The spirit and scope of the present disclosure will be apparent from the following description of the preferred embodiments of the present disclosure. Modifications do not depart from the spirit and scope of the disclosure.

As used herein, "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, and "connected" may also refer to two or more elemental elements. Interoperate or act.

One aspect of the present invention is a computer system that utilizes a logic control device for signal monitoring and error recovery. The computer system can be a desktop computer, a notebook computer, a network processor, a server, etc. In order to clarify the description, a server will be described as an example in the following paragraphs.

FIG. 1 is a block diagram of a computer system 100 in accordance with an embodiment of the invention. Computer system 100 includes at least one monitored device (eg, seven monitored devices D1-D7) and a logic control device 110. When noted, the monitored device can be an internal device in the computer system 100, such as, but not limited to, a south bridge chip, a basic input output system (BIOS), a baseboard management controller (baseboard). Management controller (BMC), a central processing unit (CPU), a power supply unit (PSU), a storage device, or a voltage regulator down (VRD), The description is clear. In the following paragraphs, seven monitored devices D1-D7 will be taken as an example. D1 can be a south bridge chip, D2 can be a basic input/output system, D3 can be a substrate management controller, and D4 can be a central The processor, D5 can be a power supply unit, D6 can be a storage device, and D7 can be a voltage regulator. Logic control device 110 may be, but is not limited to, a logic circuit, a programmable logic device (PLD), a complex programmable logic device (CPLD), or a field programmable gate array (FPGA). Realized.

The logic control device 110 is respectively connected to the monitored devices D1-D7 for monitoring the status signals of the monitored devices D1-D7 to determine whether the monitored devices D1-D7 are in an error state. For example, the logic control device 110 can monitor whether the south bridge chip D1 and the basic input/output system D2 send a normal signal (such as a heartbeat signal) by using a low pin count (LPC) bus bar, and interconnect by extending peripheral components. The peripheral component interconnect extended (PCI-X) monitors whether the baseboard management controller D3 sends a normal signal (such as a heartbeat signal), and monitors the central processor D4 by a general purpose input/output (GPIO) pin. Send overheat signal or error signal (such as CPU_ierr, CPU_mcerr, Thermal_trip), power supply unit D5 to send overheat signal and / or normal signal (such as power good signal (such as power good signal), and storage device D6 and voltage regulator D7 Whether to send an error signal and/or a normal signal (such as a power fault signal and/or a power good signal). Wherein, since the voltage regulator D7 can respectively output a plurality of voltage levels to the internal devices in the computer system 100, the logic control device 110 can separately monitor the error signals of each voltage level output by the voltage regulator D7 and/or Normal signal. In this way, by monitoring the error signals and/or normal signals of the monitored devices D1-D7, the logic control device 110 can determine whether the normal signals sent by the monitored devices D1-D7 are not detected, or according to the monitored device D1. -D7 issued an error Signal to determine if the monitored devices D1-D7 are in an error state.

When the monitored devices D1-D7 are in an error state, the logic control device 110 can time a preset time and determine whether the monitored devices D1-D7 return to normal after the preset time, for example, whether the normal signal is received again. Or the error signal disappears and it is determined whether the monitored device D1-D7 is reset within this preset time. For example, the logic control device 110 can utilize a plurality of general-purpose input and output pins to separately monitor a plurality of voltage levels or a plurality of voltage level power supply normal signals output by the voltage regulator D7, and corresponding to the voltage levels. Restart (eg, whether it is turned off and on) to determine if the monitored devices D1-D7 have been reset.

Then, if the monitored devices D1-D7 are not restored to normal and the monitored devices D1-D7 are not reset within the preset time period, the logic control device 110 may reset the monitored devices D1-D7. For example, the logic control device 110 can reset the single monitored device D1-D7 by sending a reset signal to the monitored devices D1-D7, or restart the main power rail to restart the computer system 100. .

Through the above settings, the logic control device 110 can monitor the status of the monitored devices D1-D7 to restart the computer system 100 or a single error when the monitored devices D1-D7 are not recovered or reset in the event of an error. The monitored devices D1-D7 ensure proper operation of the computer system 100. Moreover, since the logic control device 110 can be implemented with logic elements, the logic control device 110 can provide a more reliable error recovery mechanism than a higher order management controller such as a baseboard management controller.

In an embodiment of the invention, the logic control device 110 may further include a state mapping table 112. Logic control device when computer system 100 is in operation 110 can store the status signals of the monitored devices D1-D7 in the corresponding address in the status mapping table 112 as the correct operation data. For example, the logic potential received by the first general-purpose input and output pin can be stored in the first address in the state mapping table 112, and the logic potential received by the second general-purpose input and output pin can be stored in the state mapping table 112. The second bit address and the logic potential received by the first pin of the LPC bus can be stored in the third address in the state map 112. It is noted that in some embodiments, each address in the state mapping table 112 can point to multiple scratchpad spaces to store status signals at different times, or to store periodic status signals (eg, heartbeat signal). .

After obtaining the correct operation data, the logic control device 110 can compare the status signals of the currently monitored monitored devices D1-D7 with the correct operation data stored in the corresponding address in the state mapping table 112 in the past to determine the monitored device D1- Whether D7 is in an error state. Similarly, the logic control device 110 can also determine whether the monitored device D1-D7 returns to normal after an error. For example, if the overheat signal (eg, Thermal_trip) of the central processor D4 stored in the second address in the state mapping table 112 is a high logic potential, when the logic control device 110 finds the second general-purpose input and output pin receives When the overheat signal of the central processing unit D4 is a low logic potential, the logic control device 110 can judge that the central processing unit D4 is in an error state.

It should be noted that in other embodiments, the logic control device 110 may also compare the status signals of the monitored devices D1-D7 with the values preset by the administrator to determine whether the monitored devices D1-D7 are in an error state, and determine the manner. It is not limited to the above embodiment.

In some embodiments, the logic control device 110 can also be monitored according to A plurality of status signals in the devices D1-D7 perform an overall erroneous determination.

In addition, in an embodiment of the invention, the logic control device 110 may further include a timer 114 for counting the preset time.

Moreover, it will be apparent to those skilled in the art that the status signals of the monitored devices D1-D7 can be any signal that can be used to indicate whether the monitored devices D1-D7 are functioning properly without departing from the spirit of the present invention. The signal in the example is limited.

Another aspect of the invention is a method of operating a computer system. This method of operation can be applied to a computer system having the same or similar structure as in the first drawing. For convenience of description, the following operation method is described by taking the embodiment shown in FIG. 1 as an example, but is not limited to the embodiment of FIG. 1.

It is noted that in the steps of the following methods of operation, there is no particular order unless otherwise stated. In addition, the following steps may also be performed simultaneously or overlap in execution time.

FIG. 2 is a flow chart diagram of operation method 200 in accordance with an embodiment of the invention. Operation method 200 can include steps S1-S5. After the computer system 100 is started, the status signals of the monitored devices D1-D7 are monitored (step S1), and based on the status signals of the monitored devices D1-D7, it is determined whether the monitored devices D1-D7 are in an error state (step S2). When the monitored devices D1-D7 are in an error state, timing is started for a predetermined period of time (step S3), and then, timing is performed (step S4). After the preset time is reached, it is determined whether the monitored devices D1-D7 return to normal, and it is determined whether the monitored devices D1-D7 are reset within a preset time (step S5), if the monitored devices D1-D7 are not restored to normal And the monitored devices D1-D7 are not reset within the preset time, the monitored devices D1-D7 are reset (step S6).

For a detailed description of the monitored devices D1-D7, reference may be made to the previous embodiment, and details are not described herein.

In an example of implementation, in step S1, the computer system 100 can monitor whether the south bridge chip D1, the basic input/output system D2, and the substrate management controller D3 emit a normal signal (such as a heartbeat signal), and whether the central processing unit D4 issues an overheat. Signal or error signal, such as CPU_ierr, CPU_mcerr, Thermal_trip, whether the power supply unit D5 sends out overheating signals and/or normal signals, such as power good signal (such as power good signal), and whether the storage device D6 and the voltage regulator D7 send an error signal. And/or normal signals, such as power fault signals and/or power good signals. The computer system 100 can separately monitor the error signal and/or the normal signal of each voltage level output by the voltage regulator D7.

In step S2, the computer system 100 can determine whether the monitored device D1-D7 is in an error state according to whether the normal signal sent by the monitored device D1-D7 is not detected, or whether the monitored device D1-D7 sends an error signal. . In addition, if the monitored devices D1-D7 are not in an error state, the computer system 100 re-executes step S1 to continuously monitor the status signals of the monitored devices D1-D7.

In step S3, computer system 100 can begin timing using a timer. In some embodiments, the computer system 100 continues to monitor the status signals of the monitored devices D1-D7 during this period of time to determine if there are other errors and further make an overall erroneous determination.

In step S5, the computer system 100 can determine whether the monitored device D1-D7 is restored by whether the normal signal is received again or the error signal disappears. Normally, and can separately monitor the power level signals of multiple voltage levels or voltage levels output by the voltage regulator D7, and correspondingly whether the voltage levels are restarted (for example, whether it is turned off and then turned on) to determine Whether the monitoring devices D1-D7 have been reset. If the computer system 100 determines that the monitored devices D1-D7 have returned to normal or have been reset, it indicates that the monitored devices D1-D7 may have been processed by other error recovery mechanisms, so the computer system 100 may re-execute step S1. The status signals of the monitored devices D1-D7 are monitored again.

In step S6, the computer system 100 can reset the single monitored device D1-D7 by transmitting a reset signal to the monitored devices D1-D7, or restart the main power rail to make the computer system 100 The monitored devices D1-D7 are turned back on.

Through the above settings, the computer system 100 can monitor the status of the monitored devices D1-D7 to restart the monitored devices D1-D7 or occur when the monitored devices D1-D7 are not recovered or reset in the event of an error. The wrong monitored devices D1-D7 ensure proper operation of the computer system 100.

In an embodiment of the invention, step S2 may include the following sub-steps. (a) storing the status signals of the monitored devices D1-D7 in the corresponding address in the status mapping table 112 as the correct operation data; and then (b) comparing the status signals of the monitored devices D1-D7 with the status mapping table. The correct operation data of the corresponding address in 112 to determine whether the monitored devices D1-D7 are in an error state.

For example, the computer system 100 can store the logic of the overheat signal (such as Thermal_trip) of the central processor D4 in the second address in the state mapping table 112, as the correct operation data of the computer system 100, and then the computer The system 100 can determine whether the CPU D4 is in an error state by comparing whether the received overheat signal of the central processor D4 and the logic potential of the second address stored in the state map 112 are the same.

Moreover, in some embodiments, computer system 100 can also utilize the correct operational data stored in state map 112 to determine if monitored device D1-D7 has returned to normal after an error.

It should be noted that in other embodiments, the computer system 100 can also compare the status signals of the monitored devices D1-D7 and the values preset by the administrator to determine whether the monitored devices D1-D7 are in an error state, so that the error is determined. The manner of this is not limited to the above embodiment.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

100‧‧‧ computer system

110‧‧‧Logical control device

112‧‧‧State Mapping Table

200‧‧‧How to operate

D1-D7‧‧‧Monitored device

S1-S6‧‧‧ steps

114‧‧‧Timer

LPC, PCI-X‧‧‧ bus

1 is a block diagram of a computer system according to an embodiment of the invention; and FIG. 2 is a flow chart of a method for operating a computer system according to an embodiment of the invention.

100‧‧‧ computer system

110‧‧‧Logical control device

112‧‧‧State Mapping Table

114‧‧‧Timer

D1-D7‧‧‧Monitored device

LPC, PCI-X‧‧‧ bus

Claims (10)

A computer system comprising: at least one monitored device; and a logic control device connected to the monitored device for monitoring a status signal of the monitored device to determine whether the monitored device is in an error state, wherein When the monitoring device is in an error state, the logic control device counts a preset time, and after the preset time, determines whether the monitored device returns to normal, and determines whether the monitored device is reset within the preset time. If the monitored device does not return to normal and the monitored device does not reset within the preset time, the logic control device resets the monitored device. The computer system of claim 1, wherein the logic control device further comprises a state mapping table, wherein the logic control device stores the status signal of the monitored device in a corresponding address in the state mapping table as a correct operation data. The computer system of claim 2, wherein the logic control device compares the status signal of the monitored device with the correct operation data stored in the corresponding address in the status mapping table to determine whether the monitored device is in an error state. . The computer system of claim 1, wherein the logic control device further comprises a timer for counting the preset time. The computer system of claim 1, wherein the logic control device determines whether the monitored device is in error according to whether a normal signal sent by the monitored device is not received, or whether the monitored device sends an error signal according to whether the monitored device sends an error signal. status. The computer system of claim 1, wherein the logic control device restarts a main power rail to cause the monitored device to be powered back on. A computer system operating method, wherein the computer system includes a logic control device and at least one monitored device, the logic control device is connected to the monitored device, the operating method includes: monitoring a status signal of the monitored device; Monitoring the status signal of the device to determine whether the monitored device is in an error state; when the monitored device is in an error state, counting a preset time; after the preset time, determining whether the monitored device returns to normal, and determining Whether the monitored device is reset within the preset time; and if the monitored device does not return to normal and the monitored device does not reset within the preset time, the monitored device is reset. The operation method of claim 7, wherein the logic control device comprises a state mapping table, and the step of determining whether the monitored device is in an error state according to the status signal of the monitored device comprises: Storing the status signal of the monitored device in the status mapping table as the correct operation data; and then comparing the status signal of the monitored device with the correct operation data stored in the corresponding address in the status mapping table, To determine if the monitored device is in an error state. The operation method of claim 7, wherein the step of determining whether the monitored device is in an error state according to the status signal of the monitored device comprises: determining whether a normal signal is sent by the monitored device, or Whether the monitored device is in an error state is determined according to whether the monitored device sends an error signal. The method of operation of claim 7, wherein the step of resetting the monitored device comprises restarting the primary power rail to cause the monitored device to be powered back on.