TW201322120A - An accelerated code optimizer for a multiengine microprocessor - Google Patents

Abstract

A method for accelerating code optimization in a microprocessor. The method includes fetching an incoming macroinstruction sequence using an instruction fetch component and transferring the fetched macroinstructions to a decoding component for decoding into microinstructions. Optimization processing is performed by reordering the microinstruction sequence into an optimized microinstruction sequence comprising a plurality of dependent code groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored into a sequence cache for subsequent use upon a subsequent hit optimized microinstruction sequence.

Description

Accelerated Encoding Optimizer for Multi-Engine Microprocessors [Related application reference]

The present application is related to U.S. Patent Application Serial No. 2010/0161948, entitled "APPARATUS AND METHOD FOR FOR PROCESSING COMPLEX INSTRUCTIONS FOR MULTIPLE STRUCTURE STRUCTURES WITH SUPPORTING MULTIPLE NETWORK EXCHANGE AND VIRTUALIZATION PROGRAMS PROCESSING COMPLEX INSTRUCTION FORMATS IN A MULTITHREADED ARCHITECTURE SUPPORTING VARIOUS CONTEXT SWITCH MODES AND VIRTUALIZATION SCHEMES)", filed on January 5, 2010 by Mohammad A. Abdallah, the entire contents of which is incorporated herein.

This application is related to U.S. Patent Application Serial No. 2009/0113170, entitled "APPARATUS AND METHOD FOR PROCESSING AN INSTRUCTION MATRIX SPECIFYING PARALLEL IN DEPENDENT" OPERATIONS), filed on December 9, 2008 by Mohammad A. Abdallah, the entire contents of which is incorporated herein by reference.

This application is related to U.S. Patent Application Serial No. 61/384,198, entitled "SINGLE CYCLE MULTI-BRANCH PREDICTION INCLUDING SHADOW CACHE FOR EARLY FAR BRANCH" PREDICTION), filed on September 17, 2010 by Mohammad A. Abdallah, the entire contents of which is incorporated herein.

This application is related to U.S. Patent Application Serial No. 61/467,944, the patent The name is "EXECUTING INSTRUCTION SEQUENCE CODE BLOCKS BY USING VIRTUAL CORES INSTANTIATED BY PARTITIONABLE ENGINES" by Mohammad A. Abdallah on March 25, 2011. The entire content of the application is incorporated herein.

The present invention relates generally to digital computer systems, and more particularly to systems and methods for selecting instructions that include a sequence of instructions.

The processor needs to handle a variety of tasks that are related or completely unrelated. The internal state of such a processor typically consists of a scratchpad that can hold different values for each particular instant of execution of the program. At each instant of program execution, the internal state image is referred to as the architectural state of the processor.

When the code execution is switched to perform another function (such as another thread, program, or program), the state of the machine/processor needs to be stored so that the new function can utilize the internal scratchpad to establish its new state. Once the new function is terminated, its state can be discarded and the status of the previous context will be resumed and resumed. This switching procedure is called a context switch and usually contains tens or hundreds of loops, especially with modern architectures that use a large number of registers (such as 64, 128, 256) and/or out-of-order execution. .

In a thread-aware hardware architecture, the standard case is for hardware to support multiple contexts for a limited number of hardware support threads. In this case, the hardware is for each The support thread copies all architectural state components. This eliminates the need for context switching when executing a new thread. However, this still has several drawbacks, namely copying the area, power, and complexity of all architectural state elements (ie, scratchpads) for each additional thread supported in the hardware. In addition, if the number of software threads exceeds the number of hardware threads explicitly supported, then a thread switch must still be performed.

This has become common, as is the parallelism required on the fine-grained scale of a large number of threads. Hardware thread-aware architecture and replication context storage hardware does not help non-threaded software encoding, and only reduces the number of thread switching of threaded software. However, those threads are usually constructed for coarse grain parallelism and result in heavy software costs to initialize and synchronize, discarding fine grain parallelism, such as functional calls and loop parallel execution, without effective Thread initialization / automatic generation. The cost of this type of description also makes it difficult to auto-parallel such encoding for non-clear/simple parallel/threaded software encoding using the latest compiler or user parallelization techniques.

In one embodiment, the invention is embodied as a method for accelerating encoding optimization in a microprocessor. The method includes: using an instruction fetch component to grab a received macro instruction sequence and transferring the captured macro instruction to a decoding component for decoding into a microinstruction. The optimization process is performed by reordering the microinstruction sequence to optimize the microinstruction sequence for one of a plurality of dependent coding groups. The plurality of dependency coding groups are then output to a plurality of engines of the microprocessor for execution in parallel. A copy of the optimized microinstruction sequence is stored to a sequence of caches for subsequent use in subsequent clicks on one of the optimized microinstruction sequences.

The foregoing is a summary of the invention, and thus is inclusive of Therefore, it is to be understood that the invention may be Other aspects, features, and advantages of the invention will be set forth in the description of the appended claims.

Although the present invention has been described in connection with the specific embodiments, the present invention is not intended to be limited to the specific forms set forth herein. Rather, the invention is intended to cover alternatives, modifications, and equivalents of the inventions that are included in the scope of the invention as defined by the appended claims.

In the following detailed description, numerous specific details are set forth, such as the particular method of the embodiments, It should be understood, however, that the specific embodiments of the invention may be practiced In other instances, well-known structures, components, or connections are omitted or not described in detail to avoid unnecessarily obscuring the description.

The phrase "one embodiment" or "an embodiment" is used in the specification to mean that a particular feature, structure, or characteristic described in connection with a particular embodiment is included in the present invention. A specific embodiment of at least one embodiment of the invention. The word "in a particular embodiment" is used in many places in the specification and is not intended to refer to the specific embodiments. Moreover, many of the features described may be presented in certain embodiments. It is not presented in other specific embodiments. Similarly, many of the needs described may be desirable for certain embodiments, but are not required by other specific embodiments.

Portions of the detailed description are set forth below in terms of procedures, steps, logic blocks, processing, and other symbols that operate on the data bits in the computer memory. These descriptions and representations are the means used by those skilled in the art to best convey the substance of their work to those skilled in the art. Programs, computer-executed steps, logic blocks, processes, and the like are here and in general are contemplated as steps or instructions that result in a consistent sequence of desired results. These steps are operations for entities that require a physical quantity. Typically, but not necessarily, these quantities are in the form of electrical or magnetic signals of a computer readable storage medium and can be stored, transferred, combined, compared, or manipulated in a computer system. It has proven convenient at times (primarily for normal use) to refer to such signals as bits, values, elements, symbols, characters, terms, numbers or the like.

However, it should be noted that all of these or similar terms are related to the appropriate amount of the entity and are merely convenient symbols applied to these quantities. In the following discussion, unless otherwise specified, it is to be understood that the present invention uses, for example, "processing", "accessing", "writing", "storing", "copying". The discussion of terms such as "replicating" or similar means the operation and procedure of a computer system or similar electronic computing device, which represents a physical (electronic) amount in a computer system register and memory and other computer readable media. The data is manipulated and converted into other material similarly represented as an entity in a computer system memory or scratchpad or other such information storage, transmission, or display device.

In a specific embodiment, the invention is implemented to be added to a microprocessor The method of speed coding optimization. The method includes fetching a received macro instruction sequence using an instruction fetching component, and transferring the fetched macro instruction to a decoding component for decoding into a microinstruction. The optimization procedure is implemented by reordering the microinstruction sequence into a sequence of optimal microinstructions comprising one of a plurality of dependent coding groups. The optimized microinstruction sequence is output to a microprocessor pipeline for execution. A copy of the optimized microinstruction sequence is stored in the sequence cache for subsequent use in subsequent clicks on the optimized microinstruction sequence.

1 shows a schematic diagram of the dispatch/release phase of microprocessor 100 in accordance with an embodiment of the present invention. As shown in FIG. 1, the microprocessor 100 includes a capture component 101, a native decoding component 102, and an instruction scheduling and optimizer component 110 of the microprocessor and a remaining pipeline 105.

In the particular embodiment of FIG. 1, the macro instruction is captured by the capture component 101 and decoded by the native decoding component 102 into a native microinstruction, which in turn provides microinstruction to microinstruction cache 121 and instruction scheduling and optimal. The chemist member 110. In a specific embodiment, the fetched macro instruction includes a sequence of instructions that are assembled by predicting a particular branch.

The macro instruction sequence is decoded by the native decoding component 102 into a resulting microinstruction sequence. The microinstruction sequence is then transmitted through multiplexer 103 to instruction schedule and optimizer component 110. The instruction scheduling and optimizer components function by performing an optimization procedure, such as by reordering specific instructions of the microinstruction sequence for more efficient execution. This produces an optimized sequence of microinstructions that are then transferred via multiplexer 104 to the remaining pipelines 105 (e.g., dispatch, distribution, execution, and retirement phases, etc.). Optimizing the microinstruction sequence results in faster and more efficient instruction execution.

In one embodiment, the macro instruction may be an instruction from a higher order instruction set architecture and the micro instruction is a lower order machine instruction. In another embodiment, the macro instruction can be a guest instruction from a plurality of different instruction set architectures (eg, CISC, x86, RISC, MIPS, SPARC, ARM, virtual like, JAVA, and the like) And microinstructions are low-order machine instructions or instructions of different native instruction set architectures. Similarly, in one embodiment, the macro instruction can be a native instruction of an architecture, and the microinstruction can be a native microinstruction of the same architecture that has been reordered and optimized. For example, X86 macro instructions and X86 microcoded micro instructions.

In a specific embodiment, in order to speed up the execution efficiency of frequently encountered codes (such as hot codes), a frequently encountered copy of the microinstruction sequence is cached in the microinstruction cache 121, and often encounters The optimized microinstruction sequence is cached in the sequence cache 122. When the code is captured, decoded, optimized, and executed, the particular optimized microinstruction may be evicted or fetched via the depicted eviction and fill path 130 based on the size of the sequence cache. sequence. This eviction and fill path allows the optimized microinstruction sequence to be transferred back and forth across the memory level of the microprocessor (eg, L1 cache, L2 cache, specific cacheable memory range, or the like).

It should be noted that in a particular embodiment, the microinstruction cache 121 may be omitted. In such a specific embodiment, the thermally encoded acceleration is provided by optimizing the storage of the microinstruction sequences within the sequence cache 122. For example, the space saved by omitting the microinstruction cache 121 can be used, for example, to implement a larger sequence cache 122.

2 shows a schematic diagram depicting an optimization procedure in accordance with an embodiment of the present invention. The left side of Figure 2 shows a sequence of received microinstructions, such as native decoding. The piece 102 or the microinstruction cache 121 is received. They are not optimized when they are initially received.

One purpose of the optimization process is to locate and identify interdependent instructions and move them to their individual dependency groups so that they can be executed more efficiently. In a specific embodiment, groups of dependent instructions can be distributed together so that they can be executed more efficiently because their individual sources and destinations are grouped together for locality. It should be noted that the optimization procedure can be used for both out-of-order processors and sequential processors. For example, in a sequential processor, the instructions are delivered sequentially. However, the instructions can be moved around so that the dependent instructions are placed in individual groups so that the group can then be executed independently, as described above.

For example, received instructions include loading, manipulation, and storage. For example, the instruction 1 includes the operation of one of the source registers (such as the scratchpad 9 and the scratchpad 5) and the result stored in the scratchpad 5. Therefore, the register 5 is the destination, and the register 9 and the register 5 are the source. In this mode, the sequence of 16 instructions contains the destination register and the source register, as shown.

The embodiment of Figure 2 performs reordering of instructions to generate a dependency group, wherein the commands belonging to a group are dependent on each other. To accomplish this, an algorithm is executed that performs a hazard check on the loading and storage of the 16 received instructions. For example, under the uncorrelated check, the store cannot cross the earlier load. Storage cannot pass earlier storage. Under the non-dependency check, the load cannot pass the earlier storage. Loading can be done by loading. The instructions can predict branches (eg, dynamically constructed branches) through previous paths by using a rename technique. In the case of a non-dynamic pre-branch branch, the movement of the instructions needs to take into account the extent of the branch. Each of the above rules can Implemented by adding virtual dependencies (eg, by artificially joining a virtual source or destination to an instruction to execute a rule).

Still referring to FIG. 2, as described above, one purpose of the optimization procedure is to locate dependent instructions and move them into a common dependency group. This procedure must be done according to the hazard check algorithm. The optimization algorithm is looking for instruction dependencies. Instruction dependencies include real dependencies, output dependencies, and inverse dependencies.

The algorithm begins by looking for true dependencies. To identify true dependencies, each destination of the 16 instruction sequences is compared to other sequence sources that occurred later in the 16 instruction sequences. Subsequent instructions that are true to an earlier instruction are marked as "_1" to indicate their true dependencies. This is shown in Figure 2 as an instruction number, which is performed from left to right across 16 sequences of instructions. For example, considering instruction number 4, destination register R3 is compared to the source of subsequent instructions, and each subsequent source is labeled "_1" to indicate the true dependencies of the instruction. In this case, the instruction 6, the instruction 7, the instruction 11, and the instruction 15 are marked as "_1".

The algorithm then looks for output dependencies. To identify output dependencies, each destination is compared to the destination of other subsequent instructions. Moreover, for each of the 16 instructions, each subsequent destination of the match is marked as "1_" (eg, sometimes represented as red).

The algorithm then looks for anti-dependency. To identify the inverse dependency, for each of the 16 instructions, each source is compared to the source of the earlier instruction to identify a match. If a match occurs, the instruction under consideration marks itself as "1_" (for example, sometimes in red).

In this manner, the algorithm has a dependency matrix of columns and rows for a sequence of 16 instructions. The dependency matrix contains tags that indicate different dependency types for each of the 16 instructions. In one embodiment, the dependency matrix is assembled in a loop using CAM matching hardware and appropriate broadcast logic. For example, the destination is broadcast down via the remaining instructions, compared to the source of subsequent instructions (eg, true dependencies) and the destination of subsequent instructions (eg, output dependencies), while the destination can be broadcast up via previous instructions To the source of the previous instruction (such as reverse phase dependency).

The optimization algorithm uses a dependency matrix to select which instructions will move together to the common dependency group. Preferably, the instructions that are truly dependent on each other are moved to the same group. The register rename is used to eliminate the inverse dependency to allow those inversions to be moved according to the instruction. The movement is done according to the above rules and hazard checks. For example, in the case of a non-dependency check, the store cannot pass the earlier load. Storage cannot pass earlier storage. Under the non-dependency check, the load cannot pass the earlier storage. Loading can be done by loading. The instructions can predict branches (eg, dynamically constructed branches) through previous paths by using a rename technique. In the case of a non-dynamic pre-branch branch, the movement of the instructions needs to take into account the extent of the branch.

In a specific embodiment, a priority encoder can be implemented to determine which instructions are moved to be grouped with other instructions. The priority encoder will act according to the information provided by the dependency matrix.

3 and 4 illustrate a multi-step optimization procedure in accordance with an embodiment of the present invention. In a specific embodiment, the optimization procedure is iteration, After the instruction moves into the first channel by moving its dependency row, the dependency matrix is again assembled and the new opportunity is reviewed again to move the instruction. In a specific embodiment, the dependency matrix aggregation procedure is repeated three times. This is shown in Figure 4, which shows the instructions that have been moved and then reviewed again, looking for opportunities to move other instructions. The sequence of numbers on the right side of each of the 16 instructions shows the group in which the instruction is located and the group in which the instruction is at the end of the program, with a mediation group in between. For example, Figure 4 shows how instruction 6 begins in group 4 but moves into group 1.

In this manner, Figures 2 through 4 depict the operation of an optimization algorithm in accordance with one embodiment of the present invention. It should be noted that although Figures 2 through 4 depict a dispatch/release phase, this functionality can also be implemented in a local scheduler/distribution phase.

FIG. 5 shows a flow chart of the steps of an exemplary hardware optimization process 500 in accordance with an embodiment of the present invention. As shown in FIG. 5, in accordance with an embodiment of the present invention, the flowchart shows that the operational steps of the optimization procedure are implemented in a dispatch/release phase of a microprocessor.

The process 500 begins in step 501, in which a received macro instruction sequence is captured using an instruction fetching component (such as the grabbing component 101 of FIG. 1). As mentioned above, the fetched instructions include compiling a sequence by predicting a particular instruction branch.

In step 502, the fetched macro instruction is transferred to a decoding component for decoding into a microinstruction. The macro instruction sequence is decoded into a microinstruction sequence based on the branch prediction. In one embodiment, the microinstruction sequence is then stored into a microinstruction cache.

In step 503, the microinstruction sequence is then optimized by reordering the microinstructions containing the sequence into a dependency group. Reordering is performed by an instruction reordering component, such as instruction scheduling and optimizer component 110. This procedure is described in Figures 2 to 4.

In step 504, the optimized microinstruction sequence is an output to the microprocessor pipeline for execution. As described above, the optimized microinstruction sequence is forwarded to the remainder of the machine for execution (e.g., remaining pipeline 105).

Subsequently, in step 505, a copy of the optimized microinstruction sequence is stored in a sequence of caches for subsequent use in subsequent clicks on the sequence. In this manner, the sequence cache enables access to the optimized microinstruction sequence upon subsequent clicks on the sequences, thereby accelerating the thermal encoding.

FIG. 6 shows a flow chart of the steps of another example hardware optimization process 600 in accordance with an embodiment of the present invention. As shown in FIG. 6, in accordance with another embodiment of the present invention, the flowchart shows that the operational steps of the optimization procedure are implemented in a dispatch/release phase of a microprocessor.

The process 600 begins in step 601, in which a received macro instruction sequence is captured using an instruction fetching component (such as the grabbing component 101 of FIG. 1). As mentioned above, the fetched instructions include compiling a sequence by predicting a particular instruction branch.

In step 602, the fetched macro instruction is transferred to a decoding component for decoding into a microinstruction. The macro instruction sequence is decoded into microinstructions according to branch prediction sequence. In one embodiment, the microinstruction sequence is then stored into a microinstruction cache.

In step 603, the decoded microinstructions are stored in a sequence in the microinstruction sequence cache. The sequence in the microinstruction cache is formed based on the basic block boundaries to begin. These sequences are not optimized at this time.

In step 604, the microinstruction sequence is then optimized by reordering the microinstructions containing the sequence into a dependency group. Reordering is performed by an instruction reordering component, such as instruction scheduling and optimizer component 110. This procedure is described in Figures 2 to 4.

In step 605, the optimized microinstruction sequence is an output to the microprocessor pipeline for execution. As described above, the optimized microinstruction sequence is forwarded to the remainder of the machine for execution (e.g., remaining pipeline 105).

Subsequently, in step 606, a copy of the optimized microinstruction sequence is stored in a sequence of caches for subsequent use in subsequent clicks on the sequence. In this manner, the sequence cache enables access to the optimized microinstruction sequence upon subsequent clicks on the sequences, thereby accelerating the thermal encoding.

Figure 7 shows a diagram showing the operation of the CAM matching hardware and the priority encoding hardware of the dispatch/release phase in accordance with an embodiment of the present invention. As illustrated in Figure 7, the destination of the command is to receive the CAM array from the left broadcast. Three sample instruction destinations are displayed. Lighter shaded CAMs (eg, green) are matched for true dependencies and output dependencies, so the destination is broadcast down. Darker shadow The CAM (eg blue) is inverted for affinity matching, so the destination is broadcast up. These matches aggregate a dependency matrix as described above. The priority encoder is shown on the right and it acts by scanning the columns of the CAM to find the first match, "_1" or "1_". As discussed above with respect to Figures 2 through 4, the program can be an iterative implementation. For example, if "_1" is blocked by "1_", the destination can be renamed and moved.

Figure 8 shows a diagram depicting an optimized scheduling instruction prior to a branch in accordance with an embodiment of the present invention. As shown in Figure 8, a hardware optimization example is shown side by side with a conventional timely compiler example. The left side of Figure 8 shows the original unoptimized code, which includes the branching error "Branch C to L1". The middle row of Figure 8 shows a traditional timely compiler optimization where the scratchpad is renamed and the instruction is moved before the branch. In this example, the timely compiler inserts a compensation code to account for those cases where the branch bias is determined to be wrong (eg, actually taking a branch, as opposed to not taking it). Conversely, the line to the right of Figure 8 shows the hardware expansion optimization. In this case, the scratchpad is renamed and the command is moved before the branch. However, it should be noted that no compensation code is inserted. The hardware continues to track whether the branch bias is true. In the case of a fault prediction branch, the hardware automatically returns to its state to execute the correct sequence of instructions. The hardware optimizer solution avoids the use of compensation coding because in those cases where the branch is a prediction of the error, the hardware jumps to the source code in the memory and executes the correct sequence from there, and flushes the error prediction. Sequence of instructions.

Figure 9 shows a diagram depicting an optimized schedule-loading prior to storage in accordance with an embodiment of the present invention. As shown in Figure 9, the hardware optimization paradigm is depicted along a conventional timely compiler paradigm. The left side of Figure 9 shows the original unoptimized code containing "R3<-LD[R5]". One line in the middle of Figure 9 shows Traditional and timely compiler optimization, where the scratchpad is renamed and the loader is moved to storage. In this example, the timely compiler inserts a compensation code to indicate that the address of the load instruction is the one that names the address of the store instruction (eg, the load is not appropriate before moving to storage). Conversely, the line to the right of Figure 9 shows the hardware expansion optimization. In this case, the scratchpad is renamed and the load is also moved to before storage. However, it should be noted that no compensation code is inserted. In the case of an error before the move is loaded into storage, the hard system automatically returns to its state to execute the correct sequence of instructions. The hardware optimizer solution can avoid the use of compensation coding, because in the case of the address alias-check branch is error prediction, the hardware jumps to the original code in the memory, and the correct sequence is executed there, simultaneously Clear the sequence of instructions for error prediction. In this case, the sequence is assumed to have no aliases. It should be noted that in one particular embodiment, the functionality illustrated in FIG. 9 may be performed by the instruction schedule and optimizer component 110 of FIG. Similarly, it should be noted that in a particular embodiment, the functionality illustrated in Figure 9 can be performed by software optimizer 1000 as described below in Figure 10.

Furthermore, with regard to dynamic unrolling sequences, it should be noted that instructions can predict branches (such as dynamically constructed branches) through previous paths by using renames. In the case of a non-dynamic predictive branch, the movement of the instruction should take into account the extent of the branch. The loop can be expanded to the desired range and optimization can be applied throughout the sequence. This can be done, for example, by renaming the destination register of the instruction that moves through the branch. One of the benefits of this feature is that it does not require compensation coding or extensive analysis of the range of branches. This feature therefore greatly speeds up and simplifies the optimization process.

Additional information regarding the compilation of branch predictions and sequences of instructions can be found in U.S. Patent Application Serial No. 61/384,198, entitled "Included for Early Dividing "Single Cycle Multi-Branch Prediction Including Shadow Cache For Early Far Branch Prediction", applied by Mohammad A. Abdallah on September 17, 2010, the overall content of which is incorporated This article.

10 shows a schematic diagram of an exemplary software optimization procedure in accordance with an embodiment of the present invention. In the particular embodiment of FIG. 10, the command schedule and optimizer components (such as member 110 of FIG. 1) are replaced by a software-based optimizer 1000.

In the particular embodiment of FIG. 10, software optimizer 1000 performs an optimization procedure performed by hardware-based instruction scheduling and optimizer component 110. The software optimizer maintains a copy of the optimized sequence in the memory hierarchy (eg, L1, L2, system memory). This allows the software optimizer to maintain a larger collection of optimized sequences than is stored in the sequence cache.

It should be noted that the software optimizer 1000 can include code that resides in the memory hierarchy, such as input for optimization and output from the optimization program.

It should be noted that in a particular embodiment, the microinstruction cache may be omitted. In this specific case example, only the optimized microinstruction sequence is cached.

11 shows a flow diagram of a SIMD software-based optimization procedure in accordance with an embodiment of the present invention. The top of Figure 11 shows how the software-based optimizer reviews each instruction of the input instruction sequence. Figure 11 shows how SIMD comparisons can be used to match one-to-many (e.g., SIMD byte comparison first source "Src1" with all second source bytes "Src2"). In a specific embodiment, Src1 contains any The destination scratchpad of the instruction, and Src2 contains a source from each of the other sequence instructions. A match is completed for each destination with all subsequent source of instructions (eg, a true dependency check). This is a pairing match that indicates the group required for the instruction. The matching is done between each destination and each subsequent instruction destination (eg, an output dependency check). This is a blocking match that can be renamed to resolve. The matching is done between each destination and each of the previous instruction sources (eg, reverse-phase checking). This is blocking the match, which can be renamed to resolve. The result can be used to assemble columns and rows of the dependency matrix.

12 shows a flow diagram of an exemplary SIMD software-based optimization procedure 1200, in accordance with an embodiment of the present invention. The program 1200 is described in the context of the flow chart of FIG.

In step 1201, the input sequence of instructions is accessed by using a software-based optimizer that is instantiated to one of the memories.

In step 1202, a dependency matrix is populated using a SIMD instruction having dependency information retrieved from the input sequence of instructions by using a sequence of SIMD comparison instructions.

In step 1203, the columns of the matrix are scanned from right to left for the first match (eg, the dependency flag).

In step 1204, each first match is analyzed to determine the type of match.

In step 1205, if the first flag matches as a blocking dependency (blocking) Requires a complete renaming for this destination.

In step 1206, all first matches for each column of the matrix are identified, and the row corresponding to the match is moved to a given dependency group.

In step 1207, the scanning process is repeated several times to reorder the instructions containing the input sequence to produce an optimized output sequence.

In step 1208, the optimized instruction sequence is output to the execution pipeline of the microprocessor for execution.

In step 1209, the optimized output sequence is stored in a sequence of caches for subsequent consumption (eg, accelerated thermal coding).

It should be noted that software optimization can be done serially using SIMD instructions. For example, optimization can be implemented by processing an instruction at the source and destination of a scan instruction at a time (eg, from an earlier instruction in a sequence to a subsequent instruction). According to the above optimization algorithm and SIMD instruction, the software uses SIMD instructions to compare current command sources and destinations with previous instruction sources and destinations in parallel (eg, detecting true dependencies, output dependencies, and inverse dependencies). ).

Figure 13 shows a software-based dependency broadcast procedure in accordance with an embodiment of the present invention. The embodiment of Figure 13 shows a flow diagram of an exemplary software scheduling program that processes groups of instructions without the expense of implementing a complete parallel hardware implementation as described above. However, the FIG. 13 embodiment may still use SIMD to process smaller groups of instructions in parallel.

The software scheduling procedure of Fig. 13 is performed as follows. First, the program initializes three registers. The program takes the instruction number and loads it into the first scratchpad. The program then takes the destination scratchpad number and loads it into the second scratchpad. Next, the program takes the value in the first register and broadcasts it to a location in the third result register based on a location number in the second register. The program is then overwritten from left to right in the second register, and in those cases where the broadcaster proceeds to the same location in the result register, the leftmost value will overwrite the value to the right. The location that has not been written in the third scratchpad will be bypassed. This information is used to assemble a dependency matrix.

The particular embodiment of Figure 13 also shows the manner in which the input sequence of instructions can be processed into a plurality of groups. For example, 16 instruction input sequences can be processed as a first group of 8 instructions and a second group of 8 instructions. In the first group, the instruction number is loaded into the first register, the instruction destination number is loaded into the second register, and the value in the first register is based on the second register. The location number is broadcasted to a location in the third register (eg, the result register) (eg, a group broadcast). The location that has not been written in the third scratchpad will be skipped. The third register is now the basis for processing the second group. For example, the result register from group 1 now becomes the result register for group two.

In the second group, the instruction number is loaded into the first register, the instruction destination number is loaded into the second register, and the value in the first register is based on the location in the second register. The number is broadcast to the location in the third register (such as the result register). The location in the third register can overwrite the result written during the first group processing. The location that has not been written in the third scratchpad will be skipped. On this side In the formula, the second group updates the basis from the first group, and thus generates a new basis for the processing of the third group, and the like.

The instructions in the second group may inherit the dependency information generated in the processing of the first group. It should be noted that it is not necessary to process all of the second groups to update the dependencies in the result register. For example, the dependencies of the instructions 12 may be generated in the processing of the first group, followed by the instructions in the second group up to the instruction 11. This updates the result register to a state up to instruction 12. In a particular embodiment, a mask can be used to avoid updating of the remaining instructions of the second group (eg, instructions 12 through 16). To determine the dependencies of instruction 12, the resulting registers are reviewed for R2 and R5. R5 will be updated with instruction 1, and R2 will be updated with instruction 11. It should be noted that in the case where group 2 is all processed, R2 will be updated with instruction 15.

Furthermore, it should be noted that all instructions of the second group, such as instructions 9 through 16, can be processed independently of each other. In this case, the instructions of the second group rely only on the result register of the first group. Once the result register is updated from the processing of the first group, the instructions of the second group can be processed in parallel. In this manner, the group of instructions can be processed in parallel in parallel. In one embodiment, each group is processed using SIMD instructions (such as SIMD broadcast instructions) whereby all instructions for each group are processed in parallel.

14 shows an example flow diagram showing how a dependency group of instructions can be used to establish a variable bounding group of dependencies instructions in accordance with an embodiment of the present invention. In the description of Figures 2 through 4, the size of the group is limited, in each case three instructions per group. Figure 14 shows how the instructions can be reordered into groups of variable sizes, which can then be dispatched to a plurality of computing engines. For example, Figure 14 shows Show 4 engines. Since the group can be variably sized according to its characteristics, the engine 1 can assign a group larger than, for example, the engine 2. This may occur, for example, in the case where the engine 2 has instructions that are not specifically dependent on one of the other instructions in the group.

Figure 15 shows a flow diagram illustrating hierarchical scheduling of instructions in accordance with an embodiment of the present invention. As mentioned previously, a dependency group of instructions can be used to establish a variable bounding group. Figure 15 shows features in which various levels of dependencies exist within a dependency group. For example, instruction 1 does not depend on any other instruction within this sequence of instructions, thus making instruction 1 a L0 dependency level. However, instruction 4 is dependent on instruction 1, thus making instruction 4 an L1 dependency level. In this manner, each instruction of the sequence of instructions assigns a dependency level as shown.

The dependency level for each instruction is used by the second level hierarchy scheduler to distribute the instructions in such a way as to ensure that available resources are available for the dependency instructions to execute. For example, in one embodiment, the L0 command loads the array of instructions processed by the second level schedulers 1 through 4. The L0 instruction is loaded so that it is loaded before each queue, after the L1 instruction is loaded, after each queue, after the L2 instruction is tied, and so on. In Figure 15, this is shown by the dependency level, from L0 to Ln. The hierarchical scheduling of schedulers 1 through 4 advantageously utilizes locality-in-time and instruction-dependent dependencies to make scheduling decisions in an optimal manner.

In this manner, embodiments of the present invention display dependency group slot allocation of instructions of a sequence of instructions. For example, implementing an out-of-order micro-architecture, the instruction of the instruction sequence is unordered. In a specific embodiment, the readiness of the instructions is checked in each cycle. If all instructions are dependent on one instruction This order is ready when it has been previously delivered. The scheduler structure acts by examining those dependencies. In a specific embodiment, the scheduler is a joint scheduler and all dependencies are performed in the joint scheduler structure. In another embodiment, the scheduler function is distributed across a distribution queue of execution units of a plurality of engines. Thus, in one embodiment the scheduler is united, while in another embodiment the scheduler is decentralized. With both solutions, each instruction source checks the source of each instruction at each destination.

Thus, Figure 15 shows a hierarchical schedule performed by a particular embodiment of the present invention. As before, the instructions are first grouped to form a dependency chain (eg, a dependency group). Information about these dependency chains can be done statically or dynamically by software or hardware. Once these dependency chains have been formed, they can be distributed/distributed to an engine. In this manner, the grouping by dependency allows for out-of-order scheduling of groups that are sequentially formed. The group of dependencies also spreads all of the dependency groups to a plurality of engines (such as cores or threads). Grouping by dependency also contributes to hierarchical scheduling, as described above, wherein the dependency instructions are grouped in the first step and scheduled in the second step.

It should be noted that the functions illustrated in Figures 14 through 19 may function independently of any method by which the instructions are grouped (e.g., whether the grouping function is performed by hardware, software, etc.). In addition, the dependency group shown in FIGS. 14 to 19 may include a matrix of dependency groups, wherein each group further includes a dependency instruction. In addition, it should be noted that the scheduler can also be an engine. In this particular embodiment, each of schedulers 1 through 4 can be incorporated into its individual engines (as shown in Figure 22, where each segment contains a common partition scheduler).

Figure 16 shows a flow chart showing three according to an embodiment of the present invention. The hierarchical schedule of the slot dependency group instruction. As previously mentioned, a dependency group of instructions can be used to establish a variable bounding group. In this particular embodiment, the dependency group contains three slots. Figure 16 shows the various levels of dependency averaged in a three-slot dependency group. As previously mentioned, instruction 1 does not depend on any other instructions in this sequence of instructions, thus making instruction 1 a L0 dependency level. However, instruction 4 is dependent on instruction 1, thus making instruction 4 an L1 dependency level. In this manner, each instruction of the sequence of instructions assigns a dependency level as shown.

As previously mentioned, the dependency level of each instruction is used by the second level hierarchy scheduler to distribute the instructions in such a way as to ensure that available resources are available for the dependency instructions to execute. The L0 command loads the array of instructions processed by the second level schedulers 1 through 4. The L0 instruction is loaded so that it is loaded before each queue, the L1 instruction is loaded after each queue, the L2 instruction is connected after it, etc., as shown by the dependency level, from L0 of Figure 16 to Ln. It should be noted that the group number four (eg, from the top fourth group) begins at L2, even if it is an independent group. This is because instruction 7 is dependent on instruction 4, which in turn depends on instruction 1, and thus instruction 7 is L2 dependent.

In this manner, Figure 16 shows that every three dependency commands are collectively scheduled on one of the given schedulers 1 through 4. The second level group is scheduled after the first level group, and then the group is rotated.

17 shows a flow diagram illustrating a hierarchical movement window schedule for a three-slot dependency group instruction in accordance with an embodiment of the present invention. In this particular embodiment, the hierarchical scheduling of the three-slot dependency group is performed via a joint mobile window scheduler. The mobile window scheduler processes the instructions in the queue and distributes the instructions in one way. Order to ensure that resources are available for dependencies to execute. As previously mentioned, the L0 command loads the array of instructions processed by the second level schedulers 1 through 4. The L0 instruction is loaded so that it is loaded before each queue, the L1 instruction is loaded after each queue, the L2 instruction is connected after it, etc., as shown by the dependency level, from L0 of Figure 17 to Ln. The moving window describes how the L0 command can be dispatched from each queue, even though it can be more than one queue in a queue. In this manner, the mobile window scheduler is a distribution instruction such as a left-to-right queue flow, as shown in FIG.

Figure 18 illustrates how a variable size dependency chain (e.g., a variable bounding group) of instructions is dispatched to a plurality of computing engines in accordance with an embodiment of the present invention.

As shown in FIG. 18, the processor includes an instruction scheduler component 10 and a plurality of engines 11 to 14. The instruction scheduler component generates code blocks and genetic vectors to support the execution of dependent code blocks (eg, variable bound groups) on their respective engines. Each dependency coding block may belong to the same logical core/thread or belong to a different logical core/thread. The instruction scheduler component will process the dependent coding block and the individual genetic vectors. These dependency coding blocks and individual genetic vector systems are assigned to specific engines 11 through 14, as shown. The universal interconnect 30 supports the necessary communication for each of the engines 11 through 14. It should be noted that the grouping of dependencies relating to instructions to establish a variable bounding group of dependencies instructions (as discussed above with respect to FIG. 14) is performed by the command scheduler component 10 of the FIG. 18 embodiment.

FIG. 19 shows a flow chart illustrating a hierarchical movement window schedule for a block assignment to a schedule queue and a three slot dependency group instruction in accordance with an embodiment of the present invention. As mentioned above, the hierarchical scheduling of the three-slot dependency group can be performed via a joint mobile window scheduler. Figure 19 shows how the dependency group becomes loaded into the schedule queue. Block. In the particular embodiment of Figure 19, two dependency groups can load each queue as a half block. This is shown at the top of Figure 19, where group 1 forms a half block and group 4 forms another half block that is loaded into the first schedule queue.

As previously mentioned, the mobile window scheduler processes the instructions in the queue, distributing the instructions in such a way as to ensure that available resources are available for the dependency instructions to execute. The bottom of Figure 19 shows how the L0 instruction is loaded into the array of instructions processed by the second level scheduler.

20 illustrates how dependency coding blocks, such as dependency groups or dependency chains, are executed on engines 11 through 14, in accordance with an embodiment of the present invention. As previously described, the instruction scheduler component generates code blocks and inheritance vectors to support the execution of dependent code blocks (eg, variable bound groups, three-slot groups, etc.) on their respective engines. As illustrated in Figure 19, Figure 20 further shows how two independent groups can be loaded into each engine as a coded block. Figure 20 shows how these coded blocks are distributed to engines 11 through 14, where the dependency instructions are executed on a stack (e.g., serially connected) execution units of each engine. For example, in the upper left of FIG. 20, in the first dependency group or the code block, the instructions are distributed to the engine 11, wherein they are stacked on the execution unit in the order of their dependencies, so that the L0 system is stacked on The top of L1, while the L1 is stacked on L2. As such, the result of L0 flows to the execution unit of L1, which in turn can flow to the execution of L2.

In this manner, the dependency group shown in FIG. 20 may include a matrix of independent groups, wherein each group further includes a dependency instruction. The benefit of group independence is the ability and attributes to distribute and execute them in parallel, thereby minimizing the need to traverse interconnected communications between engines. In addition, it should be noted that it is displayed on engines 11 to 14 The execution unit in the middle can include a CPU or a GPU.

In accordance with an embodiment of the present invention, it is understood that the instruction extracts a received dependency group or block or instruction matrix based on its dependencies. Grouping instructions based on their dependencies facilitate a more streamlined scheduling procedure with larger instruction windows, such as larger instruction input sequences. The aforementioned grouping removes the instruction changes and uniformly extracts the variation, thus allowing for simple, homogeneous, and uniform scheduling decisions. The above grouping function increases the throughput of the scheduler without increasing the complexity of the scheduler. For example, in a scheduler for four engines, the scheduler can deliver four groups, with each group having three instructions. In this way, the scheduler only handles the superscalar complexity of the four lanes and delivers 12 instructions at the same time. In addition, each block can contain parallel independent groups that increase the number of delivery instructions.

21 shows an overview of a plurality of engines and their components, including a multi-core processor, a universal front-end grab & scheduler, and a scratchpad file, a universal interconnect, and a component, in accordance with an embodiment of the present invention. Fragment memory subsystem. As shown in Fig. 21, four memory segments 101 to 104 are displayed. The memory fragment hierarchy is the same at each cache level (eg L1 cache, L2 cache, and load store buffer). Data can be exchanged between each L1 cache, each L2 cache, and each load storage buffer via memory universal interconnect 110a.

The memory universal interconnect includes a routing matrix that allows a plurality of cores (such as address calculation and execution units 121-124) to access data, and the data can be stored in the segment cache hierarchy (eg, L1 cache, load storage buffer, and Any point in L2 cache). Figure 21 also illustrates the manner in which each of the segments 101-104 can be accessed by the address calculation and execution units 121-124 via the memory universal interconnect 110a.

Execution universal interconnect 110b similarly includes a routing matrix that allows a plurality of cores (e.g., address calculation and execution units 121-124) to access data stored in any sector register file. Thus, the core has access to the data stored in any of the segments and the data stored in any of the segments via the memory universal interconnect 110a or the universal interconnect 110b.

Figure 21 further shows a generic front-end grab/schedule that has an observation of the overall machine and that manages the use of the scratchpad file section and the segment memory subsystem. The address generation contains the basis for the definition of the fragment. The generic front-end crawler & scheduler acts by dispatching a sequence of instructions to each section.

Figure 22 shows a plurality of segments, a plurality of segments sharing a scheduler and interconnects and a segment to a segment, in accordance with an embodiment of the present invention. As shown in Figure 22, each segment is shown as having a common partition scheduler. The common partition scheduler acts by scheduling instructions within its individual sections. These instructions are then received from the general front end grab and scheduler. In this particular embodiment, the general purpose scheduler is configured to work in conjunction with a generic front end grab and scheduler. The section is also shown with four read writes, which provide read/write access to the operand/result buffer, thread register file, and common partition scheduler.

In a specific embodiment, a decentralized access procedure is performed to control access to each competing resource using a reserved adder and a critical limiter using interconnects and local interconnects, in this case, to each zone The paradox of the paragraph. In this embodiment, in order to access a resource, a core needs to retain the required bus and the bandwidth required for the flow.

23 shows a diagram of an example microprocessor pipeline 2200 in accordance with an embodiment of the present invention. Microprocessor pipeline 2200 includes a capture module 2301 that performs the functions of the program to identify and retrieve instructions that include an execution, as previously described. In the specific embodiment of FIG. 23, the capture module is followed by a decoding module 2202, a dispatch module 2203, a distribution module 2204, an execution module 2205, and a retirement module 2206. It should be noted that microprocessor pipeline 2200 is merely an example of a pipeline that performs the functions of the specific embodiments of the invention described above. Those skilled in the art will appreciate that other microprocessor pipelines can be implemented to include the functionality of the above described decoding modules.

For the purposes of explanation, the foregoing description refers to specific embodiments, which are not intended to be exhaustive or limiting. There may be many modifications and variations in compliance with the above teachings. The present invention has been chosen and described in order to best explain the embodiments of the invention .

10‧‧‧Instruction Scheduler Components

11‧‧‧ Engine

12‧‧‧ Engine

13‧‧‧ Engine

14‧‧‧ engine

30‧‧‧Common Interconnect

100‧‧‧Microprocessor

101‧‧‧Grab components

102‧‧‧ Native decoding components

103‧‧‧Multiplexer

104‧‧‧Multiplexer

105‧‧‧Remaining pipeline

110‧‧‧Instruction scheduling and optimizer components

110a‧‧‧Memory General Interconnect

110b‧‧‧Executing universal interconnection

121‧‧‧Micro-instruction cache

122‧‧‧Sequence cache

123‧‧‧Address calculation and execution unit

124‧‧‧Address calculation and execution unit

130‧‧‧Exit and fill path

1000‧‧‧Software Optimizer

2200‧‧‧Microprocessor pipeline

2201‧‧‧Grab module

2202‧‧‧Decoding module

2203‧‧‧Distribution module

2204‧‧‧Distribution module

2205‧‧‧Execution module

2206‧‧‧Retirement module

The present invention is described by way of example and not by way of limitation, and in the FIG.

1 shows a schematic diagram of a dispatch/release phase of a microprocessor in accordance with an embodiment of the present invention; FIG. 2 shows a schematic diagram depicting an optimization procedure in accordance with an embodiment of the present invention; FIG. 3 shows a schematic diagram in accordance with the present invention. A multi-step optimization program of a specific embodiment; FIG. 4 shows a multi-step optimization and instruction movement program according to an embodiment of the present invention; FIG. 5 shows an example hardware according to an embodiment of the present invention. Optimal process FIG. 6 shows a flow chart of steps of another example hardware optimization process in accordance with an embodiment of the present invention; FIG. 7 shows a diagram showing a dispatch/release phase in accordance with an embodiment of the present invention. CAM Matching Hardware and Priority Encoding Hardware Operation; FIG. 8 shows a diagram depicting an optimized schedule prior to a branch in accordance with an embodiment of the present invention; FIG. 9 shows a diagram depicting FIG. 10 shows a schematic diagram of an exemplary software optimization procedure in accordance with an embodiment of the present invention; FIG. 11 shows a SIMD based on a specific embodiment of the present invention. Flowchart of a software optimization process; FIG. 12 is a flow chart showing an SIMD software-based optimization procedure according to an embodiment of the present invention; FIG. 13 is a software-based dependency according to an embodiment of the present invention. Sex broadcast program.

14 shows an example flow diagram showing how a dependency group of instructions is used to establish a variable bounding group of dependencies in accordance with an embodiment of the present invention; FIG. 15 shows a flowchart depicting FIG. 16 shows a hierarchical flowchart illustrating a hierarchical scheduling of a three-slot dependency group instruction according to an embodiment of the present invention; FIG. 17 shows a flowchart. A hierarchical movement window schedule of a three-slot dependency group instruction according to an embodiment of the present invention is illustrated; 18 illustrates how a variable size dependency chain (eg, a variable bounding group) of instructions is dispatched to a plurality of computing engines in accordance with an embodiment of the present invention; FIG. 19 shows a flowchart depicting an implementation in accordance with the present invention. The block of the example is assigned to the hierarchical movement window schedule of the scheduling queue and the three-slot dependency group instruction; FIG. 20 shows the dependency coding block (such as the dependency group or the dependency chain according to an embodiment of the invention) How to execute on the engine; Figure 21 shows an overview of a plurality of engines and their components, including a multi-core processor, a generic front-end crawler & scheduler, and a scratchpad file, in accordance with an embodiment of the present invention. , a general-purpose interconnect, and a segment memory sub-system; FIG. 22 shows a plurality of segments, a plurality of segments, a common partition scheduler, and interconnects and segments to the segments according to an embodiment of the present invention; 23 shows a diagram of an exemplary microprocessor pipeline in accordance with an embodiment of the present invention.

101‧‧‧Grab components

102‧‧‧ Native decoding components

103‧‧‧Multiplexer

104‧‧‧Multiplexer

105‧‧‧Remaining pipeline

110‧‧‧Instruction scheduling and optimizer components

121‧‧‧Micro-instruction cache

122‧‧‧Sequence cache

130‧‧‧Exit and fill path

Claims (21)

A method for speeding up encoding optimization in a microprocessor, comprising: using an instruction fetching component to fetch a received macro instruction sequence; transferring the fetched macro instruction to a decoding component to decode a microinstruction; performing an optimization procedure by reordering the microinstruction sequence to optimize a microinstruction sequence comprising one of a plurality of dependency encoding groups; outputting the plurality of dependent encoding groups to the microprocessor A plurality of engines are executed in parallel; and a copy of the optimized microinstruction sequence is stored to a sequence of caches for subsequent use in subsequent clicks on one of the optimized microinstruction sequences. The method of claim 1, wherein the replica of the decoded microinstruction is stored in a microinstruction cache. The method of claim 1, wherein the optimizing program is executed using one of the dispatch and release phases of the microprocessor. The method of claim 3, wherein the dispatching and publishing phase further comprises an instruction scheduling and optimizer component, the instruction scheduling and optimizer component reordering the microinstruction sequence as the optimization micro Instruction sequence. The method of claim 1, wherein the optimizing program further comprises dynamically expanding the sequence of microinstructions. The method of claim 1, wherein the optimizing the program is performed via a plurality of iterations. The method of claim 1, wherein the optimizing program is executed by a register renaming program to enable the reordering. A microprocessor includes: an instruction fetching component for fetching a received macro instruction sequence; a decoding component coupled to the instruction fetching component to receive the fetched macro instruction sequence and decoding a microinstruction sequence; a dispatching and issuing phase coupled to the decoding component to receive the microinstruction sequence, by reordering the microinstruction sequence to perform one of a plurality of dependent coding groups to optimize the microinstruction sequence An optimization engine; a plurality of engines of the microprocessor coupled to the dispatch and release phase to receive a plurality of dependent code groups for execution in parallel; and a sequence of caches coupled to the dispatch and release phase for receiving And storing a copy of the optimized microinstruction sequence for subsequent use in subsequent clicks on one of the optimized microinstruction sequences. The microprocessor of claim 8 wherein the copy of the decoded microinstruction is stored in a microinstruction cache. The microprocessor of claim 8 wherein the optimizing program is executed using one of the dispatch and release phases of the microprocessor. The microprocessor of claim 10, wherein the dispatching and publishing stages The segment further includes an instruction scheduler and optimizer component, and the instruction scheduler and optimizer component reorders the microinstruction sequence into the optimized microinstruction sequence. The microprocessor of claim 8, wherein the optimizing program further comprises dynamically expanding the sequence of microinstructions. The microprocessor of claim 8, wherein the optimizing program is executed via a plurality of iterations. The microprocessor of claim 8, wherein the optimizing program is executed by a register renaming program to enable the reordering. A method for speeding up encoding optimization in a microprocessor, comprising: accessing an input microinstruction sequence using a software-based optimizer entityized in the memory; using the SIMD instruction to assemble the slave Inputting a dependency matrix of the dependency information of the microinstruction sequence; scanning a plurality of columns of the dependency matrix to optimize the microinstruction sequence by reordering the microinstruction sequence to one of a plurality of dependent coding groups An instruction sequence is executed to perform an optimization process; outputting the plurality of dependency coding groups to the plurality of engines of the microprocessor for execution in parallel; and storing a copy of the optimized microinstruction sequence to a sequence of caches, For subsequent use in subsequent clicks on one of the optimized microinstruction sequences. The method of claim 15, wherein the optimizing program further comprises scanning a plurality of columns of the dependency matrix to identify matching instructions. The method of claim 16, wherein the optimizing program further comprises analyzing the matching instruction to determine whether the matching instruction includes a blocking dependency, and wherein the renaming is performed to remove the blocking dependency. The method of claim 17, wherein the first matching instruction sequence for each column of the dependency matrix is moved into a corresponding dependency group. The method of claim 15 wherein the copy of the optimized microinstruction sequence is stored in a memory hierarchy of the microprocessor. The method of claim 19, wherein the memory hierarchy comprises an L1 cache and an L2 cache. The method of claim 20, wherein the memory hierarchy further comprises a system memory.