TW201316677A - Method for designing wideband low noise amplifier - Google Patents

Abstract

The present invention discloses a method for designing a wideband low-noise amplifier (LNA), which is processed with a simulation software. The method is mainly to design the wideband LNA constructed by cascading a common-gate amplifier and a common-source amplifier with an inter-stage matching network. According to a predetermined design frequency band to obtain a resonant frequency and choosing the transistor specifications of the common-gate amplifier and the common-source amplifier, conjugate matching at high and low bands of the common-gate amplifier and the common-source amplifier is achieved by applying the proposed matching technique and the mid-band gain is compensated for by the common-source amplifier. After combining the two amplifiers to form the wideband LNA, the wideband LNA provides enough gain in the entire band. The method of the invention quickly and efficiently enables a wideband LNA design.

Description

Design method of broadband low noise amplifier

The invention is a design method of a broadband low noise amplifier, and particularly relates to a design method of a broadband low noise amplifier applied to a communication system.

In broadband wireless communication systems, the most challenging task in designing a wideband low noise amplifier is impedance matching and minimum noise index matching. The parasitic effects and impedance matching techniques of conventional transistors often limit the bandwidth of amplifiers. For example, "An ultrawideband CMOS low noise amplifier for 3.1-10.6 GHz wireless receivers" published in the IEEE Transactions of Solid State Circuits in 2004 is Using the LC ladder-filter method for input matching, the LC ladder filter is placed at the input of the common source amplifier, but the insertion loss of the opposite LC ladder filter increases the noise index.

Another example is the "A 3.1-10.6 GHz ultrawideband CMOS low noise amplifier with current-reused technique" published in "IEEE Microwave Wireless Comp. Lett." in 2007, in which another intermediate-level inductor-capacitor circuit is used to increase the power gain. However, the noise index in the 10 GHz band is as high as about 6 dB, and this circuit architecture will result in a higher noise index.

"Radio frequency integrated circuits and technologies" published by F. Ellinger in "Springer" in 2007 revealed a technique for reducing the parasitic effect of capacitance by using a higher gate voltage to a small-sized transistor while maintaining transduction. Content, so at the same noise size, a wider frequency band can be obtained. However, this technical content still increases power consumption and bandwidth is still limited.

In the prior art, although the distributed amplifier can provide a larger bandwidth, it also has a larger power consumption, occupies a larger wafer area, and has a higher noise index. For example, in "IEEE Microwave Wireless Comp. Lett." in 2007, the "A 0.6v low power UWB CMOS LNA" was used, which used a large wafer area and caused problems in chip design and product application.

In order to have better noise index and stability characteristics, a conventional wideband amplifier has been designed using negative feedback techniques, such as "Resistive-feedback low-noise" published by IEEE Trans. Microwave Theory Tech. in 2008. "Amplifers for multiband applications" uses the aforementioned negative feedback technique to make the amplifier have a low noise index and better stability characteristics. For example, in "2010 Trans. Microwave Theory Tech.", "Low-noise" Amplifier design with dual reactive feedback for broadband simultaneous noise and impedance matching uses a dual reactance feedback method to achieve wideband low noise and impedance matching for a common source amplifier, or for example, IEEE Trans. Microwave Theory Tech. "Analysis and design of a CMOS UWB LNA with dual-RLC branch wideband input matching network" is designed to provide a noise figure of 3.7-4.7 dB in the 3.1-10.6 GHz band using resistor feedback and inductance compensation techniques. However, using a negative feedback technique to design a wideband amplifier can replace the flatness of the wideband gain, but it will degrade the gain and noise index.

The common gate structure is a well-known broadband characteristic and input impedance matching technique. However, the common-gate amplifier of the first stage does not have enough gain, so multi-level common-gate amplifiers must be connected in series to increase the gain, for example, IEEE Int. The "A wideband mm-wave CMOS receiver for Gb/s communications employing interstage coupled resonator" disclosed in Solid-State Conf." is designed by designing a V-band series-connected common-source amplifier and using coupled resonance as an intermediate-level matching circuit. In order to obtain a wide-band low-noise amplifier, but due to the matching problem of the intermediate-level matching circuit, the bandwidth is reduced.

Based on the shortcomings of the above-mentioned prior art, if a method for rapidly designing a broadband low noise amplifier can be provided, the time for attempting errors in the design process can be shortened and the miniaturization cost of the broadband application product can be reduced, and by this method Design amplifiers with low noise index, impedance matching, and wideband gain.

The invention relates to a design method of a broadband low noise amplifier circuit, which is connected with an intermediate matching circuit between a common gate amplifying circuit and a common source amplifying circuit, and transmits a common gate amplifying circuit in a low frequency band and a high frequency band. It has a higher gain, and the common source amplifying circuit has a higher gain in the middle frequency band, so that the combined wide frequency low noise amplifier circuit can have sufficient gain over the entire wide frequency band, and by designing the intermediate matching circuit The inductor and the inductance connected to the common gate amplifying circuit and the common source amplifying circuit thereby extending the bandwidth.

The invention provides a design method of a broadband low noise amplifier circuit, which is matched with an analog software. The design method comprises the following steps: providing a broadband low noise amplifier circuit, comprising: a common gate amplification circuit, comprising a a first input end and a first output end, the common gate amplifying circuit is externally connected with a first inductor and a second inductor; a common source amplifying circuit includes a second input end and a second output end, the common source The pole amplifier circuit is externally connected with a third inductor; and an intermediate matching circuit includes a fourth inductor, the fourth inductor is connected in series between the first output end and the second input end; and a predetermined design frequency band is determined by X GHz~ Y GHz is provided to the first input terminal, and a resonant frequency is derived by designing the frequency band calculation; selecting a transistor, which selects a transistor specification and a bias voltage of the common gate amplifying circuit and the common source amplifying circuit; The first input end is impedance matched, which adjusts the first inductance to match the first input end to the resonant frequency; adjusts the first output end impedance matching, which adjusts the second inductance to make the first input End-to-resonance frequency matching; designing a third inductance value, which adjusts the third inductance so that the input impedance of the common source amplifying circuit reaches a design resistance value; adjusting the impedance matching of the intermediate matching circuit, which adjusts the fourth inductance to make the middle The input end of the matching circuit and the first output end reach a resonance frequency; and the optimal gain and the optimal input matching of the common source amplifying circuit are adjusted, and the third inductance is adjusted again to make the gain and the bandwidth of the common source amplifying circuit reach the maximum Jiahua.

With the implementation of the present invention, at least the following advancements can be achieved:

First, it can quickly estimate the approximate position of high frequency, intermediate frequency and low frequency to achieve broadband characteristics.

Second, it can effectively save time in trying to make mistakes in the design process.

Third, can be used to design broadband low noise amplifiers in different frequency bands.

In order to make those skilled in the art understand the technical content of the present invention and implement it, and according to the disclosure, the patent scope and the drawings, the related objects and advantages of the present invention can be easily understood by those skilled in the art. The detailed features and advantages of the present invention will be described in detail in the embodiments.

FIG. 1 is a flow chart of a method for designing a broadband low noise amplifier circuit according to an embodiment of the present invention. 2 is a circuit block diagram of a broadband low noise amplifier according to an embodiment of the present invention. FIG. 3A is a circuit diagram of a broadband low noise amplifier circuit having a frequency band of 3.1-10.3 GHz according to an embodiment of the present invention. FIG. 3B is a circuit diagram of a broadband low noise amplifier circuit having a frequency band of 14.3-29.3 GHz according to an embodiment of the present invention. 4A and 4B are diagrams showing a transistor small signal analysis circuit of a broadband low noise amplifier according to an embodiment of the present invention. Figure 5 is a plot of the input/output impedance of the intermediate matching circuit in the 3.1-10.3 GHz band. Figure 6 is a plot of the input/output impedance of the intermediate matching circuit in the analog 14.3-29.3 GHz band. Figure 7 is a diagram showing the relationship of the output gain characteristic curve of the analog 3.1-10.3 GHz band according to an embodiment of the present invention. Figure 8 is a diagram showing the relationship of the output gain characteristic curves of the analog 14.3-29.3 GHz band according to an embodiment of the present invention.

As shown in FIG. 1, this embodiment is a design method of a broadband low noise amplifier circuit (step S100), which is performed in conjunction with a simulation software. The component model used in this embodiment is a standard component model, and is simulated by the RF circuit simulation software Agilent ADS, and then the characteristics can be adjusted through the analog software. The simulation software can simulate the microwave RF IC and design the complete front-end circuit to the back-end circuit. And layout.

The design method of the broadband low noise amplifier circuit (step S100) comprises the steps of: providing a broadband low noise amplifier circuit (step S10); predetermining a design frequency band (step S20); selecting a transistor (step S30); adjusting the first Input impedance matching (step S40); adjusting first output impedance matching (step S50); designing a third inductance value (step S60); adjusting intermediate matching circuit impedance matching (step S70); and adjusting the common source amplifying circuit Good gain and optimal input matching (step S80).

As shown in FIG. 2, a wideband low noise amplifier circuit is provided (step S10): the wideband low noise amplifier circuit 100 used in this embodiment includes at least: a common gate amplifying circuit 200; a common source amplifying circuit 400; An intermediate matching circuit 300 in which the common gate amplifying circuit 200, the intermediate matching circuit 300, and the common source amplifying circuit 400 are serially connected in series.

The broadband low noise amplifier circuit 100 has a signal input terminal RF _in and a signal output terminal RF _out , and the signal input terminal RF _in is used to receive an RF signal, and passes through the common gate amplifying circuit 200, the intermediate matching circuit 300 and After the common source amplifying circuit 400, an amplified output signal is outputted from the signal output terminal RF _out . In practical applications, the broadband low noise amplifier circuit 100 of the present embodiment can be integrated into a wireless communication device or a mobile phone device for use as a low noise amplifier in a wideband receiving circuit system.

As shown in FIGS. 3A and 3B, the common gate amplifying circuit 200 includes a first transistor M ₁ connected in parallel with a first sub-crystal M _1a and a second sub-crystal M _1b . The gate, the source and the drain are connected to each other to form a common gate amplifying circuit 200.

The common gate amplifying circuit 200 includes a first input terminal IP ₁ and a first output terminal OP ₁ , wherein the first input terminal IP _{1 is} the source of the first sub-transistor M _1a and the second sub-transistor M _1b The first output terminal OP ₁ is the drain of the first sub-transistor M _1a and the second sub-transistor M _1b . A first inductor L _{1 is} connected between the first input terminal IP _{1 of the} common gate amplifying circuit 200 and a ground terminal, and a DC blocking capacitor C _b1 is further connected in series between the first input terminal IP ₁ and the signal input terminal RF _in .

The gates of the first sub-transistor M _1a and the second sub-transistor M _1b are also connected to a fixed voltage source V _g1 to provide gate bias of the first sub-transistor M _1a and the second sub-transistor M _1b a voltage, and a grounding capacitor C _bp1 is connected in series between the fixed voltage source V _g1 and the ground to isolate the noise, and the drain of the fixed voltage source V _g1 and the first sub-crystal M _1a and the second sub-crystal M _1b There is a second inductance L ₂ connected in series.

In addition, the first sub-transistor M _1a and the second sub-transistor M _1b in the common gate amplifying circuit 200 may be an N-type metal oxide semiconductor transistor (NMOS), and may be oxidized by a multi-finger gate gate metal. The structure of the semiconductor transistor (Multi-finger MOSFET), for example, the first sub-transistor M _1a and the second sub-crystal M _1b may have 47 multi-fingers gate structures, and the total gate width is 70.5. The bias voltage of the output of μm, the fixed voltage source V _g1 is 0.7V, the transconductance g _m1 is 0.05 s, and each of the interdigitated forms is 1.5 μm wide.

In this embodiment, the system provides a first transistor M ₂ through inductor L by a second fixed voltage source bias voltage V _{g1 1} drain electrode and gate electrode. In actual operation, the first transistor M ₁ can provide a gain signal amplification function to the input signal terminal RF _in , and transmit the amplified signal to the common source amplifying circuit 400 via the intermediate matching circuit 300 . Since the first transistor M ₁ is integrally connected by the first sub-crystal M _1a and the second sub-crystal M _1b , if the inter-fork width is less than 1 μm, the cutoff frequency will be reduced. Therefore, appropriately reducing the resistance of the gate terminal not only increases the cutoff frequency, but also reduces the noise index.

As shown in FIG. 3A, the common source amplifying circuit 400 may be a common-source cascode amplifying circuit or a common-source cascade amplifying circuit as shown in FIG. 3B. . In the circuit architecture shown in FIG. 3A, the wideband low noise amplifier circuit 100 operates between 3.1 GHz and 10.3 GHz, and in the circuit architecture shown in FIG. 3B, the wide frequency low noise amplifier circuit 100 operates. Between 14.3 GHz and 29.3 GHz.

As shown in FIG. 3A, in the broadband low noise amplifier circuit 100 having the band 3.1-10.3 GHz, the architecture of the common source amplifying circuit 400 includes: a second transistor M ₂ and a third transistor M ₃ , The second transistor M ₂ and the third transistor M ₃ are cascoded in a common-source and a common-gate manner, and the drain of the second transistor M ₂ the third transistor M is connected to the source electrode _3.

The common source amplifying circuit 400 includes a second input terminal IP ₂ and a second output terminal OP ₂ , and the second input terminal IP ₂ is a gate of the second transistor M ₂ and is connected to the output terminal of the intermediate matching circuit 300. In addition, the second input terminal IP ₂ is first connected in series with a first resistor R ₁ and then connected to a fixed voltage source V _g2 to provide a gate bias voltage of the second transistor M ₂ through the fixed voltage source V _g2 . The third inductor L ₃ is connected in series between the source and the ground of the second transistor M ₂ .

The second output terminal OP ₂ is the drain of the third transistor M ₃ , and the second output terminal OP _{2 is} connected in series with the DC blocking capacitor C _b3 and then connected to the signal output terminal RF _out . In addition, a load inductor L _d2 is connected in series between the gate of the second output terminal OP ₂ and the third transistor M ₃ , and the gate of the third transistor M ₃ is first connected in series with a second resistor R ₂ and then V _g3 is electrically connected to a fixed voltage source, to provide a third transistor M gate electrode ₃ of a bias voltage. In addition, a grounding capacitor C _bp2 is connected in series between the fixed voltage source V _g3 and the ground to isolate the noise.

Similarly, the second transistor M ₂ and the third transistor M ₃ are an N-type metal oxide semiconductor transistor (NMOS), and the bias voltage of the fixed voltage source V _g2 is 0.7 V, and the fixed voltage source V _g3 The output bias voltage is 1.5V.

As shown in FIG. 3B, the same common gate amplifying circuit 200 architecture as in FIG. 3A can be used in the wideband low noise amplifier circuit 100 having the frequency band 14.3-29.3 GHz, and therefore only the common source amplifying circuit 400 is used here. The circuit architecture is described. The first sub-transistor M _1a and the second sub-transistor M _{1b of the} common gate amplifying circuit 200 also have a multi-finger gate structure, but the total gate width is 44 μm, and the output of the fixed voltage source V _g1 is biased. The voltage is 0.8V.

The structure of the common source amplifying circuit 400 includes: a second transistor M ₂ and a third transistor M ₃ , wherein the second transistor M ₂ and the third transistor M ₃ are two-stage common source (common- The amplifier circuit is connected in series to form a common-source cascade amplifier circuit, and the drain of the second transistor M ₂ passes through the gate of the DC blocking capacitor C _b4 and the third transistor M ₃ . connection. In this embodiment, a common source series amplifying circuit is used to compensate for the shortage of the band gain in the common gate amplifying circuit 200.

The common source amplifying circuit 400 includes a second input terminal IP ₂ and a second output terminal OP ₂ , and the second input terminal IP ₂ is a gate of the second transistor M ₂ and is connected to the output end of the intermediate matching circuit 300. In addition, the second input terminal IP ₂ is first connected in series with a first resistor R ₁ and then connected to a fixed voltage source V _g2 to provide a gate bias voltage of the second transistor M ₂ through the fixed voltage source V _g2 . The third inductor L ₃ is connected in series between the source and the ground of the second transistor M ₂ . A load inductor L _d3 is further connected in series between the drain of the second transistor M ₂ and a fixed voltage source V _d2 , and a grounding capacitor C _bp3 is connected in series between the fixed voltage source V _d2 and the ground to isolate the noise.

The second output terminal OP ₂ is a drain of the third transistor M ₃ , and is connected in series with the DC blocking capacitor C _b3 and then connected to the signal output terminal RF _out . The gate of the third transistor M ₃ is connected in series with a third resistor R ₃ and then connected to a fixed voltage source V _g3 to provide a gate bias voltage of the third transistor M ₃ through the fixed voltage source V _g3 . A grounding inductance L _s3 is connected in series between the source and the ground of the third transistor M ₃ , and between the drain of the third transistor M ₃ (ie, the second output terminal OP ₂ ) and a fixed voltage source V _d3 A load inductor L _d2 is connected in series, and a grounding capacitor C _bp2 is connected in series between the fixed voltage source V _d3 and the ground to isolate the noise.

The second transistor M ₂ and the third transistor M ₃ are an N-type metal oxide semiconductor transistor (NMOS), and the bias voltages of the fixed voltage sources V _g2 and V _g3 are 0.8 V, and the fixed voltage source is The bias voltages of V _d2 and V _d3 are 1.2V.

As shown in FIG. 3A and second FIG. 3B, the intermediate matching circuit 300, which comprises a L _4, L ₄ fourth inductor connected in series to a first output terminal system OP ₁ and the second input terminal IP ₂ between the pair of the fourth inductor, and A DC blocking capacitor C _b2 may be further connected in series between the one end of the fourth inductor L ₄ and the first output terminal OP ₁ .

A design band is predetermined (step S20): the design band is selected by the circuit designer and is the frequency band in which the wideband low noise amplifier circuit 100 is to operate. The design band is provided to the first input IP ₁ and is between X GHz and Y GHz, for example between 3.1 GHz and 10.3 GHz or between 14.3 GHz and 29.3 GHz. More importantly, when the design frequency band is determined, a resonant frequency can be derived by designing the frequency band calculation, and the resonant frequency derivation is one-half of the sum of the maximum and minimum values in the design frequency band ( That is, one-half of the X frequency plus the Y frequency). Therefore, when the design frequency band is 3.1 GHz to 10.3 GHz, the resonance frequency is 6.7 GHz, and when the design frequency band is 14.3 GHz to 29.3 GHz, the resonance frequency is 21.8 GHz.

Selecting a transistor (step S30): when the resonant frequency is derived, the second transistor M ₁ and the third transistor M ₂ and the third transistor of the common transistor M ₁ and the common source amplifying circuit 400 in the common gate amplifying circuit 200 can be selected. The transistor specification and bias voltage of M ₃ can determine the transconductance and parasitic capacitance of the first transistor M ₁ , the second transistor M _{2 ,} and the third transistor M ₃ , and should be selected in the common gate amplifying circuit 200 a first transistor M ₁ transduction one parameter, so that the value of the parameter corresponding to the transduction of a first input terminal IP of _an input impedance of 50 ohms or less, to help reduce noise.

Determining a first transistor M _1, a second transistor M ₂ and the third transducing transistor M ₃ and the parasitic capacitance will be able to learn the first transistor M _1, M ₂ of the second transistor and the third The parameters of the transistor M ₃ . The impedance matching technique is required between the common gate amplifying circuit 200 and the common source amplifying circuit 400, and the inductances of the first inductor L ₁ , the second inductor L ₂ , the third inductor L _{3 ,} and the fourth inductor L ₄ are designed. The value, in turn, has a higher gain in the low frequency band and the high frequency band through the common gate amplifying circuit 200, and the common source amplifying circuit 400 has a higher gain in the middle frequency band, so that the combined wide frequency low noise amplifier circuit 100 can There is sufficient gain for the entire wide frequency band.

Therefore, the small signal analysis is performed below for the first transistor M ₁ in the common gate amplifying circuit 200, the intermediate matching circuit 300, and the second transistor M ₂ in the common source amplifying circuit 400.

As shown in Figure 4A, a first common gate transistor M amplifying circuit transduction g _{m1 1} in the first transistor M ₁ to the drain D and the source S ₁ rooms offer _a current source, and the first The parasitic capacitance between the gate G ₁ and the source S ₁ of the transistor M ₁ is C _gs1 , the parasitic capacitance of the gate G ₁ and the drain D ₁ is C _gd1 , and the resistance of the drain D ₁ and the source S ₁ is r _ds1 , the voltage difference between the gate G ₁ and the source S ₁ is V _gs1 , and the capacitances C _b1 and C _b2 are DC blocking capacitors. The second transistor M ₂ in the common source amplifying circuit transduces g _m2 to provide a current source between the drain D ₂ and the source S _{2 of the} second transistor M ₂ , and the capacitor C _gs2 is the gate G ₂ and the source The parasitic capacitance between S ₂ , the resistance R _o2 is the output resistance of the common source amplifying circuit 400, and V _gs2 is the voltage difference between the gate G ₂ and the source D ₂ . Z _in refers to the input impedance seen from the source S _{1 of the} first transistor M ₁ , Z _L is the load impedance seen from the drain D _{1 of the} first transistor M ₁ , and Z _p is the common gate The output impedance of the amplifying circuit 200, Z _{s ,} is the input impedance of the common source amplifying circuit 400.

As shown in FIG. 4A and FIG. 4B, the second inductor L _{2 is} connected to the drain D ₁ end of the first transistor M ₁ , and the inductor L is connected in series with the fourth inductor L ₄ and the third inductor L ₃ , and the resistor is connected. R _o is the equivalent output resistance of the parallel capacitor and the inductor (the second inductor L ₂ and the parasitic capacitor C _gd1 ), and the resistor R _I is a series capacitor and an inductor (the inductor L and the parasitic capacitor C _gs2 ). Effective input resistance.

Thereby, the output impedance of the common gate amplifying circuit can be resonantly matched with the input impedance of the common source amplifying circuit to reduce the loss caused by signal reflection, that is, the parallel resonant capacitor and the inductor to the series capacitor and the inductor have the same resonant frequency. . Parallel to the inductance and capacitance circuit is connected to the gate of the first transistor M _1, a second inductor electrode G ₁ and the drain of the parasitic capacitance of the drain D of the C _{gd1 1} Room parallel to the first transistor M ₁ and L ₂ extreme When the circuit resonance is reached, its resonant frequency is The series inductors and capacitors (L and C _gs2 ) are formed by connecting the inductor L and the parasitic capacitance C _gs2 between the gate G ₂ and the source S ₂ of the second transistor M ₂ . When the circuit resonance is matched, the resonance Frequency is

Z _in is the input impedance seen from the source S _{1 of the} first transistor M ₁ , and the input impedance Z _in can be expressed as follows:

Wherein, the resistance r _ds1 is the resistance between the drain D ₁ of the first transistor M ₁ and the source S ₁ , and Z _L is the load impedance seen from the drain D _{1 of the} first transistor M ₁ , and g _m1 is the first The transconductance of the transistor M ₁ , the capacitance C _gs1 is the parasitic capacitance between the gate G ₁ and the source S ₁ of the first transistor M ₁ , C _b1 is a DC blocking capacitor, and the inductance L _s1 is the source of the first transistor M ₁ The inductance of the pole S ₁ is the first inductance L ₁ . At low frequencies, Z _{in is} approximately 1/g _m , so that broadband impedance matching can be achieved. As the frequency increases, the parasitic capacitance C _{gs1 of the} first transistor M ₁ will degrade at high frequencies, which can be compensated by inductance. Capacitance effect, at this time, the gain curve of the amplifying circuit is relatively flat, so it can reach wide frequency.

When designing the input to match the 3.1-10.3 GHz band, the input inductor and capacitor resonant circuit architecture consists of a capacitor C _{gs1 in} parallel with the first inductor L ₁ , which has a resonant frequency of 6.7 GHz and a broadband response at 2.5-10.6 GHz. The insertion loss is less than 0.9 dB. In the design input matched to the frequency band 14.3-29.3 GHz, the resonant frequency is 21.8 GHz and the broadband response is achieved, with an insertion loss of less than 1 dB at 13-30 GHz.

As shown in FIG. 5, for example, analog 3.1-10.3 GHz band and Z _s Z _p this embodiment, the common gate circuit 200 amplifying the output impedance compared with _{Z p = R P + jX p} , whose resonance frequency is 6.7 GHz . The input impedance of the common source amplifying circuit 400 is Z _s = R _s + jX _s , and the resonant frequency is also 6.7 GHz. In order to eliminate the imaginary part of Z _p and Z _s to form a real impedance, when X _p =-X _s condition, a conjugate matching is formed, and the frequencies at which the imaginary part is cancelled are 3.7 GHz and 10 GHz, respectively. At the 6.7 GHz frequency, the output resistance of the common gate amplifying circuit 200 does not match the input resistance of the common source amplifying circuit 400, which causes the power gain of the common gate amplifying circuit 200 to decrease and a dual frequency response occurs.

As shown in FIG. 6, the present embodiment the analog 14.3-29.3 GHz band and Z _s Z _p embodiments, at high frequencies the resistance R _s (the real part of the common source electrode of the input impedance of the amplifier circuit 400) is not a constant, because The source inductance value of the common source amplifying circuit 400 increases as the frequency increases, thereby increasing the input impedance of the common source amplifying circuit 400. Thus at high frequencies due Z _s Z _p and imaginary part are no longer destructive, it is not possible to achieve conjugate matching, the gain decreases.

In addition, the noise factor of the broadband low noise amplifier 100 is illustrated as follows:

In the noise factor expression, L _ip is the loss of signal for the input passive component, R _s is the resistance of the signal source, A ₁ is the power gain of the common gate amplifying circuit 200, and F ₂ is the noise factor of the next stage. , α=g _m /g _ds0 , g _m is the transduction of the transistor, g _ds0 is the zero-biased bucking conductance coefficient, γ is the channel thermal noise coefficient, and g _m1 is the transduction of the first transistor M ₁ , ω _T is the cutoff frequency of the transistor, and δ is the gate noise coefficient. It is found that the noise factor has the greatest influence on the two parameters, g _m1 and A _{1 respectively} , and adding g _m1 and A ₁ can reduce the noise, so by selecting the appropriate g _m1 and considering the dual frequency of the common gate amplifying circuit 200 The feature will reduce the noise factor of the entire broadband.

Therefore, in practical applications, the channel width and length dimensions of the first transistor M ₁ are selected to be 141 μm and 0.18 μm in the broadband low noise amplifier circuit 100 of the 3.1-10.3 GHz band, and the bias voltage V _g1 = V _d1 = 0.7V. , g _m1 = 0.05 s, or the channel width and length dimensions of the first transistor M ₁ selected in the 14.3-29.3 GHz broadband low noise amplifier circuit 100 are 88 μm and 0.18 μm, and the bias voltage V _g1 = V _d1 = 0.8 V, g _m1 = 0.041 s can have a larger transduction to help reduce noise.

As shown in FIG. 7 and FIG. 8 , which is the analog broadband output gain characteristic curve of the present embodiment, the wide difference between the wide frequency low noise amplifier circuit 100 and the conventional low noise amplifier disclosed in this embodiment is that Broadband gain. When the common gate amplifying circuit 200 alone has only a low gain wide frequency, the common and high frequency band portions are amplified by the common gate amplifying circuit 200 and the common source amplifying circuit 400 is connected in series by an intermediate matching circuit to amplify and The mid-band portion is compensated, and finally a broadband gain is obtained. Therefore, in addition to increasing the gain in series, a plurality of amplifying circuits can achieve the purpose of wide frequency.

In summary, in order to achieve impedance matching between the common gate amplifying circuit 200 and the common source amplifying circuit 400, the first inductor L ₁ , the second inductor L ₂ , the third inductor L _{3 ,} and the third Four inductors L ₄ to effectively save time in trying to make mistakes in the design process.

As FIG. 3A, FIG. 3B, FIG. 4A shown in FIG. 4 B second, adjusting the first input impedance matching (Step S40): By adjusting the first inductor L _1, the first input terminal of the resonant IP ₁ The frequency matching, that is, adjusting the first inductance L ₁ to achieve a resonance frequency matching with the gate-source parasitic capacitance C _gs1 of the first transistor M _{1 in} the common gate amplifying circuit 200. By adjusting the size of the inductance of the first inductance value L _1, the input impedance can be controlled, so that the real part of the impedance to achieve real and imaginary part is zero.

Adjusting the impedance matching of the first output end (step S50): adjusting the second inductance L ₂ to make the first output end OP ₁ reach the resonance frequency matching, that is, adjusting the second inductance L ₂ to be in the common gate amplification circuit 200 The gate-drain parasitic capacitance C _{gd1 of the} first transistor M _{1 achieves} a resonant frequency match. By adjusting the magnitude of the inductance of the second inductor L ₂ , the output impedance can be controlled such that the real part reaches the real impedance and the imaginary part is zero.

Design of a third inductance value (Step S60): By adjusting the third inductor L ₃ so that the common-source circuit 400 amplifying the input impedance of a resistance value of a design in which the design value of the resistance is set by the circuit designer in advance, for example, may be set to 50 ohms. The third inductor L ₃ can also be referred to as a common source degeneration inductor, and the real source input impedance is generated by the common source degeneration inductance, the gate-source parasitic capacitance C _gs2 and the fourth inductance L ₄ at the resonance frequency, and the input is real. The impedance is determined by the cutoff frequency of the second transistor M ₂ and the third inductance L ₃ .

Adjusting the intermediate matching circuit impedance matching (step S70): adjusting the fourth inductance L _{4 to} make the input end of the intermediate matching circuit 300 and the first output end OP ₁ reach the same resonant frequency, and thus adjusting the inductance value of the fourth inductor L ₄ The size can be used to control the input impedance so that the real part reaches the real impedance and the imaginary part is zero.

Adjusting the common-source amplifier and the optimum gain optimal input matching (Step S80): adjusting the third inductor L ₃ again so that the common-source amplifier 400 of gain and bandwidth of optimization. Since the real value of the impedance is determined by the selection of the inductance, the equivalent input impedance R _I of the common source amplifying circuit 400 can be calculated after adjusting the third inductance L ₃ again, since the equivalent input impedance R _{I is} small. , can not be directly adjusted, so the equivalent input impedance can be brought into the second inductance L ₂ formula L ₂ = R _I × R _O × C _gs2 to calculate the L ₂ inductance, where R _o is the parallel capacitance and inductance Effective output resistance, this R _o is calculated by the analog software, the parasitic capacitance C _{gs2 is} determined by the size of the second transistor M ₂ , plus the resonance condition L ₂ × C _gd1 = L × C _gs2 to recalculate the first transistor M ₁ Parasitic capacitance C _gd1 .

Step S80 may further include the step of selecting the transistor again, which again selects the specification of the first transistor M _{1 in} the common gate amplifying circuit 200 and adjusts the bias voltage so that the first output terminal OP ₁ and the second input terminal The IP ₂ again reaches the same resonant frequency.

The above formula must be greater than R _o R _I, wherein the resistance R _o M ₁ comprises a first transistor drain and the source S D ₁ channel resistance of r _{ds1 1} Room. Moreover, since C _gd1 is the parasitic capacitance of the first transistor M ₁ , adjusting the transistor size of the first transistor M ₁ changes the capacitance value of the parasitic capacitance, and also affects the transconductance value g _m1 . Maintain the same transconductance and allow input impedance matching and appropriate gain to be achieved.

The following describes the operational characteristics of the wideband low noise amplifier circuit 100 of the present embodiment after performing circuit simulation and actual measurement results. The wideband low noise amplifier circuit 100 of the present embodiment 3.1-10.3 GHz and 14.3-29.3 GHz is fabricated through a 0.18 μm CMOS process, and the obtained wafer area is 0.83 μm × 0.82 μm, and the latter is 0.83 μm × 0.65 μm. Test points are provided as sexual energy measurements.

For the input and output ends of the wideband low noise amplifier circuit 100 of the present embodiment, the probe is measured at the test point. In the wide frequency range of 3.1 GHz to 10.3 GHz, the signal input terminal RF _in and the signal output terminal RF _out S The parameter measurement system uses the Agilent PNA N5230 vector network analyzer measurement and calibration program SOLT (Short-Open-Load-Through) for measurement error correction. The noise index is measured by the Agilent N8975A; the wide frequency range is 14.3 GHz to 29.3 GHz. The S parameter measurement system of the signal input terminal RF _in and the signal output terminal RF _out is measured by the Agilent PNA E8361A vector network analyzer measurement and calibration program SOLT (Short-Open-Load-Through) for measurement error correction, noise index It is measured by the Agilent N8975A.

Figure 9 is a graph showing the measurement results of the frequency response characteristic curve of the output gain S ₂₁ of the 3.1-10.3 GHz band according to an embodiment of the present invention. Figure 10 is a graph showing the measurement results of the frequency response characteristic curve of the output gain S ₂₁ of the 14.3-29.3 GHz band according to an embodiment of the present invention. As shown in Figure 9, the gain is greater than 9.6 dB over the wide frequency range of 3.1 GHz to 10.3 GHz; as shown in Figure 10, the gain is 8.25 ± 1.65 over the wide frequency range of 14.3 GHz to 29.3 GHz. dB.

Figure 11 is a graph showing the measurement results of the frequency response characteristic curve of the input end reflection coefficient S ₁₁ of the 3.1-10.3 GHz band in the embodiment of the present invention. Figure 12 is a graph showing the measurement results of the frequency response characteristic curve of the input end reflection coefficient S ₁₁ of the 14.3-29.3 GHz band in the embodiment of the present invention. As shown in Figure 11, the reflection coefficient S ₁₁ at the input is less than -9 dB over the wide frequency range of 3.1 GHz to 10.3 GHz; as shown in Figure 12, in the wide frequency range of 14.5 GHz to 29 GHz, The reflection coefficient S _{11 at} its input is below -10 dB.

Figure 13 is a graph showing the measurement results of the noise characteristic curve (Noise Figure, NF) of the 3.1-10.3 GHz band with respect to the input signal frequency according to an embodiment of the present invention. Figure 14 is a graph showing measurement results of a characteristic curve of a noise index in the 14.3-29.3 GHz band with respect to an input signal frequency according to an embodiment of the present invention. As shown in Figure 13, the noise figure is less than 3.9 dB over a wide frequency range of 3.1 GHz to 10.3 GHz with a minimum noise figure of 2.5 dB; as shown in Figure 14, at 14.3 GHz to 29.3 GHz In the wide frequency range, the noise index is below 5.8 dB and the minimum noise index is 4.3 dB.

Figure 15 is a third-order intermodulation intercept point of the output power of the 3.1-10.3 GHz band with respect to the input signal power according to an embodiment of the present invention. IIP ₃ and 1 dB gain compression point (1 dB) Compression point) P _1dB characteristic curve measurement results. Figure 16 is a graph showing the measurement results of the characteristic curve of the third-order intermodulation crossover IIP ₃ and the 1 dB gain compression point P _1dB of the output power of the 14.3-29.3 GHz band with respect to the input signal power according to an embodiment of the present invention. As shown in Figure 15, the third-order intermodulation crossover IIP ₃ is 1 dBm over a wide frequency range of 3.1 GHz to 10.3 GHz, while the 1 dB gain compression point P _1dB is -12.5 dBm; As shown, the third-order intermodulation crossover IIP ₃ is -2 dBm over the wide frequency range of 14.3 GHz to 29.3 GHz, while the 1 dB gain compression point P _1dB is -12 dBm.

In the above embodiments, according to the design method of the broadband low noise amplifier circuit 100, the impedance matching of the circuit is mainly designed to adjust the four inductors, which are respectively connected to the first inductor L of the source S ₁ of the first transistor M ₁ . _{1, 1} is connected to the drain D of the first transistor M _1, a second inductor L _2, is connected to the second transistor M ₂ between the gate G ₁ of the fourth transistor M ₂ and the first drain electrode D ₁ The inductor L ₄ and the third inductor L ₃ connected to the source S ₂ of the second transistor M ₂ respectively have a resonance frequency of about 6 GHz or 22 GHz, thereby increasing the operating bandwidth thereof.

In summary, since the present invention proposes a design method of a broadband low noise amplifier circuit, the conventional design method is more systematic, and can quickly estimate the approximate positions of the high frequency, the intermediate frequency, and the low frequency to achieve the broadband characteristic, and save the design process. Try the wrong time.

The embodiments are described to illustrate the features of the present invention, and the objects of the present invention will be understood by those skilled in the art, and are not intended to limit the scope of the present invention. Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the patent application described below.

100. . . Broadband low noise amplifier circuit

200. . . Common gate amplifying circuit

300. . . Intermediate matching circuit

400. . . Common source amplifying circuit

RF _in . . . Signal input

RF _out . . . Signal output

IP ₁ . . . First input

OP ₁ . . . First output

IP ₂ . . . Second input

OP ₂ . . . Second output

M ₁ . . . First transistor

M _1a . . . First sub-crystal

M _1b . . . Second sub-crystal

M ₂ . . . Second transistor

M ₃ . . . Third transistor

L. . . inductance

L ₁ . . . First inductance

L ₂ . . . Second inductance

L ₃ . . . Third inductance

L ₄ . . . Fourth inductance

L _d2 , L _d3 . . . Load inductance

L _s3 . . . Grounding inductance

C _b1 , C _b2 , C _b3 , C _b4 . . . DC blocking capacitor

C _bp1 , C _bp2 , C _bp3 . . . Grounding capacitor

C _gs1 , C _gs2 , C _gd1 . . . Parasitic capacitance

R ₁ . . . First resistance

R ₂ . . . Second resistance

R ₃ . . . Third resistance

r _ds1 . . . Equivalent resistance between the drain and the source

R _o . . . Parallel capacitor and inductor equivalent output resistance

R _o2 . . . Output resistance of common source amplifier circuit

R _I . . . Series capacitor and inductor equivalent input resistance

V _g1 , V _g2 , V _g3 , V _d2 , V _d3 . . . Fixed voltage source

V _gs1 , V _gs2 . . . Voltage difference between gate and source

g _m1 , g _m2 . . . divert

Z _in . . . input resistance

Z _L . . . Load impedance

Z _p . . . Output impedance

Z _s . . . input resistance

D ₁ , D ₂ . . . Bungee

G ₁ , G ₂ . . . Gate

S ₁ , S ₂ . . . Source

FIG. 1 is a flow chart of a method for designing a broadband low noise amplifier circuit according to an embodiment of the present invention.

2 is a circuit block diagram of a broadband low noise amplifier according to an embodiment of the present invention.

FIG. 3A is a circuit diagram of a broadband low noise amplifier circuit having a frequency band of 3.1-10.3 GHz according to an embodiment of the present invention.

FIG. 3B is a circuit diagram of a broadband low noise amplifier circuit having a frequency band of 14.3-29.3 GHz according to an embodiment of the present invention.

4A and 4B are diagrams showing a transistor small signal analysis circuit of a broadband low noise amplifier according to an embodiment of the present invention.

Figure 5 is a plot of the input/output impedance of the intermediate matching circuit in the 3.1-10.3 GHz band.

Figure 6 is a plot of the input/output impedance of the intermediate matching circuit in the analog 14.3-29.3 GHz band.

Figure 7 is a diagram showing the relationship of the output gain characteristic curve of the analog 3.1-10.3 GHz band according to an embodiment of the present invention.

Figure 8 is a diagram showing the relationship of the output gain characteristic curves of the analog 14.3-29.3 GHz band according to an embodiment of the present invention.

Figure 9 is a graph showing the measurement results of the frequency response characteristic curve of the output gain S ₂₁ of the 3.1-10.3 GHz band according to an embodiment of the present invention.

Figure 10 is a graph showing the measurement results of the frequency response characteristic curve of the output gain S ₂₁ of the 14.3-29.3 GHz band according to an embodiment of the present invention.

Figure 11 is a graph showing the measurement results of the frequency response characteristic curve of the input end reflection coefficient S ₁₁ of the 3.1-10.3 GHz band in the embodiment of the present invention.

Figure 12 is a graph showing the measurement results of the frequency response characteristic curve of the input end reflection coefficient S ₁₁ of the 14.3-29.3 GHz band in the embodiment of the present invention.

Figure 13 is a graph showing measurement results of a variation characteristic of a noise index of a 3.1-10.3 GHz band with respect to an input signal frequency according to an embodiment of the present invention.

Figure 14 is a graph showing measurement results of a characteristic curve of a noise index in the 14.3-29.3 GHz band with respect to an input signal frequency according to an embodiment of the present invention.

Figure 15 is a graph showing the measurement results of the characteristic curve of the third-order cross-modulation intersection IIP ₃ and the 1 dB gain compression point P _1dB of the output power of the 3.1-10.3 GHz band with respect to the input signal power according to an embodiment of the present invention.

Figure 16 is a graph showing the measurement results of the characteristic curve of the third-order intermodulation crossover IIP ₃ and the 1 dB gain compression point P _1dB of the output power of the 14.3-29.3 GHz band with respect to the input signal power according to an embodiment of the present invention.

100. . . Broadband low noise amplifier circuit

200. . . Common gate amplifying circuit

300. . . Intermediate matching circuit

400. . . Common source amplifying circuit

RF _in . . . Signal input

RF _out . . . Signal output

L ₁ . . . First inductance

L ₂ . . . Second inductance

L ₃ . . . Third inductance

Claims (12)

A design method of a broadband low noise amplifier circuit is carried out in conjunction with an analog software, the design method comprising the steps of: providing a broadband low noise amplifier circuit comprising: a common gate amplifying circuit comprising a first An input terminal and a first output terminal, the common gate amplifying circuit is externally connected with a first inductor and a second inductor; and a common source amplifying circuit includes a second input end and a second output end, the common source The pole amplifier circuit is externally connected with a third inductor; and an intermediate matching circuit includes a fourth inductor connected in series between the first output end and the second input end; X GHz~Y GHz is provided to the first input end, and a resonant frequency is derived by calculating the design frequency band; selecting a transistor, which selects the common gate amplifying circuit and the common source amplifying circuit Crystal specification and bias voltage; adjusting impedance matching of the first input end, which adjusts the first inductance, so that the first input end reaches the resonance frequency matching; adjusting the impedance matching of the first output end, and adjusting the impedance The second inductor is configured to match the first output end to the resonant frequency; the third inductance value is designed to adjust the third inductance so that the input impedance of the common source amplifying circuit reaches a design resistance value; The intermediate matching circuit impedance matching adjusts the fourth inductance such that the input end of the intermediate matching circuit reaches the resonant frequency with the first output end; and adjusts the optimal gain and the optimal input matching of the common source amplifying circuit, The third inductance is adjusted again to optimize the gain and bandwidth of the common source amplifying circuit. The design method described in claim 1, wherein the X GHz to Y GHz is 3.1 GHz to 10.3 GHz or 14.3 GHz to 29.3 GHz. The design method of claim 1, wherein the common gate amplifying circuit adopts a multi-finger fork gate metal oxide semiconductor transistor structure. The design method of claim 1, wherein the common source amplifying circuit is a common source amplifying circuit. The design method of claim 4, wherein the common source amplifying circuit operates at 3.1 GHz to 10.3 GHz. The design method of claim 1, wherein the common source amplifying circuit is a common source series amplifying circuit. The design method of claim 6, wherein the common source amplifying circuit operates at 14.3 GHz to 29.3 GHz. The design method of claim 1, wherein the resonant frequency is one-half of the X frequency plus the Y frequency. The design method of claim 1, wherein the selecting a transistor step further comprises selecting a one of the transistors of the common gate amplifying circuit and transducing the parameter, and the transducing parameter corresponds to the first The input impedance of an input is less than or equal to 50 ohms. The design method of claim 1, wherein the adjusting the first input impedance matching step adjusts the first inductor to a gate-source of the transistor in the common gate amplifying circuit The parasitic capacitance between the poles achieves this resonance frequency matching. The design method of claim 1, wherein the adjusting the first output impedance matching step adjusts the second inductance to a gate of the transistor in the common gate amplifying circuit The parasitic capacitance between the poles achieves this resonance frequency matching. The design method of claim 1, wherein the adjusting the third inductor further comprises a step of selecting a transistor again, which again selects a transistor specification and a bias voltage of the common gate amplifying circuit. So that the resonant frequency is reached again between the first output end and the second input end.